target/linux/lantiq/patches-3.2/0009-MIPS-lantiq-add-support-for-FALC-ON-GPIOs.patch

   1 From 95e7c9e7b37b06462c8b3b8431dc64d60369eb38 Mon Sep 17 00:00:00 2001
   2 From: John Crispin <blogic@openwrt.org>
   3 Date: Thu, 11 Aug 2011 14:35:02 +0200
   4 Subject: [PATCH 09/70] MIPS: lantiq: add support for FALC-ON GPIOs
   5
   6 FALC-ON uses a different GPIO core than the other Lantiq SoCs. This patch adds
   7 the new driver.
   8
   9 Signed-off-by: Thomas Langer <thomas.langer@lantiq.com>
  10 Signed-off-by: John Crispin <blogic@openwrt.org>
  11 ---
  12  arch/mips/lantiq/falcon/Makefile  |    2 +-
  13  arch/mips/lantiq/falcon/devices.c |   41 ++++
  14  arch/mips/lantiq/falcon/devices.h |    2 +
  15  arch/mips/lantiq/falcon/gpio.c    |  399 +++++++++++++++++++++++++++++++++++++
  16  4 files changed, 443 insertions(+), 1 deletions(-)
  17  create mode 100644 arch/mips/lantiq/falcon/gpio.c
  18
  19 --- a/arch/mips/lantiq/falcon/Makefile
  20 +++ b/arch/mips/lantiq/falcon/Makefile
  21 @@ -1 +1 @@
  22 -obj-y := clk.o prom.o reset.o sysctrl.o devices.o
  23 +obj-y := clk.o prom.o reset.o sysctrl.o devices.o gpio.o
  24 --- a/arch/mips/lantiq/falcon/devices.c
  25 +++ b/arch/mips/lantiq/falcon/devices.c
  26 @@ -9,6 +9,7 @@
  27
  28  #include <linux/platform_device.h>
  29  #include <linux/mtd/nand.h>
  30 +#include <linux/gpio.h>
  31
  32  #include <lantiq_soc.h>
  33
  34 @@ -85,3 +86,43 @@ falcon_register_nand(void)
  35  {
  36         platform_device_register(&ltq_flash_nand);
  37  }
  38 +
  39 +/* gpio */
  40 +#define DECLARE_GPIO_RES(port) \
  41 +static struct resource falcon_gpio ## port ## _res[] = { \
  42 +       MEM_RES("gpio"#port, LTQ_GPIO ## port ## _BASE_ADDR, \
  43 +               LTQ_GPIO ## port ## _SIZE), \
  44 +       MEM_RES("padctrl"#port, LTQ_PADCTRL ## port ## _BASE_ADDR, \
  45 +               LTQ_PADCTRL ## port ## _SIZE), \
  46 +       IRQ_RES("gpio_mux"#port, FALCON_IRQ_GPIO_P ## port) \
  47 +}
  48 +DECLARE_GPIO_RES(0);
  49 +DECLARE_GPIO_RES(1);
  50 +DECLARE_GPIO_RES(2);
  51 +DECLARE_GPIO_RES(3);
  52 +DECLARE_GPIO_RES(4);
  53 +
  54 +void __init
  55 +falcon_register_gpio(void)
  56 +{
  57 +       platform_device_register_simple("falcon_gpio", 0,
  58 +               falcon_gpio0_res, ARRAY_SIZE(falcon_gpio0_res));
  59 +       platform_device_register_simple("falcon_gpio", 1,
  60 +               falcon_gpio1_res, ARRAY_SIZE(falcon_gpio1_res));
  61 +       platform_device_register_simple("falcon_gpio", 2,
  62 +               falcon_gpio2_res, ARRAY_SIZE(falcon_gpio2_res));
  63 +       ltq_sysctl_activate(SYSCTL_SYS1, ACTS_PADCTRL1 | ACTS_P1);
  64 +       ltq_sysctl_activate(SYSCTL_SYSETH, ACTS_PADCTRL0 |
  65 +               ACTS_PADCTRL2 | ACTS_P0 | ACTS_P2);
  66 +}
  67 +
  68 +void __init
  69 +falcon_register_gpio_extra(void)
  70 +{
  71 +       platform_device_register_simple("falcon_gpio", 3,
  72 +               falcon_gpio3_res, ARRAY_SIZE(falcon_gpio3_res));
  73 +       platform_device_register_simple("falcon_gpio", 4,
  74 +               falcon_gpio4_res, ARRAY_SIZE(falcon_gpio4_res));
  75 +       ltq_sysctl_activate(SYSCTL_SYS1,
  76 +               ACTS_PADCTRL3 | ACTS_PADCTRL4 | ACTS_P3 | ACTS_P4);
  77 +}
  78 --- a/arch/mips/lantiq/falcon/devices.h
  79 +++ b/arch/mips/lantiq/falcon/devices.h
  80 @@ -14,5 +14,7 @@
  81  #include "../devices.h"
  82
  83  extern void falcon_register_nand(void);
  84 +extern void falcon_register_gpio(void);
  85 +extern void falcon_register_gpio_extra(void);
  86
  87  #endif
  88 --- /dev/null
  89 +++ b/arch/mips/lantiq/falcon/gpio.c
  90 @@ -0,0 +1,399 @@
  91 +/*
  92 + *  This program is free software; you can redistribute it and/or modify it
  93 + *  under the terms of the GNU General Public License version 2 as published
  94 + *  by the Free Software Foundation.
  95 + *
  96 + *  Copyright (C) 2011 Thomas Langer <thomas.langer@lantiq.com>
  97 + *  Copyright (C) 2011 John Crispin <blogic@openwrt.org>
  98 + */
  99 +
 100 +#include <linux/gpio.h>
 101 +#include <linux/interrupt.h>
 102 +#include <linux/slab.h>
 103 +#include <linux/export.h>
 104 +#include <linux/platform_device.h>
 105 +
 106 +#include <lantiq_soc.h>
 107 +
 108 +/* Multiplexer Control Register */
 109 +#define LTQ_PADC_MUX(x)         (x * 0x4)
 110 +/* Pad Control Availability Register */
 111 +#define LTQ_PADC_AVAIL          0x000000F0
 112 +
 113 +/* Data Output Register */
 114 +#define LTQ_GPIO_OUT            0x00000000
 115 +/* Data Input Register */
 116 +#define LTQ_GPIO_IN             0x00000004
 117 +/* Direction Register */
 118 +#define LTQ_GPIO_DIR            0x00000008
 119 +/* External Interrupt Control Register 0 */
 120 +#define LTQ_GPIO_EXINTCR0       0x00000018
 121 +/* External Interrupt Control Register 1 */
 122 +#define LTQ_GPIO_EXINTCR1       0x0000001C
 123 +/* IRN Capture Register */
 124 +#define LTQ_GPIO_IRNCR          0x00000020
 125 +/* IRN Interrupt Configuration Register */
 126 +#define LTQ_GPIO_IRNCFG                0x0000002C
 127 +/* IRN Interrupt Enable Set Register */
 128 +#define LTQ_GPIO_IRNRNSET       0x00000030
 129 +/* IRN Interrupt Enable Clear Register */
 130 +#define LTQ_GPIO_IRNENCLR       0x00000034
 131 +/* Output Set Register */
 132 +#define LTQ_GPIO_OUTSET         0x00000040
 133 +/* Output Cler Register */
 134 +#define LTQ_GPIO_OUTCLR         0x00000044
 135 +/* Direction Clear Register */
 136 +#define LTQ_GPIO_DIRSET         0x00000048
 137 +/* Direction Set Register */
 138 +#define LTQ_GPIO_DIRCLR         0x0000004C
 139 +
 140 +/* turn a gpio_chip into a falcon_gpio_port */
 141 +#define ctop(c)                container_of(c, struct falcon_gpio_port, gpio_chip)
 142 +/* turn a irq_data into a falcon_gpio_port */
 143 +#define itop(i)                ((struct falcon_gpio_port *) irq_get_chip_data(i->irq))
 144 +
 145 +#define ltq_pad_r32(p, reg)            ltq_r32(p->pad + reg)
 146 +#define ltq_pad_w32(p, val, reg)       ltq_w32(val, p->pad + reg)
 147 +#define ltq_pad_w32_mask(c, clear, set, reg) \
 148 +               ltq_pad_w32(c, (ltq_pad_r32(c, reg) & ~(clear)) | (set), reg)
 149 +
 150 +#define ltq_port_r32(p, reg)           ltq_r32(p->port + reg)
 151 +#define ltq_port_w32(p, val, reg)      ltq_w32(val, p->port + reg)
 152 +#define ltq_port_w32_mask(p, clear, set, reg) \
 153 +               ltq_port_w32(p, (ltq_port_r32(p, reg) & ~(clear)) | (set), reg)
 154 +
 155 +#define MAX_PORTS              5
 156 +#define PINS_PER_PORT          32
 157 +
 158 +struct falcon_gpio_port {
 159 +       struct gpio_chip gpio_chip;
 160 +       void __iomem *pad;
 161 +       void __iomem *port;
 162 +       unsigned int irq_base;
 163 +       unsigned int chained_irq;
 164 +};
 165 +
 166 +static struct falcon_gpio_port ltq_gpio_port[MAX_PORTS];
 167 +
 168 +int gpio_to_irq(unsigned int gpio)
 169 +{
 170 +       return __gpio_to_irq(gpio);
 171 +}
 172 +EXPORT_SYMBOL(gpio_to_irq);
 173 +
 174 +int ltq_gpio_mux_set(unsigned int pin, unsigned int mux)
 175 +{
 176 +       int port = pin / 100;
 177 +       int offset = pin % 100;
 178 +       struct falcon_gpio_port *gpio_port;
 179 +
 180 +       if ((offset >= PINS_PER_PORT) || (port >= MAX_PORTS))
 181 +               return -EINVAL;
 182 +
 183 +       gpio_port = &ltq_gpio_port[port];
 184 +       ltq_pad_w32(gpio_port, mux & 0x3, LTQ_PADC_MUX(offset));
 185 +
 186 +       return 0;
 187 +}
 188 +EXPORT_SYMBOL(ltq_gpio_mux_set);
 189 +
 190 +int ltq_gpio_request(unsigned int pin, unsigned int mux,
 191 +                       unsigned int dir, const char *name)
 192 +{
 193 +       int port = pin / 100;
 194 +       int offset = pin % 100;
 195 +
 196 +       if (offset >= PINS_PER_PORT || port >= MAX_PORTS)
 197 +               return -EINVAL;
 198 +
 199 +       if (gpio_request(pin, name)) {
 200 +               pr_err("failed to setup lantiq gpio: %s\n", name);
 201 +               return -EBUSY;
 202 +       }
 203 +
 204 +       if (dir)
 205 +               gpio_direction_output(pin, 1);
 206 +       else
 207 +               gpio_direction_input(pin);
 208 +
 209 +       return ltq_gpio_mux_set(pin, mux);
 210 +}
 211 +EXPORT_SYMBOL(ltq_gpio_request);
 212 +
 213 +static int
 214 +falcon_gpio_direction_input(struct gpio_chip *chip, unsigned int offset)
 215 +{
 216 +       ltq_port_w32(ctop(chip), 1 << offset, LTQ_GPIO_DIRCLR);
 217 +
 218 +       return 0;
 219 +}
 220 +
 221 +static void
 222 +falcon_gpio_set(struct gpio_chip *chip, unsigned int offset, int value)
 223 +{
 224 +       if (value)
 225 +               ltq_port_w32(ctop(chip), 1 << offset, LTQ_GPIO_OUTSET);
 226 +       else
 227 +               ltq_port_w32(ctop(chip), 1 << offset, LTQ_GPIO_OUTCLR);
 228 +}
 229 +
 230 +static int
 231 +falcon_gpio_direction_output(struct gpio_chip *chip,
 232 +                       unsigned int offset, int value)
 233 +{
 234 +       falcon_gpio_set(chip, offset, value);
 235 +       ltq_port_w32(ctop(chip), 1 << offset, LTQ_GPIO_DIRSET);
 236 +
 237 +       return 0;
 238 +}
 239 +
 240 +static int
 241 +falcon_gpio_get(struct gpio_chip *chip, unsigned int offset)
 242 +{
 243 +       if ((ltq_port_r32(ctop(chip), LTQ_GPIO_DIR) >> offset) & 1)
 244 +               return (ltq_port_r32(ctop(chip), LTQ_GPIO_OUT) >> offset) & 1;
 245 +       else
 246 +               return (ltq_port_r32(ctop(chip), LTQ_GPIO_IN) >> offset) & 1;
 247 +}
 248 +
 249 +static int
 250 +falcon_gpio_request(struct gpio_chip *chip, unsigned offset)
 251 +{
 252 +       if ((ltq_pad_r32(ctop(chip), LTQ_PADC_AVAIL) >> offset) & 1) {
 253 +               if (ltq_pad_r32(ctop(chip), LTQ_PADC_MUX(offset)) > 1)
 254 +                       return -EBUSY;
 255 +               /* switch on gpio function */
 256 +               ltq_pad_w32(ctop(chip), 1, LTQ_PADC_MUX(offset));
 257 +               return 0;
 258 +       }
 259 +
 260 +       return -ENODEV;
 261 +}
 262 +
 263 +static void
 264 +falcon_gpio_free(struct gpio_chip *chip, unsigned offset)
 265 +{
 266 +       if ((ltq_pad_r32(ctop(chip), LTQ_PADC_AVAIL) >> offset) & 1) {
 267 +               if (ltq_pad_r32(ctop(chip), LTQ_PADC_MUX(offset)) > 1)
 268 +                       return;
 269 +               /* switch off gpio function */
 270 +               ltq_pad_w32(ctop(chip), 0, LTQ_PADC_MUX(offset));
 271 +       }
 272 +}
 273 +
 274 +static int
 275 +falcon_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
 276 +{
 277 +       return ctop(chip)->irq_base + offset;
 278 +}
 279 +
 280 +static void
 281 +falcon_gpio_disable_irq(struct irq_data *d)
 282 +{
 283 +       unsigned int offset = d->irq - itop(d)->irq_base;
 284 +
 285 +       ltq_port_w32(itop(d), 1 << offset, LTQ_GPIO_IRNENCLR);
 286 +}
 287 +
 288 +static void
 289 +falcon_gpio_enable_irq(struct irq_data *d)
 290 +{
 291 +       unsigned int offset = d->irq - itop(d)->irq_base;
 292 +
 293 +       if (!ltq_pad_r32(itop(d), LTQ_PADC_MUX(offset)) < 1)
 294 +               /* switch on gpio function */
 295 +               ltq_pad_w32(itop(d), 1, LTQ_PADC_MUX(offset));
 296 +
 297 +       ltq_port_w32(itop(d), 1 << offset, LTQ_GPIO_IRNRNSET);
 298 +}
 299 +
 300 +static void
 301 +falcon_gpio_ack_irq(struct irq_data *d)
 302 +{
 303 +       unsigned int offset = d->irq - itop(d)->irq_base;
 304 +
 305 +       ltq_port_w32(itop(d), 1 << offset, LTQ_GPIO_IRNCR);
 306 +}
 307 +
 308 +static void
 309 +falcon_gpio_mask_and_ack_irq(struct irq_data *d)
 310 +{
 311 +       unsigned int offset = d->irq - itop(d)->irq_base;
 312 +
 313 +       ltq_port_w32(itop(d), 1 << offset, LTQ_GPIO_IRNENCLR);
 314 +       ltq_port_w32(itop(d), 1 << offset, LTQ_GPIO_IRNCR);
 315 +}
 316 +
 317 +static struct irq_chip falcon_gpio_irq_chip;
 318 +static int
 319 +falcon_gpio_irq_type(struct irq_data *d, unsigned int type)
 320 +{
 321 +       unsigned int offset = d->irq - itop(d)->irq_base;
 322 +       unsigned int mask = 1 << offset;
 323 +
 324 +       if ((type & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_NONE)
 325 +               return 0;
 326 +
 327 +       if ((type & (IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW)) != 0) {
 328 +               /* level triggered */
 329 +               ltq_port_w32_mask(itop(d), 0, mask, LTQ_GPIO_IRNCFG);
 330 +               irq_set_chip_and_handler_name(d->irq,
 331 +                               &falcon_gpio_irq_chip, handle_level_irq, "mux");
 332 +       } else {
 333 +               /* edge triggered */
 334 +               ltq_port_w32_mask(itop(d), mask, 0, LTQ_GPIO_IRNCFG);
 335 +               irq_set_chip_and_handler_name(d->irq,
 336 +                       &falcon_gpio_irq_chip, handle_simple_irq, "mux");
 337 +       }
 338 +
 339 +       if ((type & IRQ_TYPE_EDGE_BOTH) == IRQ_TYPE_EDGE_BOTH) {
 340 +               ltq_port_w32_mask(itop(d), mask, 0, LTQ_GPIO_EXINTCR0);
 341 +               ltq_port_w32_mask(itop(d), 0, mask, LTQ_GPIO_EXINTCR1);
 342 +       } else {
 343 +               if ((type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_LEVEL_HIGH)) != 0)
 344 +                       /* positive logic: rising edge, high level */
 345 +                       ltq_port_w32_mask(itop(d), mask, 0, LTQ_GPIO_EXINTCR0);
 346 +               else
 347 +                       /* negative logic: falling edge, low level */
 348 +                       ltq_port_w32_mask(itop(d), 0, mask, LTQ_GPIO_EXINTCR0);
 349 +               ltq_port_w32_mask(itop(d), mask, 0, LTQ_GPIO_EXINTCR1);
 350 +       }
 351 +
 352 +       return gpio_direction_input(itop(d)->gpio_chip.base + offset);
 353 +}
 354 +
 355 +static void
 356 +falcon_gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
 357 +{
 358 +       struct falcon_gpio_port *gpio_port = irq_desc_get_handler_data(desc);
 359 +       unsigned long irncr;
 360 +       int offset;
 361 +
 362 +       /* acknowledge interrupt */
 363 +       irncr = ltq_port_r32(gpio_port, LTQ_GPIO_IRNCR);
 364 +       ltq_port_w32(gpio_port, irncr, LTQ_GPIO_IRNCR);
 365 +
 366 +       desc->irq_data.chip->irq_ack(&desc->irq_data);
 367 +
 368 +       for_each_set_bit(offset, &irncr, gpio_port->gpio_chip.ngpio)
 369 +               generic_handle_irq(gpio_port->irq_base + offset);
 370 +}
 371 +
 372 +static struct irq_chip falcon_gpio_irq_chip = {
 373 +       .name = "gpio_irq_mux",
 374 +       .irq_mask = falcon_gpio_disable_irq,
 375 +       .irq_unmask = falcon_gpio_enable_irq,
 376 +       .irq_ack = falcon_gpio_ack_irq,
 377 +       .irq_mask_ack = falcon_gpio_mask_and_ack_irq,
 378 +       .irq_set_type = falcon_gpio_irq_type,
 379 +};
 380 +
 381 +static struct irqaction gpio_cascade = {
 382 +       .handler = no_action,
 383 +       .flags = IRQF_DISABLED,
 384 +       .name = "gpio_cascade",
 385 +};
 386 +
 387 +static int
 388 +falcon_gpio_probe(struct platform_device *pdev)
 389 +{
 390 +       struct falcon_gpio_port *gpio_port;
 391 +       int ret, i;
 392 +       struct resource *gpiores, *padres;
 393 +       int irq;
 394 +
 395 +       if (pdev->id >= MAX_PORTS)
 396 +               return -ENODEV;
 397 +
 398 +       gpiores = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 399 +       padres = platform_get_resource(pdev, IORESOURCE_MEM, 1);
 400 +       irq = platform_get_irq(pdev, 0);
 401 +       if (!gpiores || !padres)
 402 +               return -ENODEV;
 403 +
 404 +       gpio_port = &ltq_gpio_port[pdev->id];
 405 +       gpio_port->gpio_chip.label = "falcon-gpio";
 406 +       gpio_port->gpio_chip.direction_input = falcon_gpio_direction_input;
 407 +       gpio_port->gpio_chip.direction_output = falcon_gpio_direction_output;
 408 +       gpio_port->gpio_chip.get = falcon_gpio_get;
 409 +       gpio_port->gpio_chip.set = falcon_gpio_set;
 410 +       gpio_port->gpio_chip.request = falcon_gpio_request;
 411 +       gpio_port->gpio_chip.free = falcon_gpio_free;
 412 +       gpio_port->gpio_chip.base = 100 * pdev->id;
 413 +       gpio_port->gpio_chip.ngpio = 32;
 414 +       gpio_port->gpio_chip.dev = &pdev->dev;
 415 +
 416 +       gpio_port->port = ltq_remap_resource(gpiores);
 417 +       gpio_port->pad = ltq_remap_resource(padres);
 418 +
 419 +       if (!gpio_port->port || !gpio_port->pad) {
 420 +               dev_err(&pdev->dev, "Could not map io ranges\n");
 421 +               ret = -ENOMEM;
 422 +               goto err;
 423 +       }
 424 +
 425 +       if (irq > 0) {
 426 +               /* irq_chip support */
 427 +               gpio_port->gpio_chip.to_irq = falcon_gpio_to_irq;
 428 +               gpio_port->irq_base = INT_NUM_EXTRA_START + (32 * pdev->id);
 429 +
 430 +               for (i = 0; i < 32; i++) {
 431 +                       irq_set_chip_and_handler_name(gpio_port->irq_base + i,
 432 +                               &falcon_gpio_irq_chip, handle_simple_irq,
 433 +                               "mux");
 434 +                       irq_set_chip_data(gpio_port->irq_base + i, gpio_port);
 435 +                       /* set to negative logic (falling edge, low level) */
 436 +                       ltq_port_w32_mask(gpio_port, 0, 1 << i,
 437 +                               LTQ_GPIO_EXINTCR0);
 438 +               }
 439 +
 440 +               gpio_port->chained_irq = irq;
 441 +               setup_irq(irq, &gpio_cascade);
 442 +               irq_set_handler_data(irq, gpio_port);
 443 +               irq_set_chained_handler(irq, falcon_gpio_irq_handler);
 444 +       }
 445 +
 446 +       ret = gpiochip_add(&gpio_port->gpio_chip);
 447 +       if (ret < 0) {
 448 +               dev_err(&pdev->dev, "Could not register gpiochip %d, %d\n",
 449 +                       pdev->id, ret);
 450 +               goto err;
 451 +       }
 452 +       platform_set_drvdata(pdev, gpio_port);
 453 +       return ret;
 454 +
 455 +err:
 456 +       dev_err(&pdev->dev, "Error in gpio_probe %d, %d\n", pdev->id, ret);
 457 +       if (gpiores)
 458 +               release_resource(gpiores);
 459 +       if (padres)
 460 +               release_resource(padres);
 461 +
 462 +       if (gpio_port->port)
 463 +               iounmap(gpio_port->port);
 464 +       if (gpio_port->pad)
 465 +               iounmap(gpio_port->pad);
 466 +       return ret;
 467 +}
 468 +
 469 +static struct platform_driver falcon_gpio_driver = {
 470 +       .probe = falcon_gpio_probe,
 471 +       .driver = {
 472 +               .name = "falcon_gpio",
 473 +               .owner = THIS_MODULE,
 474 +       },
 475 +};
 476 +
 477 +int __init
 478 +falcon_gpio_init(void)
 479 +{
 480 +       int ret;
 481 +
 482 +       pr_info("FALC(tm) ON GPIO Driver, (C) 2011 Lantiq Deutschland Gmbh\n");
 483 +       ret = platform_driver_register(&falcon_gpio_driver);
 484 +       if (ret)
 485 +               pr_err("falcon_gpio: Error registering platform driver!");
 486 +       return ret;
 487 +}
 488 +
 489 +postcore_initcall(falcon_gpio_init);