1 From 06663beb0230c02d1962eca8d9f6709c2e852328 Mon Sep 17 00:00:00 2001
2 From: John Crispin <blogic@openwrt.org>
3 Date: Wed, 21 Mar 2012 18:14:06 +0100
4 Subject: [PATCH 44/70] MIPS: NET: several fixes to etop driver
7 drivers/net/ethernet/lantiq_etop.c | 208 +++++++++++++++++++-----------------
8 1 files changed, 108 insertions(+), 100 deletions(-)
10 --- a/drivers/net/ethernet/lantiq_etop.c
11 +++ b/drivers/net/ethernet/lantiq_etop.c
13 /* the newer xway socks have a embedded 3/7 port gbit multiplexer */
14 #define ltq_has_gbit() (ltq_is_ar9() || ltq_is_vr9())
16 -/* use 2 static channels for TX/RX
17 - depending on the SoC we need to use different DMA channels for ethernet */
18 -#define LTQ_ETOP_TX_CHANNEL 1
19 -#define LTQ_ETOP_RX_CHANNEL ((ltq_is_ase()) ? (5) : \
20 - ((ltq_has_gbit()) ? (0) : (6)))
22 -#define IS_TX(x) (x == LTQ_ETOP_TX_CHANNEL)
23 -#define IS_RX(x) (x == LTQ_ETOP_RX_CHANNEL)
25 #define ltq_etop_r32(x) ltq_r32(ltq_etop_membase + (x))
26 #define ltq_etop_w32(x, y) ltq_w32(x, ltq_etop_membase + (y))
27 #define ltq_etop_w32_mask(x, y, z) \
28 @@ -128,8 +119,8 @@ static void __iomem *ltq_etop_membase;
29 static void __iomem *ltq_gbit_membase;
31 struct ltq_etop_chan {
35 struct net_device *netdev;
36 struct napi_struct napi;
37 struct ltq_dma_channel dma;
38 @@ -144,8 +135,8 @@ struct ltq_etop_priv {
39 struct mii_bus *mii_bus;
40 struct phy_device *phydev;
42 - struct ltq_etop_chan ch[MAX_DMA_CHAN];
43 - int tx_free[MAX_DMA_CHAN >> 1];
44 + struct ltq_etop_chan txch;
45 + struct ltq_etop_chan rxch;
49 @@ -206,8 +197,10 @@ ltq_etop_poll_rx(struct napi_struct *nap
51 struct ltq_etop_chan *ch = container_of(napi,
52 struct ltq_etop_chan, napi);
53 + struct ltq_etop_priv *priv = netdev_priv(ch->netdev);
56 + unsigned long flags;
58 while ((rx < budget) && !complete) {
59 struct ltq_dma_desc *desc = &ch->dma.desc_base[ch->dma.desc];
60 @@ -221,7 +214,9 @@ ltq_etop_poll_rx(struct napi_struct *nap
62 if (complete || !rx) {
63 napi_complete(&ch->napi);
64 + spin_lock_irqsave(&priv->lock, flags);
65 ltq_dma_ack_irq(&ch->dma);
66 + spin_unlock_irqrestore(&priv->lock, flags);
70 @@ -233,7 +228,7 @@ ltq_etop_poll_tx(struct napi_struct *nap
71 container_of(napi, struct ltq_etop_chan, napi);
72 struct ltq_etop_priv *priv = netdev_priv(ch->netdev);
73 struct netdev_queue *txq =
74 - netdev_get_tx_queue(ch->netdev, ch->idx >> 1);
75 + netdev_get_tx_queue(ch->netdev, ch->dma.nr >> 1);
78 spin_lock_irqsave(&priv->lock, flags);
79 @@ -251,7 +246,9 @@ ltq_etop_poll_tx(struct napi_struct *nap
80 if (netif_tx_queue_stopped(txq))
81 netif_tx_start_queue(txq);
82 napi_complete(&ch->napi);
83 + spin_lock_irqsave(&priv->lock, flags);
84 ltq_dma_ack_irq(&ch->dma);
85 + spin_unlock_irqrestore(&priv->lock, flags);
89 @@ -259,9 +256,10 @@ static irqreturn_t
90 ltq_etop_dma_irq(int irq, void *_priv)
92 struct ltq_etop_priv *priv = _priv;
93 - int ch = irq - LTQ_DMA_ETOP;
95 - napi_schedule(&priv->ch[ch].napi);
96 + if (irq == priv->txch.dma.irq)
97 + napi_schedule(&priv->txch.napi);
99 + napi_schedule(&priv->rxch.napi);
103 @@ -273,7 +271,7 @@ ltq_etop_free_channel(struct net_device
104 ltq_dma_free(&ch->dma);
106 free_irq(ch->dma.irq, priv);
107 - if (IS_RX(ch->idx)) {
108 + if (ch == &priv->txch) {
110 for (desc = 0; desc < LTQ_DESC_NUM; desc++)
111 dev_kfree_skb_any(ch->skb[ch->dma.desc]);
112 @@ -284,7 +282,6 @@ static void
113 ltq_etop_hw_exit(struct net_device *dev)
115 struct ltq_etop_priv *priv = netdev_priv(dev);
118 clk_disable(priv->clk_ppe);
120 @@ -296,9 +293,8 @@ ltq_etop_hw_exit(struct net_device *dev)
121 clk_disable(priv->clk_ephycgu);
124 - for (i = 0; i < MAX_DMA_CHAN; i++)
125 - if (IS_TX(i) || IS_RX(i))
126 - ltq_etop_free_channel(dev, &priv->ch[i]);
127 + ltq_etop_free_channel(dev, &priv->txch);
128 + ltq_etop_free_channel(dev, &priv->rxch);
132 @@ -326,8 +322,6 @@ ltq_etop_hw_init(struct net_device *dev)
134 struct ltq_etop_priv *priv = netdev_priv(dev);
135 unsigned int mii_mode = priv->pldata->mii_mode;
139 clk_enable(priv->clk_ppe);
141 @@ -369,31 +363,50 @@ ltq_etop_hw_init(struct net_device *dev)
142 /* enable crc generation */
143 ltq_etop_w32(PPE32_CGEN, LQ_PPE32_ENET_MAC_CFG);
149 +ltq_etop_dma_init(struct net_device *dev)
151 + struct ltq_etop_priv *priv = netdev_priv(dev);
153 + int rx = ((ltq_is_ase()) ? (5) : \
154 + ((ltq_is_ar9()) ? (0) : (6)));
155 + int tx_irq = LTQ_DMA_ETOP + tx;
156 + int rx_irq = LTQ_DMA_ETOP + rx;
159 ltq_dma_init_port(DMA_PORT_ETOP);
161 - for (i = 0; i < MAX_DMA_CHAN && !err; i++) {
162 - int irq = LTQ_DMA_ETOP + i;
163 - struct ltq_etop_chan *ch = &priv->ch[i];
165 - ch->idx = ch->dma.nr = i;
168 - ltq_dma_alloc_tx(&ch->dma);
169 - err = request_irq(irq, ltq_etop_dma_irq, IRQF_DISABLED,
171 - } else if (IS_RX(i)) {
172 - ltq_dma_alloc_rx(&ch->dma);
173 - for (ch->dma.desc = 0; ch->dma.desc < LTQ_DESC_NUM;
175 - if (ltq_etop_alloc_skb(ch))
178 - err = request_irq(irq, ltq_etop_dma_irq, IRQF_DISABLED,
180 + priv->txch.dma.nr = tx;
181 + ltq_dma_alloc_tx(&priv->txch.dma);
182 + err = request_irq(tx_irq, ltq_etop_dma_irq, IRQF_DISABLED,
185 + netdev_err(dev, "failed to allocate tx irq\n");
188 + priv->txch.dma.irq = tx_irq;
190 + priv->rxch.dma.nr = rx;
191 + ltq_dma_alloc_rx(&priv->rxch.dma);
192 + for (priv->rxch.dma.desc = 0; priv->rxch.dma.desc < LTQ_DESC_NUM;
193 + priv->rxch.dma.desc++) {
194 + if (ltq_etop_alloc_skb(&priv->rxch)) {
195 + netdev_err(dev, "failed to allocate skbs\n");
202 + priv->rxch.dma.desc = 0;
203 + err = request_irq(rx_irq, ltq_etop_dma_irq, IRQF_DISABLED,
206 + netdev_err(dev, "failed to allocate rx irq\n");
208 + priv->rxch.dma.irq = rx_irq;
213 @@ -410,7 +423,10 @@ ltq_etop_get_settings(struct net_device
215 struct ltq_etop_priv *priv = netdev_priv(dev);
217 - return phy_ethtool_gset(priv->phydev, cmd);
219 + return phy_ethtool_gset(priv->phydev, cmd);
225 @@ -418,7 +434,10 @@ ltq_etop_set_settings(struct net_device
227 struct ltq_etop_priv *priv = netdev_priv(dev);
229 - return phy_ethtool_sset(priv->phydev, cmd);
231 + return phy_ethtool_sset(priv->phydev, cmd);
237 @@ -426,7 +445,10 @@ ltq_etop_nway_reset(struct net_device *d
239 struct ltq_etop_priv *priv = netdev_priv(dev);
241 - return phy_start_aneg(priv->phydev);
243 + return phy_start_aneg(priv->phydev);
248 static const struct ethtool_ops ltq_etop_ethtool_ops = {
249 @@ -618,18 +640,19 @@ static int
250 ltq_etop_open(struct net_device *dev)
252 struct ltq_etop_priv *priv = netdev_priv(dev);
254 + unsigned long flags;
256 - for (i = 0; i < MAX_DMA_CHAN; i++) {
257 - struct ltq_etop_chan *ch = &priv->ch[i];
258 + napi_enable(&priv->txch.napi);
259 + napi_enable(&priv->rxch.napi);
261 + spin_lock_irqsave(&priv->lock, flags);
262 + ltq_dma_open(&priv->txch.dma);
263 + ltq_dma_open(&priv->rxch.dma);
264 + spin_unlock_irqrestore(&priv->lock, flags);
266 - if (!IS_TX(i) && (!IS_RX(i)))
268 - ltq_dma_open(&ch->dma);
269 - napi_enable(&ch->napi);
272 phy_start(priv->phydev);
274 netif_tx_start_all_queues(dev);
277 @@ -638,19 +661,19 @@ static int
278 ltq_etop_stop(struct net_device *dev)
280 struct ltq_etop_priv *priv = netdev_priv(dev);
282 + unsigned long flags;
284 netif_tx_stop_all_queues(dev);
286 phy_stop(priv->phydev);
287 - for (i = 0; i < MAX_DMA_CHAN; i++) {
288 - struct ltq_etop_chan *ch = &priv->ch[i];
289 + napi_disable(&priv->txch.napi);
290 + napi_disable(&priv->rxch.napi);
292 + spin_lock_irqsave(&priv->lock, flags);
293 + ltq_dma_close(&priv->txch.dma);
294 + ltq_dma_close(&priv->rxch.dma);
295 + spin_unlock_irqrestore(&priv->lock, flags);
297 - if (!IS_RX(i) && !IS_TX(i))
299 - napi_disable(&ch->napi);
300 - ltq_dma_close(&ch->dma);
305 @@ -660,16 +683,16 @@ ltq_etop_tx(struct sk_buff *skb, struct
306 int queue = skb_get_queue_mapping(skb);
307 struct netdev_queue *txq = netdev_get_tx_queue(dev, queue);
308 struct ltq_etop_priv *priv = netdev_priv(dev);
309 - struct ltq_etop_chan *ch = &priv->ch[(queue << 1) | 1];
310 - struct ltq_dma_desc *desc = &ch->dma.desc_base[ch->dma.desc];
311 + struct ltq_dma_desc *desc =
312 + &priv->txch.dma.desc_base[priv->txch.dma.desc];
317 len = skb->len < ETH_ZLEN ? ETH_ZLEN : skb->len;
319 - if ((desc->ctl & (LTQ_DMA_OWN | LTQ_DMA_C)) || ch->skb[ch->dma.desc]) {
320 - dev_kfree_skb_any(skb);
321 + if ((desc->ctl & (LTQ_DMA_OWN | LTQ_DMA_C)) ||
322 + priv->txch.skb[priv->txch.dma.desc]) {
323 netdev_err(dev, "tx ring full\n");
324 netif_tx_stop_queue(txq);
325 return NETDEV_TX_BUSY;
326 @@ -677,7 +700,7 @@ ltq_etop_tx(struct sk_buff *skb, struct
328 /* dma needs to start on a 16 byte aligned address */
329 byte_offset = CPHYSADDR(skb->data) % 16;
330 - ch->skb[ch->dma.desc] = skb;
331 + priv->txch.skb[priv->txch.dma.desc] = skb;
333 dev->trans_start = jiffies;
335 @@ -687,11 +710,11 @@ ltq_etop_tx(struct sk_buff *skb, struct
337 desc->ctl = LTQ_DMA_OWN | LTQ_DMA_SOP | LTQ_DMA_EOP |
338 LTQ_DMA_TX_OFFSET(byte_offset) | (len & LTQ_DMA_SIZE_MASK);
340 - ch->dma.desc %= LTQ_DESC_NUM;
341 + priv->txch.dma.desc++;
342 + priv->txch.dma.desc %= LTQ_DESC_NUM;
343 spin_unlock_irqrestore(&priv->lock, flags);
345 - if (ch->dma.desc_base[ch->dma.desc].ctl & LTQ_DMA_OWN)
346 + if (priv->txch.dma.desc_base[priv->txch.dma.desc].ctl & LTQ_DMA_OWN)
347 netif_tx_stop_queue(txq);
350 @@ -776,6 +799,10 @@ ltq_etop_init(struct net_device *dev)
351 err = ltq_etop_hw_init(dev);
354 + err = ltq_etop_dma_init(dev);
358 ltq_etop_change_mtu(dev, 1500);
360 memcpy(&mac, &priv->pldata->mac, sizeof(struct sockaddr));
361 @@ -811,6 +838,9 @@ ltq_etop_tx_timeout(struct net_device *d
362 err = ltq_etop_hw_init(dev);
365 + err = ltq_etop_dma_init(dev);
368 dev->trans_start = jiffies;
369 netif_wake_queue(dev);
371 @@ -834,14 +864,13 @@ static const struct net_device_ops ltq_e
372 .ndo_tx_timeout = ltq_etop_tx_timeout,
376 +static int __devinit
377 ltq_etop_probe(struct platform_device *pdev)
379 struct net_device *dev;
380 struct ltq_etop_priv *priv;
381 struct resource *res, *gbit_res;
385 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
387 @@ -917,15 +946,10 @@ ltq_etop_probe(struct platform_device *p
389 spin_lock_init(&priv->lock);
391 - for (i = 0; i < MAX_DMA_CHAN; i++) {
393 - netif_napi_add(dev, &priv->ch[i].napi,
394 - ltq_etop_poll_tx, 8);
396 - netif_napi_add(dev, &priv->ch[i].napi,
397 - ltq_etop_poll_rx, 32);
398 - priv->ch[i].netdev = dev;
400 + netif_napi_add(dev, &priv->txch.napi, ltq_etop_poll_tx, 8);
401 + netif_napi_add(dev, &priv->rxch.napi, ltq_etop_poll_rx, 32);
402 + priv->txch.netdev = dev;
403 + priv->rxch.netdev = dev;
405 err = register_netdev(dev);
407 @@ -955,6 +979,7 @@ ltq_etop_remove(struct platform_device *
410 static struct platform_driver ltq_mii_driver = {
411 + .probe = ltq_etop_probe,
412 .remove = __devexit_p(ltq_etop_remove),
415 @@ -962,24 +987,7 @@ static struct platform_driver ltq_mii_dr
422 - int ret = platform_driver_probe(<q_mii_driver, ltq_etop_probe);
425 - pr_err("ltq_etop: Error registering platfom driver!");
432 - platform_driver_unregister(<q_mii_driver);
435 -module_init(init_ltq_etop);
436 -module_exit(exit_ltq_etop);
437 +module_platform_driver(ltq_mii_driver);
439 MODULE_AUTHOR("John Crispin <blogic@openwrt.org>");
440 MODULE_DESCRIPTION("Lantiq SoC ETOP");