target/linux/lantiq/patches-3.2/0062-MIPS-cleanup-reset-code.patch

   1 From 1748dc7b4974109040d0249ac1fc322c120eb528 Mon Sep 17 00:00:00 2001
   2 From: John Crispin <blogic@openwrt.org>
   3 Date: Fri, 16 Mar 2012 15:49:32 +0100
   4 Subject: [PATCH 62/70] MIPS: cleanup reset code
   5
   6 ---
   7  arch/mips/lantiq/xway/reset.c |   59 ++++++++++++++++++++++++++++++++++------
   8  1 files changed, 50 insertions(+), 9 deletions(-)
   9
  10 --- a/arch/mips/lantiq/xway/reset.c
  11 +++ b/arch/mips/lantiq/xway/reset.c
  12 @@ -11,6 +11,7 @@
  13  #include <linux/ioport.h>
  14  #include <linux/pm.h>
  15  #include <linux/export.h>
  16 +#include <linux/delay.h>
  17  #include <asm/reboot.h>
  18
  19  #include <lantiq_soc.h>
  20 @@ -20,12 +21,45 @@
  21  #define ltq_rcu_w32(x, y)      ltq_w32((x), ltq_rcu_membase + (y))
  22  #define ltq_rcu_r32(x)         ltq_r32(ltq_rcu_membase + (x))
  23
  24 -/* register definitions */
  25 -#define LTQ_RCU_RST            0x0010
  26 -#define LTQ_RCU_RST_ALL                0x40000000
  27 -
  28 -#define LTQ_RCU_RST_STAT       0x0014
  29 -#define LTQ_RCU_STAT_SHIFT     26
  30 +/* reset request register */
  31 +#define RCU_RST_REQ    0x0010
  32 +/* reset status register */
  33 +#define RCU_RST_STAT   0x0014
  34 +
  35 +/* reset cause */
  36 +#define RCU_STAT_SHIFT 26
  37 +/* Global SW Reset */
  38 +#define RCU_RD_SRST            BIT(30)
  39 +/* Memory Controller */
  40 +#define RCU_RD_MC              BIT(14)
  41 +/* PCI core */
  42 +#define RCU_RD_PCI             BIT(13)
  43 +/* Voice DFE/AFE */
  44 +#define RCU_RD_DFE_AFE         BIT(12)
  45 +/* DSL AFE */
  46 +#define RCU_RD_DSL_AFE         BIT(11)
  47 +/* SDIO core */
  48 +#define RCU_RD_SDIO            BIT(10)
  49 +/* DMA core */
  50 +#define RCU_RD_DMA             BIT(9)
  51 +/* PPE core */
  52 +#define RCU_RD_PPE             BIT(8)
  53 +/* ARC/DFE core */
  54 +#define RCU_RD_ARC_DFE         BIT(7)
  55 +/* AHB bus */
  56 +#define RCU_RD_AHB             BIT(6)
  57 +/* Ethernet MAC1 */
  58 +#define RCU_RD_ENET_MAC1       BIT(5)
  59 +/* USB and Phy core */
  60 +#define RCU_RD_USB             BIT(4)
  61 +/* CPU1 subsystem */
  62 +#define RCU_RD_CPU1            BIT(3)
  63 +/* FPI bus */
  64 +#define RCU_RD_FPI             BIT(2)
  65 +/* CPU0 subsystem */
  66 +#define RCU_RD_CPU0            BIT(1)
  67 +/* HW reset via HRST pin */
  68 +#define RCU_RD_HRST            BIT(0)
  69
  70  static struct resource ltq_rcu_resource =
  71         MEM_RES("rcu", LTQ_RCU_BASE_ADDR, LTQ_RCU_SIZE);
  72 @@ -36,16 +70,23 @@ static void __iomem *ltq_rcu_membase;
  73  /* This function is used by the watchdog driver */
  74  int ltq_reset_cause(void)
  75  {
  76 -       u32 val = ltq_rcu_r32(LTQ_RCU_RST_STAT);
  77 -       return val >> LTQ_RCU_STAT_SHIFT;
  78 +       u32 val = ltq_rcu_r32(RCU_RST_STAT);
  79 +       return val >> RCU_STAT_SHIFT;
  80  }
  81  EXPORT_SYMBOL_GPL(ltq_reset_cause);
  82
  83 +void ltq_reset_once(unsigned int module, ulong usec)
  84 +{
  85 +       ltq_rcu_w32(ltq_rcu_r32(RCU_RST_REQ) | module, RCU_RST_REQ);
  86 +       udelay(usec);
  87 +       ltq_rcu_w32(ltq_rcu_r32(RCU_RST_REQ) & ~module, RCU_RST_REQ);
  88 +}
  89 +
  90  static void ltq_machine_restart(char *command)
  91  {
  92         pr_notice("System restart\n");
  93         local_irq_disable();
  94 -       ltq_rcu_w32(ltq_rcu_r32(LTQ_RCU_RST) | LTQ_RCU_RST_ALL, LTQ_RCU_RST);
  95 +       ltq_rcu_w32(ltq_rcu_r32(RCU_RST_REQ) | RCU_RD_SRST, RCU_RST_REQ);
  96         unreachable();
  97  }
  98