package/ltq-dsl/src/ifxmips_atm_ppe_danube.h

   1 #ifndef IFXMIPS_ATM_PPE_DANUBE_H
   2 #define IFXMIPS_ATM_PPE_DANUBE_H
   3
   4 #include <lantiq.h>
   5
   6 /*
   7  *  FPI Configuration Bus Register and Memory Address Mapping
   8  */
   9 #define IFX_PPE                         (KSEG1 | 0x1E180000)
  10 #define PP32_DEBUG_REG_ADDR(i, x)       ((volatile unsigned int*)(IFX_PPE + (((x) + 0x0000) << 2)))
  11 #define PPM_INT_REG_ADDR(i, x)          ((volatile unsigned int*)(IFX_PPE + (((x) + 0x0030) << 2)))
  12 #define PP32_INTERNAL_RES_ADDR(i, x)    ((volatile unsigned int*)(IFX_PPE + (((x) + 0x0040) << 2)))
  13 #define CDM_CODE_MEMORY(i, x)           ((volatile unsigned int*)(IFX_PPE + (((x) + 0x1000) << 2)))
  14 #define PPE_REG_ADDR(x)                 ((volatile unsigned int*)(IFX_PPE + (((x) + 0x4000) << 2)))
  15 #define CDM_DATA_MEMORY(i, x)           ((volatile unsigned int*)(IFX_PPE + (((x) + 0x5000) << 2)))
  16 #define PPM_INT_UNIT_ADDR(x)            ((volatile unsigned int*)(IFX_PPE + (((x) + 0x6000) << 2)))
  17 #define PPM_TIMER0_ADDR(x)              ((volatile unsigned int*)(IFX_PPE + (((x) + 0x6100) << 2)))
  18 #define PPM_TASK_IND_REG_ADDR(x)        ((volatile unsigned int*)(IFX_PPE + (((x) + 0x6200) << 2)))
  19 #define PPS_BRK_ADDR(x)                 ((volatile unsigned int*)(IFX_PPE + (((x) + 0x6300) << 2)))
  20 #define PPM_TIMER1_ADDR(x)              ((volatile unsigned int*)(IFX_PPE + (((x) + 0x6400) << 2)))
  21 #define SB_RAM0_ADDR(x)                 ((volatile unsigned int*)(IFX_PPE + (((x) + 0x8000) << 2)))
  22 #define SB_RAM1_ADDR(x)                 ((volatile unsigned int*)(IFX_PPE + (((x) + 0x8400) << 2)))
  23 #define SB_RAM2_ADDR(x)                 ((volatile unsigned int*)(IFX_PPE + (((x) + 0x8C00) << 2)))
  24 #define SB_RAM3_ADDR(x)                 ((volatile unsigned int*)(IFX_PPE + (((x) + 0x9600) << 2)))
  25 #define QSB_CONF_REG_ADDR(x)            ((volatile unsigned int*)(IFX_PPE + (((x) + 0xC000) << 2)))
  26
  27 /*
  28  *  DWORD-Length of Memory Blocks
  29  */
  30 #define PP32_DEBUG_REG_DWLEN            0x0030
  31 #define PPM_INT_REG_DWLEN               0x0010
  32 #define PP32_INTERNAL_RES_DWLEN         0x00C0
  33 #define CDM_CODE_MEMORYn_DWLEN(n)       ((n) == 0 ? 0x1000 : 0x0800)
  34 #define PPE_REG_DWLEN                   0x1000
  35 #define CDM_DATA_MEMORY_DWLEN           CDM_CODE_MEMORYn_DWLEN(1)
  36 #define PPM_INT_UNIT_DWLEN              0x0100
  37 #define PPM_TIMER0_DWLEN                0x0100
  38 #define PPM_TASK_IND_REG_DWLEN          0x0100
  39 #define PPS_BRK_DWLEN                   0x0100
  40 #define PPM_TIMER1_DWLEN                0x0100
  41 #define SB_RAM0_DWLEN                   0x0400
  42 #define SB_RAM1_DWLEN                   0x0800
  43 #define SB_RAM2_DWLEN                   0x0A00
  44 #define SB_RAM3_DWLEN                   0x0400
  45 #define QSB_CONF_REG_DWLEN              0x0100
  46
  47 /*
  48  *  PP32 to FPI Address Mapping
  49  */
  50 #define SB_BUFFER(__sb_addr)            ((volatile unsigned int *)((((__sb_addr) >= 0x2000) && ((__sb_addr) <= 0x23FF)) ? SB_RAM0_ADDR((__sb_addr) - 0x2000) :   \
  51                                                                    (((__sb_addr) >= 0x2400) && ((__sb_addr) <= 0x2BFF)) ? SB_RAM1_ADDR((__sb_addr) - 0x2400) :   \
  52                                                                    (((__sb_addr) >= 0x2C00) && ((__sb_addr) <= 0x35FF)) ? SB_RAM2_ADDR((__sb_addr) - 0x2C00) :   \
  53                                                                    (((__sb_addr) >= 0x3600) && ((__sb_addr) <= 0x39FF)) ? SB_RAM3_ADDR((__sb_addr) - 0x3600) :   \
  54                                                                 0))
  55
  56 /*
  57  *  PP32 Debug Control Register
  58  */
  59 #define PP32_DBG_CTRL                   PP32_DEBUG_REG_ADDR(0, 0x0000)
  60
  61 #define DBG_CTRL_START_SET(value)       ((value) ? (1 << 0) : 0)
  62 #define DBG_CTRL_STOP_SET(value)        ((value) ? (1 << 1) : 0)
  63 #define DBG_CTRL_STEP_SET(value)        ((value) ? (1 << 2) : 0)
  64
  65 #define PP32_HALT_STAT                  PP32_DEBUG_REG_ADDR(0, 0x0001)
  66
  67 #define PP32_BRK_SRC                    PP32_DEBUG_REG_ADDR(0, 0x0002)
  68
  69 #define PP32_DBG_PC_MIN(i)              PP32_DEBUG_REG_ADDR(0, 0x0010 + (i))
  70 #define PP32_DBG_PC_MAX(i)              PP32_DEBUG_REG_ADDR(0, 0x0014 + (i))
  71 #define PP32_DBG_DATA_MIN(i)            PP32_DEBUG_REG_ADDR(0, 0x0018 + (i))
  72 #define PP32_DBG_DATA_MAX(i)            PP32_DEBUG_REG_ADDR(0, 0x001A + (i))
  73 #define PP32_DBG_DATA_VAL(i)            PP32_DEBUG_REG_ADDR(0, 0x001C + (i))
  74
  75 #define PP32_DBG_CUR_PC                 PP32_DEBUG_REG_ADDR(0, 0x0080)
  76
  77 #define PP32_DBG_TASK_NO                PP32_DEBUG_REG_ADDR(0, 0x0081)
  78
  79 /*
  80  *  EMA Registers
  81  */
  82 #define EMA_CMDCFG                      PPE_REG_ADDR(0x0A00)
  83 #define EMA_DATACFG                     PPE_REG_ADDR(0x0A01)
  84 #define EMA_CMDCNT                      PPE_REG_ADDR(0x0A02)
  85 #define EMA_DATACNT                     PPE_REG_ADDR(0x0A03)
  86 #define EMA_ISR                         PPE_REG_ADDR(0x0A04)
  87 #define EMA_IER                         PPE_REG_ADDR(0x0A05)
  88 #define EMA_CFG                         PPE_REG_ADDR(0x0A06)
  89 #define EMA_SUBID                       PPE_REG_ADDR(0x0A07)
  90
  91 #define EMA_ALIGNMENT                   4
  92
  93 /*
  94  *  Mailbox IGU1 Interrupt
  95  */
  96 #define PPE_MAILBOX_IGU1_INT            LQ_PPE_MBOX_INT
  97
  98
  99
 100 #endif  //  IFXMIPS_ATM_PPE_DANUBE_H