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[adm5120] generate firmware images for the CAS-700/771/790/861 devices
[openwrt.git] / target / linux / brcm47xx / patches-2.6.23 / 120-b44_ssb_support.patch
1 Index: linux-2.6.23/drivers/net/b44.c
2 ===================================================================
3 --- linux-2.6.23.orig/drivers/net/b44.c 2007-10-13 10:58:27.872607266 +0200
4 +++ linux-2.6.23/drivers/net/b44.c 2007-10-13 11:00:46.916530927 +0200
5 @@ -1,7 +1,9 @@
6 -/* b44.c: Broadcom 4400 device driver.
7 +/* b44.c: Broadcom 4400/47xx device driver.
8 *
9 * Copyright (C) 2002 David S. Miller (davem@redhat.com)
10 - * Fixed by Pekka Pietikainen (pp@ee.oulu.fi)
11 + * Copyright (C) 2004 Pekka Pietikainen (pp@ee.oulu.fi)
12 + * Copyright (C) 2004 Florian Schirmer (jolt@tuxbox.org)
13 + * Copyright (C) 2006 Felix Fietkau (nbd@openwrt.org)
14 * Copyright (C) 2006 Broadcom Corporation.
15 *
16 * Distribute under GPL.
17 @@ -21,11 +23,13 @@
18 #include <linux/delay.h>
19 #include <linux/init.h>
20 #include <linux/dma-mapping.h>
21 +#include <linux/ssb/ssb.h>
22
23 #include <asm/uaccess.h>
24 #include <asm/io.h>
25 #include <asm/irq.h>
26
27 +
28 #include "b44.h"
29
30 #define DRV_MODULE_NAME "b44"
31 @@ -87,8 +91,8 @@
32 static char version[] __devinitdata =
33 DRV_MODULE_NAME ".c:v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
34
35 -MODULE_AUTHOR("Florian Schirmer, Pekka Pietikainen, David S. Miller");
36 -MODULE_DESCRIPTION("Broadcom 4400 10/100 PCI ethernet driver");
37 +MODULE_AUTHOR("Felix Fietkau, Florian Schirmer, Pekka Pietikainen, David S. Miller");
38 +MODULE_DESCRIPTION("Broadcom 4400/47xx 10/100 PCI ethernet driver");
39 MODULE_LICENSE("GPL");
40 MODULE_VERSION(DRV_MODULE_VERSION);
41
42 @@ -96,18 +100,11 @@
43 module_param(b44_debug, int, 0);
44 MODULE_PARM_DESC(b44_debug, "B44 bitmapped debugging message enable value");
45
46 -static struct pci_device_id b44_pci_tbl[] = {
47 - { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_BCM4401,
48 - PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
49 - { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_BCM4401B0,
50 - PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
51 - { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_BCM4401B1,
52 - PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
53 - { } /* terminate list with empty entry */
54 +static struct ssb_device_id b44_ssb_tbl[] = {
55 + SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_ETHERNET, SSB_ANY_REV),
56 + SSB_DEVTABLE_END
57 };
58
59 -MODULE_DEVICE_TABLE(pci, b44_pci_tbl);
60 -
61 static void b44_halt(struct b44 *);
62 static void b44_init_rings(struct b44 *);
63
64 @@ -119,6 +116,7 @@
65
66 static int dma_desc_align_mask;
67 static int dma_desc_sync_size;
68 +static int instance;
69
70 static const char b44_gstrings[][ETH_GSTRING_LEN] = {
71 #define _B44(x...) # x,
72 @@ -126,35 +124,24 @@
73 #undef _B44
74 };
75
76 -static inline void b44_sync_dma_desc_for_device(struct pci_dev *pdev,
77 - dma_addr_t dma_base,
78 - unsigned long offset,
79 - enum dma_data_direction dir)
80 -{
81 - dma_sync_single_range_for_device(&pdev->dev, dma_base,
82 - offset & dma_desc_align_mask,
83 - dma_desc_sync_size, dir);
84 -}
85 -
86 -static inline void b44_sync_dma_desc_for_cpu(struct pci_dev *pdev,
87 - dma_addr_t dma_base,
88 - unsigned long offset,
89 - enum dma_data_direction dir)
90 -{
91 - dma_sync_single_range_for_cpu(&pdev->dev, dma_base,
92 - offset & dma_desc_align_mask,
93 - dma_desc_sync_size, dir);
94 -}
95 -
96 -static inline unsigned long br32(const struct b44 *bp, unsigned long reg)
97 -{
98 - return readl(bp->regs + reg);
99 -}
100 -
101 -static inline void bw32(const struct b44 *bp,
102 - unsigned long reg, unsigned long val)
103 -{
104 - writel(val, bp->regs + reg);
105 +static inline void b44_sync_dma_desc_for_device(struct ssb_device *sdev,
106 + dma_addr_t dma_base,
107 + unsigned long offset,
108 + enum dma_data_direction dir)
109 +{
110 + dma_sync_single_range_for_device(sdev->dev, dma_base,
111 + offset & dma_desc_align_mask,
112 + dma_desc_sync_size, dir);
113 +}
114 +
115 +static inline void b44_sync_dma_desc_for_cpu(struct ssb_device *sdev,
116 + dma_addr_t dma_base,
117 + unsigned long offset,
118 + enum dma_data_direction dir)
119 +{
120 + dma_sync_single_range_for_cpu(sdev->dev, dma_base,
121 + offset & dma_desc_align_mask,
122 + dma_desc_sync_size, dir);
123 }
124
125 static int b44_wait_bit(struct b44 *bp, unsigned long reg,
126 @@ -182,117 +169,29 @@
127 return 0;
128 }
129
130 -/* Sonics SiliconBackplane support routines. ROFL, you should see all the
131 - * buzz words used on this company's website :-)
132 - *
133 - * All of these routines must be invoked with bp->lock held and
134 - * interrupts disabled.
135 - */
136 -
137 -#define SB_PCI_DMA 0x40000000 /* Client Mode PCI memory access space (1 GB) */
138 -#define BCM4400_PCI_CORE_ADDR 0x18002000 /* Address of PCI core on BCM4400 cards */
139 -
140 -static u32 ssb_get_core_rev(struct b44 *bp)
141 -{
142 - return (br32(bp, B44_SBIDHIGH) & SBIDHIGH_RC_MASK);
143 -}
144 -
145 -static u32 ssb_pci_setup(struct b44 *bp, u32 cores)
146 -{
147 - u32 bar_orig, pci_rev, val;
148 -
149 - pci_read_config_dword(bp->pdev, SSB_BAR0_WIN, &bar_orig);
150 - pci_write_config_dword(bp->pdev, SSB_BAR0_WIN, BCM4400_PCI_CORE_ADDR);
151 - pci_rev = ssb_get_core_rev(bp);
152 -
153 - val = br32(bp, B44_SBINTVEC);
154 - val |= cores;
155 - bw32(bp, B44_SBINTVEC, val);
156 -
157 - val = br32(bp, SSB_PCI_TRANS_2);
158 - val |= SSB_PCI_PREF | SSB_PCI_BURST;
159 - bw32(bp, SSB_PCI_TRANS_2, val);
160 -
161 - pci_write_config_dword(bp->pdev, SSB_BAR0_WIN, bar_orig);
162 -
163 - return pci_rev;
164 -}
165 -
166 -static void ssb_core_disable(struct b44 *bp)
167 -{
168 - if (br32(bp, B44_SBTMSLOW) & SBTMSLOW_RESET)
169 - return;
170 -
171 - bw32(bp, B44_SBTMSLOW, (SBTMSLOW_REJECT | SBTMSLOW_CLOCK));
172 - b44_wait_bit(bp, B44_SBTMSLOW, SBTMSLOW_REJECT, 100000, 0);
173 - b44_wait_bit(bp, B44_SBTMSHIGH, SBTMSHIGH_BUSY, 100000, 1);
174 - bw32(bp, B44_SBTMSLOW, (SBTMSLOW_FGC | SBTMSLOW_CLOCK |
175 - SBTMSLOW_REJECT | SBTMSLOW_RESET));
176 - br32(bp, B44_SBTMSLOW);
177 - udelay(1);
178 - bw32(bp, B44_SBTMSLOW, (SBTMSLOW_REJECT | SBTMSLOW_RESET));
179 - br32(bp, B44_SBTMSLOW);
180 - udelay(1);
181 -}
182 -
183 -static void ssb_core_reset(struct b44 *bp)
184 +static inline void __b44_cam_read(struct b44 *bp, unsigned char *data, int index)
185 {
186 u32 val;
187
188 - ssb_core_disable(bp);
189 - bw32(bp, B44_SBTMSLOW, (SBTMSLOW_RESET | SBTMSLOW_CLOCK | SBTMSLOW_FGC));
190 - br32(bp, B44_SBTMSLOW);
191 - udelay(1);
192 -
193 - /* Clear SERR if set, this is a hw bug workaround. */
194 - if (br32(bp, B44_SBTMSHIGH) & SBTMSHIGH_SERR)
195 - bw32(bp, B44_SBTMSHIGH, 0);
196 -
197 - val = br32(bp, B44_SBIMSTATE);
198 - if (val & (SBIMSTATE_IBE | SBIMSTATE_TO))
199 - bw32(bp, B44_SBIMSTATE, val & ~(SBIMSTATE_IBE | SBIMSTATE_TO));
200 -
201 - bw32(bp, B44_SBTMSLOW, (SBTMSLOW_CLOCK | SBTMSLOW_FGC));
202 - br32(bp, B44_SBTMSLOW);
203 - udelay(1);
204 + bw32(bp, B44_CAM_CTRL, (CAM_CTRL_READ |
205 + (index << CAM_CTRL_INDEX_SHIFT)));
206
207 - bw32(bp, B44_SBTMSLOW, (SBTMSLOW_CLOCK));
208 - br32(bp, B44_SBTMSLOW);
209 - udelay(1);
210 -}
211 + b44_wait_bit(bp, B44_CAM_CTRL, CAM_CTRL_BUSY, 100, 1);
212
213 -static int ssb_core_unit(struct b44 *bp)
214 -{
215 -#if 0
216 - u32 val = br32(bp, B44_SBADMATCH0);
217 - u32 base;
218 + val = br32(bp, B44_CAM_DATA_LO);
219
220 - type = val & SBADMATCH0_TYPE_MASK;
221 - switch (type) {
222 - case 0:
223 - base = val & SBADMATCH0_BS0_MASK;
224 - break;
225 + data[2] = (val >> 24) & 0xFF;
226 + data[3] = (val >> 16) & 0xFF;
227 + data[4] = (val >> 8) & 0xFF;
228 + data[5] = (val >> 0) & 0xFF;
229
230 - case 1:
231 - base = val & SBADMATCH0_BS1_MASK;
232 - break;
233 + val = br32(bp, B44_CAM_DATA_HI);
234
235 - case 2:
236 - default:
237 - base = val & SBADMATCH0_BS2_MASK;
238 - break;
239 - };
240 -#endif
241 - return 0;
242 + data[0] = (val >> 8) & 0xFF;
243 + data[1] = (val >> 0) & 0xFF;
244 }
245
246 -static int ssb_is_core_up(struct b44 *bp)
247 -{
248 - return ((br32(bp, B44_SBTMSLOW) & (SBTMSLOW_RESET | SBTMSLOW_REJECT | SBTMSLOW_CLOCK))
249 - == SBTMSLOW_CLOCK);
250 -}
251 -
252 -static void __b44_cam_write(struct b44 *bp, unsigned char *data, int index)
253 +static inline void __b44_cam_write(struct b44 *bp, unsigned char *data, int index)
254 {
255 u32 val;
256
257 @@ -328,14 +227,14 @@
258 bw32(bp, B44_IMASK, bp->imask);
259 }
260
261 -static int b44_readphy(struct b44 *bp, int reg, u32 *val)
262 +static int __b44_readphy(struct b44 *bp, int phy_addr, int reg, u32 *val)
263 {
264 int err;
265
266 bw32(bp, B44_EMAC_ISTAT, EMAC_INT_MII);
267 bw32(bp, B44_MDIO_DATA, (MDIO_DATA_SB_START |
268 (MDIO_OP_READ << MDIO_DATA_OP_SHIFT) |
269 - (bp->phy_addr << MDIO_DATA_PMD_SHIFT) |
270 + (phy_addr << MDIO_DATA_PMD_SHIFT) |
271 (reg << MDIO_DATA_RA_SHIFT) |
272 (MDIO_TA_VALID << MDIO_DATA_TA_SHIFT)));
273 err = b44_wait_bit(bp, B44_EMAC_ISTAT, EMAC_INT_MII, 100, 0);
274 @@ -344,18 +243,34 @@
275 return err;
276 }
277
278 -static int b44_writephy(struct b44 *bp, int reg, u32 val)
279 +static int __b44_writephy(struct b44 *bp, int phy_addr, int reg, u32 val)
280 {
281 bw32(bp, B44_EMAC_ISTAT, EMAC_INT_MII);
282 bw32(bp, B44_MDIO_DATA, (MDIO_DATA_SB_START |
283 (MDIO_OP_WRITE << MDIO_DATA_OP_SHIFT) |
284 - (bp->phy_addr << MDIO_DATA_PMD_SHIFT) |
285 + (phy_addr << MDIO_DATA_PMD_SHIFT) |
286 (reg << MDIO_DATA_RA_SHIFT) |
287 (MDIO_TA_VALID << MDIO_DATA_TA_SHIFT) |
288 (val & MDIO_DATA_DATA)));
289 return b44_wait_bit(bp, B44_EMAC_ISTAT, EMAC_INT_MII, 100, 0);
290 }
291
292 +static inline int b44_readphy(struct b44 *bp, int reg, u32 *val)
293 +{
294 + if (bp->phy_addr == B44_PHY_ADDR_NO_PHY)
295 + return 0;
296 +
297 + return __b44_readphy(bp, bp->phy_addr, reg, val);
298 +}
299 +
300 +static inline int b44_writephy(struct b44 *bp, int reg, u32 val)
301 +{
302 + if (bp->phy_addr == B44_PHY_ADDR_NO_PHY)
303 + return 0;
304 +
305 + return __b44_writephy(bp, bp->phy_addr, reg, val);
306 +}
307 +
308 /* miilib interface */
309 /* FIXME FIXME: phy_id is ignored, bp->phy_addr use is unconditional
310 * due to code existing before miilib use was added to this driver.
311 @@ -384,6 +299,8 @@
312 u32 val;
313 int err;
314
315 + if (bp->phy_addr == B44_PHY_ADDR_NO_PHY)
316 + return 0;
317 err = b44_writephy(bp, MII_BMCR, BMCR_RESET);
318 if (err)
319 return err;
320 @@ -442,11 +359,27 @@
321 __b44_set_flow_ctrl(bp, pause_enab);
322 }
323
324 +
325 +extern char *nvram_get(char *name); //FIXME: move elsewhere
326 static int b44_setup_phy(struct b44 *bp)
327 {
328 u32 val;
329 int err;
330
331 + /*
332 + * workaround for bad hardware design in Linksys WAP54G v1.0
333 + * see https://dev.openwrt.org/ticket/146
334 + * check and reset bit "isolate"
335 + */
336 + if ((atoi(nvram_get("boardnum")) == 2) &&
337 + (__b44_readphy(bp, 0, MII_BMCR, &val) == 0) &&
338 + (val & BMCR_ISOLATE) &&
339 + (__b44_writephy(bp, 0, MII_BMCR, val & ~BMCR_ISOLATE) != 0)) {
340 + printk(KERN_WARNING PFX "PHY: cannot reset MII transceiver isolate bit.\n");
341 + }
342 +
343 + if (bp->phy_addr == B44_PHY_ADDR_NO_PHY)
344 + return 0;
345 if ((err = b44_readphy(bp, B44_MII_ALEDCTRL, &val)) != 0)
346 goto out;
347 if ((err = b44_writephy(bp, B44_MII_ALEDCTRL,
348 @@ -542,6 +475,19 @@
349 {
350 u32 bmsr, aux;
351
352 + if (bp->phy_addr == B44_PHY_ADDR_NO_PHY) {
353 + bp->flags |= B44_FLAG_100_BASE_T;
354 + bp->flags |= B44_FLAG_FULL_DUPLEX;
355 + if (!netif_carrier_ok(bp->dev)) {
356 + u32 val = br32(bp, B44_TX_CTRL);
357 + val |= TX_CTRL_DUPLEX;
358 + bw32(bp, B44_TX_CTRL, val);
359 + netif_carrier_on(bp->dev);
360 + b44_link_report(bp);
361 + }
362 + return;
363 + }
364 +
365 if (!b44_readphy(bp, MII_BMSR, &bmsr) &&
366 !b44_readphy(bp, B44_MII_AUXCTRL, &aux) &&
367 (bmsr != 0xffff)) {
368 @@ -617,10 +563,10 @@
369
370 BUG_ON(skb == NULL);
371
372 - pci_unmap_single(bp->pdev,
373 + dma_unmap_single(bp->sdev->dev,
374 pci_unmap_addr(rp, mapping),
375 skb->len,
376 - PCI_DMA_TODEVICE);
377 + DMA_TO_DEVICE);
378 rp->skb = NULL;
379 dev_kfree_skb_irq(skb);
380 }
381 @@ -657,9 +603,9 @@
382 if (skb == NULL)
383 return -ENOMEM;
384
385 - mapping = pci_map_single(bp->pdev, skb->data,
386 + mapping = dma_map_single(bp->sdev->dev, skb->data,
387 RX_PKT_BUF_SZ,
388 - PCI_DMA_FROMDEVICE);
389 + DMA_FROM_DEVICE);
390
391 /* Hardware bug work-around, the chip is unable to do PCI DMA
392 to/from anything above 1GB :-( */
393 @@ -667,18 +613,18 @@
394 mapping + RX_PKT_BUF_SZ > DMA_30BIT_MASK) {
395 /* Sigh... */
396 if (!dma_mapping_error(mapping))
397 - pci_unmap_single(bp->pdev, mapping, RX_PKT_BUF_SZ,PCI_DMA_FROMDEVICE);
398 + dma_unmap_single(bp->sdev->dev, mapping, RX_PKT_BUF_SZ,DMA_FROM_DEVICE);
399 dev_kfree_skb_any(skb);
400 skb = __netdev_alloc_skb(bp->dev, RX_PKT_BUF_SZ, GFP_ATOMIC|GFP_DMA);
401 if (skb == NULL)
402 return -ENOMEM;
403 - mapping = pci_map_single(bp->pdev, skb->data,
404 + mapping = dma_map_single(bp->sdev->dev, skb->data,
405 RX_PKT_BUF_SZ,
406 - PCI_DMA_FROMDEVICE);
407 + DMA_FROM_DEVICE);
408 if (dma_mapping_error(mapping) ||
409 mapping + RX_PKT_BUF_SZ > DMA_30BIT_MASK) {
410 if (!dma_mapping_error(mapping))
411 - pci_unmap_single(bp->pdev, mapping, RX_PKT_BUF_SZ,PCI_DMA_FROMDEVICE);
412 + dma_unmap_single(bp->sdev->dev, mapping, RX_PKT_BUF_SZ,DMA_FROM_DEVICE);
413 dev_kfree_skb_any(skb);
414 return -ENOMEM;
415 }
416 @@ -705,9 +651,9 @@
417 dp->addr = cpu_to_le32((u32) mapping + RX_PKT_OFFSET + bp->dma_offset);
418
419 if (bp->flags & B44_FLAG_RX_RING_HACK)
420 - b44_sync_dma_desc_for_device(bp->pdev, bp->rx_ring_dma,
421 - dest_idx * sizeof(dp),
422 - DMA_BIDIRECTIONAL);
423 + b44_sync_dma_desc_for_device(bp->sdev, bp->rx_ring_dma,
424 + dest_idx * sizeof(dp),
425 + DMA_BIDIRECTIONAL);
426
427 return RX_PKT_BUF_SZ;
428 }
429 @@ -734,9 +680,9 @@
430 pci_unmap_addr(src_map, mapping));
431
432 if (bp->flags & B44_FLAG_RX_RING_HACK)
433 - b44_sync_dma_desc_for_cpu(bp->pdev, bp->rx_ring_dma,
434 - src_idx * sizeof(src_desc),
435 - DMA_BIDIRECTIONAL);
436 + b44_sync_dma_desc_for_cpu(bp->sdev, bp->rx_ring_dma,
437 + src_idx * sizeof(src_desc),
438 + DMA_BIDIRECTIONAL);
439
440 ctrl = src_desc->ctrl;
441 if (dest_idx == (B44_RX_RING_SIZE - 1))
442 @@ -750,13 +696,13 @@
443 src_map->skb = NULL;
444
445 if (bp->flags & B44_FLAG_RX_RING_HACK)
446 - b44_sync_dma_desc_for_device(bp->pdev, bp->rx_ring_dma,
447 - dest_idx * sizeof(dest_desc),
448 - DMA_BIDIRECTIONAL);
449 + b44_sync_dma_desc_for_device(bp->sdev, bp->rx_ring_dma,
450 + dest_idx * sizeof(dest_desc),
451 + DMA_BIDIRECTIONAL);
452
453 - pci_dma_sync_single_for_device(bp->pdev, le32_to_cpu(src_desc->addr),
454 + dma_sync_single_for_device(bp->sdev->dev, le32_to_cpu(src_desc->addr),
455 RX_PKT_BUF_SZ,
456 - PCI_DMA_FROMDEVICE);
457 + DMA_FROM_DEVICE);
458 }
459
460 static int b44_rx(struct b44 *bp, int budget)
461 @@ -776,9 +722,9 @@
462 struct rx_header *rh;
463 u16 len;
464
465 - pci_dma_sync_single_for_cpu(bp->pdev, map,
466 + dma_sync_single_for_cpu(bp->sdev->dev, map,
467 RX_PKT_BUF_SZ,
468 - PCI_DMA_FROMDEVICE);
469 + DMA_FROM_DEVICE);
470 rh = (struct rx_header *) skb->data;
471 len = le16_to_cpu(rh->len);
472 if ((len > (RX_PKT_BUF_SZ - RX_PKT_OFFSET)) ||
473 @@ -810,8 +756,8 @@
474 skb_size = b44_alloc_rx_skb(bp, cons, bp->rx_prod);
475 if (skb_size < 0)
476 goto drop_it;
477 - pci_unmap_single(bp->pdev, map,
478 - skb_size, PCI_DMA_FROMDEVICE);
479 + dma_unmap_single(bp->sdev->dev, map,
480 + skb_size, DMA_FROM_DEVICE);
481 /* Leave out rx_header */
482 skb_put(skb, len + RX_PKT_OFFSET);
483 skb_pull(skb, RX_PKT_OFFSET);
484 @@ -982,24 +928,24 @@
485 goto err_out;
486 }
487
488 - mapping = pci_map_single(bp->pdev, skb->data, len, PCI_DMA_TODEVICE);
489 + mapping = dma_map_single(bp->sdev->dev, skb->data, len, DMA_TO_DEVICE);
490 if (dma_mapping_error(mapping) || mapping + len > DMA_30BIT_MASK) {
491 struct sk_buff *bounce_skb;
492
493 /* Chip can't handle DMA to/from >1GB, use bounce buffer */
494 if (!dma_mapping_error(mapping))
495 - pci_unmap_single(bp->pdev, mapping, len, PCI_DMA_TODEVICE);
496 + dma_unmap_single(bp->sdev->dev, mapping, len, DMA_TO_DEVICE);
497
498 bounce_skb = __dev_alloc_skb(len, GFP_ATOMIC | GFP_DMA);
499 if (!bounce_skb)
500 goto err_out;
501
502 - mapping = pci_map_single(bp->pdev, bounce_skb->data,
503 - len, PCI_DMA_TODEVICE);
504 + mapping = dma_map_single(bp->sdev->dev, bounce_skb->data,
505 + len, DMA_TO_DEVICE);
506 if (dma_mapping_error(mapping) || mapping + len > DMA_30BIT_MASK) {
507 if (!dma_mapping_error(mapping))
508 - pci_unmap_single(bp->pdev, mapping,
509 - len, PCI_DMA_TODEVICE);
510 + dma_unmap_single(bp->sdev->dev, mapping,
511 + len, DMA_TO_DEVICE);
512 dev_kfree_skb_any(bounce_skb);
513 goto err_out;
514 }
515 @@ -1022,9 +968,9 @@
516 bp->tx_ring[entry].addr = cpu_to_le32((u32) mapping+bp->dma_offset);
517
518 if (bp->flags & B44_FLAG_TX_RING_HACK)
519 - b44_sync_dma_desc_for_device(bp->pdev, bp->tx_ring_dma,
520 - entry * sizeof(bp->tx_ring[0]),
521 - DMA_TO_DEVICE);
522 + b44_sync_dma_desc_for_device(bp->sdev, bp->tx_ring_dma,
523 + entry * sizeof(bp->tx_ring[0]),
524 + DMA_TO_DEVICE);
525
526 entry = NEXT_TX(entry);
527
528 @@ -1097,10 +1043,10 @@
529
530 if (rp->skb == NULL)
531 continue;
532 - pci_unmap_single(bp->pdev,
533 + dma_unmap_single(bp->sdev->dev,
534 pci_unmap_addr(rp, mapping),
535 RX_PKT_BUF_SZ,
536 - PCI_DMA_FROMDEVICE);
537 + DMA_FROM_DEVICE);
538 dev_kfree_skb_any(rp->skb);
539 rp->skb = NULL;
540 }
541 @@ -1111,10 +1057,10 @@
542
543 if (rp->skb == NULL)
544 continue;
545 - pci_unmap_single(bp->pdev,
546 + dma_unmap_single(bp->sdev->dev,
547 pci_unmap_addr(rp, mapping),
548 rp->skb->len,
549 - PCI_DMA_TODEVICE);
550 + DMA_TO_DEVICE);
551 dev_kfree_skb_any(rp->skb);
552 rp->skb = NULL;
553 }
554 @@ -1136,14 +1082,14 @@
555 memset(bp->tx_ring, 0, B44_TX_RING_BYTES);
556
557 if (bp->flags & B44_FLAG_RX_RING_HACK)
558 - dma_sync_single_for_device(&bp->pdev->dev, bp->rx_ring_dma,
559 - DMA_TABLE_BYTES,
560 - PCI_DMA_BIDIRECTIONAL);
561 + dma_sync_single_for_device(bp->sdev->dev, bp->rx_ring_dma,
562 + DMA_TABLE_BYTES,
563 + DMA_BIDIRECTIONAL);
564
565 if (bp->flags & B44_FLAG_TX_RING_HACK)
566 - dma_sync_single_for_device(&bp->pdev->dev, bp->tx_ring_dma,
567 - DMA_TABLE_BYTES,
568 - PCI_DMA_TODEVICE);
569 + dma_sync_single_for_device(bp->sdev->dev, bp->tx_ring_dma,
570 + DMA_TABLE_BYTES,
571 + DMA_TO_DEVICE);
572
573 for (i = 0; i < bp->rx_pending; i++) {
574 if (b44_alloc_rx_skb(bp, -1, i) < 0)
575 @@ -1163,24 +1109,24 @@
576 bp->tx_buffers = NULL;
577 if (bp->rx_ring) {
578 if (bp->flags & B44_FLAG_RX_RING_HACK) {
579 - dma_unmap_single(&bp->pdev->dev, bp->rx_ring_dma,
580 - DMA_TABLE_BYTES,
581 - DMA_BIDIRECTIONAL);
582 + dma_unmap_single(bp->sdev->dev, bp->rx_ring_dma,
583 + DMA_TABLE_BYTES,
584 + DMA_BIDIRECTIONAL);
585 kfree(bp->rx_ring);
586 } else
587 - pci_free_consistent(bp->pdev, DMA_TABLE_BYTES,
588 + dma_free_coherent(bp->sdev->dev, DMA_TABLE_BYTES,
589 bp->rx_ring, bp->rx_ring_dma);
590 bp->rx_ring = NULL;
591 bp->flags &= ~B44_FLAG_RX_RING_HACK;
592 }
593 if (bp->tx_ring) {
594 if (bp->flags & B44_FLAG_TX_RING_HACK) {
595 - dma_unmap_single(&bp->pdev->dev, bp->tx_ring_dma,
596 - DMA_TABLE_BYTES,
597 - DMA_TO_DEVICE);
598 + dma_unmap_single(bp->sdev->dev, bp->tx_ring_dma,
599 + DMA_TABLE_BYTES,
600 + DMA_TO_DEVICE);
601 kfree(bp->tx_ring);
602 } else
603 - pci_free_consistent(bp->pdev, DMA_TABLE_BYTES,
604 + dma_free_coherent(bp->sdev->dev, DMA_TABLE_BYTES,
605 bp->tx_ring, bp->tx_ring_dma);
606 bp->tx_ring = NULL;
607 bp->flags &= ~B44_FLAG_TX_RING_HACK;
608 @@ -1206,7 +1152,7 @@
609 goto out_err;
610
611 size = DMA_TABLE_BYTES;
612 - bp->rx_ring = pci_alloc_consistent(bp->pdev, size, &bp->rx_ring_dma);
613 + bp->rx_ring = dma_alloc_coherent(bp->sdev->dev, size, &bp->rx_ring_dma, GFP_ATOMIC);
614 if (!bp->rx_ring) {
615 /* Allocation may have failed due to pci_alloc_consistent
616 insisting on use of GFP_DMA, which is more restrictive
617 @@ -1218,9 +1164,9 @@
618 if (!rx_ring)
619 goto out_err;
620
621 - rx_ring_dma = dma_map_single(&bp->pdev->dev, rx_ring,
622 - DMA_TABLE_BYTES,
623 - DMA_BIDIRECTIONAL);
624 + rx_ring_dma = dma_map_single(bp->sdev->dev, rx_ring,
625 + DMA_TABLE_BYTES,
626 + DMA_BIDIRECTIONAL);
627
628 if (dma_mapping_error(rx_ring_dma) ||
629 rx_ring_dma + size > DMA_30BIT_MASK) {
630 @@ -1233,9 +1179,9 @@
631 bp->flags |= B44_FLAG_RX_RING_HACK;
632 }
633
634 - bp->tx_ring = pci_alloc_consistent(bp->pdev, size, &bp->tx_ring_dma);
635 + bp->tx_ring = dma_alloc_coherent(bp->sdev->dev, size, &bp->tx_ring_dma, GFP_ATOMIC);
636 if (!bp->tx_ring) {
637 - /* Allocation may have failed due to pci_alloc_consistent
638 + /* Allocation may have failed due to dma_alloc_coherent
639 insisting on use of GFP_DMA, which is more restrictive
640 than necessary... */
641 struct dma_desc *tx_ring;
642 @@ -1245,9 +1191,9 @@
643 if (!tx_ring)
644 goto out_err;
645
646 - tx_ring_dma = dma_map_single(&bp->pdev->dev, tx_ring,
647 - DMA_TABLE_BYTES,
648 - DMA_TO_DEVICE);
649 + tx_ring_dma = dma_map_single(bp->sdev->dev, tx_ring,
650 + DMA_TABLE_BYTES,
651 + DMA_TO_DEVICE);
652
653 if (dma_mapping_error(tx_ring_dma) ||
654 tx_ring_dma + size > DMA_30BIT_MASK) {
655 @@ -1282,7 +1228,9 @@
656 /* bp->lock is held. */
657 static void b44_chip_reset(struct b44 *bp)
658 {
659 - if (ssb_is_core_up(bp)) {
660 + struct ssb_device *sdev = bp->sdev;
661 +
662 + if (ssb_device_is_enabled(bp->sdev)) {
663 bw32(bp, B44_RCV_LAZY, 0);
664 bw32(bp, B44_ENET_CTRL, ENET_CTRL_DISABLE);
665 b44_wait_bit(bp, B44_ENET_CTRL, ENET_CTRL_DISABLE, 200, 1);
666 @@ -1294,19 +1242,23 @@
667 }
668 bw32(bp, B44_DMARX_CTRL, 0);
669 bp->rx_prod = bp->rx_cons = 0;
670 - } else {
671 - ssb_pci_setup(bp, (bp->core_unit == 0 ?
672 - SBINTVEC_ENET0 :
673 - SBINTVEC_ENET1));
674 }
675
676 - ssb_core_reset(bp);
677 -
678 + ssb_device_enable(bp->sdev, 0);
679 b44_clear_stats(bp);
680
681 - /* Make PHY accessible. */
682 - bw32(bp, B44_MDIO_CTRL, (MDIO_CTRL_PREAMBLE |
683 + switch (sdev->bus->bustype) {
684 + case SSB_BUSTYPE_SSB:
685 + bw32(bp, B44_MDIO_CTRL, (MDIO_CTRL_PREAMBLE |
686 + (((ssb_clockspeed(sdev->bus) + (B44_MDC_RATIO / 2)) / B44_MDC_RATIO)
687 + & MDIO_CTRL_MAXF_MASK)));
688 + break;
689 + case SSB_BUSTYPE_PCI:
690 + bw32(bp, B44_MDIO_CTRL, (MDIO_CTRL_PREAMBLE |
691 (0x0d & MDIO_CTRL_MAXF_MASK)));
692 + break;
693 + }
694 +
695 br32(bp, B44_MDIO_CTRL);
696
697 if (!(br32(bp, B44_DEVCTRL) & DEVCTRL_IPP)) {
698 @@ -1349,6 +1301,7 @@
699 {
700 struct b44 *bp = netdev_priv(dev);
701 struct sockaddr *addr = p;
702 + u32 val;
703
704 if (netif_running(dev))
705 return -EBUSY;
706 @@ -1359,7 +1312,11 @@
707 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
708
709 spin_lock_irq(&bp->lock);
710 - __b44_set_mac_addr(bp);
711 +
712 + val = br32(bp, B44_RXCONFIG);
713 + if (!(val & RXCONFIG_CAM_ABSENT))
714 + __b44_set_mac_addr(bp);
715 +
716 spin_unlock_irq(&bp->lock);
717
718 return 0;
719 @@ -1445,18 +1402,6 @@
720 return err;
721 }
722
723 -#if 0
724 -/*static*/ void b44_dump_state(struct b44 *bp)
725 -{
726 - u32 val32, val32_2, val32_3, val32_4, val32_5;
727 - u16 val16;
728 -
729 - pci_read_config_word(bp->pdev, PCI_STATUS, &val16);
730 - printk("DEBUG: PCI status [%04x] \n", val16);
731 -
732 -}
733 -#endif
734 -
735 #ifdef CONFIG_NET_POLL_CONTROLLER
736 /*
737 * Polling receive - used by netconsole and other diagnostic tools
738 @@ -1570,7 +1515,6 @@
739 static void b44_setup_wol(struct b44 *bp)
740 {
741 u32 val;
742 - u16 pmval;
743
744 bw32(bp, B44_RXCONFIG, RXCONFIG_ALLMULTI);
745
746 @@ -1594,13 +1538,6 @@
747 } else {
748 b44_setup_pseudo_magicp(bp);
749 }
750 -
751 - val = br32(bp, B44_SBTMSLOW);
752 - bw32(bp, B44_SBTMSLOW, val | SBTMSLOW_PE);
753 -
754 - pci_read_config_word(bp->pdev, SSB_PMCSR, &pmval);
755 - pci_write_config_word(bp->pdev, SSB_PMCSR, pmval | SSB_PE);
756 -
757 }
758
759 static int b44_close(struct net_device *dev)
760 @@ -1700,7 +1637,7 @@
761
762 val = br32(bp, B44_RXCONFIG);
763 val &= ~(RXCONFIG_PROMISC | RXCONFIG_ALLMULTI);
764 - if (dev->flags & IFF_PROMISC) {
765 + if ((dev->flags & IFF_PROMISC) || (val & RXCONFIG_CAM_ABSENT)) {
766 val |= RXCONFIG_PROMISC;
767 bw32(bp, B44_RXCONFIG, val);
768 } else {
769 @@ -1747,12 +1684,8 @@
770
771 static void b44_get_drvinfo (struct net_device *dev, struct ethtool_drvinfo *info)
772 {
773 - struct b44 *bp = netdev_priv(dev);
774 - struct pci_dev *pci_dev = bp->pdev;
775 -
776 strcpy (info->driver, DRV_MODULE_NAME);
777 strcpy (info->version, DRV_MODULE_VERSION);
778 - strcpy (info->bus_info, pci_name(pci_dev));
779 }
780
781 static int b44_nway_reset(struct net_device *dev)
782 @@ -2035,6 +1968,245 @@
783 .get_ethtool_stats = b44_get_ethtool_stats,
784 };
785
786 +static int b44_ethtool_ioctl (struct net_device *dev, void __user *useraddr)
787 +{
788 + struct b44 *bp = dev->priv;
789 + u32 ethcmd;
790 +
791 + if (copy_from_user (&ethcmd, useraddr, sizeof (ethcmd)))
792 + return -EFAULT;
793 +
794 + switch (ethcmd) {
795 + case ETHTOOL_GDRVINFO: {
796 + struct ethtool_drvinfo info = { ETHTOOL_GDRVINFO };
797 + strcpy (info.driver, DRV_MODULE_NAME);
798 + strcpy (info.version, DRV_MODULE_VERSION);
799 + memset(&info.fw_version, 0, sizeof(info.fw_version));
800 + info.eedump_len = 0;
801 + info.regdump_len = 0;
802 + if (copy_to_user (useraddr, &info, sizeof (info)))
803 + return -EFAULT;
804 + return 0;
805 + }
806 +
807 + case ETHTOOL_GSET: {
808 + struct ethtool_cmd cmd = { ETHTOOL_GSET };
809 +
810 + if (!(bp->flags & B44_FLAG_INIT_COMPLETE))
811 + return -EAGAIN;
812 + cmd.supported = (SUPPORTED_Autoneg);
813 + cmd.supported |= (SUPPORTED_100baseT_Half |
814 + SUPPORTED_100baseT_Full |
815 + SUPPORTED_10baseT_Half |
816 + SUPPORTED_10baseT_Full |
817 + SUPPORTED_MII);
818 +
819 + cmd.advertising = 0;
820 + if (bp->flags & B44_FLAG_ADV_10HALF)
821 + cmd.advertising |= ADVERTISE_10HALF;
822 + if (bp->flags & B44_FLAG_ADV_10FULL)
823 + cmd.advertising |= ADVERTISE_10FULL;
824 + if (bp->flags & B44_FLAG_ADV_100HALF)
825 + cmd.advertising |= ADVERTISE_100HALF;
826 + if (bp->flags & B44_FLAG_ADV_100FULL)
827 + cmd.advertising |= ADVERTISE_100FULL;
828 + cmd.advertising |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
829 + cmd.speed = (bp->flags & B44_FLAG_100_BASE_T) ?
830 + SPEED_100 : SPEED_10;
831 + cmd.duplex = (bp->flags & B44_FLAG_FULL_DUPLEX) ?
832 + DUPLEX_FULL : DUPLEX_HALF;
833 + cmd.port = 0;
834 + cmd.phy_address = bp->phy_addr;
835 + cmd.transceiver = (bp->flags & B44_FLAG_INTERNAL_PHY) ?
836 + XCVR_INTERNAL : XCVR_EXTERNAL;
837 + cmd.autoneg = (bp->flags & B44_FLAG_FORCE_LINK) ?
838 + AUTONEG_DISABLE : AUTONEG_ENABLE;
839 + cmd.maxtxpkt = 0;
840 + cmd.maxrxpkt = 0;
841 + if (copy_to_user(useraddr, &cmd, sizeof(cmd)))
842 + return -EFAULT;
843 + return 0;
844 + }
845 + case ETHTOOL_SSET: {
846 + struct ethtool_cmd cmd;
847 +
848 + if (!(bp->flags & B44_FLAG_INIT_COMPLETE))
849 + return -EAGAIN;
850 +
851 + if (copy_from_user(&cmd, useraddr, sizeof(cmd)))
852 + return -EFAULT;
853 +
854 + /* We do not support gigabit. */
855 + if (cmd.autoneg == AUTONEG_ENABLE) {
856 + if (cmd.advertising &
857 + (ADVERTISED_1000baseT_Half |
858 + ADVERTISED_1000baseT_Full))
859 + return -EINVAL;
860 + } else if ((cmd.speed != SPEED_100 &&
861 + cmd.speed != SPEED_10) ||
862 + (cmd.duplex != DUPLEX_HALF &&
863 + cmd.duplex != DUPLEX_FULL)) {
864 + return -EINVAL;
865 + }
866 +
867 + spin_lock_irq(&bp->lock);
868 +
869 + if (cmd.autoneg == AUTONEG_ENABLE) {
870 + bp->flags &= ~B44_FLAG_FORCE_LINK;
871 + bp->flags &= ~(B44_FLAG_ADV_10HALF |
872 + B44_FLAG_ADV_10FULL |
873 + B44_FLAG_ADV_100HALF |
874 + B44_FLAG_ADV_100FULL);
875 + if (cmd.advertising & ADVERTISE_10HALF)
876 + bp->flags |= B44_FLAG_ADV_10HALF;
877 + if (cmd.advertising & ADVERTISE_10FULL)
878 + bp->flags |= B44_FLAG_ADV_10FULL;
879 + if (cmd.advertising & ADVERTISE_100HALF)
880 + bp->flags |= B44_FLAG_ADV_100HALF;
881 + if (cmd.advertising & ADVERTISE_100FULL)
882 + bp->flags |= B44_FLAG_ADV_100FULL;
883 + } else {
884 + bp->flags |= B44_FLAG_FORCE_LINK;
885 + if (cmd.speed == SPEED_100)
886 + bp->flags |= B44_FLAG_100_BASE_T;
887 + if (cmd.duplex == DUPLEX_FULL)
888 + bp->flags |= B44_FLAG_FULL_DUPLEX;
889 + }
890 +
891 + b44_setup_phy(bp);
892 +
893 + spin_unlock_irq(&bp->lock);
894 +
895 + return 0;
896 + }
897 +
898 + case ETHTOOL_GMSGLVL: {
899 + struct ethtool_value edata = { ETHTOOL_GMSGLVL };
900 + edata.data = bp->msg_enable;
901 + if (copy_to_user(useraddr, &edata, sizeof(edata)))
902 + return -EFAULT;
903 + return 0;
904 + }
905 + case ETHTOOL_SMSGLVL: {
906 + struct ethtool_value edata;
907 + if (copy_from_user(&edata, useraddr, sizeof(edata)))
908 + return -EFAULT;
909 + bp->msg_enable = edata.data;
910 + return 0;
911 + }
912 + case ETHTOOL_NWAY_RST: {
913 + u32 bmcr;
914 + int r;
915 +
916 + spin_lock_irq(&bp->lock);
917 + b44_readphy(bp, MII_BMCR, &bmcr);
918 + b44_readphy(bp, MII_BMCR, &bmcr);
919 + r = -EINVAL;
920 + if (bmcr & BMCR_ANENABLE) {
921 + b44_writephy(bp, MII_BMCR,
922 + bmcr | BMCR_ANRESTART);
923 + r = 0;
924 + }
925 + spin_unlock_irq(&bp->lock);
926 +
927 + return r;
928 + }
929 + case ETHTOOL_GLINK: {
930 + struct ethtool_value edata = { ETHTOOL_GLINK };
931 + edata.data = netif_carrier_ok(bp->dev) ? 1 : 0;
932 + if (copy_to_user(useraddr, &edata, sizeof(edata)))
933 + return -EFAULT;
934 + return 0;
935 + }
936 + case ETHTOOL_GRINGPARAM: {
937 + struct ethtool_ringparam ering = { ETHTOOL_GRINGPARAM };
938 +
939 + ering.rx_max_pending = B44_RX_RING_SIZE - 1;
940 + ering.rx_pending = bp->rx_pending;
941 +
942 + /* XXX ethtool lacks a tx_max_pending, oops... */
943 +
944 + if (copy_to_user(useraddr, &ering, sizeof(ering)))
945 + return -EFAULT;
946 + return 0;
947 + }
948 + case ETHTOOL_SRINGPARAM: {
949 + struct ethtool_ringparam ering;
950 +
951 + if (copy_from_user(&ering, useraddr, sizeof(ering)))
952 + return -EFAULT;
953 +
954 + if ((ering.rx_pending > B44_RX_RING_SIZE - 1) ||
955 + (ering.rx_mini_pending != 0) ||
956 + (ering.rx_jumbo_pending != 0) ||
957 + (ering.tx_pending > B44_TX_RING_SIZE - 1))
958 + return -EINVAL;
959 +
960 + spin_lock_irq(&bp->lock);
961 +
962 + bp->rx_pending = ering.rx_pending;
963 + bp->tx_pending = ering.tx_pending;
964 +
965 + b44_halt(bp);
966 + b44_init_rings(bp);
967 + b44_init_hw(bp, 1);
968 + netif_wake_queue(bp->dev);
969 + spin_unlock_irq(&bp->lock);
970 +
971 + b44_enable_ints(bp);
972 +
973 + return 0;
974 + }
975 + case ETHTOOL_GPAUSEPARAM: {
976 + struct ethtool_pauseparam epause = { ETHTOOL_GPAUSEPARAM };
977 +
978 + epause.autoneg =
979 + (bp->flags & B44_FLAG_PAUSE_AUTO) != 0;
980 + epause.rx_pause =
981 + (bp->flags & B44_FLAG_RX_PAUSE) != 0;
982 + epause.tx_pause =
983 + (bp->flags & B44_FLAG_TX_PAUSE) != 0;
984 + if (copy_to_user(useraddr, &epause, sizeof(epause)))
985 + return -EFAULT;
986 + return 0;
987 + }
988 + case ETHTOOL_SPAUSEPARAM: {
989 + struct ethtool_pauseparam epause;
990 +
991 + if (copy_from_user(&epause, useraddr, sizeof(epause)))
992 + return -EFAULT;
993 +
994 + spin_lock_irq(&bp->lock);
995 + if (epause.autoneg)
996 + bp->flags |= B44_FLAG_PAUSE_AUTO;
997 + else
998 + bp->flags &= ~B44_FLAG_PAUSE_AUTO;
999 + if (epause.rx_pause)
1000 + bp->flags |= B44_FLAG_RX_PAUSE;
1001 + else
1002 + bp->flags &= ~B44_FLAG_RX_PAUSE;
1003 + if (epause.tx_pause)
1004 + bp->flags |= B44_FLAG_TX_PAUSE;
1005 + else
1006 + bp->flags &= ~B44_FLAG_TX_PAUSE;
1007 + if (bp->flags & B44_FLAG_PAUSE_AUTO) {
1008 + b44_halt(bp);
1009 + b44_init_rings(bp);
1010 + b44_init_hw(bp, 1);
1011 + } else {
1012 + __b44_set_flow_ctrl(bp, bp->flags);
1013 + }
1014 + spin_unlock_irq(&bp->lock);
1015 +
1016 + b44_enable_ints(bp);
1017 +
1018 + return 0;
1019 + }
1020 + };
1021 +
1022 + return -EOPNOTSUPP;
1023 +}
1024 +
1025 static int b44_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1026 {
1027 struct mii_ioctl_data *data = if_mii(ifr);
1028 @@ -2044,40 +2216,64 @@
1029 if (!netif_running(dev))
1030 goto out;
1031
1032 - spin_lock_irq(&bp->lock);
1033 - err = generic_mii_ioctl(&bp->mii_if, data, cmd, NULL);
1034 - spin_unlock_irq(&bp->lock);
1035 -out:
1036 - return err;
1037 -}
1038 + switch (cmd) {
1039 + case SIOCETHTOOL:
1040 + return b44_ethtool_ioctl(dev, (void __user*) ifr->ifr_data);
1041
1042 -/* Read 128-bytes of EEPROM. */
1043 -static int b44_read_eeprom(struct b44 *bp, u8 *data)
1044 -{
1045 - long i;
1046 - __le16 *ptr = (__le16 *) data;
1047 + case SIOCGMIIPHY:
1048 + data->phy_id = bp->phy_addr;
1049
1050 - for (i = 0; i < 128; i += 2)
1051 - ptr[i / 2] = cpu_to_le16(readw(bp->regs + 4096 + i));
1052 + /* fallthru */
1053 + case SIOCGMIIREG: {
1054 + u32 mii_regval;
1055 + spin_lock_irq(&bp->lock);
1056 + err = __b44_readphy(bp, data->phy_id & 0x1f, data->reg_num & 0x1f, &mii_regval);
1057 + spin_unlock_irq(&bp->lock);
1058
1059 - return 0;
1060 + data->val_out = mii_regval;
1061 +
1062 + return err;
1063 + }
1064 +
1065 + case SIOCSMIIREG:
1066 + if (!capable(CAP_NET_ADMIN))
1067 + return -EPERM;
1068 +
1069 + spin_lock_irq(&bp->lock);
1070 + err = __b44_writephy(bp, data->phy_id & 0x1f, data->reg_num & 0x1f, data->val_in);
1071 + spin_unlock_irq(&bp->lock);
1072 +
1073 + return err;
1074 +
1075 + default:
1076 + break;
1077 + };
1078 + return -EOPNOTSUPP;
1079 +
1080 +out:
1081 + return err;
1082 }
1083
1084 static int __devinit b44_get_invariants(struct b44 *bp)
1085 {
1086 - u8 eeprom[128];
1087 - int err;
1088 + struct ssb_device *sdev = bp->sdev;
1089 + int err = 0;
1090 + u8 *addr;
1091
1092 - err = b44_read_eeprom(bp, &eeprom[0]);
1093 - if (err)
1094 - goto out;
1095 + bp->dma_offset = ssb_dma_translation(sdev);
1096
1097 - bp->dev->dev_addr[0] = eeprom[79];
1098 - bp->dev->dev_addr[1] = eeprom[78];
1099 - bp->dev->dev_addr[2] = eeprom[81];
1100 - bp->dev->dev_addr[3] = eeprom[80];
1101 - bp->dev->dev_addr[4] = eeprom[83];
1102 - bp->dev->dev_addr[5] = eeprom[82];
1103 + switch (instance) {
1104 + case 1:
1105 + addr = sdev->bus->sprom.r1.et0mac;
1106 + bp->phy_addr = sdev->bus->sprom.r1.et0phyaddr;
1107 + break;
1108 + default:
1109 + addr = sdev->bus->sprom.r1.et1mac;
1110 + bp->phy_addr = sdev->bus->sprom.r1.et1phyaddr;
1111 + break;
1112 + }
1113 +
1114 + memcpy(bp->dev->dev_addr, addr, 6);
1115
1116 if (!is_valid_ether_addr(&bp->dev->dev_addr[0])){
1117 printk(KERN_ERR PFX "Invalid MAC address found in EEPROM\n");
1118 @@ -2086,103 +2282,52 @@
1119
1120 memcpy(bp->dev->perm_addr, bp->dev->dev_addr, bp->dev->addr_len);
1121
1122 - bp->phy_addr = eeprom[90] & 0x1f;
1123 -
1124 bp->imask = IMASK_DEF;
1125
1126 - bp->core_unit = ssb_core_unit(bp);
1127 - bp->dma_offset = SB_PCI_DMA;
1128 -
1129 /* XXX - really required?
1130 bp->flags |= B44_FLAG_BUGGY_TXPTR;
1131 */
1132
1133 - if (ssb_get_core_rev(bp) >= 7)
1134 + if (bp->sdev->id.revision >= 7)
1135 bp->flags |= B44_FLAG_B0_ANDLATER;
1136
1137 -out:
1138 return err;
1139 }
1140
1141 -static int __devinit b44_init_one(struct pci_dev *pdev,
1142 - const struct pci_device_id *ent)
1143 +static int __devinit b44_init_one(struct ssb_device *sdev,
1144 + const struct ssb_device_id *ent)
1145 {
1146 static int b44_version_printed = 0;
1147 - unsigned long b44reg_base, b44reg_len;
1148 struct net_device *dev;
1149 struct b44 *bp;
1150 int err, i;
1151
1152 + instance++;
1153 +
1154 if (b44_version_printed++ == 0)
1155 printk(KERN_INFO "%s", version);
1156
1157 - err = pci_enable_device(pdev);
1158 - if (err) {
1159 - dev_err(&pdev->dev, "Cannot enable PCI device, "
1160 - "aborting.\n");
1161 - return err;
1162 - }
1163 -
1164 - if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
1165 - dev_err(&pdev->dev,
1166 - "Cannot find proper PCI device "
1167 - "base address, aborting.\n");
1168 - err = -ENODEV;
1169 - goto err_out_disable_pdev;
1170 - }
1171 -
1172 - err = pci_request_regions(pdev, DRV_MODULE_NAME);
1173 - if (err) {
1174 - dev_err(&pdev->dev,
1175 - "Cannot obtain PCI resources, aborting.\n");
1176 - goto err_out_disable_pdev;
1177 - }
1178 -
1179 - pci_set_master(pdev);
1180 -
1181 - err = pci_set_dma_mask(pdev, (u64) DMA_30BIT_MASK);
1182 - if (err) {
1183 - dev_err(&pdev->dev, "No usable DMA configuration, aborting.\n");
1184 - goto err_out_free_res;
1185 - }
1186 -
1187 - err = pci_set_consistent_dma_mask(pdev, (u64) DMA_30BIT_MASK);
1188 - if (err) {
1189 - dev_err(&pdev->dev, "No usable DMA configuration, aborting.\n");
1190 - goto err_out_free_res;
1191 - }
1192 -
1193 - b44reg_base = pci_resource_start(pdev, 0);
1194 - b44reg_len = pci_resource_len(pdev, 0);
1195 -
1196 dev = alloc_etherdev(sizeof(*bp));
1197 if (!dev) {
1198 - dev_err(&pdev->dev, "Etherdev alloc failed, aborting.\n");
1199 + dev_err(sdev->dev, "Etherdev alloc failed, aborting.\n");
1200 err = -ENOMEM;
1201 - goto err_out_free_res;
1202 + goto out;
1203 }
1204
1205 SET_MODULE_OWNER(dev);
1206 - SET_NETDEV_DEV(dev,&pdev->dev);
1207 + SET_NETDEV_DEV(dev,sdev->dev);
1208
1209 /* No interesting netdevice features in this card... */
1210 dev->features |= 0;
1211
1212 bp = netdev_priv(dev);
1213 - bp->pdev = pdev;
1214 + bp->sdev = sdev;
1215 bp->dev = dev;
1216
1217 bp->msg_enable = netif_msg_init(b44_debug, B44_DEF_MSG_ENABLE);
1218
1219 spin_lock_init(&bp->lock);
1220
1221 - bp->regs = ioremap(b44reg_base, b44reg_len);
1222 - if (bp->regs == 0UL) {
1223 - dev_err(&pdev->dev, "Cannot map device registers, aborting.\n");
1224 - err = -ENOMEM;
1225 - goto err_out_free_dev;
1226 - }
1227 -
1228 bp->rx_pending = B44_DEF_RX_RING_PENDING;
1229 bp->tx_pending = B44_DEF_TX_RING_PENDING;
1230
1231 @@ -2201,16 +2346,16 @@
1232 dev->poll_controller = b44_poll_controller;
1233 #endif
1234 dev->change_mtu = b44_change_mtu;
1235 - dev->irq = pdev->irq;
1236 + dev->irq = sdev->irq;
1237 SET_ETHTOOL_OPS(dev, &b44_ethtool_ops);
1238
1239 netif_carrier_off(dev);
1240
1241 err = b44_get_invariants(bp);
1242 if (err) {
1243 - dev_err(&pdev->dev,
1244 + dev_err(sdev->dev,
1245 "Problem fetching invariants of chip, aborting.\n");
1246 - goto err_out_iounmap;
1247 + goto err_out_free_dev;
1248 }
1249
1250 bp->mii_if.dev = dev;
1251 @@ -2229,61 +2374,52 @@
1252
1253 err = register_netdev(dev);
1254 if (err) {
1255 - dev_err(&pdev->dev, "Cannot register net device, aborting.\n");
1256 - goto err_out_iounmap;
1257 + dev_err(sdev->dev, "Cannot register net device, aborting.\n");
1258 + goto out;
1259 }
1260
1261 - pci_set_drvdata(pdev, dev);
1262 -
1263 - pci_save_state(bp->pdev);
1264 + ssb_set_drvdata(sdev, dev);
1265
1266 /* Chip reset provides power to the b44 MAC & PCI cores, which
1267 * is necessary for MAC register access.
1268 */
1269 b44_chip_reset(bp);
1270
1271 - printk(KERN_INFO "%s: Broadcom 4400 10/100BaseT Ethernet ", dev->name);
1272 + printk(KERN_INFO "%s: Broadcom 10/100BaseT Ethernet ", dev->name);
1273 for (i = 0; i < 6; i++)
1274 printk("%2.2x%c", dev->dev_addr[i],
1275 i == 5 ? '\n' : ':');
1276
1277 - return 0;
1278 + /* Initialize phy */
1279 + spin_lock_irq(&bp->lock);
1280 + b44_chip_reset(bp);
1281 + spin_unlock_irq(&bp->lock);
1282
1283 -err_out_iounmap:
1284 - iounmap(bp->regs);
1285 + return 0;
1286
1287 err_out_free_dev:
1288 free_netdev(dev);
1289
1290 -err_out_free_res:
1291 - pci_release_regions(pdev);
1292 -
1293 -err_out_disable_pdev:
1294 - pci_disable_device(pdev);
1295 - pci_set_drvdata(pdev, NULL);
1296 +out:
1297 return err;
1298 }
1299
1300 -static void __devexit b44_remove_one(struct pci_dev *pdev)
1301 +static void __devexit b44_remove_one(struct ssb_device *pdev)
1302 {
1303 - struct net_device *dev = pci_get_drvdata(pdev);
1304 - struct b44 *bp = netdev_priv(dev);
1305 + struct net_device *dev = ssb_get_drvdata(pdev);
1306
1307 unregister_netdev(dev);
1308 - iounmap(bp->regs);
1309 free_netdev(dev);
1310 - pci_release_regions(pdev);
1311 - pci_disable_device(pdev);
1312 - pci_set_drvdata(pdev, NULL);
1313 + ssb_set_drvdata(pdev, NULL);
1314 }
1315
1316 -static int b44_suspend(struct pci_dev *pdev, pm_message_t state)
1317 +static int b44_suspend(struct ssb_device *pdev, pm_message_t state)
1318 {
1319 - struct net_device *dev = pci_get_drvdata(pdev);
1320 + struct net_device *dev = ssb_get_drvdata(pdev);
1321 struct b44 *bp = netdev_priv(dev);
1322
1323 if (!netif_running(dev))
1324 - return 0;
1325 + return 0;
1326
1327 del_timer_sync(&bp->timer);
1328
1329 @@ -2301,33 +2437,22 @@
1330 b44_init_hw(bp, B44_PARTIAL_RESET);
1331 b44_setup_wol(bp);
1332 }
1333 - pci_disable_device(pdev);
1334 +
1335 return 0;
1336 }
1337
1338 -static int b44_resume(struct pci_dev *pdev)
1339 +static int b44_resume(struct ssb_device *pdev)
1340 {
1341 - struct net_device *dev = pci_get_drvdata(pdev);
1342 + struct net_device *dev = ssb_get_drvdata(pdev);
1343 struct b44 *bp = netdev_priv(dev);
1344 int rc = 0;
1345
1346 - pci_restore_state(pdev);
1347 - rc = pci_enable_device(pdev);
1348 - if (rc) {
1349 - printk(KERN_ERR PFX "%s: pci_enable_device failed\n",
1350 - dev->name);
1351 - return rc;
1352 - }
1353 -
1354 - pci_set_master(pdev);
1355 -
1356 if (!netif_running(dev))
1357 return 0;
1358
1359 rc = request_irq(dev->irq, b44_interrupt, IRQF_SHARED, dev->name, dev);
1360 if (rc) {
1361 printk(KERN_ERR PFX "%s: request_irq failed\n", dev->name);
1362 - pci_disable_device(pdev);
1363 return rc;
1364 }
1365
1366 @@ -2346,29 +2471,31 @@
1367 return 0;
1368 }
1369
1370 -static struct pci_driver b44_driver = {
1371 +static struct ssb_driver b44_driver = {
1372 .name = DRV_MODULE_NAME,
1373 - .id_table = b44_pci_tbl,
1374 + .id_table = b44_ssb_tbl,
1375 .probe = b44_init_one,
1376 .remove = __devexit_p(b44_remove_one),
1377 - .suspend = b44_suspend,
1378 - .resume = b44_resume,
1379 + .suspend = b44_suspend,
1380 + .resume = b44_resume,
1381 };
1382
1383 static int __init b44_init(void)
1384 {
1385 unsigned int dma_desc_align_size = dma_get_cache_alignment();
1386
1387 + instance = 0;
1388 +
1389 /* Setup paramaters for syncing RX/TX DMA descriptors */
1390 dma_desc_align_mask = ~(dma_desc_align_size - 1);
1391 dma_desc_sync_size = max_t(unsigned int, dma_desc_align_size, sizeof(struct dma_desc));
1392
1393 - return pci_register_driver(&b44_driver);
1394 + return ssb_driver_register(&b44_driver);
1395 }
1396
1397 static void __exit b44_cleanup(void)
1398 {
1399 - pci_unregister_driver(&b44_driver);
1400 + ssb_driver_unregister(&b44_driver);
1401 }
1402
1403 module_init(b44_init);
1404 Index: linux-2.6.23/drivers/net/b44.h
1405 ===================================================================
1406 --- linux-2.6.23.orig/drivers/net/b44.h 2007-10-13 10:58:27.880607722 +0200
1407 +++ linux-2.6.23/drivers/net/b44.h 2007-10-13 11:00:46.904530245 +0200
1408 @@ -129,6 +129,7 @@
1409 #define RXCONFIG_FLOW 0x00000020 /* Flow Control Enable */
1410 #define RXCONFIG_FLOW_ACCEPT 0x00000040 /* Accept Unicast Flow Control Frame */
1411 #define RXCONFIG_RFILT 0x00000080 /* Reject Filter */
1412 +#define RXCONFIG_CAM_ABSENT 0x00000100 /* CAM Absent */
1413 #define B44_RXMAXLEN 0x0404UL /* EMAC RX Max Packet Length */
1414 #define B44_TXMAXLEN 0x0408UL /* EMAC TX Max Packet Length */
1415 #define B44_MDIO_CTRL 0x0410UL /* EMAC MDIO Control */
1416 @@ -227,75 +228,9 @@
1417 #define B44_RX_PAUSE 0x05D4UL /* MIB RX Pause Packets */
1418 #define B44_RX_NPAUSE 0x05D8UL /* MIB RX Non-Pause Packets */
1419
1420 -/* Silicon backplane register definitions */
1421 -#define B44_SBIMSTATE 0x0F90UL /* SB Initiator Agent State */
1422 -#define SBIMSTATE_PC 0x0000000f /* Pipe Count */
1423 -#define SBIMSTATE_AP_MASK 0x00000030 /* Arbitration Priority */
1424 -#define SBIMSTATE_AP_BOTH 0x00000000 /* Use both timeslices and token */
1425 -#define SBIMSTATE_AP_TS 0x00000010 /* Use timeslices only */
1426 -#define SBIMSTATE_AP_TK 0x00000020 /* Use token only */
1427 -#define SBIMSTATE_AP_RSV 0x00000030 /* Reserved */
1428 -#define SBIMSTATE_IBE 0x00020000 /* In Band Error */
1429 -#define SBIMSTATE_TO 0x00040000 /* Timeout */
1430 -#define B44_SBINTVEC 0x0F94UL /* SB Interrupt Mask */
1431 -#define SBINTVEC_PCI 0x00000001 /* Enable interrupts for PCI */
1432 -#define SBINTVEC_ENET0 0x00000002 /* Enable interrupts for enet 0 */
1433 -#define SBINTVEC_ILINE20 0x00000004 /* Enable interrupts for iline20 */
1434 -#define SBINTVEC_CODEC 0x00000008 /* Enable interrupts for v90 codec */
1435 -#define SBINTVEC_USB 0x00000010 /* Enable interrupts for usb */
1436 -#define SBINTVEC_EXTIF 0x00000020 /* Enable interrupts for external i/f */
1437 -#define SBINTVEC_ENET1 0x00000040 /* Enable interrupts for enet 1 */
1438 -#define B44_SBTMSLOW 0x0F98UL /* SB Target State Low */
1439 -#define SBTMSLOW_RESET 0x00000001 /* Reset */
1440 -#define SBTMSLOW_REJECT 0x00000002 /* Reject */
1441 -#define SBTMSLOW_CLOCK 0x00010000 /* Clock Enable */
1442 -#define SBTMSLOW_FGC 0x00020000 /* Force Gated Clocks On */
1443 -#define SBTMSLOW_PE 0x40000000 /* Power Management Enable */
1444 -#define SBTMSLOW_BE 0x80000000 /* BIST Enable */
1445 -#define B44_SBTMSHIGH 0x0F9CUL /* SB Target State High */
1446 -#define SBTMSHIGH_SERR 0x00000001 /* S-error */
1447 -#define SBTMSHIGH_INT 0x00000002 /* Interrupt */
1448 -#define SBTMSHIGH_BUSY 0x00000004 /* Busy */
1449 -#define SBTMSHIGH_GCR 0x20000000 /* Gated Clock Request */
1450 -#define SBTMSHIGH_BISTF 0x40000000 /* BIST Failed */
1451 -#define SBTMSHIGH_BISTD 0x80000000 /* BIST Done */
1452 -#define B44_SBIDHIGH 0x0FFCUL /* SB Identification High */
1453 -#define SBIDHIGH_RC_MASK 0x0000000f /* Revision Code */
1454 -#define SBIDHIGH_CC_MASK 0x0000fff0 /* Core Code */
1455 -#define SBIDHIGH_CC_SHIFT 4
1456 -#define SBIDHIGH_VC_MASK 0xffff0000 /* Vendor Code */
1457 -#define SBIDHIGH_VC_SHIFT 16
1458 -
1459 -/* SSB PCI config space registers. */
1460 -#define SSB_PMCSR 0x44
1461 -#define SSB_PE 0x100
1462 -#define SSB_BAR0_WIN 0x80
1463 -#define SSB_BAR1_WIN 0x84
1464 -#define SSB_SPROM_CONTROL 0x88
1465 -#define SSB_BAR1_CONTROL 0x8c
1466 -
1467 -/* SSB core and host control registers. */
1468 -#define SSB_CONTROL 0x0000UL
1469 -#define SSB_ARBCONTROL 0x0010UL
1470 -#define SSB_ISTAT 0x0020UL
1471 -#define SSB_IMASK 0x0024UL
1472 -#define SSB_MBOX 0x0028UL
1473 -#define SSB_BCAST_ADDR 0x0050UL
1474 -#define SSB_BCAST_DATA 0x0054UL
1475 -#define SSB_PCI_TRANS_0 0x0100UL
1476 -#define SSB_PCI_TRANS_1 0x0104UL
1477 -#define SSB_PCI_TRANS_2 0x0108UL
1478 -#define SSB_SPROM 0x0800UL
1479 -
1480 -#define SSB_PCI_MEM 0x00000000
1481 -#define SSB_PCI_IO 0x00000001
1482 -#define SSB_PCI_CFG0 0x00000002
1483 -#define SSB_PCI_CFG1 0x00000003
1484 -#define SSB_PCI_PREF 0x00000004
1485 -#define SSB_PCI_BURST 0x00000008
1486 -#define SSB_PCI_MASK0 0xfc000000
1487 -#define SSB_PCI_MASK1 0xfc000000
1488 -#define SSB_PCI_MASK2 0xc0000000
1489 +#define br32(bp, REG) ssb_read32((bp)->sdev, (REG))
1490 +#define bw32(bp, REG, VAL) ssb_write32((bp)->sdev, (REG), (VAL))
1491 +#define atoi(str) simple_strtoul(((str != NULL) ? str : ""), NULL, 0)
1492
1493 /* 4400 PHY registers */
1494 #define B44_MII_AUXCTRL 24 /* Auxiliary Control */
1495 @@ -346,10 +281,12 @@
1496
1497 struct ring_info {
1498 struct sk_buff *skb;
1499 - DECLARE_PCI_UNMAP_ADDR(mapping);
1500 + dma_addr_t mapping;
1501 };
1502
1503 #define B44_MCAST_TABLE_SIZE 32
1504 +#define B44_PHY_ADDR_NO_PHY 30
1505 +#define B44_MDC_RATIO 5000000
1506
1507 #define B44_STAT_REG_DECLARE \
1508 _B44(tx_good_octets) \
1509 @@ -425,9 +362,10 @@
1510
1511 u32 dma_offset;
1512 u32 flags;
1513 -#define B44_FLAG_B0_ANDLATER 0x00000001
1514 +#define B44_FLAG_INIT_COMPLETE 0x00000001
1515 #define B44_FLAG_BUGGY_TXPTR 0x00000002
1516 #define B44_FLAG_REORDER_BUG 0x00000004
1517 +#define B44_FLAG_B0_ANDLATER 0x00000008
1518 #define B44_FLAG_PAUSE_AUTO 0x00008000
1519 #define B44_FLAG_FULL_DUPLEX 0x00010000
1520 #define B44_FLAG_100_BASE_T 0x00020000
1521 @@ -450,8 +388,7 @@
1522 struct net_device_stats stats;
1523 struct b44_hw_stats hw_stats;
1524
1525 - void __iomem *regs;
1526 - struct pci_dev *pdev;
1527 + struct ssb_device *sdev;
1528 struct net_device *dev;
1529
1530 dma_addr_t rx_ring_dma, tx_ring_dma;
1531 Index: linux-2.6.23/drivers/net/Kconfig
1532 ===================================================================
1533 --- linux-2.6.23.orig/drivers/net/Kconfig 2007-10-13 10:58:27.888608180 +0200
1534 +++ linux-2.6.23/drivers/net/Kconfig 2007-10-13 11:00:46.912530699 +0200
1535 @@ -1577,7 +1577,7 @@
1536
1537 config B44
1538 tristate "Broadcom 4400 ethernet support"
1539 - depends on NET_PCI && PCI
1540 + depends on SSB && EXPERIMENTAL
1541 select MII
1542 help
1543 If you have a network (Ethernet) controller of this type, say Y and
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