target/linux/coldfire/files-2.6.31/arch/m68k/include/asm/MCD_dma.h

   1 /*********************************************************************
   2  *
   3  * Copyright (C) 2004  Motorola, Inc.
   4  *  MOTOROLA, INC. All Rights Reserved.
   5  *  Copyright 2009 Freescale Semiconductor, Inc.
   6  *  Shrek Wu b16972@freescale.com
   7  *
   8  *  You are hereby granted a copyright license to use
   9  *  the SOFTWARE so long as this entire notice is
  10  *  retained without alteration in any modified and/or redistributed
  11  *  versions, and that such modified versions are clearly identified
  12  *  as such. No licenses are granted by implication, estoppel or
  13  *  otherwise under any patents or trademarks of Motorola, Inc. This
  14  *  software is provided on an "AS IS" basis and without warranty.
  15  *
  16  *  To the maximum extent permitted by applicable law, MOTOROLA
  17  *  DISCLAIMS ALL WARRANTIES WHETHER EXPRESS OR IMPLIED, INCLUDING
  18  *  IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR
  19  *  PURPOSE AND ANY WARRANTY AGAINST INFRINGEMENT WITH REGARD TO THE
  20  *  SOFTWARE (INCLUDING ANY MODIFIED VERSIONS THEREOF) AND ANY
  21  *  ACCOMPANYING WRITTEN MATERIALS.
  22  *
  23  *  To the maximum extent permitted by applicable law, IN NO EVENT
  24  *  SHALL MOTOROLA BE LIABLE FOR ANY DAMAGES WHATSOEVER (INCLUDING
  25  *  WITHOUT LIMITATION, DAMAGES FOR LOSS OF BUSINESS PROFITS, BUSINESS
  26  *  INTERRUPTION, LOSS OF BUSINESS INFORMATION, OR OTHER PECUNIARY
  27  *  LOSS) ARISING OF THE USE OR INABILITY TO USE THE SOFTWARE.
  28  *
  29  *  Motorola assumes no responsibility for the maintenance and support
  30  *  of this software
  31  ********************************************************************/
  32
  33 /*
  34  * File:        MCD_dma.h
  35  * Purpose:     Main header file for multi-channel DMA API.
  36  *
  37  * Notes:
  38  *
  39  * Modifications:
  40  */
  41 #ifndef _MCD_API_H
  42 #define _MCD_API_H
  43
  44 #include <asm/types.h>
  45
  46 /*
  47  * Turn Execution Unit tasks ON (#define) or OFF (#undef)
  48  */
  49 #undef MCD_INCLUDE_EU
  50
  51 /*
  52  * Number of DMA channels
  53  */
  54 #define NCHANNELS 16
  55
  56 /*
  57  * Total number of variants
  58  */
  59 #ifdef MCD_INCLUDE_EU
  60 #define NUMOFVARIANTS   6
  61 #else
  62 #define NUMOFVARIANTS   4
  63 #endif
  64
  65 /*
  66  * Define sizes of the various tables
  67  */
  68 #define TASK_TABLE_SIZE     (NCHANNELS*32)
  69 #define VAR_TAB_SIZE        (128)
  70 #define CONTEXT_SAVE_SIZE   (128)
  71 #define FUNCDESC_TAB_SIZE   (256)
  72
  73 #ifdef MCD_INCLUDE_EU
  74 #define FUNCDESC_TAB_NUM    16
  75 #else
  76 #define FUNCDESC_TAB_NUM    1
  77 #endif
  78
  79
  80 #ifndef DEFINESONLY
  81
  82 /*
  83  * Portability typedefs
  84  */
  85  /*
  86 #ifndef s32
  87 typedef int s32;
  88 #endif
  89 #ifndef u32
  90 typedef unsigned int u32;
  91 #endif
  92 #ifndef s16
  93 typedef short s16;
  94 #endif
  95 #ifndef u16
  96 typedef unsigned short u16;
  97 #endif
  98 #ifndef s8
  99 typedef char s8;
 100 #endif
 101 #ifndef u8
 102 typedef unsigned char u8;
 103 #endif
 104 */
 105 /*
 106  * These structures represent the internal registers of the
 107  * multi-channel DMA
 108  */
 109 struct dmaRegs_s {
 110    u32 taskbar;         /* task table base address register */
 111    u32 currPtr;
 112    u32 endPtr;
 113    u32 varTablePtr;
 114    u16 dma_rsvd0;
 115    u16 ptdControl;      /* ptd control */
 116    u32 intPending;      /* interrupt pending register */
 117    u32 intMask;         /* interrupt mask register */
 118    u16 taskControl[16]; /* task control registers */
 119    u8  priority[32];    /* priority registers */
 120    u32 initiatorMux;    /* initiator mux control */
 121    u32 taskSize0;       /* task size control register 0. */
 122    u32 taskSize1;       /* task size control register 1. */
 123    u32 dma_rsvd1;       /* reserved */
 124    u32 dma_rsvd2;       /* reserved */
 125    u32 debugComp1;      /* debug comparator 1 */
 126    u32 debugComp2;      /* debug comparator 2 */
 127    u32 debugControl;    /* debug control */
 128    u32 debugStatus;     /* debug status */
 129    u32 ptdDebug;        /* priority task decode debug */
 130    u32 dma_rsvd3[31];   /* reserved */
 131 };
 132 typedef volatile struct dmaRegs_s dmaRegs;
 133
 134 #endif
 135
 136 /*
 137  * PTD contrl reg bits
 138  */
 139 #define PTD_CTL_TSK_PRI         0x8000
 140 #define PTD_CTL_COMM_PREFETCH   0x0001
 141
 142 /*
 143  * Task Control reg bits and field masks
 144  */
 145 #define TASK_CTL_EN             0x8000
 146 #define TASK_CTL_VALID          0x4000
 147 #define TASK_CTL_ALWAYS         0x2000
 148 #define TASK_CTL_INIT_MASK      0x1f00
 149 #define TASK_CTL_ASTRT          0x0080
 150 #define TASK_CTL_HIPRITSKEN     0x0040
 151 #define TASK_CTL_HLDINITNUM     0x0020
 152 #define TASK_CTL_ASTSKNUM_MASK  0x000f
 153
 154 /*
 155  * Priority reg bits and field masks
 156  */
 157 #define PRIORITY_HLD            0x80
 158 #define PRIORITY_PRI_MASK       0x07
 159
 160 /*
 161  * Debug Control reg bits and field masks
 162  */
 163 #define DBG_CTL_BLOCK_TASKS_MASK    0xffff0000
 164 #define DBG_CTL_AUTO_ARM            0x00008000
 165 #define DBG_CTL_BREAK               0x00004000
 166 #define DBG_CTL_COMP1_TYP_MASK      0x00003800
 167 #define DBG_CTL_COMP2_TYP_MASK      0x00000070
 168 #define DBG_CTL_EXT_BREAK           0x00000004
 169 #define DBG_CTL_INT_BREAK           0x00000002
 170
 171 /*
 172  * PTD Debug reg selector addresses
 173  * This reg must be written with a value to show the contents of
 174  * one of the desired internal register.
 175  */
 176 #define PTD_DBG_REQ             0x00 /* shows the state of 31 initiators */
 177 #define PTD_DBG_TSK_VLD_INIT    0x01 /* shows which 16 tasks are valid and
 178                                         have initiators asserted */
 179
 180
 181 /*
 182  * General return values
 183  */
 184 #define MCD_OK                   0
 185 #define MCD_ERROR               -1
 186 #define MCD_TABLE_UNALIGNED     -2
 187 #define MCD_CHANNEL_INVALID     -3
 188
 189 /*
 190  * MCD_initDma input flags
 191  */
 192 #define MCD_RELOC_TASKS         0x00000001
 193 #define MCD_NO_RELOC_TASKS      0x00000000
 194 #define MCD_COMM_PREFETCH_EN    0x00000002
 195 /* Commbus Prefetching - MCF547x/548x ONLY */
 196
 197 /*
 198  * MCD_dmaStatus Status Values for each channel
 199  */
 200 #define MCD_NO_DMA  1 /* No DMA has been requested since reset */
 201 #define MCD_IDLE    2 /* DMA active, but the initiator is currently inactive */
 202 #define MCD_RUNNING 3 /* DMA active, and the initiator is currently active */
 203 #define MCD_PAUSED  4 /* DMA active but it is currently paused */
 204 #define MCD_HALTED  5
 205 /* the most recent DMA has been killed with MCD_killTask() */
 206 #define MCD_DONE    6 /* the most recent DMA has completed. */
 207
 208
 209 /*
 210  * MCD_startDma parameter defines
 211  */
 212
 213 /*
 214  * Constants for the funcDesc parameter
 215  */
 216 /* Byte swapping: */
 217 #define MCD_NO_BYTE_SWAP    0x00045670  /* to disable byte swapping. */
 218 #define MCD_BYTE_REVERSE    0x00076540
 219 /* to reverse the bytes of each u32 of the DMAed data. */
 220 #define MCD_U16_REVERSE     0x00067450  /* to reverse the 16-bit halves of
 221                         each 32-bit data value being DMAed.*/
 222 #define MCD_U16_BYTE_REVERSE    0x00054760 /* to reverse the byte halves of each
 223                         16-bit half of each 32-bit data value DMAed */
 224 #define MCD_NO_BIT_REV  0x00000000
 225 /* do not reverse the bits of each byte DMAed. */
 226 #define MCD_BIT_REV     0x00088880  /* reverse the bits of each byte DMAed */
 227 /* CRCing: */
 228 #define MCD_CRC16       0xc0100000  /* to perform CRC-16 on DMAed data. */
 229 #define MCD_CRCCCITT    0xc0200000  /* to perform CRC-CCITT on DMAed data. */
 230 #define MCD_CRC32       0xc0300000  /* to perform CRC-32 on DMAed data. */
 231 #define MCD_CSUMINET    0xc0400000
 232 /* to perform internet checksums on DMAed data.*/
 233 #define MCD_NO_CSUM     0xa0000000  /* to perform no checksumming. */
 234
 235 #define MCD_FUNC_NOEU1 (MCD_NO_BYTE_SWAP | MCD_NO_BIT_REV | MCD_NO_CSUM)
 236 #define MCD_FUNC_NOEU2 (MCD_NO_BYTE_SWAP | MCD_NO_CSUM)
 237
 238 /*
 239  * Constants for the flags parameter
 240  */
 241 #define MCD_TT_FLAGS_RL   0x00000001 /* Read line */
 242 #define MCD_TT_FLAGS_CW   0x00000002 /* Combine Writes */
 243 #define MCD_TT_FLAGS_SP   0x00000004
 244 /* Speculative prefetch(XLB) MCF547x/548x ONLY  */
 245 #define MCD_TT_FLAGS_MASK 0x000000ff
 246 #define MCD_TT_FLAGS_DEF  (MCD_TT_FLAGS_RL | MCD_TT_FLAGS_CW)
 247
 248 #define MCD_SINGLE_DMA  0x00000100 /* Unchained DMA */
 249 #define MCD_CHAIN_DMA              /* TBD */
 250 #define MCD_EU_DMA                 /* TBD */
 251 #define MCD_FECTX_DMA   0x00001000 /* FEC TX ring DMA */
 252 #define MCD_FECRX_DMA   0x00002000 /* FEC RX ring DMA */
 253
 254
 255 /* these flags are valid for MCD_startDma and the chained buffer descriptors */
 256 #define MCD_BUF_READY   0x80000000
 257 /* indicates that this buffer is now under the DMA's control */
 258 #define MCD_WRAP        0x20000000
 259 /* to tell the FEC Dmas to wrap to the first BD */
 260 #define MCD_INTERRUPT   0x10000000
 261 /* to generate an interrupt after completion of the DMA. */
 262 #define MCD_END_FRAME   0x08000000
 263 /* tell the DMA to end the frame when transferring
 264         last byte of data in buffer */
 265 #define MCD_CRC_RESTART 0x40000000 /* to empty out the accumulated checksum
 266         prior to performing the DMA. */
 267
 268 /* Defines for the FEC buffer descriptor control/status word*/
 269 #define MCD_FEC_BUF_READY   0x8000
 270 #define MCD_FEC_WRAP        0x2000
 271 #define MCD_FEC_INTERRUPT   0x1000
 272 #define MCD_FEC_END_FRAME   0x0800
 273
 274
 275 /*
 276  * Defines for general intuitiveness
 277  */
 278
 279 #define MCD_TRUE  1
 280 #define MCD_FALSE 0
 281
 282 /*
 283  * Three different cases for destination and source.
 284  */
 285 #define MINUS1          -1
 286 #define ZERO            0
 287 #define PLUS1           1
 288
 289 #ifndef DEFINESONLY
 290
 291 /* Task Table Entry struct*/
 292 typedef struct {
 293     u32 TDTstart;   /* task descriptor table start */
 294     u32 TDTend;     /* task descriptor table end */
 295     u32 varTab;     /* variable table start */
 296     u32 FDTandFlags;    /* function descriptor table start and flags */
 297     volatile u32 descAddrAndStatus;
 298     volatile u32 modifiedVarTab;
 299     u32 contextSaveSpace;   /* context save space start */
 300     u32 literalBases;
 301 } TaskTableEntry;
 302
 303
 304 /* Chained buffer descriptor */
 305 typedef volatile struct MCD_bufDesc_struct MCD_bufDesc;
 306 struct MCD_bufDesc_struct {
 307    u32 flags;         /* flags describing the DMA */
 308    u32 csumResult;
 309         /* checksum from checksumming performed since last checksum reset */
 310    s8  *srcAddr;      /* the address to move data from */
 311    s8  *destAddr;     /* the address to move data to */
 312    s8  *lastDestAddr; /* the last address written to */
 313    u32 dmaSize;
 314         /* the number of bytes to transfer independent of the transfer size */
 315    MCD_bufDesc *next; /* next buffer descriptor in chain */
 316    u32 info;
 317         /* private information about this descriptor;  DMA does not affect it */
 318 };
 319
 320 /* Progress Query struct */
 321 typedef volatile struct MCD_XferProg_struct {
 322    s8 *lastSrcAddr;
 323         /* the most-recent or last, post-increment source address */
 324    s8 *lastDestAddr;
 325         /* the most-recent or last, post-increment destination address */
 326    u32  dmaSize;
 327         /* the amount of data transferred for the current buffer */
 328    MCD_bufDesc *currBufDesc;
 329         /* pointer to the current buffer descriptor being DMAed */
 330 } MCD_XferProg;
 331
 332
 333 /* FEC buffer descriptor */
 334 typedef volatile struct MCD_bufDescFec_struct {
 335     u16 statCtrl;
 336     u16 length;
 337     u32 dataPointer;
 338 } MCD_bufDescFec;
 339
 340
 341 /*************************************************************************/
 342 /*
 343  * API function Prototypes  - see MCD_dmaApi.c for further notes
 344  */
 345
 346 /*
 347  * MCD_startDma starts a particular kind of DMA .
 348  */
 349 int MCD_startDma(
 350    int channel,   /* the channel on which to run the DMA */
 351    s8  *srcAddr,
 352         /* the address to move data from, or buffer-descriptor address */
 353    s16 srcIncr,   /* the amount to increment the source address per transfer */
 354    s8  *destAddr, /* the address to move data to */
 355    s16 destIncr,
 356         /* the amount to increment the destination address per transfer */
 357    u32 dmaSize,
 358         /* the number of bytes to transfer independent of the transfer size */
 359    u32 xferSize,  /* the number bytes in of each data movement (1, 2, or 4) */
 360    u32 initiator, /* what device initiates the DMA */
 361    int priority,  /* priority of the DMA */
 362    u32 flags,     /* flags describing the DMA */
 363    u32 funcDesc
 364 /* a description of byte swapping, bit swapping, and CRC actions */
 365 );
 366
 367 /*
 368  * MCD_initDma() initializes the DMA API by setting up a pointer to the DMA
 369  * registers, relocating and creating the appropriate task structures, and
 370  * setting up some global settings
 371  */
 372 int MCD_initDma(dmaRegs *sDmaBarAddr, void *taskTableDest, u32 flags);
 373
 374 /*
 375  * MCD_dmaStatus() returns the status of the DMA on the requested channel.
 376  */
 377 int MCD_dmaStatus(int channel);
 378
 379 /*
 380  * MCD_XferProgrQuery() returns progress of DMA on requested channel
 381  */
 382 int MCD_XferProgrQuery(int channel, MCD_XferProg *progRep);
 383
 384 /*
 385  * MCD_killDma() halts the DMA on the requested channel, without any
 386  * intention of resuming the DMA.
 387  */
 388 int MCD_killDma(int channel);
 389
 390 /*
 391  * MCD_continDma() continues a DMA which as stopped due to encountering an
 392  * unready buffer descriptor.
 393  */
 394 int MCD_continDma(int channel);
 395
 396 /*
 397  * MCD_pauseDma() pauses the DMA on the given channel ( if any DMA is
 398  * running on that channel).
 399  */
 400 int MCD_pauseDma(int channel);
 401
 402 /*
 403  * MCD_resumeDma() resumes the DMA on a given channel (if any DMA is
 404  * running on that channel).
 405  */
 406 int MCD_resumeDma(int channel);
 407
 408 /*
 409  * MCD_csumQuery provides the checksum/CRC after performing a non-chained DMA
 410  */
 411 int MCD_csumQuery(int channel, u32 *csum);
 412
 413 /*
 414  * MCD_getCodeSize provides the packed size required by the microcoded task
 415  * and structures.
 416  */
 417 int MCD_getCodeSize(void);
 418
 419 /*
 420  * MCD_getVersion provides a pointer to a version string and returns a
 421  * version number.
 422  */
 423 int MCD_getVersion(char **longVersion);
 424
 425 /* macro for setting a location in the variable table */
 426 #define MCD_SET_VAR(taskTab, idx, value) ((u32 *)(taskTab)->varTab)[idx] = value
 427    /* Note that MCD_SET_VAR() is invoked many times in firing up a DMA function,
 428       so I'm avoiding surrounding it with "do {} while(0)" */
 429
 430 #endif  /* DEFINESONLY */
 431
 432 #endif /* _MCD_API_H */