rtl8366_smi: implement a function for detecting whether the attached switch is RTL836...
[openwrt.git] / target / linux / coldfire / files-2.6.31 / arch / m68k / include / asm / m5485gpt.h
1 /*
2 * Copyright 2007-2009 Freescale Semiconductor, Inc. All Rights Reserved.
3 * File: mcf548x_gpt.h
4 * Purpose: Register and bit definitions for the MCF548X
5 *
6 * Notes:
7 *
8 */
9
10 #ifndef __MCF548X_GPT_H__
11 #define __MCF548X_GPT_H__
12
13 /*********************************************************************
14 *
15 * General Purpose Timers (GPT)
16 *
17 *********************************************************************/
18
19 /* Register read/write macros */
20 #define MCF_GPT_GMS0 MCF_REG32(0x000800)
21 #define MCF_GPT_GCIR0 MCF_REG32(0x000804)
22 #define MCF_GPT_GPWM0 MCF_REG32(0x000808)
23 #define MCF_GPT_GSR0 MCF_REG32(0x00080C)
24 #define MCF_GPT_GMS1 MCF_REG32(0x000810)
25 #define MCF_GPT_GCIR1 MCF_REG32(0x000814)
26 #define MCF_GPT_GPWM1 MCF_REG32(0x000818)
27 #define MCF_GPT_GSR1 MCF_REG32(0x00081C)
28 #define MCF_GPT_GMS2 MCF_REG32(0x000820)
29 #define MCF_GPT_GCIR2 MCF_REG32(0x000824)
30 #define MCF_GPT_GPWM2 MCF_REG32(0x000828)
31 #define MCF_GPT_GSR2 MCF_REG32(0x00082C)
32 #define MCF_GPT_GMS3 MCF_REG32(0x000830)
33 #define MCF_GPT_GCIR3 MCF_REG32(0x000834)
34 #define MCF_GPT_GPWM3 MCF_REG32(0x000838)
35 #define MCF_GPT_GSR3 MCF_REG32(0x00083C)
36 #define MCF_GPT_GMS(x) MCF_REG32(0x000800+((x)*0x010))
37 #define MCF_GPT_GCIR(x) MCF_REG32(0x000804+((x)*0x010))
38 #define MCF_GPT_GPWM(x) MCF_REG32(0x000808+((x)*0x010))
39 #define MCF_GPT_GSR(x) MCF_REG32(0x00080C+((x)*0x010))
40
41 /* Bit definitions and macros for MCF_GPT_GMS */
42 #define MCF_GPT_GMS_TMS(x) (((x)&0x00000007)<<0)
43 #define MCF_GPT_GMS_GPIO(x) (((x)&0x00000003)<<4)
44 #define MCF_GPT_GMS_IEN (0x00000100)
45 #define MCF_GPT_GMS_OD (0x00000200)
46 #define MCF_GPT_GMS_SC (0x00000400)
47 #define MCF_GPT_GMS_CE (0x00001000)
48 #define MCF_GPT_GMS_WDEN (0x00008000)
49 #define MCF_GPT_GMS_ICT(x) (((x)&0x00000003)<<16)
50 #define MCF_GPT_GMS_OCT(x) (((x)&0x00000003)<<20)
51 #define MCF_GPT_GMS_OCPW(x) (((x)&0x000000FF)<<24)
52 #define MCF_GPT_GMS_OCT_FRCLOW (0x00000000)
53 #define MCF_GPT_GMS_OCT_PULSEHI (0x00100000)
54 #define MCF_GPT_GMS_OCT_PULSELO (0x00200000)
55 #define MCF_GPT_GMS_OCT_TOGGLE (0x00300000)
56 #define MCF_GPT_GMS_ICT_ANY (0x00000000)
57 #define MCF_GPT_GMS_ICT_RISE (0x00010000)
58 #define MCF_GPT_GMS_ICT_FALL (0x00020000)
59 #define MCF_GPT_GMS_ICT_PULSE (0x00030000)
60 #define MCF_GPT_GMS_GPIO_INPUT (0x00000000)
61 #define MCF_GPT_GMS_GPIO_OUTLO (0x00000020)
62 #define MCF_GPT_GMS_GPIO_OUTHI (0x00000030)
63 #define MCF_GPT_GMS_TMS_DISABLE (0x00000000)
64 #define MCF_GPT_GMS_TMS_INCAPT (0x00000001)
65 #define MCF_GPT_GMS_TMS_OUTCAPT (0x00000002)
66 #define MCF_GPT_GMS_TMS_PWM (0x00000003)
67 #define MCF_GPT_GMS_TMS_GPIO (0x00000004)
68
69 /* Bit definitions and macros for MCF_GPT_GCIR */
70 #define MCF_GPT_GCIR_CNT(x) (((x)&0x0000FFFF)<<0)
71 #define MCF_GPT_GCIR_PRE(x) (((x)&0x0000FFFF)<<16)
72
73 /* Bit definitions and macros for MCF_GPT_GPWM */
74 #define MCF_GPT_GPWM_LOAD (0x00000001)
75 #define MCF_GPT_GPWM_PWMOP (0x00000100)
76 #define MCF_GPT_GPWM_WIDTH(x) (((x)&0x0000FFFF)<<16)
77
78 /* Bit definitions and macros for MCF_GPT_GSR */
79 #define MCF_GPT_GSR_CAPT (0x00000001)
80 #define MCF_GPT_GSR_COMP (0x00000002)
81 #define MCF_GPT_GSR_PWMP (0x00000004)
82 #define MCF_GPT_GSR_TEXP (0x00000008)
83 #define MCF_GPT_GSR_PIN (0x00000100)
84 #define MCF_GPT_GSR_OVF(x) (((x)&0x00000007)<<12)
85 #define MCF_GPT_GSR_CAPTURE(x) (((x)&0x0000FFFF)<<16)
86
87 #define MCF_GPT_MAX_TIMEOUT 30
88 /********************************************************************/
89
90 #endif /* __MCF548X_GPT_H__ */
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