target/linux/coldfire/files-2.6.31/arch/m68k/include/asm/m5485sec.h

   1 /*
   2  * Copyright 2007-2009 Freescale Semiconductor, Inc. All Rights Reserved.
   3  */
   4
   5 #ifndef M5485SEC_H
   6 #define M5484SEC_H
   7
   8 #define   SEC_EUACR_U                   MCF_REG32(0x21000)
   9 #define   SEC_EUACR_L                   MCF_REG32(0x21004)
  10 #define   SEC_EUASR_U                   MCF_REG32(0x21028)
  11 #define   SEC_EUASR_L                   MCF_REG32(0x2102C)
  12 #define   SEC_SMCR                      MCF_REG32(0x21030)
  13 #define   SEC_SISR_U                    MCF_REG32(0x21010)
  14 #define   SEC_SISR_L                    MCF_REG32(0x21014)
  15 #define   SEC_SICR_U                    MCF_REG32(0x21018)
  16 #define   SEC_SICR_L                    MCF_REG32(0x2101C)
  17 #define   SEC_SIMR_U                    MCF_REG32(0x21008)
  18 #define   SEC_SIMR_L                    MCF_REG32(0x2100C)
  19 #define   SEC_SID                       MCF_REG32(0x21020)
  20
  21 #define   SEC_SMCR_RESET                0x01000000
  22 #define   SEC_SIMR_MASK_U               0x00000000
  23 #define   SEC_SIMR_MASK_L               0x03333340
  24
  25 #define   SEC_CC0_FR                    MCF_REG32(0x2204C)
  26 #define   SEC_CC0_CR                    MCF_REG32(0x2200C)
  27 #define   SEC_CC0_CDPR                  MCF_REG32(0x22044)
  28 #define   SEC_CC0_PSR_U                 MCF_REG32(0x22010)
  29 #define   SEC_CC0_PSR_L                 MCF_REG32(0x22014)
  30 #define   SEC_CC1_FR                    MCF_REG32(0x2304C)
  31 #define   SEC_CC1_CR                    MCF_REG32(0x2300C)
  32 #define   SEC_CC1_CDPR                  MCF_REG32(0x23044)
  33 #define   SEC_CC1_PSR_U                 MCF_REG32(0x23010)
  34 #define   SEC_CC1_PSR_L                 MCF_REG32(0x23014)
  35
  36 #define   SEC_CC_CR_RESET               0x00000001
  37 #define   SEC_CC_CR_CONFIGURATION       0x0000001E
  38 #define   SEC_CC_PSR_U_ERR_CH0          0x20000000
  39 #define   SEC_CC_PSR_U_ERR_CH1          0x80000000
  40 #define   SEC_CC_PSR_U_DN_CH0           0x10000000
  41 #define   SEC_CC_PSR_U_DN_CH1           0x40000000
  42
  43 #define   SEC_DEU_DRCR                  MCF_REG32(0x2A018)
  44 #define   SEC_DEU_DSR                   MCF_REG32(0x2A028)
  45 #define   SEC_DEU_DISR                  MCF_REG32(0x2A030)
  46 #define   SEC_DEU_DIMR                  MCF_REG32(0x2A038)
  47
  48 #define   SEC_DEU_DRCR_RESET            0x01000000
  49 #define   SEC_DEU_DSR_RD                0x01000000
  50 #define   SEC_DEU_DIMR_MASK             0xF63F0000
  51
  52 #define   SEC_AFEU_AFRCR                MCF_REG32(0x28018)
  53 #define   SEC_AFEU_AFSR                 MCF_REG32(0x28028)
  54 #define   SEC_AFEU_AFISR                MCF_REG32(0x28030)
  55 #define   SEC_AFEU_AFIMR                MCF_REG32(0x28038)
  56
  57 #define   SEC_AFEU_AFRCR_RESET          0x01000000
  58 #define   SEC_AFEU_AFSR_RD              0x01000000
  59 #define   SEC_AFEU_AFIMR_MASK           0xF61F0000
  60
  61
  62 #define   SEC_MDEU_MDRCR                MCF_REG32(0x2C018)
  63 #define   SEC_MDEU_MDSR                 MCF_REG32(0x2C028)
  64 #define   SEC_MDEU_MDISR                MCF_REG32(0x2C030)
  65 #define   SEC_MDEU_MDIMR                MCF_REG32(0x2C038)
  66
  67 #define   SEC_MDEU_MDRCR_RESET          0x01000000
  68 #define   SEC_MDEU_MDSR_RD              0x01000000
  69 #define   SEC_MDEU_MDIMR_MASK           0xC41F0000
  70
  71
  72 #define   SEC_RNG_RNGRCR                MCF_REG32(0x2E018)
  73 #define   SEC_RNG_RNGSR                 MCF_REG32(0x2E028)
  74 #define   SEC_RNG_RNGISR                MCF_REG32(0x2E030)
  75 #define   SEC_RNG_RNGIMR                MCF_REG32(0x2E038)
  76
  77 #define   SEC_RNG_RNGRCR_RESET          0x01000000
  78 #define   SEC_RNG_RNGSR_RD              0x01000000
  79 #define   SEC_RNG_RNGIMR_MASK           0xC2100000
  80
  81 #define   SEC_AESU_AESRCR               MCF_REG32(0x32018)
  82 #define   SEC_AESU_AESSR                MCF_REG32(0x32028)
  83 #define   SEC_AESU_AESISR               MCF_REG32(0x32030)
  84 #define   SEC_AESU_AESIMR               MCF_REG32(0x32038)
  85
  86 #define   SEC_AESU_AESRCR_RESET         0x01000000
  87 #define   SEC_AESU_AESSR_RD             0x01000000
  88 #define   SEC_AESU_AESIMR_MASK          0xF61F0000
  89
  90
  91 #define   SEC_DESC_NUM                  20
  92 #define   SEC_CHANNEL_NUMBER            2
  93 #define   SEC_MAX_BUF_SIZE              32*1024
  94 #define   SEC_INIT_TIMEOUT              1*HZ
  95 #define   SEC_INTERRUPT                 37
  96
  97 /* Header descriptor values*/
  98 #define   SEC_ALG_ENCR_DES_ECB_SINGLE   0x20100010
  99 #define   SEC_ALG_DECR_DES_ECB_SINGLE   0x20000010
 100 #define   SEC_ALG_ENCR_DES_ECB_TRIPLE   0x20300010
 101 #define   SEC_ALG_DECR_DES_ECB_TRIPLE   0x20200010
 102 #define   SEC_ALG_ENCR_DES_CBC_SINGLE   0x20500010
 103 #define   SEC_ALG_DECR_DES_CBC_SINGLE   0x20400010
 104 #define   SEC_ALG_ENCR_DES_CBC_TRIPLE   0x20700010
 105 #define   SEC_ALG_DECR_DES_CBC_TRIPLE   0x20600010
 106
 107 #define   SEC_ALG_MDEU_SHA256           0x30500010
 108 #define   SEC_ALG_MDEU_MD5              0x30600010
 109 #define   SEC_ALG_MDEU_SHA              0x30400010
 110 #define   SEC_ALG_MDEU_SHA256_HMAC      0x31D00010
 111 #define   SEC_ALG_MDEU_MD5_HMAC         0x31E00010
 112 #define   SEC_ALG_MDEU_SHA_HMAC         0x31C00010
 113
 114 #define   SEC_ALG_RNG                   0x40000010
 115
 116
 117 #define   SEC_ALG_AFEU_KEY              0x10200050
 118 #define   SEC_ALG_AFEU_CONTEXT          0x10700050
 119
 120 #define   SEC_ALG_ENCR_AESU_CBC         0x60300010
 121 #define   SEC_ALG_DECR_AESU_CBC         0x60200010
 122 #define   SEC_ALG_ENCR_AESU_ECB         0x60100010
 123 #define   SEC_ALG_DECR_AESU_ECB         0x60000010
 124 #define   SEC_ALG_AESU_CTR              0x60600010
 125
 126
 127
 128 #define   SEC_DESCHEAD_ERROR            0xFE000000
 129 #define   SEC_DESCHEAD_COMPLETED        0xFF000000
 130
 131 #define SEC_DEVICE_NAME                 "cfsec"
 132
 133 /*!!! This number must be changed*/
 134 #define SEC_MAJOR                       130
 135
 136 #define SEC_DEV_BUF                         1024
 137 #define SEC_DEV_KEY_LEN                     64
 138 #define SEC_DEV_VECTOR_LEN                  259
 139
 140 #define SEC_AES_BLCK_LEN                   16
 141 #define SEC_DES_BLCK_LEN                   8
 142
 143
 144 /* Descriptor structure of SEC*/
 145 struct sec_descriptor {
 146         volatile unsigned long secdesc_header;
 147         unsigned long secdesc_len1;
 148         void *secdesc_ptr1;
 149         unsigned long secdesc_iv_in_len;
 150         void *secdesc_iv_in_ptr;
 151         unsigned long secdesc_key_len;
 152         void *secdesc_key_ptr;
 153         unsigned long secdesc_data_in_len;
 154         void *secdesc_data_in_ptr;
 155         unsigned long secdesc_data_out_len;
 156         void *secdesc_data_out_ptr;
 157         unsigned long secdesc_iv_out_len;
 158         void *secdesc_iv_out_ptr;
 159         unsigned long secdesc_len7;
 160         void *secdesc_ptr7;
 161         void *secdesc_ptrnext;
 162 };
 163
 164 struct sec_device_data {
 165         unsigned char secdev_inbuf[SEC_DEV_BUF];
 166         unsigned char secdev_outbuf[SEC_DEV_BUF];
 167         unsigned char secdev_key[SEC_DEV_KEY_LEN];
 168         unsigned char secdev_iv[SEC_DEV_VECTOR_LEN];
 169         unsigned char secdev_ov[SEC_DEV_VECTOR_LEN];
 170         struct sec_descriptor *secdev_desc;
 171 };
 172
 173 struct sec_descriptor *sec_desc_alloc(void);
 174 inline void sec_desc_free(struct sec_descriptor *desc);
 175 int sec_execute(int channel, struct sec_descriptor *desc, int timeout);
 176 int sec_nonblock_execute(struct sec_descriptor *desc);
 177 #endif