target/linux/rb532/files-2.6.23/arch/mips/rb500/setup.c

   1 /*
   2  * setup.c - boot time setup code
   3  */
   4
   5 #include <linux/init.h>
   6 #include <linux/mm.h>
   7 #include <linux/sched.h>
   8 #include <linux/irq.h>
   9 #include <linux/ioport.h>
  10 #include <linux/pm.h>
  11 #include <asm/bootinfo.h>
  12 #include <asm/mipsregs.h>
  13 #include <asm/pgtable.h>
  14 #include <asm/reboot.h>
  15 #include <asm/addrspace.h>     /* for KSEG1ADDR() */
  16 #include <asm/time.h>
  17 #include <asm/io.h>
  18 #include <asm/rc32434/rc32434.h>
  19 #include <asm/rc32434/pci.h>
  20
  21 #ifdef CONFIG_PCI
  22 extern void rc32434_time_init(void);
  23 extern int __init rc32434_pcibridge_init(void);
  24 #endif
  25
  26 #define epldMask ((volatile unsigned char *)0xB900000d)
  27
  28 static void rb_machine_restart(char *command)
  29 {
  30         /* just jump to the reset vector */
  31         * (volatile unsigned *) KSEG1ADDR(0x18008000) = 0x80000001;
  32         ((void (*)(void))KSEG1ADDR(0x1FC00000u))();
  33 }
  34
  35 static void rb_machine_halt(void)
  36 {
  37         for(;;) continue;
  38 }
  39
  40 #ifdef CONFIG_CPU_HAS_WB
  41 void (*__wbflush) (void);
  42
  43 static void rb_write_buffer_flush(void)
  44 {
  45         __asm__ __volatile__
  46             ("sync\n\t" "nop\n\t" "loop: bc0f loop\n\t" "nop\n\t");
  47 }
  48 #endif
  49
  50 void __init plat_mem_setup(void)
  51 {
  52         unsigned int pciCntlVal;
  53
  54         board_time_init = rc32434_time_init;
  55
  56 #ifdef CONFIG_CPU_HAS_WB
  57         __wbflush = rb_write_buffer_flush;
  58 #endif
  59         _machine_restart = rb_machine_restart;
  60         _machine_halt = rb_machine_halt;
  61         /*_machine_power_off = rb_machine_power_halt;*/
  62         pm_power_off = rb_machine_halt;
  63
  64         set_io_port_base(KSEG1);
  65
  66         pciCntlVal=rc32434_pci->pcic;
  67         pciCntlVal &= 0xFFFFFF7;
  68         rc32434_pci->pcic = pciCntlVal;
  69
  70 #ifdef CONFIG_PCI
  71         /* Enable PCI interrupts in EPLD Mask register */
  72         *epldMask = 0x0;
  73         *(epldMask + 1) = 0x0;
  74 #endif
  75         write_c0_wired(0);
  76 }
  77
  78 const char *get_system_type(void)
  79 {
  80         return "MIPS RB500";
  81 }