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ixp4xx: rename config-default to config-2.6.26
[openwrt.git] / target / linux / brcm47xx / patches-2.6.25 / 700-ssb-gigabit-ethernet-driver.patch
1 --- a/drivers/ssb/Kconfig
2 +++ b/drivers/ssb/Kconfig
3 @@ -125,4 +125,13 @@
4
5 If unsure, say N
6
7 +config SSB_DRIVER_GIGE
8 + bool "SSB Broadcom Gigabit Ethernet driver"
9 + depends on SSB_PCIHOST_POSSIBLE && SSB_EMBEDDED && MIPS
10 + help
11 + Driver for the Sonics Silicon Backplane attached
12 + Broadcom Gigabit Ethernet.
13 +
14 + If unsure, say N
15 +
16 endmenu
17 --- a/drivers/ssb/Makefile
18 +++ b/drivers/ssb/Makefile
19 @@ -11,6 +11,7 @@
20 ssb-$(CONFIG_SSB_DRIVER_MIPS) += driver_mipscore.o
21 ssb-$(CONFIG_SSB_DRIVER_EXTIF) += driver_extif.o
22 ssb-$(CONFIG_SSB_DRIVER_PCICORE) += driver_pcicore.o
23 +ssb-$(CONFIG_SSB_DRIVER_GIGE) += driver_gige.o
24
25 # b43 pci-ssb-bridge driver
26 # Not strictly a part of SSB, but kept here for convenience
27 --- /dev/null
28 +++ b/drivers/ssb/driver_gige.c
29 @@ -0,0 +1,294 @@
30 +/*
31 + * Sonics Silicon Backplane
32 + * Broadcom Gigabit Ethernet core driver
33 + *
34 + * Copyright 2008, Broadcom Corporation
35 + * Copyright 2008, Michael Buesch <mb@bu3sch.de>
36 + *
37 + * Licensed under the GNU/GPL. See COPYING for details.
38 + */
39 +
40 +#include <linux/ssb/ssb.h>
41 +#include <linux/ssb/ssb_driver_gige.h>
42 +#include <linux/pci.h>
43 +#include <linux/pci_regs.h>
44 +
45 +
46 +/*
47 +MODULE_DESCRIPTION("SSB Broadcom Gigabit Ethernet driver");
48 +MODULE_AUTHOR("Michael Buesch");
49 +MODULE_LICENSE("GPL");
50 +*/
51 +
52 +static const struct ssb_device_id ssb_gige_tbl[] = {
53 + SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_ETHERNET_GBIT, SSB_ANY_REV),
54 + SSB_DEVTABLE_END
55 +};
56 +/* MODULE_DEVICE_TABLE(ssb, ssb_gige_tbl); */
57 +
58 +
59 +static inline u8 gige_read8(struct ssb_gige *dev, u16 offset)
60 +{
61 + return ssb_read8(dev->dev, offset);
62 +}
63 +
64 +static inline u16 gige_read16(struct ssb_gige *dev, u16 offset)
65 +{
66 + return ssb_read16(dev->dev, offset);
67 +}
68 +
69 +static inline u32 gige_read32(struct ssb_gige *dev, u16 offset)
70 +{
71 + return ssb_read32(dev->dev, offset);
72 +}
73 +
74 +static inline void gige_write8(struct ssb_gige *dev,
75 + u16 offset, u8 value)
76 +{
77 + ssb_write8(dev->dev, offset, value);
78 +}
79 +
80 +static inline void gige_write16(struct ssb_gige *dev,
81 + u16 offset, u16 value)
82 +{
83 + ssb_write16(dev->dev, offset, value);
84 +}
85 +
86 +static inline void gige_write32(struct ssb_gige *dev,
87 + u16 offset, u32 value)
88 +{
89 + ssb_write32(dev->dev, offset, value);
90 +}
91 +
92 +static inline
93 +u8 gige_pcicfg_read8(struct ssb_gige *dev, unsigned int offset)
94 +{
95 + BUG_ON(offset >= 256);
96 + return gige_read8(dev, SSB_GIGE_PCICFG + offset);
97 +}
98 +
99 +static inline
100 +u16 gige_pcicfg_read16(struct ssb_gige *dev, unsigned int offset)
101 +{
102 + BUG_ON(offset >= 256);
103 + return gige_read16(dev, SSB_GIGE_PCICFG + offset);
104 +}
105 +
106 +static inline
107 +u32 gige_pcicfg_read32(struct ssb_gige *dev, unsigned int offset)
108 +{
109 + BUG_ON(offset >= 256);
110 + return gige_read32(dev, SSB_GIGE_PCICFG + offset);
111 +}
112 +
113 +static inline
114 +void gige_pcicfg_write8(struct ssb_gige *dev,
115 + unsigned int offset, u8 value)
116 +{
117 + BUG_ON(offset >= 256);
118 + gige_write8(dev, SSB_GIGE_PCICFG + offset, value);
119 +}
120 +
121 +static inline
122 +void gige_pcicfg_write16(struct ssb_gige *dev,
123 + unsigned int offset, u16 value)
124 +{
125 + BUG_ON(offset >= 256);
126 + gige_write16(dev, SSB_GIGE_PCICFG + offset, value);
127 +}
128 +
129 +static inline
130 +void gige_pcicfg_write32(struct ssb_gige *dev,
131 + unsigned int offset, u32 value)
132 +{
133 + BUG_ON(offset >= 256);
134 + gige_write32(dev, SSB_GIGE_PCICFG + offset, value);
135 +}
136 +
137 +static int ssb_gige_pci_read_config(struct pci_bus *bus, unsigned int devfn,
138 + int reg, int size, u32 *val)
139 +{
140 + struct ssb_gige *dev = container_of(bus->ops, struct ssb_gige, pci_ops);
141 + unsigned long flags;
142 +
143 + if ((PCI_SLOT(devfn) > 0) || (PCI_FUNC(devfn) > 0))
144 + return PCIBIOS_DEVICE_NOT_FOUND;
145 + if (reg >= 256)
146 + return PCIBIOS_DEVICE_NOT_FOUND;
147 +
148 + spin_lock_irqsave(&dev->lock, flags);
149 + switch (size) {
150 + case 1:
151 + *val = gige_pcicfg_read8(dev, reg);
152 + break;
153 + case 2:
154 + *val = gige_pcicfg_read16(dev, reg);
155 + break;
156 + case 4:
157 + *val = gige_pcicfg_read32(dev, reg);
158 + break;
159 + default:
160 + WARN_ON(1);
161 + }
162 + spin_unlock_irqrestore(&dev->lock, flags);
163 +
164 + return PCIBIOS_SUCCESSFUL;
165 +}
166 +
167 +static int ssb_gige_pci_write_config(struct pci_bus *bus, unsigned int devfn,
168 + int reg, int size, u32 val)
169 +{
170 + struct ssb_gige *dev = container_of(bus->ops, struct ssb_gige, pci_ops);
171 + unsigned long flags;
172 +
173 + if ((PCI_SLOT(devfn) > 0) || (PCI_FUNC(devfn) > 0))
174 + return PCIBIOS_DEVICE_NOT_FOUND;
175 + if (reg >= 256)
176 + return PCIBIOS_DEVICE_NOT_FOUND;
177 +
178 + spin_lock_irqsave(&dev->lock, flags);
179 + switch (size) {
180 + case 1:
181 + gige_pcicfg_write8(dev, reg, val);
182 + break;
183 + case 2:
184 + gige_pcicfg_write16(dev, reg, val);
185 + break;
186 + case 4:
187 + gige_pcicfg_write32(dev, reg, val);
188 + break;
189 + default:
190 + WARN_ON(1);
191 + }
192 + spin_unlock_irqrestore(&dev->lock, flags);
193 +
194 + return PCIBIOS_SUCCESSFUL;
195 +}
196 +
197 +static int ssb_gige_probe(struct ssb_device *sdev, const struct ssb_device_id *id)
198 +{
199 + struct ssb_gige *dev;
200 + u32 base, tmslow, tmshigh;
201 +
202 + dev = kzalloc(sizeof(*dev), GFP_KERNEL);
203 + if (!dev)
204 + return -ENOMEM;
205 + dev->dev = sdev;
206 +
207 + spin_lock_init(&dev->lock);
208 + dev->pci_controller.pci_ops = &dev->pci_ops;
209 + dev->pci_controller.io_resource = &dev->io_resource;
210 + dev->pci_controller.mem_resource = &dev->mem_resource;
211 + dev->pci_controller.io_map_base = 0x800;
212 + dev->pci_ops.read = ssb_gige_pci_read_config;
213 + dev->pci_ops.write = ssb_gige_pci_write_config;
214 +
215 + dev->io_resource.name = SSB_GIGE_IO_RES_NAME;
216 + dev->io_resource.start = 0x800;
217 + dev->io_resource.end = 0x8FF;
218 + dev->io_resource.flags = IORESOURCE_IO | IORESOURCE_PCI_FIXED;
219 +
220 + if (!ssb_device_is_enabled(sdev))
221 + ssb_device_enable(sdev, 0);
222 +
223 + /* Setup BAR0. This is a 64k MMIO region. */
224 + base = ssb_admatch_base(ssb_read32(sdev, SSB_ADMATCH1));
225 + gige_pcicfg_write32(dev, PCI_BASE_ADDRESS_0, base);
226 + gige_pcicfg_write32(dev, PCI_BASE_ADDRESS_1, 0);
227 +
228 + dev->mem_resource.name = SSB_GIGE_MEM_RES_NAME;
229 + dev->mem_resource.start = base;
230 + dev->mem_resource.end = base + 0x10000 - 1;
231 + dev->mem_resource.flags = IORESOURCE_MEM | IORESOURCE_PCI_FIXED;
232 +
233 + /* Enable the memory region. */
234 + gige_pcicfg_write16(dev, PCI_COMMAND,
235 + gige_pcicfg_read16(dev, PCI_COMMAND)
236 + | PCI_COMMAND_MEMORY);
237 +
238 + /* Write flushing is controlled by the Flush Status Control register.
239 + * We want to flush every register write with a timeout and we want
240 + * to disable the IRQ mask while flushing to avoid concurrency.
241 + * Note that automatic write flushing does _not_ work from
242 + * an IRQ handler. The driver must flush manually by reading a register.
243 + */
244 + gige_write32(dev, SSB_GIGE_SHIM_FLUSHSTAT, 0x00000068);
245 +
246 + /* Check if we have an RGMII or GMII PHY-bus.
247 + * On RGMII do not bypass the DLLs */
248 + tmslow = ssb_read32(sdev, SSB_TMSLOW);
249 + tmshigh = ssb_read32(sdev, SSB_TMSHIGH);
250 + if (tmshigh & SSB_GIGE_TMSHIGH_RGMII) {
251 + tmslow &= ~SSB_GIGE_TMSLOW_TXBYPASS;
252 + tmslow &= ~SSB_GIGE_TMSLOW_RXBYPASS;
253 + dev->has_rgmii = 1;
254 + } else {
255 + tmslow |= SSB_GIGE_TMSLOW_TXBYPASS;
256 + tmslow |= SSB_GIGE_TMSLOW_RXBYPASS;
257 + dev->has_rgmii = 0;
258 + }
259 + tmslow |= SSB_GIGE_TMSLOW_DLLEN;
260 + ssb_write32(sdev, SSB_TMSLOW, tmslow);
261 +
262 + ssb_set_drvdata(sdev, dev);
263 + register_pci_controller(&dev->pci_controller);
264 +
265 + return 0;
266 +}
267 +
268 +bool pdev_is_ssb_gige_core(struct pci_dev *pdev)
269 +{
270 + if (!pdev->resource[0].name)
271 + return 0;
272 + return (strcmp(pdev->resource[0].name, SSB_GIGE_MEM_RES_NAME) == 0);
273 +}
274 +EXPORT_SYMBOL(pdev_is_ssb_gige_core);
275 +
276 +int ssb_gige_pcibios_plat_dev_init(struct ssb_device *sdev,
277 + struct pci_dev *pdev)
278 +{
279 + struct ssb_gige *dev = ssb_get_drvdata(sdev);
280 + struct resource *res;
281 +
282 + if (pdev->bus->ops != &dev->pci_ops) {
283 + /* The PCI device is not on this SSB GigE bridge device. */
284 + return -ENODEV;
285 + }
286 +
287 + /* Fixup the PCI resources. */
288 + res = &(pdev->resource[0]);
289 + res->flags = IORESOURCE_MEM | IORESOURCE_PCI_FIXED;
290 + res->name = dev->mem_resource.name;
291 + res->start = dev->mem_resource.start;
292 + res->end = dev->mem_resource.end;
293 +
294 + /* Fixup interrupt lines. */
295 + pdev->irq = ssb_mips_irq(sdev) + 2;
296 + pci_write_config_byte(pdev, PCI_INTERRUPT_LINE, pdev->irq);
297 +
298 + return 0;
299 +}
300 +
301 +int ssb_gige_map_irq(struct ssb_device *sdev,
302 + const struct pci_dev *pdev)
303 +{
304 + struct ssb_gige *dev = ssb_get_drvdata(sdev);
305 +
306 + if (pdev->bus->ops != &dev->pci_ops) {
307 + /* The PCI device is not on this SSB GigE bridge device. */
308 + return -ENODEV;
309 + }
310 +
311 + return ssb_mips_irq(sdev) + 2;
312 +}
313 +
314 +static struct ssb_driver ssb_gige_driver = {
315 + .name = "BCM-GigE",
316 + .id_table = ssb_gige_tbl,
317 + .probe = ssb_gige_probe,
318 +};
319 +
320 +int ssb_gige_init(void)
321 +{
322 + return ssb_driver_register(&ssb_gige_driver);
323 +}
324 --- /dev/null
325 +++ b/include/linux/ssb/ssb_driver_gige.h
326 @@ -0,0 +1,174 @@
327 +#ifndef LINUX_SSB_DRIVER_GIGE_H_
328 +#define LINUX_SSB_DRIVER_GIGE_H_
329 +
330 +#include <linux/ssb/ssb.h>
331 +#include <linux/pci.h>
332 +#include <linux/spinlock.h>
333 +
334 +
335 +#ifdef CONFIG_SSB_DRIVER_GIGE
336 +
337 +
338 +#define SSB_GIGE_PCIIO 0x0000 /* PCI I/O Registers (1024 bytes) */
339 +#define SSB_GIGE_RESERVED 0x0400 /* Reserved (1024 bytes) */
340 +#define SSB_GIGE_PCICFG 0x0800 /* PCI config space (256 bytes) */
341 +#define SSB_GIGE_SHIM_FLUSHSTAT 0x0C00 /* PCI to OCP: Flush status control (32bit) */
342 +#define SSB_GIGE_SHIM_FLUSHRDA 0x0C04 /* PCI to OCP: Flush read address (32bit) */
343 +#define SSB_GIGE_SHIM_FLUSHTO 0x0C08 /* PCI to OCP: Flush timeout counter (32bit) */
344 +#define SSB_GIGE_SHIM_BARRIER 0x0C0C /* PCI to OCP: Barrier register (32bit) */
345 +#define SSB_GIGE_SHIM_MAOCPSI 0x0C10 /* PCI to OCP: MaocpSI Control (32bit) */
346 +#define SSB_GIGE_SHIM_SIOCPMA 0x0C14 /* PCI to OCP: SiocpMa Control (32bit) */
347 +
348 +/* TM Status High flags */
349 +#define SSB_GIGE_TMSHIGH_RGMII 0x00010000 /* Have an RGMII PHY-bus */
350 +/* TM Status Low flags */
351 +#define SSB_GIGE_TMSLOW_TXBYPASS 0x00080000 /* TX bypass (no delay) */
352 +#define SSB_GIGE_TMSLOW_RXBYPASS 0x00100000 /* RX bypass (no delay) */
353 +#define SSB_GIGE_TMSLOW_DLLEN 0x01000000 /* Enable DLL controls */
354 +
355 +/* Boardflags (low) */
356 +#define SSB_GIGE_BFL_ROBOSWITCH 0x0010
357 +
358 +
359 +#define SSB_GIGE_MEM_RES_NAME "SSB Broadcom 47xx GigE memory"
360 +#define SSB_GIGE_IO_RES_NAME "SSB Broadcom 47xx GigE I/O"
361 +
362 +struct ssb_gige {
363 + struct ssb_device *dev;
364 +
365 + spinlock_t lock;
366 +
367 + /* True, if the device has an RGMII bus.
368 + * False, if the device has a GMII bus. */
369 + bool has_rgmii;
370 +
371 + /* The PCI controller device. */
372 + struct pci_controller pci_controller;
373 + struct pci_ops pci_ops;
374 + struct resource mem_resource;
375 + struct resource io_resource;
376 +};
377 +
378 +/* Check whether a PCI device is a SSB Gigabit Ethernet core. */
379 +extern bool pdev_is_ssb_gige_core(struct pci_dev *pdev);
380 +
381 +/* Convert a pci_dev pointer to a ssb_gige pointer. */
382 +static inline struct ssb_gige * pdev_to_ssb_gige(struct pci_dev *pdev)
383 +{
384 + if (!pdev_is_ssb_gige_core(pdev))
385 + return NULL;
386 + return container_of(pdev->bus->ops, struct ssb_gige, pci_ops);
387 +}
388 +
389 +/* Returns whether the PHY is connected by an RGMII bus. */
390 +static inline bool ssb_gige_is_rgmii(struct pci_dev *pdev)
391 +{
392 + struct ssb_gige *dev = pdev_to_ssb_gige(pdev);
393 + return (dev ? dev->has_rgmii : 0);
394 +}
395 +
396 +/* Returns whether we have a Roboswitch. */
397 +static inline bool ssb_gige_have_roboswitch(struct pci_dev *pdev)
398 +{
399 + struct ssb_gige *dev = pdev_to_ssb_gige(pdev);
400 + if (dev)
401 + return !!(dev->dev->bus->sprom.boardflags_lo &
402 + SSB_GIGE_BFL_ROBOSWITCH);
403 + return 0;
404 +}
405 +
406 +/* Returns whether we can only do one DMA at once. */
407 +static inline bool ssb_gige_one_dma_at_once(struct pci_dev *pdev)
408 +{
409 + struct ssb_gige *dev = pdev_to_ssb_gige(pdev);
410 + if (dev)
411 + return ((dev->dev->bus->chip_id == 0x4785) &&
412 + (dev->dev->bus->chip_rev < 2));
413 + return 0;
414 +}
415 +
416 +/* Returns whether we must flush posted writes. */
417 +static inline bool ssb_gige_must_flush_posted_writes(struct pci_dev *pdev)
418 +{
419 + struct ssb_gige *dev = pdev_to_ssb_gige(pdev);
420 + if (dev)
421 + return (dev->dev->bus->chip_id == 0x4785);
422 + return 0;
423 +}
424 +
425 +extern char * nvram_get(const char *name);
426 +/* Get the device MAC address */
427 +static inline void ssb_gige_get_macaddr(struct pci_dev *pdev, u8 *macaddr)
428 +{
429 +#ifdef CONFIG_BCM947XX
430 + char *res = nvram_get("et0macaddr");
431 + if (res)
432 + memcpy(macaddr, res, 6);
433 +#endif
434 +}
435 +
436 +extern int ssb_gige_pcibios_plat_dev_init(struct ssb_device *sdev,
437 + struct pci_dev *pdev);
438 +extern int ssb_gige_map_irq(struct ssb_device *sdev,
439 + const struct pci_dev *pdev);
440 +
441 +/* The GigE driver is not a standalone module, because we don't have support
442 + * for unregistering the driver. So we could not unload the module anyway. */
443 +extern int ssb_gige_init(void);
444 +static inline void ssb_gige_exit(void)
445 +{
446 + /* Currently we can not unregister the GigE driver,
447 + * because we can not unregister the PCI bridge. */
448 + BUG();
449 +}
450 +
451 +
452 +#else /* CONFIG_SSB_DRIVER_GIGE */
453 +/* Gigabit Ethernet driver disabled */
454 +
455 +
456 +static inline int ssb_gige_pcibios_plat_dev_init(struct ssb_device *sdev,
457 + struct pci_dev *pdev)
458 +{
459 + return -ENOSYS;
460 +}
461 +static inline int ssb_gige_map_irq(struct ssb_device *sdev,
462 + const struct pci_dev *pdev)
463 +{
464 + return -ENOSYS;
465 +}
466 +static inline int ssb_gige_init(void)
467 +{
468 + return 0;
469 +}
470 +static inline void ssb_gige_exit(void)
471 +{
472 +}
473 +
474 +static inline bool pdev_is_ssb_gige_core(struct pci_dev *pdev)
475 +{
476 + return 0;
477 +}
478 +static inline struct ssb_gige * pdev_to_ssb_gige(struct pci_dev *pdev)
479 +{
480 + return NULL;
481 +}
482 +static inline bool ssb_gige_is_rgmii(struct pci_dev *pdev)
483 +{
484 + return 0;
485 +}
486 +static inline bool ssb_gige_have_roboswitch(struct pci_dev *pdev)
487 +{
488 + return 0;
489 +}
490 +static inline bool ssb_gige_one_dma_at_once(struct pci_dev *pdev)
491 +{
492 + return 0;
493 +}
494 +static inline bool ssb_gige_must_flush_posted_writes(struct pci_dev *pdev)
495 +{
496 + return 0;
497 +}
498 +
499 +#endif /* CONFIG_SSB_DRIVER_GIGE */
500 +#endif /* LINUX_SSB_DRIVER_GIGE_H_ */
501 --- a/drivers/ssb/driver_pcicore.c
502 +++ b/drivers/ssb/driver_pcicore.c
503 @@ -60,78 +60,6 @@
504 /* Core to access the external PCI config space. Can only have one. */
505 static struct ssb_pcicore *extpci_core;
506
507 -static u32 ssb_pcicore_pcibus_iobase = 0x100;
508 -static u32 ssb_pcicore_pcibus_membase = SSB_PCI_DMA;
509 -
510 -int pcibios_plat_dev_init(struct pci_dev *d)
511 -{
512 - struct resource *res;
513 - int pos, size;
514 - u32 *base;
515 -
516 - ssb_printk(KERN_INFO "PCI: Fixing up device %s\n",
517 - pci_name(d));
518 -
519 - /* Fix up resource bases */
520 - for (pos = 0; pos < 6; pos++) {
521 - res = &d->resource[pos];
522 - if (res->flags & IORESOURCE_IO)
523 - base = &ssb_pcicore_pcibus_iobase;
524 - else
525 - base = &ssb_pcicore_pcibus_membase;
526 - res->flags |= IORESOURCE_PCI_FIXED;
527 - if (res->end) {
528 - size = res->end - res->start + 1;
529 - if (*base & (size - 1))
530 - *base = (*base + size) & ~(size - 1);
531 - res->start = *base;
532 - res->end = res->start + size - 1;
533 - *base += size;
534 - pci_write_config_dword(d, PCI_BASE_ADDRESS_0 + (pos << 2), res->start);
535 - }
536 - /* Fix up PCI bridge BAR0 only */
537 - if (d->bus->number == 0 && PCI_SLOT(d->devfn) == 0)
538 - break;
539 - }
540 - /* Fix up interrupt lines */
541 - d->irq = ssb_mips_irq(extpci_core->dev) + 2;
542 - pci_write_config_byte(d, PCI_INTERRUPT_LINE, d->irq);
543 -
544 - return 0;
545 -}
546 -
547 -static void __init ssb_fixup_pcibridge(struct pci_dev *dev)
548 -{
549 - u8 lat;
550 -
551 - if (dev->bus->number != 0 || PCI_SLOT(dev->devfn) != 0)
552 - return;
553 -
554 - ssb_printk(KERN_INFO "PCI: Fixing up bridge %s\n", pci_name(dev));
555 -
556 - /* Enable PCI bridge bus mastering and memory space */
557 - pci_set_master(dev);
558 - if (pcibios_enable_device(dev, ~0) < 0) {
559 - ssb_printk(KERN_ERR "PCI: SSB bridge enable failed\n");
560 - return;
561 - }
562 -
563 - /* Enable PCI bridge BAR1 prefetch and burst */
564 - pci_write_config_dword(dev, SSB_BAR1_CONTROL, 3);
565 -
566 - /* Make sure our latency is high enough to handle the devices behind us */
567 - lat = 168;
568 - ssb_printk(KERN_INFO "PCI: Fixing latency timer of device %s to %u\n",
569 - pci_name(dev), lat);
570 - pci_write_config_byte(dev, PCI_LATENCY_TIMER, lat);
571 -}
572 -DECLARE_PCI_FIXUP_EARLY(PCI_ANY_ID, PCI_ANY_ID, ssb_fixup_pcibridge);
573 -
574 -int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
575 -{
576 - return ssb_mips_irq(extpci_core->dev) + 2;
577 -}
578 -
579 static u32 get_cfgspace_addr(struct ssb_pcicore *pc,
580 unsigned int bus, unsigned int dev,
581 unsigned int func, unsigned int off)
582 @@ -320,6 +248,95 @@
583 .mem_offset = 0x24000000,
584 };
585
586 +static u32 ssb_pcicore_pcibus_iobase = 0x100;
587 +static u32 ssb_pcicore_pcibus_membase = SSB_PCI_DMA;
588 +
589 +/* This function is called when doing a pci_enable_device().
590 + * We must first check if the device is a device on the PCI-core bridge. */
591 +int ssb_pcicore_plat_dev_init(struct pci_dev *d)
592 +{
593 + struct resource *res;
594 + int pos, size;
595 + u32 *base;
596 +
597 + if (d->bus->ops != &ssb_pcicore_pciops) {
598 + /* This is not a device on the PCI-core bridge. */
599 + return -ENODEV;
600 + }
601 +
602 + ssb_printk(KERN_INFO "PCI: Fixing up device %s\n",
603 + pci_name(d));
604 +
605 + /* Fix up resource bases */
606 + for (pos = 0; pos < 6; pos++) {
607 + res = &d->resource[pos];
608 + if (res->flags & IORESOURCE_IO)
609 + base = &ssb_pcicore_pcibus_iobase;
610 + else
611 + base = &ssb_pcicore_pcibus_membase;
612 + res->flags |= IORESOURCE_PCI_FIXED;
613 + if (res->end) {
614 + size = res->end - res->start + 1;
615 + if (*base & (size - 1))
616 + *base = (*base + size) & ~(size - 1);
617 + res->start = *base;
618 + res->end = res->start + size - 1;
619 + *base += size;
620 + pci_write_config_dword(d, PCI_BASE_ADDRESS_0 + (pos << 2), res->start);
621 + }
622 + /* Fix up PCI bridge BAR0 only */
623 + if (d->bus->number == 0 && PCI_SLOT(d->devfn) == 0)
624 + break;
625 + }
626 + /* Fix up interrupt lines */
627 + d->irq = ssb_mips_irq(extpci_core->dev) + 2;
628 + pci_write_config_byte(d, PCI_INTERRUPT_LINE, d->irq);
629 +
630 + return 0;
631 +}
632 +
633 +/* Early PCI fixup for a device on the PCI-core bridge. */
634 +static void ssb_pcicore_fixup_pcibridge(struct pci_dev *dev)
635 +{
636 + u8 lat;
637 +
638 + if (dev->bus->ops != &ssb_pcicore_pciops) {
639 + /* This is not a device on the PCI-core bridge. */
640 + return;
641 + }
642 + if (dev->bus->number != 0 || PCI_SLOT(dev->devfn) != 0)
643 + return;
644 +
645 + ssb_printk(KERN_INFO "PCI: Fixing up bridge %s\n", pci_name(dev));
646 +
647 + /* Enable PCI bridge bus mastering and memory space */
648 + pci_set_master(dev);
649 + if (pcibios_enable_device(dev, ~0) < 0) {
650 + ssb_printk(KERN_ERR "PCI: SSB bridge enable failed\n");
651 + return;
652 + }
653 +
654 + /* Enable PCI bridge BAR1 prefetch and burst */
655 + pci_write_config_dword(dev, SSB_BAR1_CONTROL, 3);
656 +
657 + /* Make sure our latency is high enough to handle the devices behind us */
658 + lat = 168;
659 + ssb_printk(KERN_INFO "PCI: Fixing latency timer of device %s to %u\n",
660 + pci_name(dev), lat);
661 + pci_write_config_byte(dev, PCI_LATENCY_TIMER, lat);
662 +}
663 +DECLARE_PCI_FIXUP_EARLY(PCI_ANY_ID, PCI_ANY_ID, ssb_pcicore_fixup_pcibridge);
664 +
665 +/* PCI device IRQ mapping. */
666 +int ssb_pcicore_pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
667 +{
668 + if (dev->bus->ops != &ssb_pcicore_pciops) {
669 + /* This is not a device on the PCI-core bridge. */
670 + return -ENODEV;
671 + }
672 + return ssb_mips_irq(extpci_core->dev) + 2;
673 +}
674 +
675 static void ssb_pcicore_init_hostmode(struct ssb_pcicore *pc)
676 {
677 u32 val;
678 --- a/drivers/ssb/embedded.c
679 +++ b/drivers/ssb/embedded.c
680 @@ -10,6 +10,9 @@
681
682 #include <linux/ssb/ssb.h>
683 #include <linux/ssb/ssb_embedded.h>
684 +#include <linux/ssb/ssb_driver_pci.h>
685 +#include <linux/ssb/ssb_driver_gige.h>
686 +#include <linux/pci.h>
687
688 #include "ssb_private.h"
689
690 @@ -130,3 +133,90 @@
691 return res;
692 }
693 EXPORT_SYMBOL(ssb_gpio_polarity);
694 +
695 +#ifdef CONFIG_SSB_DRIVER_GIGE
696 +static int gige_pci_init_callback(struct ssb_bus *bus, unsigned long data)
697 +{
698 + struct pci_dev *pdev = (struct pci_dev *)data;
699 + struct ssb_device *dev;
700 + unsigned int i;
701 + int res;
702 +
703 + for (i = 0; i < bus->nr_devices; i++) {
704 + dev = &(bus->devices[i]);
705 + if (dev->id.coreid != SSB_DEV_ETHERNET_GBIT)
706 + continue;
707 + if (!dev->dev ||
708 + !dev->dev->driver ||
709 + !device_is_registered(dev->dev))
710 + continue;
711 + res = ssb_gige_pcibios_plat_dev_init(dev, pdev);
712 + if (res >= 0)
713 + return res;
714 + }
715 +
716 + return -ENODEV;
717 +}
718 +#endif /* CONFIG_SSB_DRIVER_GIGE */
719 +
720 +int ssb_pcibios_plat_dev_init(struct pci_dev *dev)
721 +{
722 + int err;
723 +
724 + err = ssb_pcicore_plat_dev_init(dev);
725 + if (!err)
726 + return 0;
727 +#ifdef CONFIG_SSB_DRIVER_GIGE
728 + err = ssb_for_each_bus_call((unsigned long)dev, gige_pci_init_callback);
729 + if (err >= 0)
730 + return err;
731 +#endif
732 + /* This is not a PCI device on any SSB device. */
733 +
734 + return -ENODEV;
735 +}
736 +
737 +#ifdef CONFIG_SSB_DRIVER_GIGE
738 +static int gige_map_irq_callback(struct ssb_bus *bus, unsigned long data)
739 +{
740 + const struct pci_dev *pdev = (const struct pci_dev *)data;
741 + struct ssb_device *dev;
742 + unsigned int i;
743 + int res;
744 +
745 + for (i = 0; i < bus->nr_devices; i++) {
746 + dev = &(bus->devices[i]);
747 + if (dev->id.coreid != SSB_DEV_ETHERNET_GBIT)
748 + continue;
749 + if (!dev->dev ||
750 + !dev->dev->driver ||
751 + !device_is_registered(dev->dev))
752 + continue;
753 + res = ssb_gige_map_irq(dev, pdev);
754 + if (res >= 0)
755 + return res;
756 + }
757 +
758 + return -ENODEV;
759 +}
760 +#endif /* CONFIG_SSB_DRIVER_GIGE */
761 +
762 +int ssb_pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
763 +{
764 + int res;
765 +
766 + /* Check if this PCI device is a device on a SSB bus or device
767 + * and return the IRQ number for it. */
768 +
769 + res = ssb_pcicore_pcibios_map_irq(dev, slot, pin);
770 + if (res >= 0)
771 + return res;
772 +#ifdef CONFIG_SSB_DRIVER_GIGE
773 + res = ssb_for_each_bus_call((unsigned long)dev, gige_map_irq_callback);
774 + if (res >= 0)
775 + return res;
776 +#endif
777 + /* This is not a PCI device on any SSB device. */
778 +
779 + return -ENODEV;
780 +}
781 --- a/include/linux/ssb/ssb.h
782 +++ b/include/linux/ssb/ssb.h
783 @@ -426,5 +426,12 @@
784 extern u32 ssb_admatch_base(u32 adm);
785 extern u32 ssb_admatch_size(u32 adm);
786
787 +/* PCI device mapping and fixup routines.
788 + * Called from the architecture pcibios init code.
789 + * These are only available on SSB_EMBEDDED configurations. */
790 +#ifdef CONFIG_SSB_EMBEDDED
791 +int ssb_pcibios_plat_dev_init(struct pci_dev *dev);
792 +int ssb_pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin);
793 +#endif /* CONFIG_SSB_EMBEDDED */
794
795 #endif /* LINUX_SSB_H_ */
796 --- a/include/linux/ssb/ssb_driver_pci.h
797 +++ b/include/linux/ssb/ssb_driver_pci.h
798 @@ -1,6 +1,11 @@
799 #ifndef LINUX_SSB_PCICORE_H_
800 #define LINUX_SSB_PCICORE_H_
801
802 +#include <linux/types.h>
803 +
804 +struct pci_dev;
805 +
806 +
807 #ifdef CONFIG_SSB_DRIVER_PCICORE
808
809 /* PCI core registers. */
810 @@ -88,6 +93,9 @@
811 extern int ssb_pcicore_dev_irqvecs_enable(struct ssb_pcicore *pc,
812 struct ssb_device *dev);
813
814 +int ssb_pcicore_plat_dev_init(struct pci_dev *d);
815 +int ssb_pcicore_pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin);
816 +
817
818 #else /* CONFIG_SSB_DRIVER_PCICORE */
819
820 @@ -107,5 +115,16 @@
821 return 0;
822 }
823
824 +static inline
825 +int ssb_pcicore_plat_dev_init(struct pci_dev *d)
826 +{
827 + return -ENODEV;
828 +}
829 +static inline
830 +int ssb_pcicore_pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
831 +{
832 + return -ENODEV;
833 +}
834 +
835 #endif /* CONFIG_SSB_DRIVER_PCICORE */
836 #endif /* LINUX_SSB_PCICORE_H_ */
837 --- a/drivers/ssb/main.c
838 +++ b/drivers/ssb/main.c
839 @@ -14,6 +14,7 @@
840 #include <linux/io.h>
841 #include <linux/ssb/ssb.h>
842 #include <linux/ssb/ssb_regs.h>
843 +#include <linux/ssb/ssb_driver_gige.h>
844 #include <linux/dma-mapping.h>
845 #include <linux/pci.h>
846
847 @@ -68,6 +69,25 @@
848 }
849 #endif /* CONFIG_SSB_PCIHOST */
850
851 +int ssb_for_each_bus_call(unsigned long data,
852 + int (*func)(struct ssb_bus *bus, unsigned long data))
853 +{
854 + struct ssb_bus *bus;
855 + int res;
856 +
857 + ssb_buses_lock();
858 + list_for_each_entry(bus, &buses, list) {
859 + res = func(bus, data);
860 + if (res >= 0) {
861 + ssb_buses_unlock();
862 + return res;
863 + }
864 + }
865 + ssb_buses_unlock();
866 +
867 + return -ENODEV;
868 +}
869 +
870 static struct ssb_device *ssb_device_get(struct ssb_device *dev)
871 {
872 if (dev)
873 @@ -1181,7 +1201,14 @@
874 err = b43_pci_ssb_bridge_init();
875 if (err) {
876 ssb_printk(KERN_ERR "Broadcom 43xx PCI-SSB-bridge "
877 - "initialization failed");
878 + "initialization failed\n");
879 + /* don't fail SSB init because of this */
880 + err = 0;
881 + }
882 + err = ssb_gige_init();
883 + if (err) {
884 + ssb_printk(KERN_ERR "SSB Broadcom Gigabit Ethernet "
885 + "driver initialization failed\n");
886 /* don't fail SSB init because of this */
887 err = 0;
888 }
889 @@ -1195,6 +1222,7 @@
890
891 static void __exit ssb_modexit(void)
892 {
893 + ssb_gige_exit();
894 b43_pci_ssb_bridge_exit();
895 bus_unregister(&ssb_bustype);
896 }
897 --- a/drivers/ssb/ssb_private.h
898 +++ b/drivers/ssb/ssb_private.h
899 @@ -118,6 +118,8 @@
900 extern int ssb_devices_freeze(struct ssb_bus *bus);
901 extern int ssb_devices_thaw(struct ssb_bus *bus);
902 extern struct ssb_bus *ssb_pci_dev_to_bus(struct pci_dev *pdev);
903 +int ssb_for_each_bus_call(unsigned long data,
904 + int (*func)(struct ssb_bus *bus, unsigned long data));
905
906 /* b43_pci_bridge.c */
907 #ifdef CONFIG_SSB_B43_PCI_BRIDGE
908 --- a/drivers/net/tg3.c
909 +++ b/drivers/net/tg3.c
910 @@ -38,6 +38,7 @@
911 #include <linux/workqueue.h>
912 #include <linux/prefetch.h>
913 #include <linux/dma-mapping.h>
914 +#include <linux/ssb/ssb_driver_gige.h>
915
916 #include <net/checksum.h>
917 #include <net/ip.h>
918 @@ -425,8 +426,9 @@
919 static inline void tw32_mailbox_flush(struct tg3 *tp, u32 off, u32 val)
920 {
921 tp->write32_mbox(tp, off, val);
922 - if (!(tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) &&
923 - !(tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND))
924 + if ((tp->tg3_flags3 & TG3_FLG3_FLUSH_POSTED_WRITES) ||
925 + (!(tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) &&
926 + !(tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND)))
927 tp->read32_mbox(tp, off);
928 }
929
930 @@ -706,7 +708,7 @@
931
932 #define PHY_BUSY_LOOPS 5000
933
934 -static int tg3_readphy(struct tg3 *tp, int reg, u32 *val)
935 +static int __tg3_readphy(struct tg3 *tp, unsigned int phy_addr, int reg, u32 *val)
936 {
937 u32 frame_val;
938 unsigned int loops;
939 @@ -720,7 +722,7 @@
940
941 *val = 0x0;
942
943 - frame_val = ((PHY_ADDR << MI_COM_PHY_ADDR_SHIFT) &
944 + frame_val = ((phy_addr << MI_COM_PHY_ADDR_SHIFT) &
945 MI_COM_PHY_ADDR_MASK);
946 frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
947 MI_COM_REG_ADDR_MASK);
948 @@ -755,7 +757,12 @@
949 return ret;
950 }
951
952 -static int tg3_writephy(struct tg3 *tp, int reg, u32 val)
953 +static int tg3_readphy(struct tg3 *tp, int reg, u32 *val)
954 +{
955 + return __tg3_readphy(tp, PHY_ADDR, reg, val);
956 +}
957 +
958 +static int __tg3_writephy(struct tg3 *tp, unsigned int phy_addr, int reg, u32 val)
959 {
960 u32 frame_val;
961 unsigned int loops;
962 @@ -771,7 +778,7 @@
963 udelay(80);
964 }
965
966 - frame_val = ((PHY_ADDR << MI_COM_PHY_ADDR_SHIFT) &
967 + frame_val = ((phy_addr << MI_COM_PHY_ADDR_SHIFT) &
968 MI_COM_PHY_ADDR_MASK);
969 frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
970 MI_COM_REG_ADDR_MASK);
971 @@ -804,6 +811,11 @@
972 return ret;
973 }
974
975 +static int tg3_writephy(struct tg3 *tp, int reg, u32 val)
976 +{
977 + return __tg3_writephy(tp, PHY_ADDR, reg, val);
978 +}
979 +
980 static void tg3_phydsp_write(struct tg3 *tp, u32 reg, u32 val)
981 {
982 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, reg);
983 @@ -2250,6 +2262,14 @@
984 }
985 }
986
987 + if (tp->tg3_flags & TG3_FLG3_ROBOSWITCH) {
988 + current_link_up = 1;
989 + current_speed = SPEED_1000; //FIXME
990 + current_duplex = DUPLEX_FULL;
991 + tp->link_config.active_speed = current_speed;
992 + tp->link_config.active_duplex = current_duplex;
993 + }
994 +
995 if (current_link_up == 1 &&
996 tp->link_config.active_duplex == DUPLEX_FULL)
997 tg3_setup_flow_control(tp, lcl_adv, rmt_adv);
998 @@ -5197,6 +5217,11 @@
999 int i;
1000 u32 val;
1001
1002 + if (tp->tg3_flags3 & TG3_FLG3_IS_SSB_CORE) {
1003 + /* We don't use firmware. */
1004 + return 0;
1005 + }
1006 +
1007 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
1008 /* Wait up to 20ms for init done. */
1009 for (i = 0; i < 200; i++) {
1010 @@ -5435,6 +5460,14 @@
1011 tw32(0x5000, 0x400);
1012 }
1013
1014 + if (tp->tg3_flags3 & TG3_FLG3_IS_SSB_CORE) {
1015 + /* BCM4785: In order to avoid repercussions from using potentially
1016 + * defective internal ROM, stop the Rx RISC CPU, which is not
1017 + * required. */
1018 + tg3_stop_fw(tp);
1019 + tg3_halt_cpu(tp, RX_CPU_BASE);
1020 + }
1021 +
1022 tw32(GRC_MODE, tp->grc_mode);
1023
1024 if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0) {
1025 @@ -5704,9 +5737,12 @@
1026 return -ENODEV;
1027 }
1028
1029 - /* Clear firmware's nvram arbitration. */
1030 - if (tp->tg3_flags & TG3_FLAG_NVRAM)
1031 - tw32(NVRAM_SWARB, SWARB_REQ_CLR0);
1032 + if (!(tp->tg3_flags3 & TG3_FLG3_IS_SSB_CORE)) {
1033 + /* Clear firmware's nvram arbitration. */
1034 + if (tp->tg3_flags & TG3_FLAG_NVRAM)
1035 + tw32(NVRAM_SWARB, SWARB_REQ_CLR0);
1036 + }
1037 +
1038 return 0;
1039 }
1040
1041 @@ -5787,6 +5823,11 @@
1042 struct fw_info info;
1043 int err, i;
1044
1045 + if (tp->tg3_flags3 & TG3_FLG3_IS_SSB_CORE) {
1046 + /* We don't use firmware. */
1047 + return 0;
1048 + }
1049 +
1050 info.text_base = TG3_FW_TEXT_ADDR;
1051 info.text_len = TG3_FW_TEXT_LEN;
1052 info.text_data = &tg3FwText[0];
1053 @@ -6345,6 +6386,11 @@
1054 unsigned long cpu_base, cpu_scratch_base, cpu_scratch_size;
1055 int err, i;
1056
1057 + if (tp->tg3_flags3 & TG3_FLG3_IS_SSB_CORE) {
1058 + /* We don't use firmware. */
1059 + return 0;
1060 + }
1061 +
1062 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
1063 return 0;
1064
1065 @@ -7306,6 +7352,11 @@
1066
1067 spin_lock(&tp->lock);
1068
1069 + if (tp->tg3_flags3 & TG3_FLG3_FLUSH_POSTED_WRITES) {
1070 + /* BCM4785: Flush posted writes from GbE to host memory. */
1071 + tr32(HOSTCC_MODE);
1072 + }
1073 +
1074 if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)) {
1075 /* All of this garbage is because when using non-tagged
1076 * IRQ status the mailbox/status_block protocol the chip
1077 @@ -8906,6 +8957,11 @@
1078 __le32 *buf;
1079 int i, j, k, err = 0, size;
1080
1081 + if (tp->tg3_flags3 & TG3_FLG3_IS_SSB_CORE) {
1082 + /* We don't have NVRAM. */
1083 + return 0;
1084 + }
1085 +
1086 if (tg3_nvram_read_swab(tp, 0, &magic) != 0)
1087 return -EIO;
1088
1089 @@ -9689,7 +9745,7 @@
1090 return -EAGAIN;
1091
1092 spin_lock_bh(&tp->lock);
1093 - err = tg3_readphy(tp, data->reg_num & 0x1f, &mii_regval);
1094 + err = __tg3_readphy(tp, data->phy_id & 0x1f, data->reg_num & 0x1f, &mii_regval);
1095 spin_unlock_bh(&tp->lock);
1096
1097 data->val_out = mii_regval;
1098 @@ -9708,7 +9764,7 @@
1099 return -EAGAIN;
1100
1101 spin_lock_bh(&tp->lock);
1102 - err = tg3_writephy(tp, data->reg_num & 0x1f, data->val_in);
1103 + err = __tg3_writephy(tp, data->phy_id & 0x1f, data->reg_num & 0x1f, data->val_in);
1104 spin_unlock_bh(&tp->lock);
1105
1106 return err;
1107 @@ -10177,6 +10233,12 @@
1108 /* Chips other than 5700/5701 use the NVRAM for fetching info. */
1109 static void __devinit tg3_nvram_init(struct tg3 *tp)
1110 {
1111 + if (tp->tg3_flags3 & TG3_FLG3_IS_SSB_CORE) {
1112 + /* No NVRAM and EEPROM on the SSB Broadcom GigE core. */
1113 + tp->tg3_flags &= ~(TG3_FLAG_NVRAM | TG3_FLAG_NVRAM_BUFFERED);
1114 + return;
1115 + }
1116 +
1117 tw32_f(GRC_EEPROM_ADDR,
1118 (EEPROM_ADDR_FSM_RESET |
1119 (EEPROM_DEFAULT_CLOCK_PERIOD <<
1120 @@ -10317,6 +10379,9 @@
1121 {
1122 int ret;
1123
1124 + if (tp->tg3_flags3 & TG3_FLG3_IS_SSB_CORE)
1125 + return -ENODEV;
1126 +
1127 if (!(tp->tg3_flags & TG3_FLAG_NVRAM))
1128 return tg3_nvram_read_using_eeprom(tp, offset, val);
1129
1130 @@ -10563,6 +10628,9 @@
1131 {
1132 int ret;
1133
1134 + if (tp->tg3_flags3 & TG3_FLG3_IS_SSB_CORE)
1135 + return -ENODEV;
1136 +
1137 if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) {
1138 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl &
1139 ~GRC_LCLCTRL_GPIO_OUTPUT1);
1140 @@ -11610,7 +11678,6 @@
1141 tp->write32 = tg3_write_flush_reg32;
1142 }
1143
1144 -
1145 if ((tp->tg3_flags & TG3_FLAG_TXD_MBOX_HWBUG) ||
1146 (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)) {
1147 tp->write32_tx_mbox = tg3_write32_tx_mbox;
1148 @@ -11646,6 +11713,11 @@
1149 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)))
1150 tp->tg3_flags |= TG3_FLAG_SRAM_USE_CONFIG;
1151
1152 + if (tp->tg3_flags3 & TG3_FLG3_FLUSH_POSTED_WRITES) {
1153 + tp->write32_tx_mbox = tg3_write_flush_reg32;
1154 + tp->write32_rx_mbox = tg3_write_flush_reg32;
1155 + }
1156 +
1157 /* Get eeprom hw config before calling tg3_set_power_state().
1158 * In particular, the TG3_FLG2_IS_NIC flag must be
1159 * determined before calling tg3_set_power_state() so that
1160 @@ -12017,6 +12089,10 @@
1161 }
1162
1163 if (!is_valid_ether_addr(&dev->dev_addr[0])) {
1164 + if (tp->tg3_flags3 & TG3_FLG3_IS_SSB_CORE)
1165 + ssb_gige_get_macaddr(tp->pdev, &dev->dev_addr[0]);
1166 + }
1167 + if (!is_valid_ether_addr(&dev->dev_addr[0])) {
1168 #ifdef CONFIG_SPARC
1169 if (!tg3_get_default_macaddr_sparc(tp))
1170 return 0;
1171 @@ -12508,6 +12584,7 @@
1172 case PHY_ID_BCM5704: return "5704";
1173 case PHY_ID_BCM5705: return "5705";
1174 case PHY_ID_BCM5750: return "5750";
1175 + case PHY_ID_BCM5750_2: return "5750-2";
1176 case PHY_ID_BCM5752: return "5752";
1177 case PHY_ID_BCM5714: return "5714";
1178 case PHY_ID_BCM5780: return "5780";
1179 @@ -12695,6 +12772,13 @@
1180 tp->msg_enable = tg3_debug;
1181 else
1182 tp->msg_enable = TG3_DEF_MSG_ENABLE;
1183 + if (pdev_is_ssb_gige_core(pdev)) {
1184 + tp->tg3_flags3 |= TG3_FLG3_IS_SSB_CORE;
1185 + if (ssb_gige_must_flush_posted_writes(pdev))
1186 + tp->tg3_flags3 |= TG3_FLG3_FLUSH_POSTED_WRITES;
1187 + if (ssb_gige_have_roboswitch(pdev))
1188 + tp->tg3_flags3 |= TG3_FLG3_ROBOSWITCH;
1189 + }
1190
1191 /* The word/byte swap controls here control register access byte
1192 * swapping. DMA data byte swapping is controlled in the GRC_MODE
1193 --- a/drivers/net/tg3.h
1194 +++ b/drivers/net/tg3.h
1195 @@ -2477,6 +2477,9 @@
1196 #define TG3_FLG3_ENABLE_APE 0x00000002
1197 #define TG3_FLG3_5761_5784_AX_FIXES 0x00000004
1198 #define TG3_FLG3_5701_DMA_BUG 0x00000008
1199 +#define TG3_FLG3_IS_SSB_CORE 0x00000010
1200 +#define TG3_FLG3_FLUSH_POSTED_WRITES 0x00000020
1201 +#define TG3_FLG3_ROBOSWITCH 0x00000040
1202
1203 struct timer_list timer;
1204 u16 timer_counter;
1205 @@ -2532,6 +2535,7 @@
1206 #define PHY_ID_BCM5714 0x60008340
1207 #define PHY_ID_BCM5780 0x60008350
1208 #define PHY_ID_BCM5755 0xbc050cc0
1209 +#define PHY_ID_BCM5750_2 0xbc050cd0
1210 #define PHY_ID_BCM5787 0xbc050ce0
1211 #define PHY_ID_BCM5756 0xbc050ed0
1212 #define PHY_ID_BCM5784 0xbc050fa0
1213 @@ -2568,7 +2572,7 @@
1214 (X) == PHY_ID_BCM5780 || (X) == PHY_ID_BCM5787 || \
1215 (X) == PHY_ID_BCM5755 || (X) == PHY_ID_BCM5756 || \
1216 (X) == PHY_ID_BCM5906 || (X) == PHY_ID_BCM5761 || \
1217 - (X) == PHY_ID_BCM8002)
1218 + (X) == PHY_ID_BCM8002 || (X) == PHY_ID_BCM5750_2)
1219
1220 struct tg3_hw_stats *hw_stats;
1221 dma_addr_t stats_mapping;
1222 --- a/drivers/ssb/driver_mipscore.c
1223 +++ b/drivers/ssb/driver_mipscore.c
1224 @@ -212,6 +212,7 @@
1225 /* fallthrough */
1226 case SSB_DEV_PCI:
1227 case SSB_DEV_ETHERNET:
1228 + case SSB_DEV_ETHERNET_GBIT:
1229 case SSB_DEV_80211:
1230 case SSB_DEV_USB20_HOST:
1231 /* These devices get their own IRQ line if available, the rest goes on IRQ0 */
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