3 * MTD driver for the SPI Flash Memory support.
5 * Copyright (c) 2005-2006 Atheros Communications Inc.
6 * Copyright (C) 2006-2007 FON Technology, SL.
7 * Copyright (C) 2006-2007 Imre Kaloz <kaloz@openwrt.org>
8 * Copyright (C) 2006-2007 Felix Fietkau <nbd@openwrt.org>
10 * This code is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
16 /*===========================================================================
17 ** !!!! VERY IMPORTANT NOTICE !!!! FLASH DATA STORED IN LITTLE ENDIAN FORMAT
19 ** This module contains the Serial Flash access routines for the Atheros SOC.
20 ** The Atheros SOC integrates a SPI flash controller that is used to access
21 ** serial flash parts. The SPI flash controller executes in "Little Endian"
22 ** mode. THEREFORE, all WRITES and READS from the MIPS CPU must be
23 ** BYTESWAPPED! The SPI Flash controller hardware by default performs READ
24 ** ONLY byteswapping when accessed via the SPI Flash Alias memory region
25 ** (Physical Address 0x0800_0000 - 0x0fff_ffff). The data stored in the
26 ** flash sectors is stored in "Little Endian" format.
28 ** The spiflash_write() routine performs byteswapping on all write
30 **===========================================================================*/
32 #include <linux/kernel.h>
33 #include <linux/module.h>
34 #include <linux/types.h>
35 #include <linux/version.h>
36 #include <linux/errno.h>
37 #include <linux/slab.h>
38 #include <linux/mtd/mtd.h>
39 #include <linux/mtd/partitions.h>
40 #include <linux/platform_device.h>
41 #include <linux/squashfs_fs.h>
42 #include <linux/root_dev.h>
43 #include <linux/delay.h>
44 #include <asm/delay.h>
49 #error This driver currently only works with big endian CPU.
54 #define SPIFLASH "spiflash: "
56 #define MIN(a,b) ((a) < (b) ? (a) : (b))
58 #define busy_wait(condition, wait) \
61 spin_unlock_bh(&spidata->mutex); \
64 else if ((wait == 1) && need_resched()) \
68 spin_lock_bh(&spidata->mutex); \
73 static __u32
spiflash_regread32(int reg
);
74 static void spiflash_regwrite32(int reg
, __u32 data
);
75 static __u32
spiflash_sendcmd (int op
, u32 addr
);
77 int __init
spiflash_init (void);
78 void __exit
spiflash_exit (void);
79 static int spiflash_probe_chip (void);
80 static int spiflash_erase (struct mtd_info
*mtd
,struct erase_info
*instr
);
81 static int spiflash_read (struct mtd_info
*mtd
, loff_t from
,size_t len
,size_t *retlen
,u_char
*buf
);
82 static int spiflash_write (struct mtd_info
*mtd
,loff_t to
,size_t len
,size_t *retlen
,const u_char
*buf
);
84 /* Flash configuration table */
90 } flashconfig_tbl
[MAX_FLASH
] =
93 { STM_1MB_BYTE_COUNT
, STM_1MB_SECTOR_COUNT
, STM_1MB_SECTOR_SIZE
, 0x0},
94 { STM_2MB_BYTE_COUNT
, STM_2MB_SECTOR_COUNT
, STM_2MB_SECTOR_SIZE
, 0x0},
95 { STM_4MB_BYTE_COUNT
, STM_4MB_SECTOR_COUNT
, STM_4MB_SECTOR_SIZE
, 0x0},
96 { STM_8MB_BYTE_COUNT
, STM_8MB_SECTOR_COUNT
, STM_8MB_SECTOR_SIZE
, 0x0},
97 { STM_16MB_BYTE_COUNT
, STM_16MB_SECTOR_COUNT
, STM_16MB_SECTOR_SIZE
, 0x0}
100 /* Mapping of generic opcodes to STM serial flash opcodes */
101 #define SPI_WRITE_ENABLE 0
102 #define SPI_WRITE_DISABLE 1
103 #define SPI_RD_STATUS 2
104 #define SPI_WR_STATUS 3
105 #define SPI_RD_DATA 4
106 #define SPI_FAST_RD_DATA 5
107 #define SPI_PAGE_PROGRAM 6
108 #define SPI_SECTOR_ERASE 7
109 #define SPI_BULK_ERASE 8
110 #define SPI_DEEP_PWRDOWN 9
111 #define SPI_RD_SIG 10
112 #define SPI_MAX_OPCODES 11
119 {STM_OP_WR_ENABLE
, 1, 0},
120 {STM_OP_WR_DISABLE
, 1, 0},
121 {STM_OP_RD_STATUS
, 1, 1},
122 {STM_OP_WR_STATUS
, 1, 0},
123 {STM_OP_RD_DATA
, 4, 4},
124 {STM_OP_FAST_RD_DATA
, 5, 0},
125 {STM_OP_PAGE_PGRM
, 8, 0},
126 {STM_OP_SECTOR_ERASE
, 4, 0},
127 {STM_OP_BULK_ERASE
, 1, 0},
128 {STM_OP_DEEP_PWRDOWN
, 1, 0},
129 {STM_OP_RD_SIG
, 4, 1},
132 /* Driver private data structure */
133 struct spiflash_data
{
134 struct mtd_info
*mtd
;
135 struct mtd_partition
*parsed_parts
; /* parsed partitions */
136 void *readaddr
; /* memory mapped data for read */
137 void *mmraddr
; /* memory mapped register space */
138 wait_queue_head_t wq
;
149 static struct spiflash_data
*spidata
;
151 extern int parse_redboot_partitions(struct mtd_info
*master
, struct mtd_partition
**pparts
);
153 /***************************************************************************************************/
156 spiflash_regread32(int reg
)
158 volatile __u32
*data
= (__u32
*)(spidata
->mmraddr
+ reg
);
164 spiflash_regwrite32(int reg
, __u32 data
)
166 volatile __u32
*addr
= (__u32
*)(spidata
->mmraddr
+ reg
);
174 spiflash_sendcmd (int op
, u32 addr
)
178 struct opcodes
*ptr_opcode
;
180 ptr_opcode
= &stm_opcodes
[op
];
181 busy_wait((reg
= spiflash_regread32(SPI_FLASH_CTL
)) & SPI_CTL_BUSY
, 0);
182 spiflash_regwrite32(SPI_FLASH_OPCODE
, ((u32
) ptr_opcode
->code
) | (addr
<< 8));
184 reg
= (reg
& ~SPI_CTL_TX_RX_CNT_MASK
) | ptr_opcode
->tx_cnt
|
185 (ptr_opcode
->rx_cnt
<< 4) | SPI_CTL_START
;
187 spiflash_regwrite32(SPI_FLASH_CTL
, reg
);
188 busy_wait(spiflash_regread32(SPI_FLASH_CTL
) & SPI_CTL_BUSY
, 0);
190 if (!ptr_opcode
->rx_cnt
)
193 reg
= (__u32
) spiflash_regread32(SPI_FLASH_DATA
);
195 switch (ptr_opcode
->rx_cnt
) {
216 /* Probe SPI flash device
217 * Function returns 0 for failure.
218 * and flashconfig_tbl array index for success.
221 spiflash_probe_chip (void)
226 /* Read the signature on the flash device */
227 spin_lock_bh(&spidata
->mutex
);
228 sig
= spiflash_sendcmd(SPI_RD_SIG
, 0);
229 spin_unlock_bh(&spidata
->mutex
);
232 case STM_8MBIT_SIGNATURE
:
233 flash_size
= FLASH_1MB
;
235 case STM_16MBIT_SIGNATURE
:
236 flash_size
= FLASH_2MB
;
238 case STM_32MBIT_SIGNATURE
:
239 flash_size
= FLASH_4MB
;
241 case STM_64MBIT_SIGNATURE
:
242 flash_size
= FLASH_8MB
;
244 case STM_128MBIT_SIGNATURE
:
245 flash_size
= FLASH_16MB
;
248 printk (KERN_WARNING SPIFLASH
"Read of flash device signature failed!\n");
256 /* wait until the flash chip is ready and grab a lock */
257 static int spiflash_wait_ready(int state
)
259 DECLARE_WAITQUEUE(wait
, current
);
262 spin_lock_bh(&spidata
->mutex
);
263 if (spidata
->state
!= FL_READY
) {
264 set_current_state(TASK_UNINTERRUPTIBLE
);
265 add_wait_queue(&spidata
->wq
, &wait
);
266 spin_unlock_bh(&spidata
->mutex
);
268 remove_wait_queue(&spidata
->wq
, &wait
);
270 if(signal_pending(current
))
275 spidata
->state
= state
;
280 static inline void spiflash_done(void)
282 spidata
->state
= FL_READY
;
283 spin_unlock_bh(&spidata
->mutex
);
284 wake_up(&spidata
->wq
);
288 spiflash_erase (struct mtd_info
*mtd
,struct erase_info
*instr
)
290 struct opcodes
*ptr_opcode
;
294 if (instr
->addr
+ instr
->len
> mtd
->size
) return (-EINVAL
);
296 if (!spiflash_wait_ready(FL_ERASING
))
299 spiflash_sendcmd(SPI_WRITE_ENABLE
, 0);
300 busy_wait((reg
= spiflash_regread32(SPI_FLASH_CTL
)) & SPI_CTL_BUSY
, 0);
301 reg
= spiflash_regread32(SPI_FLASH_CTL
);
303 ptr_opcode
= &stm_opcodes
[SPI_SECTOR_ERASE
];
304 temp
= ((__u32
)instr
->addr
<< 8) | (__u32
)(ptr_opcode
->code
);
305 spiflash_regwrite32(SPI_FLASH_OPCODE
, temp
);
307 reg
= (reg
& ~SPI_CTL_TX_RX_CNT_MASK
) | ptr_opcode
->tx_cnt
| SPI_CTL_START
;
308 spiflash_regwrite32(SPI_FLASH_CTL
, reg
);
310 /* this will take some time */
311 spin_unlock_bh(&spidata
->mutex
);
313 spin_lock_bh(&spidata
->mutex
);
315 busy_wait(spiflash_sendcmd(SPI_RD_STATUS
, 0) & SPI_STATUS_WIP
, 20);
318 instr
->state
= MTD_ERASE_DONE
;
319 if (instr
->callback
) instr
->callback (instr
);
325 spiflash_read (struct mtd_info
*mtd
, loff_t from
,size_t len
,size_t *retlen
,u_char
*buf
)
330 if (!len
) return (0);
331 if (from
+ len
> mtd
->size
) return (-EINVAL
);
333 /* we always read len bytes */
336 if (!spiflash_wait_ready(FL_READING
))
338 read_addr
= (u8
*)(spidata
->readaddr
+ from
);
339 memcpy(buf
, read_addr
, len
);
346 spiflash_write (struct mtd_info
*mtd
,loff_t to
,size_t len
,size_t *retlen
,const u_char
*buf
)
348 u32 opcode
, bytes_left
;
353 if (!len
) return (0);
354 if (to
+ len
> mtd
->size
) return (-EINVAL
);
356 opcode
= stm_opcodes
[SPI_PAGE_PROGRAM
].code
;
360 u32 xact_len
, reg
, page_offset
, spi_data
= 0;
362 xact_len
= MIN(bytes_left
, sizeof(__u32
));
364 /* 32-bit writes cannot span across a page boundary
365 * (256 bytes). This types of writes require two page
366 * program operations to handle it correctly. The STM part
367 * will write the overflow data to the beginning of the
368 * current page as opposed to the subsequent page.
370 page_offset
= (to
& (STM_PAGE_SIZE
- 1)) + xact_len
;
372 if (page_offset
> STM_PAGE_SIZE
) {
373 xact_len
-= (page_offset
- STM_PAGE_SIZE
);
376 if (!spiflash_wait_ready(FL_WRITING
))
379 spiflash_sendcmd(SPI_WRITE_ENABLE
, 0);
382 spi_data
= (u32
) ((u8
) *buf
);
385 spi_data
= (buf
[1] << 8) | buf
[0];
388 spi_data
= (buf
[2] << 16) | (buf
[1] << 8) | buf
[0];
391 spi_data
= (buf
[3] << 24) | (buf
[2] << 16) |
392 (buf
[1] << 8) | buf
[0];
399 spiflash_regwrite32(SPI_FLASH_DATA
, spi_data
);
400 opcode
= (opcode
& SPI_OPCODE_MASK
) | ((__u32
)to
<< 8);
401 spiflash_regwrite32(SPI_FLASH_OPCODE
, opcode
);
403 reg
= spiflash_regread32(SPI_FLASH_CTL
);
404 reg
= (reg
& ~SPI_CTL_TX_RX_CNT_MASK
) | (xact_len
+ 4) | SPI_CTL_START
;
405 spiflash_regwrite32(SPI_FLASH_CTL
, reg
);
407 /* give the chip some time before we start busy waiting */
408 spin_unlock_bh(&spidata
->mutex
);
410 spin_lock_bh(&spidata
->mutex
);
412 busy_wait(spiflash_sendcmd(SPI_RD_STATUS
, 0) & SPI_STATUS_WIP
, 0);
415 bytes_left
-= xact_len
;
420 } while (bytes_left
!= 0);
426 #ifdef CONFIG_MTD_PARTITIONS
427 static const char *part_probe_types
[] = { "cmdlinepart", "RedBoot", NULL
};
431 static int spiflash_probe(struct platform_device
*pdev
)
434 int index
, num_parts
;
435 struct mtd_info
*mtd
;
437 spidata
->mmraddr
= ioremap_nocache(SPI_FLASH_MMR
, SPI_FLASH_MMR_SIZE
);
438 spin_lock_init(&spidata
->mutex
);
439 init_waitqueue_head(&spidata
->wq
);
440 spidata
->state
= FL_READY
;
442 if (!spidata
->mmraddr
) {
443 printk (KERN_WARNING SPIFLASH
"Failed to map flash device\n");
448 mtd
= kzalloc(sizeof(struct mtd_info
), GFP_KERNEL
);
454 if (!(index
= spiflash_probe_chip())) {
455 printk (KERN_WARNING SPIFLASH
"Found no serial flash device\n");
459 spidata
->readaddr
= ioremap_nocache(SPI_FLASH_READ
, flashconfig_tbl
[index
].byte_cnt
);
460 if (!spidata
->readaddr
) {
461 printk (KERN_WARNING SPIFLASH
"Failed to map flash device\n");
465 mtd
->name
= "spiflash";
466 mtd
->type
= MTD_NORFLASH
;
467 mtd
->flags
= (MTD_CAP_NORFLASH
|MTD_WRITEABLE
);
468 mtd
->size
= flashconfig_tbl
[index
].byte_cnt
;
469 mtd
->erasesize
= flashconfig_tbl
[index
].sector_size
;
471 mtd
->numeraseregions
= 0;
472 mtd
->eraseregions
= NULL
;
473 mtd
->erase
= spiflash_erase
;
474 mtd
->read
= spiflash_read
;
475 mtd
->write
= spiflash_write
;
476 mtd
->owner
= THIS_MODULE
;
478 /* parse redboot partitions */
479 num_parts
= parse_mtd_partitions(mtd
, part_probe_types
, &spidata
->parsed_parts
, 0);
483 result
= add_mtd_partitions(mtd
, spidata
->parsed_parts
, num_parts
);
494 static int spiflash_remove (struct platform_device
*pdev
)
496 del_mtd_partitions (spidata
->mtd
);
501 struct platform_driver spiflash_driver
= {
502 .driver
.name
= "spiflash",
503 .probe
= spiflash_probe
,
504 .remove
= spiflash_remove
,
510 spidata
= kmalloc(sizeof(struct spiflash_data
), GFP_KERNEL
);
514 spin_lock_init(&spidata
->mutex
);
515 platform_driver_register(&spiflash_driver
);
526 module_init (spiflash_init
);
527 module_exit (spiflash_exit
);
529 MODULE_LICENSE("GPL");
530 MODULE_AUTHOR("OpenWrt.org, Atheros Communications Inc");
531 MODULE_DESCRIPTION("MTD driver for SPI Flash on Atheros SOC");