projects / openwrt.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
history | raw | HEAD
cbus-retu-wdt: Some fixes
[openwrt.git] / target / linux / omap24xx / patches-2.6.37 / 200-omap-platform.patch
1 ---
2 arch/arm/include/asm/setup.h | 12
3 arch/arm/plat-omap/Kconfig | 32 +
4 arch/arm/plat-omap/Makefile | 5
5 arch/arm/plat-omap/bootreason.c | 79 ++
6 arch/arm/plat-omap/common.c | 70 ++
7 arch/arm/plat-omap/component-version.c | 64 ++
8 arch/arm/plat-omap/gpio-switch.c | 554 ++++++++++++++++++
9 arch/arm/plat-omap/include/mach/blizzard.h | 12
10 arch/arm/plat-omap/include/mach/board-ams-delta.h | 76 ++
11 arch/arm/plat-omap/include/mach/board-sx1.h | 52 +
12 arch/arm/plat-omap/include/mach/board-voiceblue.h | 19
13 arch/arm/plat-omap/include/mach/board.h | 169 +++++
14 arch/arm/plat-omap/include/mach/cbus.h | 31 +
15 arch/arm/plat-omap/include/mach/clkdev.h | 13
16 arch/arm/plat-omap/include/mach/clkdev_omap.h | 41 +
17 arch/arm/plat-omap/include/mach/clock.h | 168 +++++
18 arch/arm/plat-omap/include/mach/clockdomain.h | 111 +++
19 arch/arm/plat-omap/include/mach/common.h | 83 ++
20 arch/arm/plat-omap/include/mach/control.h | 325 ++++++++++
21 arch/arm/plat-omap/include/mach/cpu.h | 516 +++++++++++++++++
22 arch/arm/plat-omap/include/mach/display.h | 575 +++++++++++++++++++
23 arch/arm/plat-omap/include/mach/dma.h | 640 +++++++++++++++++++++
24 arch/arm/plat-omap/include/mach/dmtimer.h | 84 ++
25 arch/arm/plat-omap/include/mach/dsp_common.h | 40 +
26 arch/arm/plat-omap/include/mach/fpga.h | 197 ++++++
27 arch/arm/plat-omap/include/mach/gpio-switch.h | 54 +
28 arch/arm/plat-omap/include/mach/gpio.h | 129 ++++
29 arch/arm/plat-omap/include/mach/gpmc-smc91x.h | 42 +
30 arch/arm/plat-omap/include/mach/gpmc.h | 115 +++
31 arch/arm/plat-omap/include/mach/hardware.h | 290 +++++++++
32 arch/arm/plat-omap/include/mach/hwa742.h | 8
33 arch/arm/plat-omap/include/mach/i2c.h | 39 +
34 arch/arm/plat-omap/include/mach/io.h | 287 +++++++++
35 arch/arm/plat-omap/include/mach/iommu.h | 168 +++++
36 arch/arm/plat-omap/include/mach/iommu2.h | 96 +++
37 arch/arm/plat-omap/include/mach/iovmm.h | 94 +++
38 arch/arm/plat-omap/include/mach/irda.h | 33 +
39 arch/arm/plat-omap/include/mach/irqs.h | 506 ++++++++++++++++
40 arch/arm/plat-omap/include/mach/keypad.h | 45 +
41 arch/arm/plat-omap/include/mach/lcd_mipid.h | 29
42 arch/arm/plat-omap/include/mach/led.h | 24
43 arch/arm/plat-omap/include/mach/mailbox.h | 111 +++
44 arch/arm/plat-omap/include/mach/mcbsp.h | 462 +++++++++++++++
45 arch/arm/plat-omap/include/mach/mcspi.h | 15
46 arch/arm/plat-omap/include/mach/memory.h | 103 +++
47 arch/arm/plat-omap/include/mach/menelaus.h | 49 +
48 arch/arm/plat-omap/include/mach/mmc.h | 157 +++++
49 arch/arm/plat-omap/include/mach/mux.h | 662 ++++++++++++++++++++++
50 arch/arm/plat-omap/include/mach/nand.h | 24
51 arch/arm/plat-omap/include/mach/omap-alsa.h | 123 ++++
52 arch/arm/plat-omap/include/mach/omap-pm.h | 301 ++++++++++
53 arch/arm/plat-omap/include/mach/omap1510.h | 50 +
54 arch/arm/plat-omap/include/mach/omap16xx.h | 202 ++++++
55 arch/arm/plat-omap/include/mach/omap24xx.h | 89 ++
56 arch/arm/plat-omap/include/mach/omap34xx.h | 86 ++
57 arch/arm/plat-omap/include/mach/omap44xx.h | 48 +
58 arch/arm/plat-omap/include/mach/omap730.h | 102 +++
59 arch/arm/plat-omap/include/mach/omap7xx.h | 104 +++
60 arch/arm/plat-omap/include/mach/omap850.h | 102 +++
61 arch/arm/plat-omap/include/mach/omap_device.h | 143 ++++
62 arch/arm/plat-omap/include/mach/omap_hwmod.h | 467 +++++++++++++++
63 arch/arm/plat-omap/include/mach/onenand.h | 43 +
64 arch/arm/plat-omap/include/mach/param.h | 8
65 arch/arm/plat-omap/include/mach/powerdomain.h | 187 ++++++
66 arch/arm/plat-omap/include/mach/prcm.h | 39 +
67 arch/arm/plat-omap/include/mach/sdrc.h | 158 +++++
68 arch/arm/plat-omap/include/mach/serial.h | 65 ++
69 arch/arm/plat-omap/include/mach/smp.h | 53 +
70 arch/arm/plat-omap/include/mach/sram.h | 78 ++
71 arch/arm/plat-omap/include/mach/system.h | 51 +
72 arch/arm/plat-omap/include/mach/tc.h | 106 +++
73 arch/arm/plat-omap/include/mach/timer-gp.h | 17
74 arch/arm/plat-omap/include/mach/timex.h | 41 +
75 arch/arm/plat-omap/include/mach/uncompress.h | 88 ++
76 arch/arm/plat-omap/include/mach/usb.h | 162 +++++
77 arch/arm/plat-omap/include/mach/vram.h | 62 ++
78 arch/arm/plat-omap/include/mach/vrfb.h | 50 +
79 arch/arm/plat-omap/include/plat/board.h | 8
80 arch/arm/plat-omap/include/plat/cbus.h | 31 +
81 79 files changed, 10573 insertions(+), 1 deletion(-)
82
83 Index: linux-2.6.37-rc1/arch/arm/plat-omap/bootreason.c
84 ===================================================================
85 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
86 +++ linux-2.6.37-rc1/arch/arm/plat-omap/bootreason.c 2010-11-05 17:36:26.171000001 +0100
87 @@ -0,0 +1,79 @@
88 +/*
89 + * linux/arch/arm/plat-omap/bootreason.c
90 + *
91 + * OMAP Bootreason passing
92 + *
93 + * Copyright (c) 2004 Nokia
94 + *
95 + * Written by David Weinehall <david.weinehall@nokia.com>
96 + *
97 + * This program is free software; you can redistribute it and/or modify it
98 + * under the terms of the GNU General Public License as published by the
99 + * Free Software Foundation; either version 2 of the License, or (at your
100 + * option) any later version.
101 + *
102 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
103 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
104 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
105 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
106 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
107 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
108 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
109 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
110 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
111 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
112 + *
113 + * You should have received a copy of the GNU General Public License along
114 + * with this program; if not, write to the Free Software Foundation, Inc.,
115 + * 675 Mass Ave, Cambridge, MA 02139, USA.
116 + */
117 +#include <linux/proc_fs.h>
118 +#include <linux/errno.h>
119 +#include <plat/board.h>
120 +
121 +static char boot_reason[16];
122 +
123 +static int omap_bootreason_read_proc(char *page, char **start, off_t off,
124 + int count, int *eof, void *data)
125 +{
126 + int len = 0;
127 +
128 + len += sprintf(page + len, "%s\n", boot_reason);
129 +
130 + *start = page + off;
131 +
132 + if (len > off)
133 + len -= off;
134 + else
135 + len = 0;
136 +
137 + return len < count ? len : count;
138 +}
139 +
140 +static int __init bootreason_init(void)
141 +{
142 + const struct omap_boot_reason_config *cfg;
143 + int reason_valid = 0;
144 +
145 + cfg = omap_get_config(OMAP_TAG_BOOT_REASON, struct omap_boot_reason_config);
146 + if (cfg != NULL) {
147 + strncpy(boot_reason, cfg->reason_str, sizeof(cfg->reason_str));
148 + boot_reason[sizeof(cfg->reason_str)] = 0;
149 + reason_valid = 1;
150 + } else {
151 + /* Read the boot reason from the OMAP registers */
152 + }
153 +
154 + if (!reason_valid)
155 + return -ENOENT;
156 +
157 + printk(KERN_INFO "Bootup reason: %s\n", boot_reason);
158 +
159 + if (!create_proc_read_entry("bootreason", S_IRUGO, NULL,
160 + omap_bootreason_read_proc, NULL))
161 + return -ENOMEM;
162 +
163 + return 0;
164 +}
165 +
166 +late_initcall(bootreason_init);
167 Index: linux-2.6.37-rc1/arch/arm/plat-omap/common.c
168 ===================================================================
169 --- linux-2.6.37-rc1.orig/arch/arm/plat-omap/common.c 2010-11-01 12:54:12.000000000 +0100
170 +++ linux-2.6.37-rc1/arch/arm/plat-omap/common.c 2010-11-05 17:39:26.051000000 +0100
171 @@ -21,17 +21,89 @@
172 #include <plat/vram.h>
173 #include <plat/dsp.h>
174
175 +#include <asm/setup.h>
176 +
177
178 #define NO_LENGTH_CHECK 0xffffffff
179
180 struct omap_board_config_kernel *omap_board_config;
181 int omap_board_config_size;
182
183 +unsigned char omap_bootloader_tag[1024];
184 +int omap_bootloader_tag_len;
185 +
186 +/* used by omap-smp.c and board-4430sdp.c */
187 +void __iomem *gic_cpu_base_addr;
188 +
189 +#ifdef CONFIG_OMAP_BOOT_TAG
190 +
191 +static int __init parse_tag_omap(const struct tag *tag)
192 +{
193 + u32 size = tag->hdr.size - (sizeof(tag->hdr) >> 2);
194 +
195 + size <<= 2;
196 + if (size > sizeof(omap_bootloader_tag))
197 + return -1;
198 +
199 + memcpy(omap_bootloader_tag, tag->u.omap.data, size);
200 + omap_bootloader_tag_len = size;
201 +
202 + return 0;
203 +}
204 +
205 +__tagtable(ATAG_BOARD, parse_tag_omap);
206 +
207 +#endif
208 +
209 static const void *get_config(u16 tag, size_t len, int skip, size_t *len_out)
210 {
211 struct omap_board_config_kernel *kinfo = NULL;
212 int i;
213
214 +#ifdef CONFIG_OMAP_BOOT_TAG
215 + struct omap_board_config_entry *info = NULL;
216 +
217 + if (omap_bootloader_tag_len > 4)
218 + info = (struct omap_board_config_entry *) omap_bootloader_tag;
219 + while (info != NULL) {
220 + u8 *next;
221 +
222 + if (info->tag == tag) {
223 + if (skip == 0)
224 + break;
225 + skip--;
226 + }
227 +
228 + if ((info->len & 0x03) != 0) {
229 + /* We bail out to avoid an alignment fault */
230 + printk(KERN_ERR "OMAP peripheral config: Length (%d) not word-aligned (tag %04x)\n",
231 + info->len, info->tag);
232 + return NULL;
233 + }
234 + next = (u8 *) info + sizeof(*info) + info->len;
235 + if (next >= omap_bootloader_tag + omap_bootloader_tag_len)
236 + info = NULL;
237 + else
238 + info = (struct omap_board_config_entry *) next;
239 + }
240 + if (info != NULL) {
241 + /* Check the length as a lame attempt to check for
242 + * binary inconsistency. */
243 + if (len != NO_LENGTH_CHECK) {
244 + /* Word-align len */
245 + if (len & 0x03)
246 + len = (len + 3) & ~0x03;
247 + if (info->len != len) {
248 + printk(KERN_ERR "OMAP peripheral config: Length mismatch with tag %x (want %d, got %d)\n",
249 + tag, len, info->len);
250 + return NULL;
251 + }
252 + }
253 + if (len_out != NULL)
254 + *len_out = info->len;
255 + return info->data;
256 + }
257 +#endif
258 /* Try to find the config from the board-specific structures
259 * in the kernel. */
260 for (i = 0; i < omap_board_config_size; i++) {
261 Index: linux-2.6.37-rc1/arch/arm/plat-omap/component-version.c
262 ===================================================================
263 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
264 +++ linux-2.6.37-rc1/arch/arm/plat-omap/component-version.c 2010-11-05 17:36:26.171000001 +0100
265 @@ -0,0 +1,64 @@
266 +/*
267 + * linux/arch/arm/plat-omap/component-version.c
268 + *
269 + * Copyright (C) 2005 Nokia Corporation
270 + * Written by Juha Yrjölä <juha.yrjola@nokia.com>
271 + *
272 + * This program is free software; you can redistribute it and/or modify
273 + * it under the terms of the GNU General Public License version 2 as
274 + * published by the Free Software Foundation.
275 + */
276 +
277 +#include <linux/init.h>
278 +#include <linux/module.h>
279 +#include <linux/err.h>
280 +#include <linux/proc_fs.h>
281 +#include <plat/board.h>
282 +
283 +static int component_version_read_proc(char *page, char **start, off_t off,
284 + int count, int *eof, void *data)
285 +{
286 + int len, i;
287 + const struct omap_version_config *ver;
288 + char *p;
289 +
290 + i = 0;
291 + p = page;
292 + while ((ver = omap_get_nr_config(OMAP_TAG_VERSION_STR,
293 + struct omap_version_config, i)) != NULL) {
294 + p += sprintf(p, "%-12s%s\n", ver->component, ver->version);
295 + i++;
296 + }
297 +
298 + len = (p - page) - off;
299 + if (len < 0)
300 + len = 0;
301 +
302 + *eof = (len <= count) ? 1 : 0;
303 + *start = page + off;
304 +
305 + return len;
306 +}
307 +
308 +static int __init component_version_init(void)
309 +{
310 + if (omap_get_config(OMAP_TAG_VERSION_STR, struct omap_version_config) == NULL)
311 + return -ENODEV;
312 + if (!create_proc_read_entry("component_version", S_IRUGO, NULL,
313 + component_version_read_proc, NULL))
314 + return -ENOMEM;
315 +
316 + return 0;
317 +}
318 +
319 +static void __exit component_version_exit(void)
320 +{
321 + remove_proc_entry("component_version", NULL);
322 +}
323 +
324 +late_initcall(component_version_init);
325 +module_exit(component_version_exit);
326 +
327 +MODULE_AUTHOR("Juha Yrjölä <juha.yrjola@nokia.com>");
328 +MODULE_DESCRIPTION("Component version driver");
329 +MODULE_LICENSE("GPL");
330 Index: linux-2.6.37-rc1/arch/arm/plat-omap/include/mach/blizzard.h
331 ===================================================================
332 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
333 +++ linux-2.6.37-rc1/arch/arm/plat-omap/include/mach/blizzard.h 2010-11-05 17:36:26.171000001 +0100
334 @@ -0,0 +1,12 @@
335 +#ifndef _BLIZZARD_H
336 +#define _BLIZZARD_H
337 +
338 +struct blizzard_platform_data {
339 + void (*power_up)(struct device *dev);
340 + void (*power_down)(struct device *dev);
341 + unsigned long (*get_clock_rate)(struct device *dev);
342 +
343 + unsigned te_connected : 1;
344 +};
345 +
346 +#endif
347 Index: linux-2.6.37-rc1/arch/arm/plat-omap/include/mach/board-ams-delta.h
348 ===================================================================
349 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
350 +++ linux-2.6.37-rc1/arch/arm/plat-omap/include/mach/board-ams-delta.h 2010-11-05 17:36:26.171000001 +0100
351 @@ -0,0 +1,76 @@
352 +/*
353 + * arch/arm/plat-omap/include/mach/board-ams-delta.h
354 + *
355 + * Copyright (C) 2006 Jonathan McDowell <noodles@earth.li>
356 + *
357 + * This program is free software; you can redistribute it and/or modify it
358 + * under the terms of the GNU General Public License as published by the
359 + * Free Software Foundation; either version 2 of the License, or (at your
360 + * option) any later version.
361 + *
362 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
363 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
364 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
365 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
366 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
367 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
368 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
369 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
370 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
371 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
372 + *
373 + * You should have received a copy of the GNU General Public License along
374 + * with this program; if not, write to the Free Software Foundation, Inc.,
375 + * 675 Mass Ave, Cambridge, MA 02139, USA.
376 + */
377 +#ifndef __ASM_ARCH_OMAP_AMS_DELTA_H
378 +#define __ASM_ARCH_OMAP_AMS_DELTA_H
379 +
380 +#if defined (CONFIG_MACH_AMS_DELTA)
381 +
382 +#define AMS_DELTA_LATCH1_PHYS 0x01000000
383 +#define AMS_DELTA_LATCH1_VIRT 0xEA000000
384 +#define AMS_DELTA_MODEM_PHYS 0x04000000
385 +#define AMS_DELTA_MODEM_VIRT 0xEB000000
386 +#define AMS_DELTA_LATCH2_PHYS 0x08000000
387 +#define AMS_DELTA_LATCH2_VIRT 0xEC000000
388 +
389 +#define AMS_DELTA_LATCH1_LED_CAMERA 0x01
390 +#define AMS_DELTA_LATCH1_LED_ADVERT 0x02
391 +#define AMS_DELTA_LATCH1_LED_EMAIL 0x04
392 +#define AMS_DELTA_LATCH1_LED_HANDSFREE 0x08
393 +#define AMS_DELTA_LATCH1_LED_VOICEMAIL 0x10
394 +#define AMS_DELTA_LATCH1_LED_VOICE 0x20
395 +
396 +#define AMS_DELTA_LATCH2_LCD_VBLEN 0x0001
397 +#define AMS_DELTA_LATCH2_LCD_NDISP 0x0002
398 +#define AMS_DELTA_LATCH2_NAND_NCE 0x0004
399 +#define AMS_DELTA_LATCH2_NAND_NRE 0x0008
400 +#define AMS_DELTA_LATCH2_NAND_NWP 0x0010
401 +#define AMS_DELTA_LATCH2_NAND_NWE 0x0020
402 +#define AMS_DELTA_LATCH2_NAND_ALE 0x0040
403 +#define AMS_DELTA_LATCH2_NAND_CLE 0x0080
404 +#define AMD_DELTA_LATCH2_KEYBRD_PWR 0x0100
405 +#define AMD_DELTA_LATCH2_KEYBRD_DATA 0x0200
406 +#define AMD_DELTA_LATCH2_SCARD_RSTIN 0x0400
407 +#define AMD_DELTA_LATCH2_SCARD_CMDVCC 0x0800
408 +#define AMS_DELTA_LATCH2_MODEM_NRESET 0x1000
409 +#define AMS_DELTA_LATCH2_MODEM_CODEC 0x2000
410 +
411 +#define AMS_DELTA_GPIO_PIN_KEYBRD_DATA 0
412 +#define AMS_DELTA_GPIO_PIN_KEYBRD_CLK 1
413 +#define AMS_DELTA_GPIO_PIN_MODEM_IRQ 2
414 +#define AMS_DELTA_GPIO_PIN_HOOK_SWITCH 4
415 +#define AMS_DELTA_GPIO_PIN_SCARD_NOFF 6
416 +#define AMS_DELTA_GPIO_PIN_SCARD_IO 7
417 +#define AMS_DELTA_GPIO_PIN_CONFIG 11
418 +#define AMS_DELTA_GPIO_PIN_NAND_RB 12
419 +
420 +#ifndef __ASSEMBLY__
421 +void ams_delta_latch1_write(u8 mask, u8 value);
422 +void ams_delta_latch2_write(u16 mask, u16 value);
423 +#endif
424 +
425 +#endif /* CONFIG_MACH_AMS_DELTA */
426 +
427 +#endif /* __ASM_ARCH_OMAP_AMS_DELTA_H */
428 Index: linux-2.6.37-rc1/arch/arm/plat-omap/include/mach/board.h
429 ===================================================================
430 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
431 +++ linux-2.6.37-rc1/arch/arm/plat-omap/include/mach/board.h 2010-11-05 17:36:26.171000001 +0100
432 @@ -0,0 +1,169 @@
433 +/*
434 + * arch/arm/plat-omap/include/mach/board.h
435 + *
436 + * Information structures for board-specific data
437 + *
438 + * Copyright (C) 2004 Nokia Corporation
439 + * Written by Juha Yrjölä <juha.yrjola@nokia.com>
440 + */
441 +
442 +#ifndef _OMAP_BOARD_H
443 +#define _OMAP_BOARD_H
444 +
445 +#include <linux/types.h>
446 +
447 +#include <plat/gpio-switch.h>
448 +
449 +/*
450 + * OMAP35x EVM revision
451 + * Run time detection of EVM revision is done by reading Ethernet
452 + * PHY ID -
453 + * GEN_1 = 0x01150000
454 + * GEN_2 = 0x92200000
455 + */
456 +enum {
457 + OMAP3EVM_BOARD_GEN_1 = 0, /* EVM Rev between A - D */
458 + OMAP3EVM_BOARD_GEN_2, /* EVM Rev >= Rev E */
459 +};
460 +
461 +/* Different peripheral ids */
462 +#define OMAP_TAG_CLOCK 0x4f01
463 +#define OMAP_TAG_LCD 0x4f05
464 +#define OMAP_TAG_GPIO_SWITCH 0x4f06
465 +#define OMAP_TAG_FBMEM 0x4f08
466 +#define OMAP_TAG_STI_CONSOLE 0x4f09
467 +#define OMAP_TAG_CAMERA_SENSOR 0x4f0a
468 +
469 +#define OMAP_TAG_BOOT_REASON 0x4f80
470 +#define OMAP_TAG_FLASH_PART 0x4f81
471 +#define OMAP_TAG_VERSION_STR 0x4f82
472 +
473 +struct omap_clock_config {
474 + /* 0 for 12 MHz, 1 for 13 MHz and 2 for 19.2 MHz */
475 + u8 system_clock_type;
476 +};
477 +
478 +struct omap_serial_console_config {
479 + u8 console_uart;
480 + u32 console_speed;
481 +};
482 +
483 +struct omap_sti_console_config {
484 + unsigned enable:1;
485 + u8 channel;
486 +};
487 +
488 +struct omap_camera_sensor_config {
489 + u16 reset_gpio;
490 + int (*power_on)(void * data);
491 + int (*power_off)(void * data);
492 +};
493 +
494 +struct omap_usb_config {
495 + /* Configure drivers according to the connectors on your board:
496 + * - "A" connector (rectagular)
497 + * ... for host/OHCI use, set "register_host".
498 + * - "B" connector (squarish) or "Mini-B"
499 + * ... for device/gadget use, set "register_dev".
500 + * - "Mini-AB" connector (very similar to Mini-B)
501 + * ... for OTG use as device OR host, initialize "otg"
502 + */
503 + unsigned register_host:1;
504 + unsigned register_dev:1;
505 + u8 otg; /* port number, 1-based: usb1 == 2 */
506 +
507 + u8 hmc_mode;
508 +
509 + /* implicitly true if otg: host supports remote wakeup? */
510 + u8 rwc;
511 +
512 + /* signaling pins used to talk to transceiver on usbN:
513 + * 0 == usbN unused
514 + * 2 == usb0-only, using internal transceiver
515 + * 3 == 3 wire bidirectional
516 + * 4 == 4 wire bidirectional
517 + * 6 == 6 wire unidirectional (or TLL)
518 + */
519 + u8 pins[3];
520 +};
521 +
522 +struct omap_lcd_config {
523 + char panel_name[16];
524 + char ctrl_name[16];
525 + s16 nreset_gpio;
526 + u8 data_lines;
527 +};
528 +
529 +struct device;
530 +struct fb_info;
531 +struct omap_backlight_config {
532 + int default_intensity;
533 + int (*set_power)(struct device *dev, int state);
534 + int (*check_fb)(struct fb_info *fb);
535 +};
536 +
537 +struct omap_fbmem_config {
538 + u32 start;
539 + u32 size;
540 +};
541 +
542 +struct omap_pwm_led_platform_data {
543 + const char *name;
544 + int intensity_timer;
545 + int blink_timer;
546 + void (*set_power)(struct omap_pwm_led_platform_data *self, int on_off);
547 +};
548 +
549 +struct omap_uart_config {
550 + /* Bit field of UARTs present; bit 0 --> UART1 */
551 + unsigned int enabled_uarts;
552 +};
553 +
554 +
555 +struct omap_flash_part_config {
556 + char part_table[0];
557 +};
558 +
559 +struct omap_boot_reason_config {
560 + char reason_str[12];
561 +};
562 +
563 +struct omap_version_config {
564 + char component[12];
565 + char version[12];
566 +};
567 +
568 +struct omap_board_config_entry {
569 + u16 tag;
570 + u16 len;
571 + u8 data[0];
572 +};
573 +
574 +struct omap_board_config_kernel {
575 + u16 tag;
576 + const void *data;
577 +};
578 +
579 +extern const void *__omap_get_config(u16 tag, size_t len, int nr);
580 +
581 +#define omap_get_config(tag, type) \
582 + ((const type *) __omap_get_config((tag), sizeof(type), 0))
583 +#define omap_get_nr_config(tag, type, nr) \
584 + ((const type *) __omap_get_config((tag), sizeof(type), (nr)))
585 +
586 +extern const void *omap_get_var_config(u16 tag, size_t *len);
587 +
588 +extern struct omap_board_config_kernel *omap_board_config;
589 +extern int omap_board_config_size;
590 +
591 +
592 +/* for TI reference platforms sharing the same debug card */
593 +extern int debug_card_init(u32 addr, unsigned gpio);
594 +
595 +/* OMAP3EVM revision */
596 +#if defined(CONFIG_MACH_OMAP3EVM)
597 +u8 get_omap3_evm_rev(void);
598 +#else
599 +#define get_omap3_evm_rev() (-EINVAL)
600 +#endif
601 +#endif
602 Index: linux-2.6.37-rc1/arch/arm/plat-omap/include/mach/board-sx1.h
603 ===================================================================
604 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
605 +++ linux-2.6.37-rc1/arch/arm/plat-omap/include/mach/board-sx1.h 2010-11-05 17:36:26.171000001 +0100
606 @@ -0,0 +1,52 @@
607 +/*
608 + * Siemens SX1 board definitions
609 + *
610 + * Copyright: Vovan888 at gmail com
611 + *
612 + * This package is free software; you can redistribute it and/or modify
613 + * it under the terms of the GNU General Public License version 2 as
614 + * published by the Free Software Foundation.
615 + *
616 + * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
617 + * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
618 + * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
619 + */
620 +
621 +#ifndef __ASM_ARCH_SX1_I2C_CHIPS_H
622 +#define __ASM_ARCH_SX1_I2C_CHIPS_H
623 +
624 +#define SOFIA_MAX_LIGHT_VAL 0x2B
625 +
626 +#define SOFIA_I2C_ADDR 0x32
627 +/* Sofia reg 3 bits masks */
628 +#define SOFIA_POWER1_REG 0x03
629 +
630 +#define SOFIA_USB_POWER 0x01
631 +#define SOFIA_MMC_POWER 0x04
632 +#define SOFIA_BLUETOOTH_POWER 0x08
633 +#define SOFIA_MMILIGHT_POWER 0x20
634 +
635 +#define SOFIA_POWER2_REG 0x04
636 +#define SOFIA_BACKLIGHT_REG 0x06
637 +#define SOFIA_KEYLIGHT_REG 0x07
638 +#define SOFIA_DIMMING_REG 0x09
639 +
640 +
641 +/* Function Prototypes for SX1 devices control on I2C bus */
642 +
643 +int sx1_setbacklight(u8 backlight);
644 +int sx1_getbacklight(u8 *backlight);
645 +int sx1_setkeylight(u8 keylight);
646 +int sx1_getkeylight(u8 *keylight);
647 +
648 +int sx1_setmmipower(u8 onoff);
649 +int sx1_setusbpower(u8 onoff);
650 +int sx1_i2c_read_byte(u8 devaddr, u8 regoffset, u8 *value);
651 +int sx1_i2c_write_byte(u8 devaddr, u8 regoffset, u8 value);
652 +
653 +/* MMC prototypes */
654 +
655 +extern void sx1_mmc_init(void);
656 +extern void sx1_mmc_slot_cover_handler(void *arg, int state);
657 +
658 +#endif /* __ASM_ARCH_SX1_I2C_CHIPS_H */
659 Index: linux-2.6.37-rc1/arch/arm/plat-omap/include/mach/board-voiceblue.h
660 ===================================================================
661 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
662 +++ linux-2.6.37-rc1/arch/arm/plat-omap/include/mach/board-voiceblue.h 2010-11-05 17:36:26.171000001 +0100
663 @@ -0,0 +1,19 @@
664 +/*
665 + * Copyright (C) 2004 2N Telekomunikace, Ladislav Michl <michl@2n.cz>
666 + *
667 + * Hardware definitions for OMAP5910 based VoiceBlue board.
668 + *
669 + * This program is free software; you can redistribute it and/or modify
670 + * it under the terms of the GNU General Public License version 2 as
671 + * published by the Free Software Foundation.
672 + */
673 +
674 +#ifndef __ASM_ARCH_VOICEBLUE_H
675 +#define __ASM_ARCH_VOICEBLUE_H
676 +
677 +extern void voiceblue_wdt_enable(void);
678 +extern void voiceblue_wdt_disable(void);
679 +extern void voiceblue_wdt_ping(void);
680 +
681 +#endif /* __ASM_ARCH_VOICEBLUE_H */
682 +
683 Index: linux-2.6.37-rc1/arch/arm/plat-omap/include/mach/cbus.h
684 ===================================================================
685 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
686 +++ linux-2.6.37-rc1/arch/arm/plat-omap/include/mach/cbus.h 2010-11-05 17:36:26.171000001 +0100
687 @@ -0,0 +1,31 @@
688 +/*
689 + * cbus.h - CBUS platform_data definition
690 + *
691 + * Copyright (C) 2004 - 2009 Nokia Corporation
692 + *
693 + * Written by Felipe Balbi <felipe.balbi@nokia.com>
694 + *
695 + * This file is subject to the terms and conditions of the GNU General
696 + * Public License. See the file "COPYING" in the main directory of this
697 + * archive for more details.
698 + *
699 + * This program is distributed in the hope that it will be useful,
700 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
701 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
702 + * GNU General Public License for more details.
703 + *
704 + * You should have received a copy of the GNU General Public License
705 + * along with this program; if not, write to the Free Software
706 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
707 + */
708 +
709 +#ifndef __PLAT_CBUS_H
710 +#define __PLAT_CBUS_H
711 +
712 +struct cbus_host_platform_data {
713 + int dat_gpio;
714 + int clk_gpio;
715 + int sel_gpio;
716 +};
717 +
718 +#endif /* __PLAT_CBUS_H */
719 Index: linux-2.6.37-rc1/arch/arm/plat-omap/include/mach/clkdev.h
720 ===================================================================
721 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
722 +++ linux-2.6.37-rc1/arch/arm/plat-omap/include/mach/clkdev.h 2010-11-05 17:36:26.171000001 +0100
723 @@ -0,0 +1,13 @@
724 +#ifndef __MACH_CLKDEV_H
725 +#define __MACH_CLKDEV_H
726 +
727 +static inline int __clk_get(struct clk *clk)
728 +{
729 + return 1;
730 +}
731 +
732 +static inline void __clk_put(struct clk *clk)
733 +{
734 +}
735 +
736 +#endif
737 Index: linux-2.6.37-rc1/arch/arm/plat-omap/include/mach/clkdev_omap.h
738 ===================================================================
739 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
740 +++ linux-2.6.37-rc1/arch/arm/plat-omap/include/mach/clkdev_omap.h 2010-11-05 17:36:26.172000001 +0100
741 @@ -0,0 +1,41 @@
742 +/*
743 + * clkdev <-> OMAP integration
744 + *
745 + * Russell King <linux@arm.linux.org.uk>
746 + *
747 + */
748 +
749 +#ifndef __ARCH_ARM_PLAT_OMAP_INCLUDE_PLAT_CLKDEV_OMAP_H
750 +#define __ARCH_ARM_PLAT_OMAP_INCLUDE_PLAT_CLKDEV_OMAP_H
751 +
752 +#include <asm/clkdev.h>
753 +
754 +struct omap_clk {
755 + u16 cpu;
756 + struct clk_lookup lk;
757 +};
758 +
759 +#define CLK(dev, con, ck, cp) \
760 + { \
761 + .cpu = cp, \
762 + .lk = { \
763 + .dev_id = dev, \
764 + .con_id = con, \
765 + .clk = ck, \
766 + }, \
767 + }
768 +
769 +
770 +#define CK_310 (1 << 0)
771 +#define CK_7XX (1 << 1)
772 +#define CK_1510 (1 << 2)
773 +#define CK_16XX (1 << 3)
774 +#define CK_243X (1 << 4)
775 +#define CK_242X (1 << 5)
776 +#define CK_343X (1 << 6)
777 +#define CK_3430ES1 (1 << 7)
778 +#define CK_3430ES2 (1 << 8)
779 +#define CK_443X (1 << 9)
780 +
781 +#endif
782 +
783 Index: linux-2.6.37-rc1/arch/arm/plat-omap/include/mach/clockdomain.h
784 ===================================================================
785 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
786 +++ linux-2.6.37-rc1/arch/arm/plat-omap/include/mach/clockdomain.h 2010-11-05 17:36:26.172000001 +0100
787 @@ -0,0 +1,111 @@
788 +/*
789 + * arch/arm/plat-omap/include/mach/clockdomain.h
790 + *
791 + * OMAP2/3 clockdomain framework functions
792 + *
793 + * Copyright (C) 2008 Texas Instruments, Inc.
794 + * Copyright (C) 2008 Nokia Corporation
795 + *
796 + * Written by Paul Walmsley
797 + *
798 + * This program is free software; you can redistribute it and/or modify
799 + * it under the terms of the GNU General Public License version 2 as
800 + * published by the Free Software Foundation.
801 + */
802 +
803 +#ifndef __ASM_ARM_ARCH_OMAP_CLOCKDOMAIN_H
804 +#define __ASM_ARM_ARCH_OMAP_CLOCKDOMAIN_H
805 +
806 +#include <plat/powerdomain.h>
807 +#include <plat/clock.h>
808 +#include <plat/cpu.h>
809 +
810 +/* Clockdomain capability flags */
811 +#define CLKDM_CAN_FORCE_SLEEP (1 << 0)
812 +#define CLKDM_CAN_FORCE_WAKEUP (1 << 1)
813 +#define CLKDM_CAN_ENABLE_AUTO (1 << 2)
814 +#define CLKDM_CAN_DISABLE_AUTO (1 << 3)
815 +
816 +#define CLKDM_CAN_HWSUP (CLKDM_CAN_ENABLE_AUTO | CLKDM_CAN_DISABLE_AUTO)
817 +#define CLKDM_CAN_SWSUP (CLKDM_CAN_FORCE_SLEEP | CLKDM_CAN_FORCE_WAKEUP)
818 +#define CLKDM_CAN_HWSUP_SWSUP (CLKDM_CAN_SWSUP | CLKDM_CAN_HWSUP)
819 +
820 +/* OMAP24XX CM_CLKSTCTRL_*.AUTOSTATE_* register bit values */
821 +#define OMAP24XX_CLKSTCTRL_DISABLE_AUTO 0x0
822 +#define OMAP24XX_CLKSTCTRL_ENABLE_AUTO 0x1
823 +
824 +/* OMAP3XXX CM_CLKSTCTRL_*.CLKTRCTRL_* register bit values */
825 +#define OMAP34XX_CLKSTCTRL_DISABLE_AUTO 0x0
826 +#define OMAP34XX_CLKSTCTRL_FORCE_SLEEP 0x1
827 +#define OMAP34XX_CLKSTCTRL_FORCE_WAKEUP 0x2
828 +#define OMAP34XX_CLKSTCTRL_ENABLE_AUTO 0x3
829 +
830 +/*
831 + * struct clkdm_pwrdm_autodep - a powerdomain that should have wkdeps
832 + * and sleepdeps added when a powerdomain should stay active in hwsup mode;
833 + * and conversely, removed when the powerdomain should be allowed to go
834 + * inactive in hwsup mode.
835 + */
836 +struct clkdm_pwrdm_autodep {
837 +
838 + union {
839 + /* Name of the powerdomain to add a wkdep/sleepdep on */
840 + const char *name;
841 +
842 + /* Powerdomain pointer (looked up at clkdm_init() time) */
843 + struct powerdomain *ptr;
844 + } pwrdm;
845 +
846 + /* OMAP chip types that this clockdomain dep is valid on */
847 + const struct omap_chip_id omap_chip;
848 +
849 +};
850 +
851 +struct clockdomain {
852 +
853 + /* Clockdomain name */
854 + const char *name;
855 +
856 + union {
857 + /* Powerdomain enclosing this clockdomain */
858 + const char *name;
859 +
860 + /* Powerdomain pointer assigned at clkdm_register() */
861 + struct powerdomain *ptr;
862 + } pwrdm;
863 +
864 + /* CLKTRCTRL/AUTOSTATE field mask in CM_CLKSTCTRL reg */
865 + const u16 clktrctrl_mask;
866 +
867 + /* Clockdomain capability flags */
868 + const u8 flags;
869 +
870 + /* OMAP chip types that this clockdomain is valid on */
871 + const struct omap_chip_id omap_chip;
872 +
873 + /* Usecount tracking */
874 + atomic_t usecount;
875 +
876 + struct list_head node;
877 +
878 +};
879 +
880 +void clkdm_init(struct clockdomain **clkdms, struct clkdm_pwrdm_autodep *autodeps);
881 +int clkdm_register(struct clockdomain *clkdm);
882 +int clkdm_unregister(struct clockdomain *clkdm);
883 +struct clockdomain *clkdm_lookup(const char *name);
884 +
885 +int clkdm_for_each(int (*fn)(struct clockdomain *clkdm, void *user),
886 + void *user);
887 +struct powerdomain *clkdm_get_pwrdm(struct clockdomain *clkdm);
888 +
889 +void omap2_clkdm_allow_idle(struct clockdomain *clkdm);
890 +void omap2_clkdm_deny_idle(struct clockdomain *clkdm);
891 +
892 +int omap2_clkdm_wakeup(struct clockdomain *clkdm);
893 +int omap2_clkdm_sleep(struct clockdomain *clkdm);
894 +
895 +int omap2_clkdm_clk_enable(struct clockdomain *clkdm, struct clk *clk);
896 +int omap2_clkdm_clk_disable(struct clockdomain *clkdm, struct clk *clk);
897 +
898 +#endif
899 Index: linux-2.6.37-rc1/arch/arm/plat-omap/include/mach/clock.h
900 ===================================================================
901 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
902 +++ linux-2.6.37-rc1/arch/arm/plat-omap/include/mach/clock.h 2010-11-05 17:36:26.172000001 +0100
903 @@ -0,0 +1,168 @@
904 +/*
905 + * arch/arm/plat-omap/include/mach/clock.h
906 + *
907 + * Copyright (C) 2004 - 2005 Nokia corporation
908 + * Written by Tuukka Tikkanen <tuukka.tikkanen@elektrobit.com>
909 + * Based on clocks.h by Tony Lindgren, Gordon McNutt and RidgeRun, Inc
910 + *
911 + * This program is free software; you can redistribute it and/or modify
912 + * it under the terms of the GNU General Public License version 2 as
913 + * published by the Free Software Foundation.
914 + */
915 +
916 +#ifndef __ARCH_ARM_OMAP_CLOCK_H
917 +#define __ARCH_ARM_OMAP_CLOCK_H
918 +
919 +#include <linux/list.h>
920 +
921 +struct module;
922 +struct clk;
923 +struct clockdomain;
924 +
925 +struct clkops {
926 + int (*enable)(struct clk *);
927 + void (*disable)(struct clk *);
928 + void (*find_idlest)(struct clk *, void __iomem **, u8 *);
929 + void (*find_companion)(struct clk *, void __iomem **, u8 *);
930 +};
931 +
932 +#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) || \
933 + defined(CONFIG_ARCH_OMAP4)
934 +
935 +struct clksel_rate {
936 + u32 val;
937 + u8 div;
938 + u8 flags;
939 +};
940 +
941 +struct clksel {
942 + struct clk *parent;
943 + const struct clksel_rate *rates;
944 +};
945 +
946 +struct dpll_data {
947 + void __iomem *mult_div1_reg;
948 + u32 mult_mask;
949 + u32 div1_mask;
950 + struct clk *clk_bypass;
951 + struct clk *clk_ref;
952 + void __iomem *control_reg;
953 + u32 enable_mask;
954 + unsigned int rate_tolerance;
955 + unsigned long last_rounded_rate;
956 + u16 last_rounded_m;
957 + u8 last_rounded_n;
958 + u8 min_divider;
959 + u8 max_divider;
960 + u32 max_tolerance;
961 + u16 max_multiplier;
962 +#if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4)
963 + u8 modes;
964 + void __iomem *autoidle_reg;
965 + void __iomem *idlest_reg;
966 + u32 autoidle_mask;
967 + u32 freqsel_mask;
968 + u32 idlest_mask;
969 + u8 auto_recal_bit;
970 + u8 recal_en_bit;
971 + u8 recal_st_bit;
972 +# endif
973 +};
974 +
975 +#endif
976 +
977 +struct clk {
978 + struct list_head node;
979 + const struct clkops *ops;
980 + const char *name;
981 + int id;
982 + struct clk *parent;
983 + struct list_head children;
984 + struct list_head sibling; /* node for children */
985 + unsigned long rate;
986 + __u32 flags;
987 + void __iomem *enable_reg;
988 + unsigned long (*recalc)(struct clk *);
989 + int (*set_rate)(struct clk *, unsigned long);
990 + long (*round_rate)(struct clk *, unsigned long);
991 + void (*init)(struct clk *);
992 + __u8 enable_bit;
993 + __s8 usecount;
994 +#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) || \
995 + defined(CONFIG_ARCH_OMAP4)
996 + u8 fixed_div;
997 + void __iomem *clksel_reg;
998 + u32 clksel_mask;
999 + const struct clksel *clksel;
1000 + struct dpll_data *dpll_data;
1001 + const char *clkdm_name;
1002 + struct clockdomain *clkdm;
1003 +#else
1004 + __u8 rate_offset;
1005 + __u8 src_offset;
1006 +#endif
1007 +#if defined(CONFIG_PM_DEBUG) && defined(CONFIG_DEBUG_FS)
1008 + struct dentry *dent; /* For visible tree hierarchy */
1009 +#endif
1010 +};
1011 +
1012 +struct cpufreq_frequency_table;
1013 +
1014 +struct clk_functions {
1015 + int (*clk_enable)(struct clk *clk);
1016 + void (*clk_disable)(struct clk *clk);
1017 + long (*clk_round_rate)(struct clk *clk, unsigned long rate);
1018 + int (*clk_set_rate)(struct clk *clk, unsigned long rate);
1019 + int (*clk_set_parent)(struct clk *clk, struct clk *parent);
1020 + void (*clk_allow_idle)(struct clk *clk);
1021 + void (*clk_deny_idle)(struct clk *clk);
1022 + void (*clk_disable_unused)(struct clk *clk);
1023 +#ifdef CONFIG_CPU_FREQ
1024 + void (*clk_init_cpufreq_table)(struct cpufreq_frequency_table **);
1025 +#endif
1026 +};
1027 +
1028 +extern unsigned int mpurate;
1029 +
1030 +extern int clk_init(struct clk_functions *custom_clocks);
1031 +extern void clk_preinit(struct clk *clk);
1032 +extern int clk_register(struct clk *clk);
1033 +extern void clk_reparent(struct clk *child, struct clk *parent);
1034 +extern void clk_unregister(struct clk *clk);
1035 +extern void propagate_rate(struct clk *clk);
1036 +extern void recalculate_root_clocks(void);
1037 +extern unsigned long followparent_recalc(struct clk *clk);
1038 +extern void clk_enable_init_clocks(void);
1039 +#ifdef CONFIG_CPU_FREQ
1040 +extern void clk_init_cpufreq_table(struct cpufreq_frequency_table **table);
1041 +#endif
1042 +
1043 +extern const struct clkops clkops_null;
1044 +
1045 +/* Clock flags */
1046 +/* bit 0 is free */
1047 +#define RATE_FIXED (1 << 1) /* Fixed clock rate */
1048 +/* bits 2-4 are free */
1049 +#define ENABLE_REG_32BIT (1 << 5) /* Use 32-bit access */
1050 +#define CLOCK_IDLE_CONTROL (1 << 7)
1051 +#define CLOCK_NO_IDLE_PARENT (1 << 8)
1052 +#define DELAYED_APP (1 << 9) /* Delay application of clock */
1053 +#define CONFIG_PARTICIPANT (1 << 10) /* Fundamental clock */
1054 +#define ENABLE_ON_INIT (1 << 11) /* Enable upon framework init */
1055 +#define INVERT_ENABLE (1 << 12) /* 0 enables, 1 disables */
1056 +#define CLOCK_IN_OMAP4430 (1 << 13)
1057 +#define ALWAYS_ENABLED (1 << 14)
1058 +/* bits 13-31 are currently free */
1059 +
1060 +/* Clksel_rate flags */
1061 +#define DEFAULT_RATE (1 << 0)
1062 +#define RATE_IN_242X (1 << 1)
1063 +#define RATE_IN_243X (1 << 2)
1064 +#define RATE_IN_343X (1 << 3) /* rates common to all 343X */
1065 +#define RATE_IN_3430ES2 (1 << 4) /* 3430ES2 rates only */
1066 +#define RATE_IN_4430 (1 << 5)
1067 +
1068 +#define RATE_IN_24XX (RATE_IN_242X | RATE_IN_243X)
1069 +
1070 +
1071 +#endif
1072 Index: linux-2.6.37-rc1/arch/arm/plat-omap/include/mach/common.h
1073 ===================================================================
1074 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
1075 +++ linux-2.6.37-rc1/arch/arm/plat-omap/include/mach/common.h 2010-11-05 17:36:26.172000001 +0100
1076 @@ -0,0 +1,83 @@
1077 +/*
1078 + * arch/arm/plat-omap/include/mach/common.h
1079 + *
1080 + * Header for code common to all OMAP machines.
1081 + *
1082 + * This program is free software; you can redistribute it and/or modify it
1083 + * under the terms of the GNU General Public License as published by the
1084 + * Free Software Foundation; either version 2 of the License, or (at your
1085 + * option) any later version.
1086 + *
1087 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
1088 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
1089 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
1090 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
1091 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
1092 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
1093 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
1094 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
1095 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
1096 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
1097 + *
1098 + * You should have received a copy of the GNU General Public License along
1099 + * with this program; if not, write to the Free Software Foundation, Inc.,
1100 + * 675 Mass Ave, Cambridge, MA 02139, USA.
1101 + */
1102 +
1103 +#ifndef __ARCH_ARM_MACH_OMAP_COMMON_H
1104 +#define __ARCH_ARM_MACH_OMAP_COMMON_H
1105 +
1106 +#include <plat/i2c.h>
1107 +
1108 +struct sys_timer;
1109 +
1110 +/* used by omap-smp.c and board-4430sdp.c */
1111 +extern void __iomem *gic_cpu_base_addr;
1112 +
1113 +extern void omap_map_common_io(void);
1114 +extern struct sys_timer omap_timer;
1115 +
1116 +/* IO bases for various OMAP processors */
1117 +struct omap_globals {
1118 + u32 class; /* OMAP class to detect */
1119 + void __iomem *tap; /* Control module ID code */
1120 + void __iomem *sdrc; /* SDRAM Controller */
1121 + void __iomem *sms; /* SDRAM Memory Scheduler */
1122 + void __iomem *ctrl; /* System Control Module */
1123 + void __iomem *prm; /* Power and Reset Management */
1124 + void __iomem *cm; /* Clock Management */
1125 + void __iomem *cm2;
1126 +};
1127 +
1128 +void omap2_set_globals_242x(void);
1129 +void omap2_set_globals_243x(void);
1130 +void omap2_set_globals_343x(void);
1131 +void omap2_set_globals_443x(void);
1132 +
1133 +/* These get called from omap2_set_globals_xxxx(), do not call these */
1134 +void omap2_set_globals_tap(struct omap_globals *);
1135 +void omap2_set_globals_sdrc(struct omap_globals *);
1136 +void omap2_set_globals_control(struct omap_globals *);
1137 +void omap2_set_globals_prcm(struct omap_globals *);
1138 +
1139 +/**
1140 + * omap_test_timeout - busy-loop, testing a condition
1141 + * @cond: condition to test until it evaluates to true
1142 + * @timeout: maximum number of microseconds in the timeout
1143 + * @index: loop index (integer)
1144 + *
1145 + * Loop waiting for @cond to become true or until at least @timeout
1146 + * microseconds have passed. To use, define some integer @index in the
1147 + * calling code. After running, if @index == @timeout, then the loop has
1148 + * timed out.
1149 + */
1150 +#define omap_test_timeout(cond, timeout, index) \
1151 +({ \
1152 + for (index = 0; index < timeout; index++) { \
1153 + if (cond) \
1154 + break; \
1155 + udelay(1); \
1156 + } \
1157 +})
1158 +
1159 +#endif /* __ARCH_ARM_MACH_OMAP_COMMON_H */
1160 Index: linux-2.6.37-rc1/arch/arm/plat-omap/include/mach/control.h
1161 ===================================================================
1162 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
1163 +++ linux-2.6.37-rc1/arch/arm/plat-omap/include/mach/control.h 2010-11-05 17:36:26.172000001 +0100
1164 @@ -0,0 +1,325 @@
1165 +/*
1166 + * arch/arm/plat-omap/include/mach/control.h
1167 + *
1168 + * OMAP2/3/4 System Control Module definitions
1169 + *
1170 + * Copyright (C) 2007-2009 Texas Instruments, Inc.
1171 + * Copyright (C) 2007-2008 Nokia Corporation
1172 + *
1173 + * Written by Paul Walmsley
1174 + *
1175 + * This program is free software; you can redistribute it and/or modify
1176 + * it under the terms of the GNU General Public License as published by
1177 + * the Free Software Foundation.
1178 + */
1179 +
1180 +#ifndef __ASM_ARCH_CONTROL_H
1181 +#define __ASM_ARCH_CONTROL_H
1182 +
1183 +#include <mach/io.h>
1184 +
1185 +#ifndef __ASSEMBLY__
1186 +#define OMAP242X_CTRL_REGADDR(reg) \
1187 + OMAP2_L4_IO_ADDRESS(OMAP242X_CTRL_BASE + (reg))
1188 +#define OMAP243X_CTRL_REGADDR(reg) \
1189 + OMAP2_L4_IO_ADDRESS(OMAP243X_CTRL_BASE + (reg))
1190 +#define OMAP343X_CTRL_REGADDR(reg) \
1191 + OMAP2_L4_IO_ADDRESS(OMAP343X_CTRL_BASE + (reg))
1192 +#else
1193 +#define OMAP242X_CTRL_REGADDR(reg) \
1194 + OMAP2_L4_IO_ADDRESS(OMAP242X_CTRL_BASE + (reg))
1195 +#define OMAP243X_CTRL_REGADDR(reg) \
1196 + OMAP2_L4_IO_ADDRESS(OMAP243X_CTRL_BASE + (reg))
1197 +#define OMAP343X_CTRL_REGADDR(reg) \
1198 + OMAP2_L4_IO_ADDRESS(OMAP343X_CTRL_BASE + (reg))
1199 +#endif /* __ASSEMBLY__ */
1200 +
1201 +/*
1202 + * As elsewhere, the "OMAP2_" prefix indicates that the macro is valid for
1203 + * OMAP24XX and OMAP34XX.
1204 + */
1205 +
1206 +/* Control submodule offsets */
1207 +
1208 +#define OMAP2_CONTROL_INTERFACE 0x000
1209 +#define OMAP2_CONTROL_PADCONFS 0x030
1210 +#define OMAP2_CONTROL_GENERAL 0x270
1211 +#define OMAP343X_CONTROL_MEM_WKUP 0x600
1212 +#define OMAP343X_CONTROL_PADCONFS_WKUP 0xa00
1213 +#define OMAP343X_CONTROL_GENERAL_WKUP 0xa60
1214 +
1215 +/* Control register offsets - read/write with omap_ctrl_{read,write}{bwl}() */
1216 +
1217 +#define OMAP2_CONTROL_SYSCONFIG (OMAP2_CONTROL_INTERFACE + 0x10)
1218 +
1219 +/* CONTROL_GENERAL register offsets common to OMAP2 & 3 */
1220 +#define OMAP2_CONTROL_DEVCONF0 (OMAP2_CONTROL_GENERAL + 0x0004)
1221 +#define OMAP2_CONTROL_MSUSPENDMUX_0 (OMAP2_CONTROL_GENERAL + 0x0020)
1222 +#define OMAP2_CONTROL_MSUSPENDMUX_1 (OMAP2_CONTROL_GENERAL + 0x0024)
1223 +#define OMAP2_CONTROL_MSUSPENDMUX_2 (OMAP2_CONTROL_GENERAL + 0x0028)
1224 +#define OMAP2_CONTROL_MSUSPENDMUX_3 (OMAP2_CONTROL_GENERAL + 0x002c)
1225 +#define OMAP2_CONTROL_MSUSPENDMUX_4 (OMAP2_CONTROL_GENERAL + 0x0030)
1226 +#define OMAP2_CONTROL_MSUSPENDMUX_5 (OMAP2_CONTROL_GENERAL + 0x0034)
1227 +#define OMAP2_CONTROL_SEC_CTRL (OMAP2_CONTROL_GENERAL + 0x0040)
1228 +#define OMAP2_CONTROL_RPUB_KEY_H_0 (OMAP2_CONTROL_GENERAL + 0x0090)
1229 +#define OMAP2_CONTROL_RPUB_KEY_H_1 (OMAP2_CONTROL_GENERAL + 0x0094)
1230 +#define OMAP2_CONTROL_RPUB_KEY_H_2 (OMAP2_CONTROL_GENERAL + 0x0098)
1231 +#define OMAP2_CONTROL_RPUB_KEY_H_3 (OMAP2_CONTROL_GENERAL + 0x009c)
1232 +
1233 +/* 242x-only CONTROL_GENERAL register offsets */
1234 +#define OMAP242X_CONTROL_DEVCONF OMAP2_CONTROL_DEVCONF0 /* match TRM */
1235 +#define OMAP242X_CONTROL_OCM_RAM_PERM (OMAP2_CONTROL_GENERAL + 0x0068)
1236 +
1237 +/* 243x-only CONTROL_GENERAL register offsets */
1238 +/* CONTROL_IVA2_BOOT{ADDR,MOD} are at the same place on 343x - noted below */
1239 +#define OMAP243X_CONTROL_DEVCONF1 (OMAP2_CONTROL_GENERAL + 0x0078)
1240 +#define OMAP243X_CONTROL_CSIRXFE (OMAP2_CONTROL_GENERAL + 0x007c)
1241 +#define OMAP243X_CONTROL_IVA2_BOOTADDR (OMAP2_CONTROL_GENERAL + 0x0190)
1242 +#define OMAP243X_CONTROL_IVA2_BOOTMOD (OMAP2_CONTROL_GENERAL + 0x0194)
1243 +#define OMAP243X_CONTROL_IVA2_GEMCFG (OMAP2_CONTROL_GENERAL + 0x0198)
1244 +#define OMAP243X_CONTROL_PBIAS_LITE (OMAP2_CONTROL_GENERAL + 0x0230)
1245 +
1246 +/* 24xx-only CONTROL_GENERAL register offsets */
1247 +#define OMAP24XX_CONTROL_DEBOBS (OMAP2_CONTROL_GENERAL + 0x0000)
1248 +#define OMAP24XX_CONTROL_EMU_SUPPORT (OMAP2_CONTROL_GENERAL + 0x0008)
1249 +#define OMAP24XX_CONTROL_SEC_TEST (OMAP2_CONTROL_GENERAL + 0x0044)
1250 +#define OMAP24XX_CONTROL_PSA_CTRL (OMAP2_CONTROL_GENERAL + 0x0048)
1251 +#define OMAP24XX_CONTROL_PSA_CMD (OMAP2_CONTROL_GENERAL + 0x004c)
1252 +#define OMAP24XX_CONTROL_PSA_VALUE (OMAP2_CONTROL_GENERAL + 0x0050)
1253 +#define OMAP24XX_CONTROL_SEC_EMU (OMAP2_CONTROL_GENERAL + 0x0060)
1254 +#define OMAP24XX_CONTROL_SEC_TAP (OMAP2_CONTROL_GENERAL + 0x0064)
1255 +#define OMAP24XX_CONTROL_OCM_PUB_RAM_ADD (OMAP2_CONTROL_GENERAL + 0x006c)
1256 +#define OMAP24XX_CONTROL_EXT_SEC_RAM_START_ADD (OMAP2_CONTROL_GENERAL + 0x0070)
1257 +#define OMAP24XX_CONTROL_EXT_SEC_RAM_STOP_ADD (OMAP2_CONTROL_GENERAL + 0x0074)
1258 +#define OMAP24XX_CONTROL_SEC_STATUS (OMAP2_CONTROL_GENERAL + 0x0080)
1259 +#define OMAP24XX_CONTROL_SEC_ERR_STATUS (OMAP2_CONTROL_GENERAL + 0x0084)
1260 +#define OMAP24XX_CONTROL_STATUS (OMAP2_CONTROL_GENERAL + 0x0088)
1261 +#define OMAP24XX_CONTROL_GENERAL_PURPOSE_STATUS (OMAP2_CONTROL_GENERAL + 0x008c)
1262 +#define OMAP24XX_CONTROL_RAND_KEY_0 (OMAP2_CONTROL_GENERAL + 0x00a0)
1263 +#define OMAP24XX_CONTROL_RAND_KEY_1 (OMAP2_CONTROL_GENERAL + 0x00a4)
1264 +#define OMAP24XX_CONTROL_RAND_KEY_2 (OMAP2_CONTROL_GENERAL + 0x00a8)
1265 +#define OMAP24XX_CONTROL_RAND_KEY_3 (OMAP2_CONTROL_GENERAL + 0x00ac)
1266 +#define OMAP24XX_CONTROL_CUST_KEY_0 (OMAP2_CONTROL_GENERAL + 0x00b0)
1267 +#define OMAP24XX_CONTROL_CUST_KEY_1 (OMAP2_CONTROL_GENERAL + 0x00b4)
1268 +#define OMAP24XX_CONTROL_TEST_KEY_0 (OMAP2_CONTROL_GENERAL + 0x00c0)
1269 +#define OMAP24XX_CONTROL_TEST_KEY_1 (OMAP2_CONTROL_GENERAL + 0x00c4)
1270 +#define OMAP24XX_CONTROL_TEST_KEY_2 (OMAP2_CONTROL_GENERAL + 0x00c8)
1271 +#define OMAP24XX_CONTROL_TEST_KEY_3 (OMAP2_CONTROL_GENERAL + 0x00cc)
1272 +#define OMAP24XX_CONTROL_TEST_KEY_4 (OMAP2_CONTROL_GENERAL + 0x00d0)
1273 +#define OMAP24XX_CONTROL_TEST_KEY_5 (OMAP2_CONTROL_GENERAL + 0x00d4)
1274 +#define OMAP24XX_CONTROL_TEST_KEY_6 (OMAP2_CONTROL_GENERAL + 0x00d8)
1275 +#define OMAP24XX_CONTROL_TEST_KEY_7 (OMAP2_CONTROL_GENERAL + 0x00dc)
1276 +#define OMAP24XX_CONTROL_TEST_KEY_8 (OMAP2_CONTROL_GENERAL + 0x00e0)
1277 +#define OMAP24XX_CONTROL_TEST_KEY_9 (OMAP2_CONTROL_GENERAL + 0x00e4)
1278 +
1279 +#define OMAP343X_CONTROL_PADCONF_SYSNIRQ (OMAP2_CONTROL_INTERFACE + 0x01b0)
1280 +
1281 +/* 34xx-only CONTROL_GENERAL register offsets */
1282 +#define OMAP343X_CONTROL_PADCONF_OFF (OMAP2_CONTROL_GENERAL + 0x0000)
1283 +#define OMAP343X_CONTROL_MEM_DFTRW0 (OMAP2_CONTROL_GENERAL + 0x0008)
1284 +#define OMAP343X_CONTROL_MEM_DFTRW1 (OMAP2_CONTROL_GENERAL + 0x000c)
1285 +#define OMAP343X_CONTROL_DEVCONF1 (OMAP2_CONTROL_GENERAL + 0x0068)
1286 +#define OMAP343X_CONTROL_CSIRXFE (OMAP2_CONTROL_GENERAL + 0x006c)
1287 +#define OMAP343X_CONTROL_SEC_STATUS (OMAP2_CONTROL_GENERAL + 0x0070)
1288 +#define OMAP343X_CONTROL_SEC_ERR_STATUS (OMAP2_CONTROL_GENERAL + 0x0074)
1289 +#define OMAP343X_CONTROL_SEC_ERR_STATUS_DEBUG (OMAP2_CONTROL_GENERAL + 0x0078)
1290 +#define OMAP343X_CONTROL_STATUS (OMAP2_CONTROL_GENERAL + 0x0080)
1291 +#define OMAP343X_CONTROL_GENERAL_PURPOSE_STATUS (OMAP2_CONTROL_GENERAL + 0x0084)
1292 +#define OMAP343X_CONTROL_RPUB_KEY_H_4 (OMAP2_CONTROL_GENERAL + 0x00a0)
1293 +#define OMAP343X_CONTROL_RAND_KEY_0 (OMAP2_CONTROL_GENERAL + 0x00a8)
1294 +#define OMAP343X_CONTROL_RAND_KEY_1 (OMAP2_CONTROL_GENERAL + 0x00ac)
1295 +#define OMAP343X_CONTROL_RAND_KEY_2 (OMAP2_CONTROL_GENERAL + 0x00b0)
1296 +#define OMAP343X_CONTROL_RAND_KEY_3 (OMAP2_CONTROL_GENERAL + 0x00b4)
1297 +#define OMAP343X_CONTROL_TEST_KEY_0 (OMAP2_CONTROL_GENERAL + 0x00c8)
1298 +#define OMAP343X_CONTROL_TEST_KEY_1 (OMAP2_CONTROL_GENERAL + 0x00cc)
1299 +#define OMAP343X_CONTROL_TEST_KEY_2 (OMAP2_CONTROL_GENERAL + 0x00d0)
1300 +#define OMAP343X_CONTROL_TEST_KEY_3 (OMAP2_CONTROL_GENERAL + 0x00d4)
1301 +#define OMAP343X_CONTROL_TEST_KEY_4 (OMAP2_CONTROL_GENERAL + 0x00d8)
1302 +#define OMAP343X_CONTROL_TEST_KEY_5 (OMAP2_CONTROL_GENERAL + 0x00dc)
1303 +#define OMAP343X_CONTROL_TEST_KEY_6 (OMAP2_CONTROL_GENERAL + 0x00e0)
1304 +#define OMAP343X_CONTROL_TEST_KEY_7 (OMAP2_CONTROL_GENERAL + 0x00e4)
1305 +#define OMAP343X_CONTROL_TEST_KEY_8 (OMAP2_CONTROL_GENERAL + 0x00e8)
1306 +#define OMAP343X_CONTROL_TEST_KEY_9 (OMAP2_CONTROL_GENERAL + 0x00ec)
1307 +#define OMAP343X_CONTROL_TEST_KEY_10 (OMAP2_CONTROL_GENERAL + 0x00f0)
1308 +#define OMAP343X_CONTROL_TEST_KEY_11 (OMAP2_CONTROL_GENERAL + 0x00f4)
1309 +#define OMAP343X_CONTROL_TEST_KEY_12 (OMAP2_CONTROL_GENERAL + 0x00f8)
1310 +#define OMAP343X_CONTROL_TEST_KEY_13 (OMAP2_CONTROL_GENERAL + 0x00fc)
1311 +#define OMAP343X_CONTROL_IVA2_BOOTADDR (OMAP2_CONTROL_GENERAL + 0x0190)
1312 +#define OMAP343X_CONTROL_IVA2_BOOTMOD (OMAP2_CONTROL_GENERAL + 0x0194)
1313 +#define OMAP343X_CONTROL_DEBOBS(i) (OMAP2_CONTROL_GENERAL + 0x01B0 \
1314 + + ((i) >> 1) * 4 + (!(i) & 1) * 2)
1315 +#define OMAP343X_CONTROL_PROG_IO0 (OMAP2_CONTROL_GENERAL + 0x01D4)
1316 +#define OMAP343X_CONTROL_PROG_IO1 (OMAP2_CONTROL_GENERAL + 0x01D8)
1317 +#define OMAP343X_CONTROL_DSS_DPLL_SPREADING (OMAP2_CONTROL_GENERAL + 0x01E0)
1318 +#define OMAP343X_CONTROL_CORE_DPLL_SPREADING (OMAP2_CONTROL_GENERAL + 0x01E4)
1319 +#define OMAP343X_CONTROL_PER_DPLL_SPREADING (OMAP2_CONTROL_GENERAL + 0x01E8)
1320 +#define OMAP343X_CONTROL_USBHOST_DPLL_SPREADING (OMAP2_CONTROL_GENERAL + 0x01EC)
1321 +#define OMAP343X_CONTROL_PBIAS_LITE (OMAP2_CONTROL_GENERAL + 0x02B0)
1322 +#define OMAP343X_CONTROL_TEMP_SENSOR (OMAP2_CONTROL_GENERAL + 0x02B4)
1323 +#define OMAP343X_CONTROL_SRAMLDO4 (OMAP2_CONTROL_GENERAL + 0x02B8)
1324 +#define OMAP343X_CONTROL_SRAMLDO5 (OMAP2_CONTROL_GENERAL + 0x02C0)
1325 +#define OMAP343X_CONTROL_CSI (OMAP2_CONTROL_GENERAL + 0x02C4)
1326 +
1327 +
1328 +/* 34xx PADCONF register offsets */
1329 +#define OMAP343X_PADCONF_ETK(i) (OMAP2_CONTROL_PADCONFS + 0x5a8 + \
1330 + (i)*2)
1331 +#define OMAP343X_PADCONF_ETK_CLK OMAP343X_PADCONF_ETK(0)
1332 +#define OMAP343X_PADCONF_ETK_CTL OMAP343X_PADCONF_ETK(1)
1333 +#define OMAP343X_PADCONF_ETK_D0 OMAP343X_PADCONF_ETK(2)
1334 +#define OMAP343X_PADCONF_ETK_D1 OMAP343X_PADCONF_ETK(3)
1335 +#define OMAP343X_PADCONF_ETK_D2 OMAP343X_PADCONF_ETK(4)
1336 +#define OMAP343X_PADCONF_ETK_D3 OMAP343X_PADCONF_ETK(5)
1337 +#define OMAP343X_PADCONF_ETK_D4 OMAP343X_PADCONF_ETK(6)
1338 +#define OMAP343X_PADCONF_ETK_D5 OMAP343X_PADCONF_ETK(7)
1339 +#define OMAP343X_PADCONF_ETK_D6 OMAP343X_PADCONF_ETK(8)
1340 +#define OMAP343X_PADCONF_ETK_D7 OMAP343X_PADCONF_ETK(9)
1341 +#define OMAP343X_PADCONF_ETK_D8 OMAP343X_PADCONF_ETK(10)
1342 +#define OMAP343X_PADCONF_ETK_D9 OMAP343X_PADCONF_ETK(11)
1343 +#define OMAP343X_PADCONF_ETK_D10 OMAP343X_PADCONF_ETK(12)
1344 +#define OMAP343X_PADCONF_ETK_D11 OMAP343X_PADCONF_ETK(13)
1345 +#define OMAP343X_PADCONF_ETK_D12 OMAP343X_PADCONF_ETK(14)
1346 +#define OMAP343X_PADCONF_ETK_D13 OMAP343X_PADCONF_ETK(15)
1347 +#define OMAP343X_PADCONF_ETK_D14 OMAP343X_PADCONF_ETK(16)
1348 +#define OMAP343X_PADCONF_ETK_D15 OMAP343X_PADCONF_ETK(17)
1349 +
1350 +/* 34xx GENERAL_WKUP regist offsets */
1351 +#define OMAP343X_CONTROL_WKUP_DEBOBSMUX(i) (OMAP343X_CONTROL_GENERAL_WKUP + \
1352 + 0x008 + (i))
1353 +#define OMAP343X_CONTROL_WKUP_DEBOBS0 (OMAP343X_CONTROL_GENERAL_WKUP + 0x008)
1354 +#define OMAP343X_CONTROL_WKUP_DEBOBS1 (OMAP343X_CONTROL_GENERAL_WKUP + 0x00C)
1355 +#define OMAP343X_CONTROL_WKUP_DEBOBS2 (OMAP343X_CONTROL_GENERAL_WKUP + 0x010)
1356 +#define OMAP343X_CONTROL_WKUP_DEBOBS3 (OMAP343X_CONTROL_GENERAL_WKUP + 0x014)
1357 +#define OMAP343X_CONTROL_WKUP_DEBOBS4 (OMAP343X_CONTROL_GENERAL_WKUP + 0x018)
1358 +
1359 +/* 34xx D2D idle-related pins, handled by PM core */
1360 +#define OMAP3_PADCONF_SAD2D_MSTANDBY 0x250
1361 +#define OMAP3_PADCONF_SAD2D_IDLEACK 0x254
1362 +
1363 +/*
1364 + * REVISIT: This list of registers is not comprehensive - there are more
1365 + * that should be added.
1366 + */
1367 +
1368 +/*
1369 + * Control module register bit defines - these should eventually go into
1370 + * their own regbits file. Some of these will be complicated, depending
1371 + * on the device type (general-purpose, emulator, test, secure, bad, other)
1372 + * and the security mode (secure, non-secure, don't care)
1373 + */
1374 +/* CONTROL_DEVCONF0 bits */
1375 +#define OMAP2_MMCSDIO1ADPCLKISEL (1 << 24) /* MMC1 loop back clock */
1376 +#define OMAP24XX_USBSTANDBYCTRL (1 << 15)
1377 +#define OMAP2_MCBSP2_CLKS_MASK (1 << 6)
1378 +#define OMAP2_MCBSP1_CLKS_MASK (1 << 2)
1379 +
1380 +/* CONTROL_DEVCONF1 bits */
1381 +#define OMAP243X_MMC1_ACTIVE_OVERWRITE (1 << 31)
1382 +#define OMAP2_MMCSDIO2ADPCLKISEL (1 << 6) /* MMC2 loop back clock */
1383 +#define OMAP2_MCBSP5_CLKS_MASK (1 << 4) /* > 242x */
1384 +#define OMAP2_MCBSP4_CLKS_MASK (1 << 2) /* > 242x */
1385 +#define OMAP2_MCBSP3_CLKS_MASK (1 << 0) /* > 242x */
1386 +
1387 +/* CONTROL_STATUS bits */
1388 +#define OMAP2_DEVICETYPE_MASK (0x7 << 8)
1389 +#define OMAP2_SYSBOOT_5_MASK (1 << 5)
1390 +#define OMAP2_SYSBOOT_4_MASK (1 << 4)
1391 +#define OMAP2_SYSBOOT_3_MASK (1 << 3)
1392 +#define OMAP2_SYSBOOT_2_MASK (1 << 2)
1393 +#define OMAP2_SYSBOOT_1_MASK (1 << 1)
1394 +#define OMAP2_SYSBOOT_0_MASK (1 << 0)
1395 +
1396 +/* CONTROL_PBIAS_LITE bits */
1397 +#define OMAP343X_PBIASLITESUPPLY_HIGH1 (1 << 15)
1398 +#define OMAP343X_PBIASLITEVMODEERROR1 (1 << 11)
1399 +#define OMAP343X_PBIASSPEEDCTRL1 (1 << 10)
1400 +#define OMAP343X_PBIASLITEPWRDNZ1 (1 << 9)
1401 +#define OMAP343X_PBIASLITEVMODE1 (1 << 8)
1402 +#define OMAP343X_PBIASLITESUPPLY_HIGH0 (1 << 7)
1403 +#define OMAP343X_PBIASLITEVMODEERROR0 (1 << 3)
1404 +#define OMAP2_PBIASSPEEDCTRL0 (1 << 2)
1405 +#define OMAP2_PBIASLITEPWRDNZ0 (1 << 1)
1406 +#define OMAP2_PBIASLITEVMODE0 (1 << 0)
1407 +
1408 +/* CONTROL_PROG_IO1 bits */
1409 +#define OMAP3630_PRG_SDMMC1_SPEEDCTRL (1 << 20)
1410 +
1411 +/* CONTROL_IVA2_BOOTMOD bits */
1412 +#define OMAP3_IVA2_BOOTMOD_SHIFT 0
1413 +#define OMAP3_IVA2_BOOTMOD_MASK (0xf << 0)
1414 +#define OMAP3_IVA2_BOOTMOD_IDLE (0x1 << 0)
1415 +
1416 +/* CONTROL_PADCONF_X bits */
1417 +#define OMAP3_PADCONF_WAKEUPEVENT0 (1 << 15)
1418 +#define OMAP3_PADCONF_WAKEUPENABLE0 (1 << 14)
1419 +
1420 +#define OMAP343X_SCRATCHPAD_ROM (OMAP343X_CTRL_BASE + 0x860)
1421 +#define OMAP343X_SCRATCHPAD (OMAP343X_CTRL_BASE + 0x910)
1422 +#define OMAP343X_SCRATCHPAD_ROM_OFFSET 0x19C
1423 +
1424 +/*
1425 + * CONTROL OMAP STATUS register to identify OMAP3 features
1426 + */
1427 +#define OMAP3_CONTROL_OMAP_STATUS 0x044c
1428 +
1429 +#define OMAP3_SGX_SHIFT 13
1430 +#define OMAP3_SGX_MASK (3 << OMAP3_SGX_SHIFT)
1431 +#define FEAT_SGX_FULL 0
1432 +#define FEAT_SGX_HALF 1
1433 +#define FEAT_SGX_NONE 2
1434 +
1435 +#define OMAP3_IVA_SHIFT 12
1436 +#define OMAP3_IVA_MASK (1 << OMAP3_SGX_SHIFT)
1437 +#define FEAT_IVA 0
1438 +#define FEAT_IVA_NONE 1
1439 +
1440 +#define OMAP3_L2CACHE_SHIFT 10
1441 +#define OMAP3_L2CACHE_MASK (3 << OMAP3_L2CACHE_SHIFT)
1442 +#define FEAT_L2CACHE_NONE 0
1443 +#define FEAT_L2CACHE_64KB 1
1444 +#define FEAT_L2CACHE_128KB 2
1445 +#define FEAT_L2CACHE_256KB 3
1446 +
1447 +#define OMAP3_ISP_SHIFT 5
1448 +#define OMAP3_ISP_MASK (1<< OMAP3_ISP_SHIFT)
1449 +#define FEAT_ISP 0
1450 +#define FEAT_ISP_NONE 1
1451 +
1452 +#define OMAP3_NEON_SHIFT 4
1453 +#define OMAP3_NEON_MASK (1<< OMAP3_NEON_SHIFT)
1454 +#define FEAT_NEON 0
1455 +#define FEAT_NEON_NONE 1
1456 +
1457 +
1458 +#ifndef __ASSEMBLY__
1459 +#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) || \
1460 + defined(CONFIG_ARCH_OMAP4)
1461 +extern void __iomem *omap_ctrl_base_get(void);
1462 +extern u8 omap_ctrl_readb(u16 offset);
1463 +extern u16 omap_ctrl_readw(u16 offset);
1464 +extern u32 omap_ctrl_readl(u16 offset);
1465 +extern void omap_ctrl_writeb(u8 val, u16 offset);
1466 +extern void omap_ctrl_writew(u16 val, u16 offset);
1467 +extern void omap_ctrl_writel(u32 val, u16 offset);
1468 +
1469 +extern void omap3_save_scratchpad_contents(void);
1470 +extern void omap3_clear_scratchpad_contents(void);
1471 +extern u32 *get_restore_pointer(void);
1472 +extern u32 *get_es3_restore_pointer(void);
1473 +extern u32 omap3_arm_context[128];
1474 +extern void omap3_control_save_context(void);
1475 +extern void omap3_control_restore_context(void);
1476 +
1477 +#else
1478 +#define omap_ctrl_base_get() 0
1479 +#define omap_ctrl_readb(x) 0
1480 +#define omap_ctrl_readw(x) 0
1481 +#define omap_ctrl_readl(x) 0
1482 +#define omap_ctrl_writeb(x, y) WARN_ON(1)
1483 +#define omap_ctrl_writew(x, y) WARN_ON(1)
1484 +#define omap_ctrl_writel(x, y) WARN_ON(1)
1485 +#endif
1486 +#endif /* __ASSEMBLY__ */
1487 +
1488 +#endif /* __ASM_ARCH_CONTROL_H */
1489 +
1490 Index: linux-2.6.37-rc1/arch/arm/plat-omap/include/mach/cpu.h
1491 ===================================================================
1492 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
1493 +++ linux-2.6.37-rc1/arch/arm/plat-omap/include/mach/cpu.h 2010-11-05 17:36:26.172000001 +0100
1494 @@ -0,0 +1,516 @@
1495 +/*
1496 + * arch/arm/plat-omap/include/mach/cpu.h
1497 + *
1498 + * OMAP cpu type detection
1499 + *
1500 + * Copyright (C) 2004, 2008 Nokia Corporation
1501 + *
1502 + * Copyright (C) 2009 Texas Instruments.
1503 + *
1504 + * Written by Tony Lindgren <tony.lindgren@nokia.com>
1505 + *
1506 + * Added OMAP4 specific defines - Santosh Shilimkar<santosh.shilimkar@ti.com>
1507 + *
1508 + * This program is free software; you can redistribute it and/or modify
1509 + * it under the terms of the GNU General Public License as published by
1510 + * the Free Software Foundation; either version 2 of the License, or
1511 + * (at your option) any later version.
1512 + *
1513 + * This program is distributed in the hope that it will be useful,
1514 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
1515 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
1516 + * GNU General Public License for more details.
1517 + *
1518 + * You should have received a copy of the GNU General Public License
1519 + * along with this program; if not, write to the Free Software
1520 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
1521 + *
1522 + */
1523 +
1524 +#ifndef __ASM_ARCH_OMAP_CPU_H
1525 +#define __ASM_ARCH_OMAP_CPU_H
1526 +
1527 +#include <linux/bitops.h>
1528 +
1529 +/*
1530 + * Omap device type i.e. EMU/HS/TST/GP/BAD
1531 + */
1532 +#define OMAP2_DEVICE_TYPE_TEST 0
1533 +#define OMAP2_DEVICE_TYPE_EMU 1
1534 +#define OMAP2_DEVICE_TYPE_SEC 2
1535 +#define OMAP2_DEVICE_TYPE_GP 3
1536 +#define OMAP2_DEVICE_TYPE_BAD 4
1537 +
1538 +int omap_type(void);
1539 +
1540 +struct omap_chip_id {
1541 + u8 oc;
1542 + u8 type;
1543 +};
1544 +
1545 +#define OMAP_CHIP_INIT(x) { .oc = x }
1546 +
1547 +/*
1548 + * omap_rev bits:
1549 + * CPU id bits (0730, 1510, 1710, 2422...) [31:16]
1550 + * CPU revision (See _REV_ defined in cpu.h) [15:08]
1551 + * CPU class bits (15xx, 16xx, 24xx, 34xx...) [07:00]
1552 + */
1553 +unsigned int omap_rev(void);
1554 +
1555 +/*
1556 + * Define CPU revision bits
1557 + *
1558 + * Verbose meaning of the revision bits may be different for a silicon
1559 + * family. This difference can be handled separately.
1560 + */
1561 +#define OMAP_REVBITS_00 0x00
1562 +#define OMAP_REVBITS_10 0x10
1563 +#define OMAP_REVBITS_20 0x20
1564 +#define OMAP_REVBITS_30 0x30
1565 +#define OMAP_REVBITS_40 0x40
1566 +
1567 +/*
1568 + * Get the CPU revision for OMAP devices
1569 + */
1570 +#define GET_OMAP_REVISION() ((omap_rev() >> 8) & 0xff)
1571 +
1572 +/*
1573 + * Test if multicore OMAP support is needed
1574 + */
1575 +#undef MULTI_OMAP1
1576 +#undef MULTI_OMAP2
1577 +#undef OMAP_NAME
1578 +
1579 +#ifdef CONFIG_ARCH_OMAP730
1580 +# ifdef OMAP_NAME
1581 +# undef MULTI_OMAP1
1582 +# define MULTI_OMAP1
1583 +# else
1584 +# define OMAP_NAME omap730
1585 +# endif
1586 +#endif
1587 +#ifdef CONFIG_ARCH_OMAP850
1588 +# ifdef OMAP_NAME
1589 +# undef MULTI_OMAP1
1590 +# define MULTI_OMAP1
1591 +# else
1592 +# define OMAP_NAME omap850
1593 +# endif
1594 +#endif
1595 +#ifdef CONFIG_ARCH_OMAP15XX
1596 +# ifdef OMAP_NAME
1597 +# undef MULTI_OMAP1
1598 +# define MULTI_OMAP1
1599 +# else
1600 +# define OMAP_NAME omap1510
1601 +# endif
1602 +#endif
1603 +#ifdef CONFIG_ARCH_OMAP16XX
1604 +# ifdef OMAP_NAME
1605 +# undef MULTI_OMAP1
1606 +# define MULTI_OMAP1
1607 +# else
1608 +# define OMAP_NAME omap16xx
1609 +# endif
1610 +#endif
1611 +#if (defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX))
1612 +# if (defined(OMAP_NAME) || defined(MULTI_OMAP1))
1613 +# error "OMAP1 and OMAP2 can't be selected at the same time"
1614 +# endif
1615 +#endif
1616 +#ifdef CONFIG_ARCH_OMAP2420
1617 +# ifdef OMAP_NAME
1618 +# undef MULTI_OMAP2
1619 +# define MULTI_OMAP2
1620 +# else
1621 +# define OMAP_NAME omap2420
1622 +# endif
1623 +#endif
1624 +#ifdef CONFIG_ARCH_OMAP2430
1625 +# ifdef OMAP_NAME
1626 +# undef MULTI_OMAP2
1627 +# define MULTI_OMAP2
1628 +# else
1629 +# define OMAP_NAME omap2430
1630 +# endif
1631 +#endif
1632 +#ifdef CONFIG_ARCH_OMAP3430
1633 +# ifdef OMAP_NAME
1634 +# undef MULTI_OMAP2
1635 +# define MULTI_OMAP2
1636 +# else
1637 +# define OMAP_NAME omap3430
1638 +# endif
1639 +#endif
1640 +
1641 +/*
1642 + * Macros to group OMAP into cpu classes.
1643 + * These can be used in most places.
1644 + * cpu_is_omap7xx(): True for OMAP730, OMAP850
1645 + * cpu_is_omap15xx(): True for OMAP1510, OMAP5910 and OMAP310
1646 + * cpu_is_omap16xx(): True for OMAP1610, OMAP5912 and OMAP1710
1647 + * cpu_is_omap24xx(): True for OMAP2420, OMAP2422, OMAP2423, OMAP2430
1648 + * cpu_is_omap242x(): True for OMAP2420, OMAP2422, OMAP2423
1649 + * cpu_is_omap243x(): True for OMAP2430
1650 + * cpu_is_omap343x(): True for OMAP3430
1651 + */
1652 +#define GET_OMAP_CLASS (omap_rev() & 0xff)
1653 +
1654 +#define IS_OMAP_CLASS(class, id) \
1655 +static inline int is_omap ##class (void) \
1656 +{ \
1657 + return (GET_OMAP_CLASS == (id)) ? 1 : 0; \
1658 +}
1659 +
1660 +#define GET_OMAP_SUBCLASS ((omap_rev() >> 20) & 0x0fff)
1661 +
1662 +#define IS_OMAP_SUBCLASS(subclass, id) \
1663 +static inline int is_omap ##subclass (void) \
1664 +{ \
1665 + return (GET_OMAP_SUBCLASS == (id)) ? 1 : 0; \
1666 +}
1667 +
1668 +IS_OMAP_CLASS(7xx, 0x07)
1669 +IS_OMAP_CLASS(15xx, 0x15)
1670 +IS_OMAP_CLASS(16xx, 0x16)
1671 +IS_OMAP_CLASS(24xx, 0x24)
1672 +IS_OMAP_CLASS(34xx, 0x34)
1673 +IS_OMAP_CLASS(44xx, 0x44)
1674 +
1675 +IS_OMAP_SUBCLASS(242x, 0x242)
1676 +IS_OMAP_SUBCLASS(243x, 0x243)
1677 +IS_OMAP_SUBCLASS(343x, 0x343)
1678 +IS_OMAP_SUBCLASS(363x, 0x363)
1679 +IS_OMAP_SUBCLASS(443x, 0x443)
1680 +
1681 +#define cpu_is_omap7xx() 0
1682 +#define cpu_is_omap15xx() 0
1683 +#define cpu_is_omap16xx() 0
1684 +#define cpu_is_omap24xx() 0
1685 +#define cpu_is_omap242x() 0
1686 +#define cpu_is_omap243x() 0
1687 +#define cpu_is_omap34xx() 0
1688 +#define cpu_is_omap343x() 0
1689 +#define cpu_is_omap44xx() 0
1690 +#define cpu_is_omap443x() 0
1691 +
1692 +#if defined(MULTI_OMAP1)
1693 +# if defined(CONFIG_ARCH_OMAP730)
1694 +# undef cpu_is_omap7xx
1695 +# define cpu_is_omap7xx() is_omap7xx()
1696 +# endif
1697 +# if defined(CONFIG_ARCH_OMAP850)
1698 +# undef cpu_is_omap7xx
1699 +# define cpu_is_omap7xx() is_omap7xx()
1700 +# endif
1701 +# if defined(CONFIG_ARCH_OMAP15XX)
1702 +# undef cpu_is_omap15xx
1703 +# define cpu_is_omap15xx() is_omap15xx()
1704 +# endif
1705 +# if defined(CONFIG_ARCH_OMAP16XX)
1706 +# undef cpu_is_omap16xx
1707 +# define cpu_is_omap16xx() is_omap16xx()
1708 +# endif
1709 +#else
1710 +# if defined(CONFIG_ARCH_OMAP730)
1711 +# undef cpu_is_omap7xx
1712 +# define cpu_is_omap7xx() 1
1713 +# endif
1714 +# if defined(CONFIG_ARCH_OMAP850)
1715 +# undef cpu_is_omap7xx
1716 +# define cpu_is_omap7xx() 1
1717 +# endif
1718 +# if defined(CONFIG_ARCH_OMAP15XX)
1719 +# undef cpu_is_omap15xx
1720 +# define cpu_is_omap15xx() 1
1721 +# endif
1722 +# if defined(CONFIG_ARCH_OMAP16XX)
1723 +# undef cpu_is_omap16xx
1724 +# define cpu_is_omap16xx() 1
1725 +# endif
1726 +#endif
1727 +
1728 +#if defined(MULTI_OMAP2)
1729 +# if defined(CONFIG_ARCH_OMAP24XX)
1730 +# undef cpu_is_omap24xx
1731 +# undef cpu_is_omap242x
1732 +# undef cpu_is_omap243x
1733 +# define cpu_is_omap24xx() is_omap24xx()
1734 +# define cpu_is_omap242x() is_omap242x()
1735 +# define cpu_is_omap243x() is_omap243x()
1736 +# endif
1737 +# if defined(CONFIG_ARCH_OMAP34XX)
1738 +# undef cpu_is_omap34xx
1739 +# undef cpu_is_omap343x
1740 +# define cpu_is_omap34xx() is_omap34xx()
1741 +# define cpu_is_omap343x() is_omap343x()
1742 +# endif
1743 +#else
1744 +# if defined(CONFIG_ARCH_OMAP24XX)
1745 +# undef cpu_is_omap24xx
1746 +# define cpu_is_omap24xx() 1
1747 +# endif
1748 +# if defined(CONFIG_ARCH_OMAP2420)
1749 +# undef cpu_is_omap242x
1750 +# define cpu_is_omap242x() 1
1751 +# endif
1752 +# if defined(CONFIG_ARCH_OMAP2430)
1753 +# undef cpu_is_omap243x
1754 +# define cpu_is_omap243x() 1
1755 +# endif
1756 +# if defined(CONFIG_ARCH_OMAP34XX)
1757 +# undef cpu_is_omap34xx
1758 +# define cpu_is_omap34xx() 1
1759 +# endif
1760 +# if defined(CONFIG_ARCH_OMAP3430)
1761 +# undef cpu_is_omap343x
1762 +# define cpu_is_omap343x() 1
1763 +# endif
1764 +#endif
1765 +
1766 +/*
1767 + * Macros to detect individual cpu types.
1768 + * These are only rarely needed.
1769 + * cpu_is_omap330(): True for OMAP330
1770 + * cpu_is_omap730(): True for OMAP730
1771 + * cpu_is_omap850(): True for OMAP850
1772 + * cpu_is_omap1510(): True for OMAP1510
1773 + * cpu_is_omap1610(): True for OMAP1610
1774 + * cpu_is_omap1611(): True for OMAP1611
1775 + * cpu_is_omap5912(): True for OMAP5912
1776 + * cpu_is_omap1621(): True for OMAP1621
1777 + * cpu_is_omap1710(): True for OMAP1710
1778 + * cpu_is_omap2420(): True for OMAP2420
1779 + * cpu_is_omap2422(): True for OMAP2422
1780 + * cpu_is_omap2423(): True for OMAP2423
1781 + * cpu_is_omap2430(): True for OMAP2430
1782 + * cpu_is_omap3430(): True for OMAP3430
1783 + * cpu_is_omap3505(): True for OMAP3505
1784 + * cpu_is_omap3517(): True for OMAP3517
1785 + */
1786 +#define GET_OMAP_TYPE ((omap_rev() >> 16) & 0xffff)
1787 +
1788 +#define IS_OMAP_TYPE(type, id) \
1789 +static inline int is_omap ##type (void) \
1790 +{ \
1791 + return (GET_OMAP_TYPE == (id)) ? 1 : 0; \
1792 +}
1793 +
1794 +IS_OMAP_TYPE(310, 0x0310)
1795 +IS_OMAP_TYPE(730, 0x0730)
1796 +IS_OMAP_TYPE(850, 0x0850)
1797 +IS_OMAP_TYPE(1510, 0x1510)
1798 +IS_OMAP_TYPE(1610, 0x1610)
1799 +IS_OMAP_TYPE(1611, 0x1611)
1800 +IS_OMAP_TYPE(5912, 0x1611)
1801 +IS_OMAP_TYPE(1621, 0x1621)
1802 +IS_OMAP_TYPE(1710, 0x1710)
1803 +IS_OMAP_TYPE(2420, 0x2420)
1804 +IS_OMAP_TYPE(2422, 0x2422)
1805 +IS_OMAP_TYPE(2423, 0x2423)
1806 +IS_OMAP_TYPE(2430, 0x2430)
1807 +IS_OMAP_TYPE(3430, 0x3430)
1808 +IS_OMAP_TYPE(3505, 0x3505)
1809 +IS_OMAP_TYPE(3517, 0x3517)
1810 +
1811 +#define cpu_is_omap310() 0
1812 +#define cpu_is_omap730() 0
1813 +#define cpu_is_omap850() 0
1814 +#define cpu_is_omap1510() 0
1815 +#define cpu_is_omap1610() 0
1816 +#define cpu_is_omap5912() 0
1817 +#define cpu_is_omap1611() 0
1818 +#define cpu_is_omap1621() 0
1819 +#define cpu_is_omap1710() 0
1820 +#define cpu_is_omap2420() 0
1821 +#define cpu_is_omap2422() 0
1822 +#define cpu_is_omap2423() 0
1823 +#define cpu_is_omap2430() 0
1824 +#define cpu_is_omap3503() 0
1825 +#define cpu_is_omap3515() 0
1826 +#define cpu_is_omap3525() 0
1827 +#define cpu_is_omap3530() 0
1828 +#define cpu_is_omap3505() 0
1829 +#define cpu_is_omap3517() 0
1830 +#define cpu_is_omap3430() 0
1831 +#define cpu_is_omap3630() 0
1832 +
1833 +/*
1834 + * Whether we have MULTI_OMAP1 or not, we still need to distinguish
1835 + * between 730 vs 850, 330 vs. 1510 and 1611B/5912 vs. 1710.
1836 + */
1837 +
1838 +#if defined(CONFIG_ARCH_OMAP730)
1839 +# undef cpu_is_omap730
1840 +# define cpu_is_omap730() is_omap730()
1841 +#endif
1842 +
1843 +#if defined(CONFIG_ARCH_OMAP850)
1844 +# undef cpu_is_omap850
1845 +# define cpu_is_omap850() is_omap850()
1846 +#endif
1847 +
1848 +#if defined(CONFIG_ARCH_OMAP15XX)
1849 +# undef cpu_is_omap310
1850 +# undef cpu_is_omap1510
1851 +# define cpu_is_omap310() is_omap310()
1852 +# define cpu_is_omap1510() is_omap1510()
1853 +#endif
1854 +
1855 +#if defined(CONFIG_ARCH_OMAP16XX)
1856 +# undef cpu_is_omap1610
1857 +# undef cpu_is_omap1611
1858 +# undef cpu_is_omap5912
1859 +# undef cpu_is_omap1621
1860 +# undef cpu_is_omap1710
1861 +# define cpu_is_omap1610() is_omap1610()
1862 +# define cpu_is_omap1611() is_omap1611()
1863 +# define cpu_is_omap5912() is_omap5912()
1864 +# define cpu_is_omap1621() is_omap1621()
1865 +# define cpu_is_omap1710() is_omap1710()
1866 +#endif
1867 +
1868 +#if defined(CONFIG_ARCH_OMAP24XX)
1869 +# undef cpu_is_omap2420
1870 +# undef cpu_is_omap2422
1871 +# undef cpu_is_omap2423
1872 +# undef cpu_is_omap2430
1873 +# define cpu_is_omap2420() is_omap2420()
1874 +# define cpu_is_omap2422() is_omap2422()
1875 +# define cpu_is_omap2423() is_omap2423()
1876 +# define cpu_is_omap2430() is_omap2430()
1877 +#endif
1878 +
1879 +#if defined(CONFIG_ARCH_OMAP34XX)
1880 +# undef cpu_is_omap3430
1881 +# undef cpu_is_omap3503
1882 +# undef cpu_is_omap3515
1883 +# undef cpu_is_omap3525
1884 +# undef cpu_is_omap3530
1885 +# undef cpu_is_omap3505
1886 +# undef cpu_is_omap3517
1887 +# define cpu_is_omap3430() is_omap3430()
1888 +# define cpu_is_omap3503() (cpu_is_omap3430() && \
1889 + (!omap3_has_iva()) && \
1890 + (!omap3_has_sgx()))
1891 +# define cpu_is_omap3515() (cpu_is_omap3430() && \
1892 + (!omap3_has_iva()) && \
1893 + (omap3_has_sgx()))
1894 +# define cpu_is_omap3525() (cpu_is_omap3430() && \
1895 + (!omap3_has_sgx()) && \
1896 + (omap3_has_iva()))
1897 +# define cpu_is_omap3530() (cpu_is_omap3430())
1898 +# define cpu_is_omap3505() is_omap3505()
1899 +# define cpu_is_omap3517() is_omap3517()
1900 +# undef cpu_is_omap3630
1901 +# define cpu_is_omap3630() is_omap363x()
1902 +#endif
1903 +
1904 +# if defined(CONFIG_ARCH_OMAP4)
1905 +# undef cpu_is_omap44xx
1906 +# undef cpu_is_omap443x
1907 +# define cpu_is_omap44xx() is_omap44xx()
1908 +# define cpu_is_omap443x() is_omap443x()
1909 +# endif
1910 +
1911 +/* Macros to detect if we have OMAP1 or OMAP2 */
1912 +#define cpu_class_is_omap1() (cpu_is_omap7xx() || cpu_is_omap15xx() || \
1913 + cpu_is_omap16xx())
1914 +#define cpu_class_is_omap2() (cpu_is_omap24xx() || cpu_is_omap34xx() || \
1915 + cpu_is_omap44xx())
1916 +
1917 +/* Various silicon revisions for omap2 */
1918 +#define OMAP242X_CLASS 0x24200024
1919 +#define OMAP2420_REV_ES1_0 0x24200024
1920 +#define OMAP2420_REV_ES2_0 0x24201024
1921 +
1922 +#define OMAP243X_CLASS 0x24300024
1923 +#define OMAP2430_REV_ES1_0 0x24300024
1924 +
1925 +#define OMAP343X_CLASS 0x34300034
1926 +#define OMAP3430_REV_ES1_0 0x34300034
1927 +#define OMAP3430_REV_ES2_0 0x34301034
1928 +#define OMAP3430_REV_ES2_1 0x34302034
1929 +#define OMAP3430_REV_ES3_0 0x34303034
1930 +#define OMAP3430_REV_ES3_1 0x34304034
1931 +
1932 +#define OMAP3630_REV_ES1_0 0x36300034
1933 +
1934 +#define OMAP35XX_CLASS 0x35000034
1935 +#define OMAP3503_REV(v) (OMAP35XX_CLASS | (0x3503 << 16) | (v << 8))
1936 +#define OMAP3515_REV(v) (OMAP35XX_CLASS | (0x3515 << 16) | (v << 8))
1937 +#define OMAP3525_REV(v) (OMAP35XX_CLASS | (0x3525 << 16) | (v << 8))
1938 +#define OMAP3530_REV(v) (OMAP35XX_CLASS | (0x3530 << 16) | (v << 8))
1939 +#define OMAP3505_REV(v) (OMAP35XX_CLASS | (0x3505 << 16) | (v << 8))
1940 +#define OMAP3517_REV(v) (OMAP35XX_CLASS | (0x3517 << 16) | (v << 8))
1941 +
1942 +#define OMAP443X_CLASS 0x44300044
1943 +#define OMAP4430_REV_ES1_0 0x44300044
1944 +
1945 +/*
1946 + * omap_chip bits
1947 + *
1948 + * CHIP_IS_OMAP{2420,2430,3430} indicate that a particular structure is
1949 + * valid on all chips of that type. CHIP_IS_OMAP3430ES{1,2} indicates
1950 + * something that is only valid on that particular ES revision.
1951 + *
1952 + * These bits may be ORed together to indicate structures that are
1953 + * available on multiple chip types.
1954 + *
1955 + * To test whether a particular structure matches the current OMAP chip type,
1956 + * use omap_chip_is().
1957 + *
1958 + */
1959 +#define CHIP_IS_OMAP2420 (1 << 0)
1960 +#define CHIP_IS_OMAP2430 (1 << 1)
1961 +#define CHIP_IS_OMAP3430 (1 << 2)
1962 +#define CHIP_IS_OMAP3430ES1 (1 << 3)
1963 +#define CHIP_IS_OMAP3430ES2 (1 << 4)
1964 +#define CHIP_IS_OMAP3430ES3_0 (1 << 5)
1965 +#define CHIP_IS_OMAP3430ES3_1 (1 << 6)
1966 +#define CHIP_IS_OMAP3630ES1 (1 << 7)
1967 +
1968 +#define CHIP_IS_OMAP24XX (CHIP_IS_OMAP2420 | CHIP_IS_OMAP2430)
1969 +
1970 +/*
1971 + * "GE" here represents "greater than or equal to" in terms of ES
1972 + * levels. So CHIP_GE_OMAP3430ES2 is intended to match all OMAP3430
1973 + * chips at ES2 and beyond, but not, for example, any OMAP lines after
1974 + * OMAP3.
1975 + */
1976 +#define CHIP_GE_OMAP3430ES2 (CHIP_IS_OMAP3430ES2 | \
1977 + CHIP_IS_OMAP3430ES3_0 | \
1978 + CHIP_IS_OMAP3430ES3_1 | \
1979 + CHIP_IS_OMAP3630ES1)
1980 +#define CHIP_GE_OMAP3430ES3_1 (CHIP_IS_OMAP3430ES3_1 | \
1981 + CHIP_IS_OMAP3630ES1)
1982 +
1983 +
1984 +int omap_chip_is(struct omap_chip_id oci);
1985 +void omap2_check_revision(void);
1986 +
1987 +/*
1988 + * Runtime detection of OMAP3 features
1989 + */
1990 +extern u32 omap3_features;
1991 +
1992 +#define OMAP3_HAS_L2CACHE BIT(0)
1993 +#define OMAP3_HAS_IVA BIT(1)
1994 +#define OMAP3_HAS_SGX BIT(2)
1995 +#define OMAP3_HAS_NEON BIT(3)
1996 +#define OMAP3_HAS_ISP BIT(4)
1997 +
1998 +#define OMAP3_HAS_FEATURE(feat,flag) \
1999 +static inline unsigned int omap3_has_ ##feat(void) \
2000 +{ \
2001 + return (omap3_features & OMAP3_HAS_ ##flag); \
2002 +} \
2003 +
2004 +OMAP3_HAS_FEATURE(l2cache, L2CACHE)
2005 +OMAP3_HAS_FEATURE(sgx, SGX)
2006 +OMAP3_HAS_FEATURE(iva, IVA)
2007 +OMAP3_HAS_FEATURE(neon, NEON)
2008 +OMAP3_HAS_FEATURE(isp, ISP)
2009 +
2010 +#endif
2011 Index: linux-2.6.37-rc1/arch/arm/plat-omap/include/mach/display.h
2012 ===================================================================
2013 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
2014 +++ linux-2.6.37-rc1/arch/arm/plat-omap/include/mach/display.h 2010-11-05 17:36:26.173000001 +0100
2015 @@ -0,0 +1,575 @@
2016 +/*
2017 + * linux/include/asm-arm/arch-omap/display.h
2018 + *
2019 + * Copyright (C) 2008 Nokia Corporation
2020 + * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
2021 + *
2022 + * This program is free software; you can redistribute it and/or modify it
2023 + * under the terms of the GNU General Public License version 2 as published by
2024 + * the Free Software Foundation.
2025 + *
2026 + * This program is distributed in the hope that it will be useful, but WITHOUT
2027 + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
2028 + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
2029 + * more details.
2030 + *
2031 + * You should have received a copy of the GNU General Public License along with
2032 + * this program. If not, see <http://www.gnu.org/licenses/>.
2033 + */
2034 +
2035 +#ifndef __ASM_ARCH_OMAP_DISPLAY_H
2036 +#define __ASM_ARCH_OMAP_DISPLAY_H
2037 +
2038 +#include <linux/list.h>
2039 +#include <linux/kobject.h>
2040 +#include <linux/device.h>
2041 +#include <asm/atomic.h>
2042 +
2043 +#define DISPC_IRQ_FRAMEDONE (1 << 0)
2044 +#define DISPC_IRQ_VSYNC (1 << 1)
2045 +#define DISPC_IRQ_EVSYNC_EVEN (1 << 2)
2046 +#define DISPC_IRQ_EVSYNC_ODD (1 << 3)
2047 +#define DISPC_IRQ_ACBIAS_COUNT_STAT (1 << 4)
2048 +#define DISPC_IRQ_PROG_LINE_NUM (1 << 5)
2049 +#define DISPC_IRQ_GFX_FIFO_UNDERFLOW (1 << 6)
2050 +#define DISPC_IRQ_GFX_END_WIN (1 << 7)
2051 +#define DISPC_IRQ_PAL_GAMMA_MASK (1 << 8)
2052 +#define DISPC_IRQ_OCP_ERR (1 << 9)
2053 +#define DISPC_IRQ_VID1_FIFO_UNDERFLOW (1 << 10)
2054 +#define DISPC_IRQ_VID1_END_WIN (1 << 11)
2055 +#define DISPC_IRQ_VID2_FIFO_UNDERFLOW (1 << 12)
2056 +#define DISPC_IRQ_VID2_END_WIN (1 << 13)
2057 +#define DISPC_IRQ_SYNC_LOST (1 << 14)
2058 +#define DISPC_IRQ_SYNC_LOST_DIGIT (1 << 15)
2059 +#define DISPC_IRQ_WAKEUP (1 << 16)
2060 +
2061 +struct omap_dss_device;
2062 +struct omap_overlay_manager;
2063 +
2064 +enum omap_display_type {
2065 + OMAP_DISPLAY_TYPE_NONE = 0,
2066 + OMAP_DISPLAY_TYPE_DPI = 1 << 0,
2067 + OMAP_DISPLAY_TYPE_DBI = 1 << 1,
2068 + OMAP_DISPLAY_TYPE_SDI = 1 << 2,
2069 + OMAP_DISPLAY_TYPE_DSI = 1 << 3,
2070 + OMAP_DISPLAY_TYPE_VENC = 1 << 4,
2071 +};
2072 +
2073 +enum omap_plane {
2074 + OMAP_DSS_GFX = 0,
2075 + OMAP_DSS_VIDEO1 = 1,
2076 + OMAP_DSS_VIDEO2 = 2
2077 +};
2078 +
2079 +enum omap_channel {
2080 + OMAP_DSS_CHANNEL_LCD = 0,
2081 + OMAP_DSS_CHANNEL_DIGIT = 1,
2082 +};
2083 +
2084 +enum omap_color_mode {
2085 + OMAP_DSS_COLOR_CLUT1 = 1 << 0, /* BITMAP 1 */
2086 + OMAP_DSS_COLOR_CLUT2 = 1 << 1, /* BITMAP 2 */
2087 + OMAP_DSS_COLOR_CLUT4 = 1 << 2, /* BITMAP 4 */
2088 + OMAP_DSS_COLOR_CLUT8 = 1 << 3, /* BITMAP 8 */
2089 + OMAP_DSS_COLOR_RGB12U = 1 << 4, /* RGB12, 16-bit container */
2090 + OMAP_DSS_COLOR_ARGB16 = 1 << 5, /* ARGB16 */
2091 + OMAP_DSS_COLOR_RGB16 = 1 << 6, /* RGB16 */
2092 + OMAP_DSS_COLOR_RGB24U = 1 << 7, /* RGB24, 32-bit container */
2093 + OMAP_DSS_COLOR_RGB24P = 1 << 8, /* RGB24, 24-bit container */
2094 + OMAP_DSS_COLOR_YUV2 = 1 << 9, /* YUV2 4:2:2 co-sited */
2095 + OMAP_DSS_COLOR_UYVY = 1 << 10, /* UYVY 4:2:2 co-sited */
2096 + OMAP_DSS_COLOR_ARGB32 = 1 << 11, /* ARGB32 */
2097 + OMAP_DSS_COLOR_RGBA32 = 1 << 12, /* RGBA32 */
2098 + OMAP_DSS_COLOR_RGBX32 = 1 << 13, /* RGBx32 */
2099 +
2100 + OMAP_DSS_COLOR_GFX_OMAP2 =
2101 + OMAP_DSS_COLOR_CLUT1 | OMAP_DSS_COLOR_CLUT2 |
2102 + OMAP_DSS_COLOR_CLUT4 | OMAP_DSS_COLOR_CLUT8 |
2103 + OMAP_DSS_COLOR_RGB12U | OMAP_DSS_COLOR_RGB16 |
2104 + OMAP_DSS_COLOR_RGB24U | OMAP_DSS_COLOR_RGB24P,
2105 +
2106 + OMAP_DSS_COLOR_VID_OMAP2 =
2107 + OMAP_DSS_COLOR_RGB16 | OMAP_DSS_COLOR_RGB24U |
2108 + OMAP_DSS_COLOR_RGB24P | OMAP_DSS_COLOR_YUV2 |
2109 + OMAP_DSS_COLOR_UYVY,
2110 +
2111 + OMAP_DSS_COLOR_GFX_OMAP3 =
2112 + OMAP_DSS_COLOR_CLUT1 | OMAP_DSS_COLOR_CLUT2 |
2113 + OMAP_DSS_COLOR_CLUT4 | OMAP_DSS_COLOR_CLUT8 |
2114 + OMAP_DSS_COLOR_RGB12U | OMAP_DSS_COLOR_ARGB16 |
2115 + OMAP_DSS_COLOR_RGB16 | OMAP_DSS_COLOR_RGB24U |
2116 + OMAP_DSS_COLOR_RGB24P | OMAP_DSS_COLOR_ARGB32 |
2117 + OMAP_DSS_COLOR_RGBA32 | OMAP_DSS_COLOR_RGBX32,
2118 +
2119 + OMAP_DSS_COLOR_VID1_OMAP3 =
2120 + OMAP_DSS_COLOR_RGB12U | OMAP_DSS_COLOR_RGB16 |
2121 + OMAP_DSS_COLOR_RGB24U | OMAP_DSS_COLOR_RGB24P |
2122 + OMAP_DSS_COLOR_YUV2 | OMAP_DSS_COLOR_UYVY,
2123 +
2124 + OMAP_DSS_COLOR_VID2_OMAP3 =
2125 + OMAP_DSS_COLOR_RGB12U | OMAP_DSS_COLOR_ARGB16 |
2126 + OMAP_DSS_COLOR_RGB16 | OMAP_DSS_COLOR_RGB24U |
2127 + OMAP_DSS_COLOR_RGB24P | OMAP_DSS_COLOR_YUV2 |
2128 + OMAP_DSS_COLOR_UYVY | OMAP_DSS_COLOR_ARGB32 |
2129 + OMAP_DSS_COLOR_RGBA32 | OMAP_DSS_COLOR_RGBX32,
2130 +};
2131 +
2132 +enum omap_lcd_display_type {
2133 + OMAP_DSS_LCD_DISPLAY_STN,
2134 + OMAP_DSS_LCD_DISPLAY_TFT,
2135 +};
2136 +
2137 +enum omap_dss_load_mode {
2138 + OMAP_DSS_LOAD_CLUT_AND_FRAME = 0,
2139 + OMAP_DSS_LOAD_CLUT_ONLY = 1,
2140 + OMAP_DSS_LOAD_FRAME_ONLY = 2,
2141 + OMAP_DSS_LOAD_CLUT_ONCE_FRAME = 3,
2142 +};
2143 +
2144 +enum omap_dss_trans_key_type {
2145 + OMAP_DSS_COLOR_KEY_GFX_DST = 0,
2146 + OMAP_DSS_COLOR_KEY_VID_SRC = 1,
2147 +};
2148 +
2149 +enum omap_rfbi_te_mode {
2150 + OMAP_DSS_RFBI_TE_MODE_1 = 1,
2151 + OMAP_DSS_RFBI_TE_MODE_2 = 2,
2152 +};
2153 +
2154 +enum omap_panel_config {
2155 + OMAP_DSS_LCD_IVS = 1<<0,
2156 + OMAP_DSS_LCD_IHS = 1<<1,
2157 + OMAP_DSS_LCD_IPC = 1<<2,
2158 + OMAP_DSS_LCD_IEO = 1<<3,
2159 + OMAP_DSS_LCD_RF = 1<<4,
2160 + OMAP_DSS_LCD_ONOFF = 1<<5,
2161 +
2162 + OMAP_DSS_LCD_TFT = 1<<20,
2163 +};
2164 +
2165 +enum omap_dss_venc_type {
2166 + OMAP_DSS_VENC_TYPE_COMPOSITE,
2167 + OMAP_DSS_VENC_TYPE_SVIDEO,
2168 +};
2169 +
2170 +enum omap_display_caps {
2171 + OMAP_DSS_DISPLAY_CAP_MANUAL_UPDATE = 1 << 0,
2172 + OMAP_DSS_DISPLAY_CAP_TEAR_ELIM = 1 << 1,
2173 +};
2174 +
2175 +enum omap_dss_update_mode {
2176 + OMAP_DSS_UPDATE_DISABLED = 0,
2177 + OMAP_DSS_UPDATE_AUTO,
2178 + OMAP_DSS_UPDATE_MANUAL,
2179 +};
2180 +
2181 +enum omap_dss_display_state {
2182 + OMAP_DSS_DISPLAY_DISABLED = 0,
2183 + OMAP_DSS_DISPLAY_ACTIVE,
2184 + OMAP_DSS_DISPLAY_SUSPENDED,
2185 +};
2186 +
2187 +/* XXX perhaps this should be removed */
2188 +enum omap_dss_overlay_managers {
2189 + OMAP_DSS_OVL_MGR_LCD,
2190 + OMAP_DSS_OVL_MGR_TV,
2191 +};
2192 +
2193 +enum omap_dss_rotation_type {
2194 + OMAP_DSS_ROT_DMA = 0,
2195 + OMAP_DSS_ROT_VRFB = 1,
2196 +};
2197 +
2198 +/* clockwise rotation angle */
2199 +enum omap_dss_rotation_angle {
2200 + OMAP_DSS_ROT_0 = 0,
2201 + OMAP_DSS_ROT_90 = 1,
2202 + OMAP_DSS_ROT_180 = 2,
2203 + OMAP_DSS_ROT_270 = 3,
2204 +};
2205 +
2206 +enum omap_overlay_caps {
2207 + OMAP_DSS_OVL_CAP_SCALE = 1 << 0,
2208 + OMAP_DSS_OVL_CAP_DISPC = 1 << 1,
2209 +};
2210 +
2211 +enum omap_overlay_manager_caps {
2212 + OMAP_DSS_OVL_MGR_CAP_DISPC = 1 << 0,
2213 +};
2214 +
2215 +/* RFBI */
2216 +
2217 +struct rfbi_timings {
2218 + int cs_on_time;
2219 + int cs_off_time;
2220 + int we_on_time;
2221 + int we_off_time;
2222 + int re_on_time;
2223 + int re_off_time;
2224 + int we_cycle_time;
2225 + int re_cycle_time;
2226 + int cs_pulse_width;
2227 + int access_time;
2228 +
2229 + int clk_div;
2230 +
2231 + u32 tim[5]; /* set by rfbi_convert_timings() */
2232 +
2233 + int converted;
2234 +};
2235 +
2236 +void omap_rfbi_write_command(const void *buf, u32 len);
2237 +void omap_rfbi_read_data(void *buf, u32 len);
2238 +void omap_rfbi_write_data(const void *buf, u32 len);
2239 +void omap_rfbi_write_pixels(const void __iomem *buf, int scr_width,
2240 + u16 x, u16 y,
2241 + u16 w, u16 h);
2242 +int omap_rfbi_enable_te(bool enable, unsigned line);
2243 +int omap_rfbi_setup_te(enum omap_rfbi_te_mode mode,
2244 + unsigned hs_pulse_time, unsigned vs_pulse_time,
2245 + int hs_pol_inv, int vs_pol_inv, int extif_div);
2246 +
2247 +/* DSI */
2248 +void dsi_bus_lock(void);
2249 +void dsi_bus_unlock(void);
2250 +int dsi_vc_dcs_write(int channel, u8 *data, int len);
2251 +int dsi_vc_dcs_write_nosync(int channel, u8 *data, int len);
2252 +int dsi_vc_dcs_read(int channel, u8 dcs_cmd, u8 *buf, int buflen);
2253 +int dsi_vc_set_max_rx_packet_size(int channel, u16 len);
2254 +int dsi_vc_send_null(int channel);
2255 +int dsi_vc_send_bta_sync(int channel);
2256 +
2257 +/* Board specific data */
2258 +struct omap_dss_board_info {
2259 + int (*get_last_off_on_transaction_id)(struct device *dev);
2260 + int num_devices;
2261 + struct omap_dss_device **devices;
2262 + struct omap_dss_device *default_device;
2263 +};
2264 +
2265 +struct omap_video_timings {
2266 + /* Unit: pixels */
2267 + u16 x_res;
2268 + /* Unit: pixels */
2269 + u16 y_res;
2270 + /* Unit: KHz */
2271 + u32 pixel_clock;
2272 + /* Unit: pixel clocks */
2273 + u16 hsw; /* Horizontal synchronization pulse width */
2274 + /* Unit: pixel clocks */
2275 + u16 hfp; /* Horizontal front porch */
2276 + /* Unit: pixel clocks */
2277 + u16 hbp; /* Horizontal back porch */
2278 + /* Unit: line clocks */
2279 + u16 vsw; /* Vertical synchronization pulse width */
2280 + /* Unit: line clocks */
2281 + u16 vfp; /* Vertical front porch */
2282 + /* Unit: line clocks */
2283 + u16 vbp; /* Vertical back porch */
2284 +};
2285 +
2286 +#ifdef CONFIG_OMAP2_DSS_VENC
2287 +/* Hardcoded timings for tv modes. Venc only uses these to
2288 + * identify the mode, and does not actually use the configs
2289 + * itself. However, the configs should be something that
2290 + * a normal monitor can also show */
2291 +const extern struct omap_video_timings omap_dss_pal_timings;
2292 +const extern struct omap_video_timings omap_dss_ntsc_timings;
2293 +#endif
2294 +
2295 +struct omap_overlay_info {
2296 + bool enabled;
2297 +
2298 + u32 paddr;
2299 + void __iomem *vaddr;
2300 + u16 screen_width;
2301 + u16 width;
2302 + u16 height;
2303 + enum omap_color_mode color_mode;
2304 + u8 rotation;
2305 + enum omap_dss_rotation_type rotation_type;
2306 + bool mirror;
2307 +
2308 + u16 pos_x;
2309 + u16 pos_y;
2310 + u16 out_width; /* if 0, out_width == width */
2311 + u16 out_height; /* if 0, out_height == height */
2312 + u8 global_alpha;
2313 +};
2314 +
2315 +struct omap_overlay {
2316 + struct kobject kobj;
2317 + struct list_head list;
2318 +
2319 + /* static fields */
2320 + const char *name;
2321 + int id;
2322 + enum omap_color_mode supported_modes;
2323 + enum omap_overlay_caps caps;
2324 +
2325 + /* dynamic fields */
2326 + struct omap_overlay_manager *manager;
2327 + struct omap_overlay_info info;
2328 +
2329 + /* if true, info has been changed, but not applied() yet */
2330 + bool info_dirty;
2331 +
2332 + int (*set_manager)(struct omap_overlay *ovl,
2333 + struct omap_overlay_manager *mgr);
2334 + int (*unset_manager)(struct omap_overlay *ovl);
2335 +
2336 + int (*set_overlay_info)(struct omap_overlay *ovl,
2337 + struct omap_overlay_info *info);
2338 + void (*get_overlay_info)(struct omap_overlay *ovl,
2339 + struct omap_overlay_info *info);
2340 +
2341 + int (*wait_for_go)(struct omap_overlay *ovl);
2342 +};
2343 +
2344 +struct omap_overlay_manager_info {
2345 + u32 default_color;
2346 +
2347 + enum omap_dss_trans_key_type trans_key_type;
2348 + u32 trans_key;
2349 + bool trans_enabled;
2350 +
2351 + bool alpha_enabled;
2352 +};
2353 +
2354 +struct omap_overlay_manager {
2355 + struct kobject kobj;
2356 + struct list_head list;
2357 +
2358 + /* static fields */
2359 + const char *name;
2360 + int id;
2361 + enum omap_overlay_manager_caps caps;
2362 + int num_overlays;
2363 + struct omap_overlay **overlays;
2364 + enum omap_display_type supported_displays;
2365 +
2366 + /* dynamic fields */
2367 + struct omap_dss_device *device;
2368 + struct omap_overlay_manager_info info;
2369 +
2370 + bool device_changed;
2371 + /* if true, info has been changed but not applied() yet */
2372 + bool info_dirty;
2373 +
2374 + int (*set_device)(struct omap_overlay_manager *mgr,
2375 + struct omap_dss_device *dssdev);
2376 + int (*unset_device)(struct omap_overlay_manager *mgr);
2377 +
2378 + int (*set_manager_info)(struct omap_overlay_manager *mgr,
2379 + struct omap_overlay_manager_info *info);
2380 + void (*get_manager_info)(struct omap_overlay_manager *mgr,
2381 + struct omap_overlay_manager_info *info);
2382 +
2383 + int (*apply)(struct omap_overlay_manager *mgr);
2384 + int (*wait_for_go)(struct omap_overlay_manager *mgr);
2385 +};
2386 +
2387 +struct omap_dss_device {
2388 + struct device dev;
2389 +
2390 + enum omap_display_type type;
2391 +
2392 + union {
2393 + struct {
2394 + u8 data_lines;
2395 + } dpi;
2396 +
2397 + struct {
2398 + u8 channel;
2399 + u8 data_lines;
2400 + } rfbi;
2401 +
2402 + struct {
2403 + u8 datapairs;
2404 + } sdi;
2405 +
2406 + struct {
2407 + u8 clk_lane;
2408 + u8 clk_pol;
2409 + u8 data1_lane;
2410 + u8 data1_pol;
2411 + u8 data2_lane;
2412 + u8 data2_pol;
2413 +
2414 + struct {
2415 + u16 regn;
2416 + u16 regm;
2417 + u16 regm3;
2418 + u16 regm4;
2419 +
2420 + u16 lp_clk_div;
2421 +
2422 + u16 lck_div;
2423 + u16 pck_div;
2424 + } div;
2425 +
2426 + bool ext_te;
2427 + u8 ext_te_gpio;
2428 + } dsi;
2429 +
2430 + struct {
2431 + enum omap_dss_venc_type type;
2432 + bool invert_polarity;
2433 + } venc;
2434 + } phy;
2435 +
2436 + struct {
2437 + struct omap_video_timings timings;
2438 +
2439 + int acbi; /* ac-bias pin transitions per interrupt */
2440 + /* Unit: line clocks */
2441 + int acb; /* ac-bias pin frequency */
2442 +
2443 + enum omap_panel_config config;
2444 +
2445 + u8 recommended_bpp;
2446 +
2447 + struct omap_dss_device *ctrl;
2448 + } panel;
2449 +
2450 + struct {
2451 + u8 pixel_size;
2452 + struct rfbi_timings rfbi_timings;
2453 + struct omap_dss_device *panel;
2454 + } ctrl;
2455 +
2456 + int reset_gpio;
2457 +
2458 + int max_backlight_level;
2459 +
2460 + const char *name;
2461 +
2462 + /* used to match device to driver */
2463 + const char *driver_name;
2464 +
2465 + void *data;
2466 +
2467 + struct omap_dss_driver *driver;
2468 +
2469 + /* helper variable for driver suspend/resume */
2470 + bool activate_after_resume;
2471 +
2472 + enum omap_display_caps caps;
2473 +
2474 + struct omap_overlay_manager *manager;
2475 +
2476 + enum omap_dss_display_state state;
2477 +
2478 + int (*enable)(struct omap_dss_device *dssdev);
2479 + void (*disable)(struct omap_dss_device *dssdev);
2480 +
2481 + int (*suspend)(struct omap_dss_device *dssdev);
2482 + int (*resume)(struct omap_dss_device *dssdev);
2483 +
2484 + void (*get_resolution)(struct omap_dss_device *dssdev,
2485 + u16 *xres, u16 *yres);
2486 + int (*get_recommended_bpp)(struct omap_dss_device *dssdev);
2487 +
2488 + int (*check_timings)(struct omap_dss_device *dssdev,
2489 + struct omap_video_timings *timings);
2490 + void (*set_timings)(struct omap_dss_device *dssdev,
2491 + struct omap_video_timings *timings);
2492 + void (*get_timings)(struct omap_dss_device *dssdev,
2493 + struct omap_video_timings *timings);
2494 + int (*update)(struct omap_dss_device *dssdev,
2495 + u16 x, u16 y, u16 w, u16 h);
2496 + int (*sync)(struct omap_dss_device *dssdev);
2497 + int (*wait_vsync)(struct omap_dss_device *dssdev);
2498 +
2499 + int (*set_update_mode)(struct omap_dss_device *dssdev,
2500 + enum omap_dss_update_mode);
2501 + enum omap_dss_update_mode (*get_update_mode)
2502 + (struct omap_dss_device *dssdev);
2503 +
2504 + int (*enable_te)(struct omap_dss_device *dssdev, bool enable);
2505 + int (*get_te)(struct omap_dss_device *dssdev);
2506 +
2507 + u8 (*get_rotate)(struct omap_dss_device *dssdev);
2508 + int (*set_rotate)(struct omap_dss_device *dssdev, u8 rotate);
2509 +
2510 + bool (*get_mirror)(struct omap_dss_device *dssdev);
2511 + int (*set_mirror)(struct omap_dss_device *dssdev, bool enable);
2512 +
2513 + int (*run_test)(struct omap_dss_device *dssdev, int test);
2514 + int (*memory_read)(struct omap_dss_device *dssdev,
2515 + void *buf, size_t size,
2516 + u16 x, u16 y, u16 w, u16 h);
2517 +
2518 + int (*set_wss)(struct omap_dss_device *dssdev, u32 wss);
2519 + u32 (*get_wss)(struct omap_dss_device *dssdev);
2520 +
2521 + /* platform specific */
2522 + int (*platform_enable)(struct omap_dss_device *dssdev);
2523 + void (*platform_disable)(struct omap_dss_device *dssdev);
2524 + int (*set_backlight)(struct omap_dss_device *dssdev, int level);
2525 + int (*get_backlight)(struct omap_dss_device *dssdev);
2526 +};
2527 +
2528 +struct omap_dss_driver {
2529 + struct device_driver driver;
2530 +
2531 + int (*probe)(struct omap_dss_device *);
2532 + void (*remove)(struct omap_dss_device *);
2533 +
2534 + int (*enable)(struct omap_dss_device *display);
2535 + void (*disable)(struct omap_dss_device *display);
2536 + int (*suspend)(struct omap_dss_device *display);
2537 + int (*resume)(struct omap_dss_device *display);
2538 + int (*run_test)(struct omap_dss_device *display, int test);
2539 +
2540 + void (*setup_update)(struct omap_dss_device *dssdev,
2541 + u16 x, u16 y, u16 w, u16 h);
2542 +
2543 + int (*enable_te)(struct omap_dss_device *dssdev, bool enable);
2544 + int (*wait_for_te)(struct omap_dss_device *dssdev);
2545 +
2546 + u8 (*get_rotate)(struct omap_dss_device *dssdev);
2547 + int (*set_rotate)(struct omap_dss_device *dssdev, u8 rotate);
2548 +
2549 + bool (*get_mirror)(struct omap_dss_device *dssdev);
2550 + int (*set_mirror)(struct omap_dss_device *dssdev, bool enable);
2551 +
2552 + int (*memory_read)(struct omap_dss_device *dssdev,
2553 + void *buf, size_t size,
2554 + u16 x, u16 y, u16 w, u16 h);
2555 +};
2556 +
2557 +int omap_dss_register_driver(struct omap_dss_driver *);
2558 +void omap_dss_unregister_driver(struct omap_dss_driver *);
2559 +
2560 +int omap_dss_register_device(struct omap_dss_device *);
2561 +void omap_dss_unregister_device(struct omap_dss_device *);
2562 +
2563 +void omap_dss_get_device(struct omap_dss_device *dssdev);
2564 +void omap_dss_put_device(struct omap_dss_device *dssdev);
2565 +#define for_each_dss_dev(d) while ((d = omap_dss_get_next_device(d)) != NULL)
2566 +struct omap_dss_device *omap_dss_get_next_device(struct omap_dss_device *from);
2567 +struct omap_dss_device *omap_dss_find_device(void *data,
2568 + int (*match)(struct omap_dss_device *dssdev, void *data));
2569 +
2570 +int omap_dss_start_device(struct omap_dss_device *dssdev);
2571 +void omap_dss_stop_device(struct omap_dss_device *dssdev);
2572 +
2573 +int omap_dss_get_num_overlay_managers(void);
2574 +struct omap_overlay_manager *omap_dss_get_overlay_manager(int num);
2575 +
2576 +int omap_dss_get_num_overlays(void);
2577 +struct omap_overlay *omap_dss_get_overlay(int num);
2578 +
2579 +typedef void (*omap_dispc_isr_t) (void *arg, u32 mask);
2580 +int omap_dispc_register_isr(omap_dispc_isr_t isr, void *arg, u32 mask);
2581 +int omap_dispc_unregister_isr(omap_dispc_isr_t isr, void *arg, u32 mask);
2582 +
2583 +int omap_dispc_wait_for_irq_timeout(u32 irqmask, unsigned long timeout);
2584 +int omap_dispc_wait_for_irq_interruptible_timeout(u32 irqmask,
2585 + unsigned long timeout);
2586 +
2587 +#define to_dss_driver(x) container_of((x), struct omap_dss_driver, driver)
2588 +#define to_dss_device(x) container_of((x), struct omap_dss_device, dev)
2589 +
2590 +#endif
2591 Index: linux-2.6.37-rc1/arch/arm/plat-omap/include/mach/dma.h
2592 ===================================================================
2593 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
2594 +++ linux-2.6.37-rc1/arch/arm/plat-omap/include/mach/dma.h 2010-11-05 17:36:26.173000001 +0100
2595 @@ -0,0 +1,640 @@
2596 +/*
2597 + * arch/arm/plat-omap/include/mach/dma.h
2598 + *
2599 + * Copyright (C) 2003 Nokia Corporation
2600 + * Author: Juha Yrjölä <juha.yrjola@nokia.com>
2601 + *
2602 + * This program is free software; you can redistribute it and/or modify
2603 + * it under the terms of the GNU General Public License as published by
2604 + * the Free Software Foundation; either version 2 of the License, or
2605 + * (at your option) any later version.
2606 + *
2607 + * This program is distributed in the hope that it will be useful,
2608 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
2609 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
2610 + * GNU General Public License for more details.
2611 + *
2612 + * You should have received a copy of the GNU General Public License
2613 + * along with this program; if not, write to the Free Software
2614 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
2615 + */
2616 +#ifndef __ASM_ARCH_DMA_H
2617 +#define __ASM_ARCH_DMA_H
2618 +
2619 +/* Hardware registers for omap1 */
2620 +#define OMAP1_DMA_BASE (0xfffed800)
2621 +
2622 +#define OMAP1_DMA_GCR 0x400
2623 +#define OMAP1_DMA_GSCR 0x404
2624 +#define OMAP1_DMA_GRST 0x408
2625 +#define OMAP1_DMA_HW_ID 0x442
2626 +#define OMAP1_DMA_PCH2_ID 0x444
2627 +#define OMAP1_DMA_PCH0_ID 0x446
2628 +#define OMAP1_DMA_PCH1_ID 0x448
2629 +#define OMAP1_DMA_PCHG_ID 0x44a
2630 +#define OMAP1_DMA_PCHD_ID 0x44c
2631 +#define OMAP1_DMA_CAPS_0_U 0x44e
2632 +#define OMAP1_DMA_CAPS_0_L 0x450
2633 +#define OMAP1_DMA_CAPS_1_U 0x452
2634 +#define OMAP1_DMA_CAPS_1_L 0x454
2635 +#define OMAP1_DMA_CAPS_2 0x456
2636 +#define OMAP1_DMA_CAPS_3 0x458
2637 +#define OMAP1_DMA_CAPS_4 0x45a
2638 +#define OMAP1_DMA_PCH2_SR 0x460
2639 +#define OMAP1_DMA_PCH0_SR 0x480
2640 +#define OMAP1_DMA_PCH1_SR 0x482
2641 +#define OMAP1_DMA_PCHD_SR 0x4c0
2642 +
2643 +/* Hardware registers for omap2 and omap3 */
2644 +#define OMAP24XX_DMA4_BASE (L4_24XX_BASE + 0x56000)
2645 +#define OMAP34XX_DMA4_BASE (L4_34XX_BASE + 0x56000)
2646 +#define OMAP44XX_DMA4_BASE (L4_44XX_BASE + 0x56000)
2647 +
2648 +#define OMAP_DMA4_REVISION 0x00
2649 +#define OMAP_DMA4_GCR 0x78
2650 +#define OMAP_DMA4_IRQSTATUS_L0 0x08
2651 +#define OMAP_DMA4_IRQSTATUS_L1 0x0c
2652 +#define OMAP_DMA4_IRQSTATUS_L2 0x10
2653 +#define OMAP_DMA4_IRQSTATUS_L3 0x14
2654 +#define OMAP_DMA4_IRQENABLE_L0 0x18
2655 +#define OMAP_DMA4_IRQENABLE_L1 0x1c
2656 +#define OMAP_DMA4_IRQENABLE_L2 0x20
2657 +#define OMAP_DMA4_IRQENABLE_L3 0x24
2658 +#define OMAP_DMA4_SYSSTATUS 0x28
2659 +#define OMAP_DMA4_OCP_SYSCONFIG 0x2c
2660 +#define OMAP_DMA4_CAPS_0 0x64
2661 +#define OMAP_DMA4_CAPS_2 0x6c
2662 +#define OMAP_DMA4_CAPS_3 0x70
2663 +#define OMAP_DMA4_CAPS_4 0x74
2664 +
2665 +#define OMAP1_LOGICAL_DMA_CH_COUNT 17
2666 +#define OMAP_DMA4_LOGICAL_DMA_CH_COUNT 32 /* REVISIT: Is this 32 + 2? */
2667 +
2668 +/* Common channel specific registers for omap1 */
2669 +#define OMAP1_DMA_CH_BASE(n) (0x40 * (n) + 0x00)
2670 +#define OMAP1_DMA_CSDP(n) (0x40 * (n) + 0x00)
2671 +#define OMAP1_DMA_CCR(n) (0x40 * (n) + 0x02)
2672 +#define OMAP1_DMA_CICR(n) (0x40 * (n) + 0x04)
2673 +#define OMAP1_DMA_CSR(n) (0x40 * (n) + 0x06)
2674 +#define OMAP1_DMA_CEN(n) (0x40 * (n) + 0x10)
2675 +#define OMAP1_DMA_CFN(n) (0x40 * (n) + 0x12)
2676 +#define OMAP1_DMA_CSFI(n) (0x40 * (n) + 0x14)
2677 +#define OMAP1_DMA_CSEI(n) (0x40 * (n) + 0x16)
2678 +#define OMAP1_DMA_CPC(n) (0x40 * (n) + 0x18) /* 15xx only */
2679 +#define OMAP1_DMA_CSAC(n) (0x40 * (n) + 0x18)
2680 +#define OMAP1_DMA_CDAC(n) (0x40 * (n) + 0x1a)
2681 +#define OMAP1_DMA_CDEI(n) (0x40 * (n) + 0x1c)
2682 +#define OMAP1_DMA_CDFI(n) (0x40 * (n) + 0x1e)
2683 +#define OMAP1_DMA_CLNK_CTRL(n) (0x40 * (n) + 0x28)
2684 +
2685 +/* Common channel specific registers for omap2 */
2686 +#define OMAP_DMA4_CH_BASE(n) (0x60 * (n) + 0x80)
2687 +#define OMAP_DMA4_CCR(n) (0x60 * (n) + 0x80)
2688 +#define OMAP_DMA4_CLNK_CTRL(n) (0x60 * (n) + 0x84)
2689 +#define OMAP_DMA4_CICR(n) (0x60 * (n) + 0x88)
2690 +#define OMAP_DMA4_CSR(n) (0x60 * (n) + 0x8c)
2691 +#define OMAP_DMA4_CSDP(n) (0x60 * (n) + 0x90)
2692 +#define OMAP_DMA4_CEN(n) (0x60 * (n) + 0x94)
2693 +#define OMAP_DMA4_CFN(n) (0x60 * (n) + 0x98)
2694 +#define OMAP_DMA4_CSEI(n) (0x60 * (n) + 0xa4)
2695 +#define OMAP_DMA4_CSFI(n) (0x60 * (n) + 0xa8)
2696 +#define OMAP_DMA4_CDEI(n) (0x60 * (n) + 0xac)
2697 +#define OMAP_DMA4_CDFI(n) (0x60 * (n) + 0xb0)
2698 +#define OMAP_DMA4_CSAC(n) (0x60 * (n) + 0xb4)
2699 +#define OMAP_DMA4_CDAC(n) (0x60 * (n) + 0xb8)
2700 +
2701 +/* Channel specific registers only on omap1 */
2702 +#define OMAP1_DMA_CSSA_L(n) (0x40 * (n) + 0x08)
2703 +#define OMAP1_DMA_CSSA_U(n) (0x40 * (n) + 0x0a)
2704 +#define OMAP1_DMA_CDSA_L(n) (0x40 * (n) + 0x0c)
2705 +#define OMAP1_DMA_CDSA_U(n) (0x40 * (n) + 0x0e)
2706 +#define OMAP1_DMA_COLOR_L(n) (0x40 * (n) + 0x20)
2707 +#define OMAP1_DMA_COLOR_U(n) (0x40 * (n) + 0x22)
2708 +#define OMAP1_DMA_CCR2(n) (0x40 * (n) + 0x24)
2709 +#define OMAP1_DMA_LCH_CTRL(n) (0x40 * (n) + 0x2a) /* not on 15xx */
2710 +#define OMAP1_DMA_CCEN(n) 0
2711 +#define OMAP1_DMA_CCFN(n) 0
2712 +
2713 +/* Channel specific registers only on omap2 */
2714 +#define OMAP_DMA4_CSSA(n) (0x60 * (n) + 0x9c)
2715 +#define OMAP_DMA4_CDSA(n) (0x60 * (n) + 0xa0)
2716 +#define OMAP_DMA4_CCEN(n) (0x60 * (n) + 0xbc)
2717 +#define OMAP_DMA4_CCFN(n) (0x60 * (n) + 0xc0)
2718 +#define OMAP_DMA4_COLOR(n) (0x60 * (n) + 0xc4)
2719 +
2720 +/* Additional registers available on OMAP4 */
2721 +#define OMAP_DMA4_CDP(n) (0x60 * (n) + 0xd0)
2722 +#define OMAP_DMA4_CNDP(n) (0x60 * (n) + 0xd4)
2723 +#define OMAP_DMA4_CCDN(n) (0x60 * (n) + 0xd8)
2724 +
2725 +/* Dummy defines to keep multi-omap compiles happy */
2726 +#define OMAP1_DMA_REVISION 0
2727 +#define OMAP1_DMA_IRQSTATUS_L0 0
2728 +#define OMAP1_DMA_IRQENABLE_L0 0
2729 +#define OMAP1_DMA_OCP_SYSCONFIG 0
2730 +#define OMAP_DMA4_HW_ID 0
2731 +#define OMAP_DMA4_CAPS_0_L 0
2732 +#define OMAP_DMA4_CAPS_0_U 0
2733 +#define OMAP_DMA4_CAPS_1_L 0
2734 +#define OMAP_DMA4_CAPS_1_U 0
2735 +#define OMAP_DMA4_GSCR 0
2736 +#define OMAP_DMA4_CPC(n) 0
2737 +
2738 +#define OMAP_DMA4_LCH_CTRL(n) 0
2739 +#define OMAP_DMA4_COLOR_L(n) 0
2740 +#define OMAP_DMA4_COLOR_U(n) 0
2741 +#define OMAP_DMA4_CCR2(n) 0
2742 +#define OMAP1_DMA_CSSA(n) 0
2743 +#define OMAP1_DMA_CDSA(n) 0
2744 +#define OMAP_DMA4_CSSA_L(n) 0
2745 +#define OMAP_DMA4_CSSA_U(n) 0
2746 +#define OMAP_DMA4_CDSA_L(n) 0
2747 +#define OMAP_DMA4_CDSA_U(n) 0
2748 +#define OMAP1_DMA_COLOR(n) 0
2749 +
2750 +/*----------------------------------------------------------------------------*/
2751 +
2752 +/* DMA channels for omap1 */
2753 +#define OMAP_DMA_NO_DEVICE 0
2754 +#define OMAP_DMA_MCSI1_TX 1
2755 +#define OMAP_DMA_MCSI1_RX 2
2756 +#define OMAP_DMA_I2C_RX 3
2757 +#define OMAP_DMA_I2C_TX 4
2758 +#define OMAP_DMA_EXT_NDMA_REQ 5
2759 +#define OMAP_DMA_EXT_NDMA_REQ2 6
2760 +#define OMAP_DMA_UWIRE_TX 7
2761 +#define OMAP_DMA_MCBSP1_TX 8
2762 +#define OMAP_DMA_MCBSP1_RX 9
2763 +#define OMAP_DMA_MCBSP3_TX 10
2764 +#define OMAP_DMA_MCBSP3_RX 11
2765 +#define OMAP_DMA_UART1_TX 12
2766 +#define OMAP_DMA_UART1_RX 13
2767 +#define OMAP_DMA_UART2_TX 14
2768 +#define OMAP_DMA_UART2_RX 15
2769 +#define OMAP_DMA_MCBSP2_TX 16
2770 +#define OMAP_DMA_MCBSP2_RX 17
2771 +#define OMAP_DMA_UART3_TX 18
2772 +#define OMAP_DMA_UART3_RX 19
2773 +#define OMAP_DMA_CAMERA_IF_RX 20
2774 +#define OMAP_DMA_MMC_TX 21
2775 +#define OMAP_DMA_MMC_RX 22
2776 +#define OMAP_DMA_NAND 23
2777 +#define OMAP_DMA_IRQ_LCD_LINE 24
2778 +#define OMAP_DMA_MEMORY_STICK 25
2779 +#define OMAP_DMA_USB_W2FC_RX0 26
2780 +#define OMAP_DMA_USB_W2FC_RX1 27
2781 +#define OMAP_DMA_USB_W2FC_RX2 28
2782 +#define OMAP_DMA_USB_W2FC_TX0 29
2783 +#define OMAP_DMA_USB_W2FC_TX1 30
2784 +#define OMAP_DMA_USB_W2FC_TX2 31
2785 +
2786 +/* These are only for 1610 */
2787 +#define OMAP_DMA_CRYPTO_DES_IN 32
2788 +#define OMAP_DMA_SPI_TX 33
2789 +#define OMAP_DMA_SPI_RX 34
2790 +#define OMAP_DMA_CRYPTO_HASH 35
2791 +#define OMAP_DMA_CCP_ATTN 36
2792 +#define OMAP_DMA_CCP_FIFO_NOT_EMPTY 37
2793 +#define OMAP_DMA_CMT_APE_TX_CHAN_0 38
2794 +#define OMAP_DMA_CMT_APE_RV_CHAN_0 39
2795 +#define OMAP_DMA_CMT_APE_TX_CHAN_1 40
2796 +#define OMAP_DMA_CMT_APE_RV_CHAN_1 41
2797 +#define OMAP_DMA_CMT_APE_TX_CHAN_2 42
2798 +#define OMAP_DMA_CMT_APE_RV_CHAN_2 43
2799 +#define OMAP_DMA_CMT_APE_TX_CHAN_3 44
2800 +#define OMAP_DMA_CMT_APE_RV_CHAN_3 45
2801 +#define OMAP_DMA_CMT_APE_TX_CHAN_4 46
2802 +#define OMAP_DMA_CMT_APE_RV_CHAN_4 47
2803 +#define OMAP_DMA_CMT_APE_TX_CHAN_5 48
2804 +#define OMAP_DMA_CMT_APE_RV_CHAN_5 49
2805 +#define OMAP_DMA_CMT_APE_TX_CHAN_6 50
2806 +#define OMAP_DMA_CMT_APE_RV_CHAN_6 51
2807 +#define OMAP_DMA_CMT_APE_TX_CHAN_7 52
2808 +#define OMAP_DMA_CMT_APE_RV_CHAN_7 53
2809 +#define OMAP_DMA_MMC2_TX 54
2810 +#define OMAP_DMA_MMC2_RX 55
2811 +#define OMAP_DMA_CRYPTO_DES_OUT 56
2812 +
2813 +/* DMA channels for 24xx */
2814 +#define OMAP24XX_DMA_NO_DEVICE 0
2815 +#define OMAP24XX_DMA_XTI_DMA 1 /* S_DMA_0 */
2816 +#define OMAP24XX_DMA_EXT_DMAREQ0 2 /* S_DMA_1 */
2817 +#define OMAP24XX_DMA_EXT_DMAREQ1 3 /* S_DMA_2 */
2818 +#define OMAP24XX_DMA_GPMC 4 /* S_DMA_3 */
2819 +#define OMAP24XX_DMA_GFX 5 /* S_DMA_4 */
2820 +#define OMAP24XX_DMA_DSS 6 /* S_DMA_5 */
2821 +#define OMAP242X_DMA_VLYNQ_TX 7 /* S_DMA_6 */
2822 +#define OMAP24XX_DMA_EXT_DMAREQ2 7 /* S_DMA_6 */
2823 +#define OMAP24XX_DMA_CWT 8 /* S_DMA_7 */
2824 +#define OMAP24XX_DMA_AES_TX 9 /* S_DMA_8 */
2825 +#define OMAP24XX_DMA_AES_RX 10 /* S_DMA_9 */
2826 +#define OMAP24XX_DMA_DES_TX 11 /* S_DMA_10 */
2827 +#define OMAP24XX_DMA_DES_RX 12 /* S_DMA_11 */
2828 +#define OMAP24XX_DMA_SHA1MD5_RX 13 /* S_DMA_12 */
2829 +#define OMAP34XX_DMA_SHA2MD5_RX 13 /* S_DMA_12 */
2830 +#define OMAP242X_DMA_EXT_DMAREQ2 14 /* S_DMA_13 */
2831 +#define OMAP242X_DMA_EXT_DMAREQ3 15 /* S_DMA_14 */
2832 +#define OMAP242X_DMA_EXT_DMAREQ4 16 /* S_DMA_15 */
2833 +#define OMAP242X_DMA_EAC_AC_RD 17 /* S_DMA_16 */
2834 +#define OMAP242X_DMA_EAC_AC_WR 18 /* S_DMA_17 */
2835 +#define OMAP242X_DMA_EAC_MD_UL_RD 19 /* S_DMA_18 */
2836 +#define OMAP242X_DMA_EAC_MD_UL_WR 20 /* S_DMA_19 */
2837 +#define OMAP242X_DMA_EAC_MD_DL_RD 21 /* S_DMA_20 */
2838 +#define OMAP242X_DMA_EAC_MD_DL_WR 22 /* S_DMA_21 */
2839 +#define OMAP242X_DMA_EAC_BT_UL_RD 23 /* S_DMA_22 */
2840 +#define OMAP242X_DMA_EAC_BT_UL_WR 24 /* S_DMA_23 */
2841 +#define OMAP242X_DMA_EAC_BT_DL_RD 25 /* S_DMA_24 */
2842 +#define OMAP242X_DMA_EAC_BT_DL_WR 26 /* S_DMA_25 */
2843 +#define OMAP243X_DMA_EXT_DMAREQ3 14 /* S_DMA_13 */
2844 +#define OMAP24XX_DMA_SPI3_TX0 15 /* S_DMA_14 */
2845 +#define OMAP24XX_DMA_SPI3_RX0 16 /* S_DMA_15 */
2846 +#define OMAP24XX_DMA_MCBSP3_TX 17 /* S_DMA_16 */
2847 +#define OMAP24XX_DMA_MCBSP3_RX 18 /* S_DMA_17 */
2848 +#define OMAP24XX_DMA_MCBSP4_TX 19 /* S_DMA_18 */
2849 +#define OMAP24XX_DMA_MCBSP4_RX 20 /* S_DMA_19 */
2850 +#define OMAP24XX_DMA_MCBSP5_TX 21 /* S_DMA_20 */
2851 +#define OMAP24XX_DMA_MCBSP5_RX 22 /* S_DMA_21 */
2852 +#define OMAP24XX_DMA_SPI3_TX1 23 /* S_DMA_22 */
2853 +#define OMAP24XX_DMA_SPI3_RX1 24 /* S_DMA_23 */
2854 +#define OMAP243X_DMA_EXT_DMAREQ4 25 /* S_DMA_24 */
2855 +#define OMAP243X_DMA_EXT_DMAREQ5 26 /* S_DMA_25 */
2856 +#define OMAP34XX_DMA_I2C3_TX 25 /* S_DMA_24 */
2857 +#define OMAP34XX_DMA_I2C3_RX 26 /* S_DMA_25 */
2858 +#define OMAP24XX_DMA_I2C1_TX 27 /* S_DMA_26 */
2859 +#define OMAP24XX_DMA_I2C1_RX 28 /* S_DMA_27 */
2860 +#define OMAP24XX_DMA_I2C2_TX 29 /* S_DMA_28 */
2861 +#define OMAP24XX_DMA_I2C2_RX 30 /* S_DMA_29 */
2862 +#define OMAP24XX_DMA_MCBSP1_TX 31 /* S_DMA_30 */
2863 +#define OMAP24XX_DMA_MCBSP1_RX 32 /* S_DMA_31 */
2864 +#define OMAP24XX_DMA_MCBSP2_TX 33 /* S_DMA_32 */
2865 +#define OMAP24XX_DMA_MCBSP2_RX 34 /* S_DMA_33 */
2866 +#define OMAP24XX_DMA_SPI1_TX0 35 /* S_DMA_34 */
2867 +#define OMAP24XX_DMA_SPI1_RX0 36 /* S_DMA_35 */
2868 +#define OMAP24XX_DMA_SPI1_TX1 37 /* S_DMA_36 */
2869 +#define OMAP24XX_DMA_SPI1_RX1 38 /* S_DMA_37 */
2870 +#define OMAP24XX_DMA_SPI1_TX2 39 /* S_DMA_38 */
2871 +#define OMAP24XX_DMA_SPI1_RX2 40 /* S_DMA_39 */
2872 +#define OMAP24XX_DMA_SPI1_TX3 41 /* S_DMA_40 */
2873 +#define OMAP24XX_DMA_SPI1_RX3 42 /* S_DMA_41 */
2874 +#define OMAP24XX_DMA_SPI2_TX0 43 /* S_DMA_42 */
2875 +#define OMAP24XX_DMA_SPI2_RX0 44 /* S_DMA_43 */
2876 +#define OMAP24XX_DMA_SPI2_TX1 45 /* S_DMA_44 */
2877 +#define OMAP24XX_DMA_SPI2_RX1 46 /* S_DMA_45 */
2878 +#define OMAP24XX_DMA_MMC2_TX 47 /* S_DMA_46 */
2879 +#define OMAP24XX_DMA_MMC2_RX 48 /* S_DMA_47 */
2880 +#define OMAP24XX_DMA_UART1_TX 49 /* S_DMA_48 */
2881 +#define OMAP24XX_DMA_UART1_RX 50 /* S_DMA_49 */
2882 +#define OMAP24XX_DMA_UART2_TX 51 /* S_DMA_50 */
2883 +#define OMAP24XX_DMA_UART2_RX 52 /* S_DMA_51 */
2884 +#define OMAP24XX_DMA_UART3_TX 53 /* S_DMA_52 */
2885 +#define OMAP24XX_DMA_UART3_RX 54 /* S_DMA_53 */
2886 +#define OMAP24XX_DMA_USB_W2FC_TX0 55 /* S_DMA_54 */
2887 +#define OMAP24XX_DMA_USB_W2FC_RX0 56 /* S_DMA_55 */
2888 +#define OMAP24XX_DMA_USB_W2FC_TX1 57 /* S_DMA_56 */
2889 +#define OMAP24XX_DMA_USB_W2FC_RX1 58 /* S_DMA_57 */
2890 +#define OMAP24XX_DMA_USB_W2FC_TX2 59 /* S_DMA_58 */
2891 +#define OMAP24XX_DMA_USB_W2FC_RX2 60 /* S_DMA_59 */
2892 +#define OMAP24XX_DMA_MMC1_TX 61 /* S_DMA_60 */
2893 +#define OMAP24XX_DMA_MMC1_RX 62 /* S_DMA_61 */
2894 +#define OMAP24XX_DMA_MS 63 /* S_DMA_62 */
2895 +#define OMAP242X_DMA_EXT_DMAREQ5 64 /* S_DMA_63 */
2896 +#define OMAP243X_DMA_EXT_DMAREQ6 64 /* S_DMA_63 */
2897 +#define OMAP34XX_DMA_EXT_DMAREQ3 64 /* S_DMA_63 */
2898 +#define OMAP34XX_DMA_AES2_TX 65 /* S_DMA_64 */
2899 +#define OMAP34XX_DMA_AES2_RX 66 /* S_DMA_65 */
2900 +#define OMAP34XX_DMA_DES2_TX 67 /* S_DMA_66 */
2901 +#define OMAP34XX_DMA_DES2_RX 68 /* S_DMA_67 */
2902 +#define OMAP34XX_DMA_SHA1MD5_RX 69 /* S_DMA_68 */
2903 +#define OMAP34XX_DMA_SPI4_TX0 70 /* S_DMA_69 */
2904 +#define OMAP34XX_DMA_SPI4_RX0 71 /* S_DMA_70 */
2905 +#define OMAP34XX_DSS_DMA0 72 /* S_DMA_71 */
2906 +#define OMAP34XX_DSS_DMA1 73 /* S_DMA_72 */
2907 +#define OMAP34XX_DSS_DMA2 74 /* S_DMA_73 */
2908 +#define OMAP34XX_DSS_DMA3 75 /* S_DMA_74 */
2909 +#define OMAP34XX_DMA_MMC3_TX 77 /* S_DMA_76 */
2910 +#define OMAP34XX_DMA_MMC3_RX 78 /* S_DMA_77 */
2911 +#define OMAP34XX_DMA_USIM_TX 79 /* S_DMA_78 */
2912 +#define OMAP34XX_DMA_USIM_RX 80 /* S_DMA_79 */
2913 +
2914 +/* DMA request lines for 44xx */
2915 +#define OMAP44XX_DMA_DSS_DISPC_REQ 6 /* S_DMA_5 */
2916 +#define OMAP44XX_DMA_SYS_REQ2 7 /* S_DMA_6 */
2917 +#define OMAP44XX_DMA_ISS_REQ1 9 /* S_DMA_8 */
2918 +#define OMAP44XX_DMA_ISS_REQ2 10 /* S_DMA_9 */
2919 +#define OMAP44XX_DMA_ISS_REQ3 12 /* S_DMA_11 */
2920 +#define OMAP44XX_DMA_ISS_REQ4 13 /* S_DMA_12 */
2921 +#define OMAP44XX_DMA_DSS_RFBI_REQ 14 /* S_DMA_13 */
2922 +#define OMAP44XX_DMA_SPI3_TX0 15 /* S_DMA_14 */
2923 +#define OMAP44XX_DMA_SPI3_RX0 16 /* S_DMA_15 */
2924 +#define OMAP44XX_DMA_MCBSP2_TX 17 /* S_DMA_16 */
2925 +#define OMAP44XX_DMA_MCBSP2_RX 18 /* S_DMA_17 */
2926 +#define OMAP44XX_DMA_MCBSP3_TX 19 /* S_DMA_18 */
2927 +#define OMAP44XX_DMA_MCBSP3_RX 20 /* S_DMA_19 */
2928 +#define OMAP44XX_DMA_SPI3_TX1 23 /* S_DMA_22 */
2929 +#define OMAP44XX_DMA_SPI3_RX1 24 /* S_DMA_23 */
2930 +#define OMAP44XX_DMA_I2C3_TX 25 /* S_DMA_24 */
2931 +#define OMAP44XX_DMA_I2C3_RX 26 /* S_DMA_25 */
2932 +#define OMAP44XX_DMA_I2C1_TX 27 /* S_DMA_26 */
2933 +#define OMAP44XX_DMA_I2C1_RX 28 /* S_DMA_27 */
2934 +#define OMAP44XX_DMA_I2C2_TX 29 /* S_DMA_28 */
2935 +#define OMAP44XX_DMA_I2C2_RX 30 /* S_DMA_29 */
2936 +#define OMAP44XX_DMA_MCBSP4_TX 31 /* S_DMA_30 */
2937 +#define OMAP44XX_DMA_MCBSP4_RX 32 /* S_DMA_31 */
2938 +#define OMAP44XX_DMA_MCBSP1_TX 33 /* S_DMA_32 */
2939 +#define OMAP44XX_DMA_MCBSP1_RX 34 /* S_DMA_33 */
2940 +#define OMAP44XX_DMA_SPI1_TX0 35 /* S_DMA_34 */
2941 +#define OMAP44XX_DMA_SPI1_RX0 36 /* S_DMA_35 */
2942 +#define OMAP44XX_DMA_SPI1_TX1 37 /* S_DMA_36 */
2943 +#define OMAP44XX_DMA_SPI1_RX1 38 /* S_DMA_37 */
2944 +#define OMAP44XX_DMA_SPI1_TX2 39 /* S_DMA_38 */
2945 +#define OMAP44XX_DMA_SPI1_RX2 40 /* S_DMA_39 */
2946 +#define OMAP44XX_DMA_SPI1_TX3 41 /* S_DMA_40 */
2947 +#define OMAP44XX_DMA_SPI1_RX3 42 /* S_DMA_41 */
2948 +#define OMAP44XX_DMA_SPI2_TX0 43 /* S_DMA_42 */
2949 +#define OMAP44XX_DMA_SPI2_RX0 44 /* S_DMA_43 */
2950 +#define OMAP44XX_DMA_SPI2_TX1 45 /* S_DMA_44 */
2951 +#define OMAP44XX_DMA_SPI2_RX1 46 /* S_DMA_45 */
2952 +#define OMAP44XX_DMA_MMC2_TX 47 /* S_DMA_46 */
2953 +#define OMAP44XX_DMA_MMC2_RX 48 /* S_DMA_47 */
2954 +#define OMAP44XX_DMA_UART1_TX 49 /* S_DMA_48 */
2955 +#define OMAP44XX_DMA_UART1_RX 50 /* S_DMA_49 */
2956 +#define OMAP44XX_DMA_UART2_TX 51 /* S_DMA_50 */
2957 +#define OMAP44XX_DMA_UART2_RX 52 /* S_DMA_51 */
2958 +#define OMAP44XX_DMA_UART3_TX 53 /* S_DMA_52 */
2959 +#define OMAP44XX_DMA_UART3_RX 54 /* S_DMA_53 */
2960 +#define OMAP44XX_DMA_UART4_TX 55 /* S_DMA_54 */
2961 +#define OMAP44XX_DMA_UART4_RX 56 /* S_DMA_55 */
2962 +#define OMAP44XX_DMA_MMC4_TX 57 /* S_DMA_56 */
2963 +#define OMAP44XX_DMA_MMC4_RX 58 /* S_DMA_57 */
2964 +#define OMAP44XX_DMA_MMC5_TX 59 /* S_DMA_58 */
2965 +#define OMAP44XX_DMA_MMC5_RX 60 /* S_DMA_59 */
2966 +#define OMAP44XX_DMA_MMC1_TX 61 /* S_DMA_60 */
2967 +#define OMAP44XX_DMA_MMC1_RX 62 /* S_DMA_61 */
2968 +#define OMAP44XX_DMA_SYS_REQ3 64 /* S_DMA_63 */
2969 +#define OMAP44XX_DMA_MCPDM_UP 65 /* S_DMA_64 */
2970 +#define OMAP44XX_DMA_MCPDM_DL 66 /* S_DMA_65 */
2971 +#define OMAP44XX_DMA_SPI4_TX0 70 /* S_DMA_69 */
2972 +#define OMAP44XX_DMA_SPI4_RX0 71 /* S_DMA_70 */
2973 +#define OMAP44XX_DMA_DSS_DSI1_REQ0 72 /* S_DMA_71 */
2974 +#define OMAP44XX_DMA_DSS_DSI1_REQ1 73 /* S_DMA_72 */
2975 +#define OMAP44XX_DMA_DSS_DSI1_REQ2 74 /* S_DMA_73 */
2976 +#define OMAP44XX_DMA_DSS_DSI1_REQ3 75 /* S_DMA_74 */
2977 +#define OMAP44XX_DMA_DSS_HDMI_REQ 76 /* S_DMA_75 */
2978 +#define OMAP44XX_DMA_MMC3_TX 77 /* S_DMA_76 */
2979 +#define OMAP44XX_DMA_MMC3_RX 78 /* S_DMA_77 */
2980 +#define OMAP44XX_DMA_USIM_TX 79 /* S_DMA_78 */
2981 +#define OMAP44XX_DMA_USIM_RX 80 /* S_DMA_79 */
2982 +#define OMAP44XX_DMA_DSS_DSI2_REQ0 81 /* S_DMA_80 */
2983 +#define OMAP44XX_DMA_DSS_DSI2_REQ1 82 /* S_DMA_81 */
2984 +#define OMAP44XX_DMA_DSS_DSI2_REQ2 83 /* S_DMA_82 */
2985 +#define OMAP44XX_DMA_DSS_DSI2_REQ3 84 /* S_DMA_83 */
2986 +#define OMAP44XX_DMA_ABE_REQ0 101 /* S_DMA_100 */
2987 +#define OMAP44XX_DMA_ABE_REQ1 102 /* S_DMA_101 */
2988 +#define OMAP44XX_DMA_ABE_REQ2 103 /* S_DMA_102 */
2989 +#define OMAP44XX_DMA_ABE_REQ3 104 /* S_DMA_103 */
2990 +#define OMAP44XX_DMA_ABE_REQ4 105 /* S_DMA_104 */
2991 +#define OMAP44XX_DMA_ABE_REQ5 106 /* S_DMA_105 */
2992 +#define OMAP44XX_DMA_ABE_REQ6 107 /* S_DMA_106 */
2993 +#define OMAP44XX_DMA_ABE_REQ7 108 /* S_DMA_107 */
2994 +#define OMAP44XX_DMA_I2C4_TX 124 /* S_DMA_123 */
2995 +#define OMAP44XX_DMA_I2C4_RX 125 /* S_DMA_124 */
2996 +
2997 +/*----------------------------------------------------------------------------*/
2998 +
2999 +#define OMAP1_DMA_TOUT_IRQ (1 << 0)
3000 +#define OMAP_DMA_DROP_IRQ (1 << 1)
3001 +#define OMAP_DMA_HALF_IRQ (1 << 2)
3002 +#define OMAP_DMA_FRAME_IRQ (1 << 3)
3003 +#define OMAP_DMA_LAST_IRQ (1 << 4)
3004 +#define OMAP_DMA_BLOCK_IRQ (1 << 5)
3005 +#define OMAP1_DMA_SYNC_IRQ (1 << 6)
3006 +#define OMAP2_DMA_PKT_IRQ (1 << 7)
3007 +#define OMAP2_DMA_TRANS_ERR_IRQ (1 << 8)
3008 +#define OMAP2_DMA_SECURE_ERR_IRQ (1 << 9)
3009 +#define OMAP2_DMA_SUPERVISOR_ERR_IRQ (1 << 10)
3010 +#define OMAP2_DMA_MISALIGNED_ERR_IRQ (1 << 11)
3011 +
3012 +#define OMAP_DMA_CCR_EN (1 << 7)
3013 +
3014 +#define OMAP_DMA_DATA_TYPE_S8 0x00
3015 +#define OMAP_DMA_DATA_TYPE_S16 0x01
3016 +#define OMAP_DMA_DATA_TYPE_S32 0x02
3017 +
3018 +#define OMAP_DMA_SYNC_ELEMENT 0x00
3019 +#define OMAP_DMA_SYNC_FRAME 0x01
3020 +#define OMAP_DMA_SYNC_BLOCK 0x02
3021 +#define OMAP_DMA_SYNC_PACKET 0x03
3022 +
3023 +#define OMAP_DMA_SRC_SYNC 0x01
3024 +#define OMAP_DMA_DST_SYNC 0x00
3025 +
3026 +#define OMAP_DMA_PORT_EMIFF 0x00
3027 +#define OMAP_DMA_PORT_EMIFS 0x01
3028 +#define OMAP_DMA_PORT_OCP_T1 0x02
3029 +#define OMAP_DMA_PORT_TIPB 0x03
3030 +#define OMAP_DMA_PORT_OCP_T2 0x04
3031 +#define OMAP_DMA_PORT_MPUI 0x05
3032 +
3033 +#define OMAP_DMA_AMODE_CONSTANT 0x00
3034 +#define OMAP_DMA_AMODE_POST_INC 0x01
3035 +#define OMAP_DMA_AMODE_SINGLE_IDX 0x02
3036 +#define OMAP_DMA_AMODE_DOUBLE_IDX 0x03
3037 +
3038 +#define DMA_DEFAULT_FIFO_DEPTH 0x10
3039 +#define DMA_DEFAULT_ARB_RATE 0x01
3040 +/* Pass THREAD_RESERVE ORed with THREAD_FIFO for tparams */
3041 +#define DMA_THREAD_RESERVE_NORM (0x00 << 12) /* Def */
3042 +#define DMA_THREAD_RESERVE_ONET (0x01 << 12)
3043 +#define DMA_THREAD_RESERVE_TWOT (0x02 << 12)
3044 +#define DMA_THREAD_RESERVE_THREET (0x03 << 12)
3045 +#define DMA_THREAD_FIFO_NONE (0x00 << 14) /* Def */
3046 +#define DMA_THREAD_FIFO_75 (0x01 << 14)
3047 +#define DMA_THREAD_FIFO_25 (0x02 << 14)
3048 +#define DMA_THREAD_FIFO_50 (0x03 << 14)
3049 +
3050 +/* DMA4_OCP_SYSCONFIG bits */
3051 +#define DMA_SYSCONFIG_MIDLEMODE_MASK (3 << 12)
3052 +#define DMA_SYSCONFIG_CLOCKACTIVITY_MASK (3 << 8)
3053 +#define DMA_SYSCONFIG_EMUFREE (1 << 5)
3054 +#define DMA_SYSCONFIG_SIDLEMODE_MASK (3 << 3)
3055 +#define DMA_SYSCONFIG_SOFTRESET (1 << 2)
3056 +#define DMA_SYSCONFIG_AUTOIDLE (1 << 0)
3057 +
3058 +#define DMA_SYSCONFIG_MIDLEMODE(n) ((n) << 12)
3059 +#define DMA_SYSCONFIG_SIDLEMODE(n) ((n) << 3)
3060 +
3061 +#define DMA_IDLEMODE_SMARTIDLE 0x2
3062 +#define DMA_IDLEMODE_NO_IDLE 0x1
3063 +#define DMA_IDLEMODE_FORCE_IDLE 0x0
3064 +
3065 +/* Chaining modes*/
3066 +#ifndef CONFIG_ARCH_OMAP1
3067 +#define OMAP_DMA_STATIC_CHAIN 0x1
3068 +#define OMAP_DMA_DYNAMIC_CHAIN 0x2
3069 +#define OMAP_DMA_CHAIN_ACTIVE 0x1
3070 +#define OMAP_DMA_CHAIN_INACTIVE 0x0
3071 +#endif
3072 +
3073 +#define DMA_CH_PRIO_HIGH 0x1
3074 +#define DMA_CH_PRIO_LOW 0x0 /* Def */
3075 +
3076 +enum omap_dma_burst_mode {
3077 + OMAP_DMA_DATA_BURST_DIS = 0,
3078 + OMAP_DMA_DATA_BURST_4,
3079 + OMAP_DMA_DATA_BURST_8,
3080 + OMAP_DMA_DATA_BURST_16,
3081 +};
3082 +
3083 +enum end_type {
3084 + OMAP_DMA_LITTLE_ENDIAN = 0,
3085 + OMAP_DMA_BIG_ENDIAN
3086 +};
3087 +
3088 +enum omap_dma_color_mode {
3089 + OMAP_DMA_COLOR_DIS = 0,
3090 + OMAP_DMA_CONSTANT_FILL,
3091 + OMAP_DMA_TRANSPARENT_COPY
3092 +};
3093 +
3094 +enum omap_dma_write_mode {
3095 + OMAP_DMA_WRITE_NON_POSTED = 0,
3096 + OMAP_DMA_WRITE_POSTED,
3097 + OMAP_DMA_WRITE_LAST_NON_POSTED
3098 +};
3099 +
3100 +enum omap_dma_channel_mode {
3101 + OMAP_DMA_LCH_2D = 0,
3102 + OMAP_DMA_LCH_G,
3103 + OMAP_DMA_LCH_P,
3104 + OMAP_DMA_LCH_PD
3105 +};
3106 +
3107 +struct omap_dma_channel_params {
3108 + int data_type; /* data type 8,16,32 */
3109 + int elem_count; /* number of elements in a frame */
3110 + int frame_count; /* number of frames in a element */
3111 +
3112 + int src_port; /* Only on OMAP1 REVISIT: Is this needed? */
3113 + int src_amode; /* constant, post increment, indexed,
3114 + double indexed */
3115 + unsigned long src_start; /* source address : physical */
3116 + int src_ei; /* source element index */
3117 + int src_fi; /* source frame index */
3118 +
3119 + int dst_port; /* Only on OMAP1 REVISIT: Is this needed? */
3120 + int dst_amode; /* constant, post increment, indexed,
3121 + double indexed */
3122 + unsigned long dst_start; /* source address : physical */
3123 + int dst_ei; /* source element index */
3124 + int dst_fi; /* source frame index */
3125 +
3126 + int trigger; /* trigger attached if the channel is
3127 + synchronized */
3128 + int sync_mode; /* sycn on element, frame , block or packet */
3129 + int src_or_dst_synch; /* source synch(1) or destination synch(0) */
3130 +
3131 + int ie; /* interrupt enabled */
3132 +
3133 + unsigned char read_prio;/* read priority */
3134 + unsigned char write_prio;/* write priority */
3135 +
3136 +#ifndef CONFIG_ARCH_OMAP1
3137 + enum omap_dma_burst_mode burst_mode; /* Burst mode 4/8/16 words */
3138 +#endif
3139 +};
3140 +
3141 +
3142 +extern void omap_set_dma_priority(int lch, int dst_port, int priority);
3143 +extern int omap_request_dma(int dev_id, const char *dev_name,
3144 + void (*callback)(int lch, u16 ch_status, void *data),
3145 + void *data, int *dma_ch);
3146 +extern void omap_enable_dma_irq(int ch, u16 irq_bits);
3147 +extern void omap_disable_dma_irq(int ch, u16 irq_bits);
3148 +extern void omap_free_dma(int ch);
3149 +extern void omap_start_dma(int lch);
3150 +extern void omap_stop_dma(int lch);
3151 +extern void omap_set_dma_transfer_params(int lch, int data_type,
3152 + int elem_count, int frame_count,
3153 + int sync_mode,
3154 + int dma_trigger, int src_or_dst_synch);
3155 +extern void omap_set_dma_color_mode(int lch, enum omap_dma_color_mode mode,
3156 + u32 color);
3157 +extern void omap_set_dma_write_mode(int lch, enum omap_dma_write_mode mode);
3158 +extern void omap_set_dma_channel_mode(int lch, enum omap_dma_channel_mode mode);
3159 +
3160 +extern void omap_set_dma_src_params(int lch, int src_port, int src_amode,
3161 + unsigned long src_start,
3162 + int src_ei, int src_fi);
3163 +extern void omap_set_dma_src_index(int lch, int eidx, int fidx);
3164 +extern void omap_set_dma_src_data_pack(int lch, int enable);
3165 +extern void omap_set_dma_src_burst_mode(int lch,
3166 + enum omap_dma_burst_mode burst_mode);
3167 +
3168 +extern void omap_set_dma_dest_params(int lch, int dest_port, int dest_amode,
3169 + unsigned long dest_start,
3170 + int dst_ei, int dst_fi);
3171 +extern void omap_set_dma_dest_index(int lch, int eidx, int fidx);
3172 +extern void omap_set_dma_dest_data_pack(int lch, int enable);
3173 +extern void omap_set_dma_dest_burst_mode(int lch,
3174 + enum omap_dma_burst_mode burst_mode);
3175 +
3176 +extern void omap_set_dma_params(int lch,
3177 + struct omap_dma_channel_params *params);
3178 +
3179 +extern void omap_dma_link_lch(int lch_head, int lch_queue);
3180 +extern void omap_dma_unlink_lch(int lch_head, int lch_queue);
3181 +
3182 +extern int omap_set_dma_callback(int lch,
3183 + void (*callback)(int lch, u16 ch_status, void *data),
3184 + void *data);
3185 +extern dma_addr_t omap_get_dma_src_pos(int lch);
3186 +extern dma_addr_t omap_get_dma_dst_pos(int lch);
3187 +extern void omap_clear_dma(int lch);
3188 +extern int omap_get_dma_active_status(int lch);
3189 +extern int omap_dma_running(void);
3190 +extern void omap_dma_set_global_params(int arb_rate, int max_fifo_depth,
3191 + int tparams);
3192 +extern int omap_dma_set_prio_lch(int lch, unsigned char read_prio,
3193 + unsigned char write_prio);
3194 +extern void omap_set_dma_dst_endian_type(int lch, enum end_type etype);
3195 +extern void omap_set_dma_src_endian_type(int lch, enum end_type etype);
3196 +extern int omap_get_dma_index(int lch, int *ei, int *fi);
3197 +
3198 +void omap_dma_global_context_save(void);
3199 +void omap_dma_global_context_restore(void);
3200 +
3201 +extern void omap_dma_disable_irq(int lch);
3202 +
3203 +/* Chaining APIs */
3204 +#ifndef CONFIG_ARCH_OMAP1
3205 +extern int omap_request_dma_chain(int dev_id, const char *dev_name,
3206 + void (*callback) (int lch, u16 ch_status,
3207 + void *data),
3208 + int *chain_id, int no_of_chans,
3209 + int chain_mode,
3210 + struct omap_dma_channel_params params);
3211 +extern int omap_free_dma_chain(int chain_id);
3212 +extern int omap_dma_chain_a_transfer(int chain_id, int src_start,
3213 + int dest_start, int elem_count,
3214 + int frame_count, void *callbk_data);
3215 +extern int omap_start_dma_chain_transfers(int chain_id);
3216 +extern int omap_stop_dma_chain_transfers(int chain_id);
3217 +extern int omap_get_dma_chain_index(int chain_id, int *ei, int *fi);
3218 +extern int omap_get_dma_chain_dst_pos(int chain_id);
3219 +extern int omap_get_dma_chain_src_pos(int chain_id);
3220 +
3221 +extern int omap_modify_dma_chain_params(int chain_id,
3222 + struct omap_dma_channel_params params);
3223 +extern int omap_dma_chain_status(int chain_id);
3224 +#endif
3225 +
3226 +#if defined(CONFIG_ARCH_OMAP1) && defined(CONFIG_FB_OMAP)
3227 +#include <mach/lcd_dma.h>
3228 +#else
3229 +static inline int omap_lcd_dma_running(void)
3230 +{
3231 + return 0;
3232 +}
3233 +#endif
3234 +
3235 +#endif /* __ASM_ARCH_DMA_H */
3236 Index: linux-2.6.37-rc1/arch/arm/plat-omap/include/mach/dmtimer.h
3237 ===================================================================
3238 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
3239 +++ linux-2.6.37-rc1/arch/arm/plat-omap/include/mach/dmtimer.h 2010-11-05 17:36:26.173000001 +0100
3240 @@ -0,0 +1,84 @@
3241 +/*
3242 + * arch/arm/plat-omap/include/mach/dmtimer.h
3243 + *
3244 + * OMAP Dual-Mode Timers
3245 + *
3246 + * Copyright (C) 2005 Nokia Corporation
3247 + * Author: Lauri Leukkunen <lauri.leukkunen@nokia.com>
3248 + * PWM and clock framwork support by Timo Teras.
3249 + *
3250 + * This program is free software; you can redistribute it and/or modify it
3251 + * under the terms of the GNU General Public License as published by the
3252 + * Free Software Foundation; either version 2 of the License, or (at your
3253 + * option) any later version.
3254 + *
3255 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
3256 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
3257 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
3258 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
3259 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
3260 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
3261 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
3262 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
3263 + *
3264 + * You should have received a copy of the GNU General Public License along
3265 + * with this program; if not, write to the Free Software Foundation, Inc.,
3266 + * 675 Mass Ave, Cambridge, MA 02139, USA.
3267 + */
3268 +
3269 +#ifndef __ASM_ARCH_DMTIMER_H
3270 +#define __ASM_ARCH_DMTIMER_H
3271 +
3272 +/* clock sources */
3273 +#define OMAP_TIMER_SRC_SYS_CLK 0x00
3274 +#define OMAP_TIMER_SRC_32_KHZ 0x01
3275 +#define OMAP_TIMER_SRC_EXT_CLK 0x02
3276 +
3277 +/* timer interrupt enable bits */
3278 +#define OMAP_TIMER_INT_CAPTURE (1 << 2)
3279 +#define OMAP_TIMER_INT_OVERFLOW (1 << 1)
3280 +#define OMAP_TIMER_INT_MATCH (1 << 0)
3281 +
3282 +/* trigger types */
3283 +#define OMAP_TIMER_TRIGGER_NONE 0x00
3284 +#define OMAP_TIMER_TRIGGER_OVERFLOW 0x01
3285 +#define OMAP_TIMER_TRIGGER_OVERFLOW_AND_COMPARE 0x02
3286 +
3287 +struct omap_dm_timer;
3288 +struct clk;
3289 +
3290 +int omap_dm_timer_init(void);
3291 +
3292 +struct omap_dm_timer *omap_dm_timer_request(void);
3293 +struct omap_dm_timer *omap_dm_timer_request_specific(int timer_id);
3294 +void omap_dm_timer_free(struct omap_dm_timer *timer);
3295 +void omap_dm_timer_enable(struct omap_dm_timer *timer);
3296 +void omap_dm_timer_disable(struct omap_dm_timer *timer);
3297 +
3298 +int omap_dm_timer_get_irq(struct omap_dm_timer *timer);
3299 +
3300 +u32 omap_dm_timer_modify_idlect_mask(u32 inputmask);
3301 +struct clk *omap_dm_timer_get_fclk(struct omap_dm_timer *timer);
3302 +
3303 +void omap_dm_timer_trigger(struct omap_dm_timer *timer);
3304 +void omap_dm_timer_start(struct omap_dm_timer *timer);
3305 +void omap_dm_timer_stop(struct omap_dm_timer *timer);
3306 +
3307 +int omap_dm_timer_set_source(struct omap_dm_timer *timer, int source);
3308 +void omap_dm_timer_set_load(struct omap_dm_timer *timer, int autoreload, unsigned int value);
3309 +void omap_dm_timer_set_load_start(struct omap_dm_timer *timer, int autoreload, unsigned int value);
3310 +void omap_dm_timer_set_match(struct omap_dm_timer *timer, int enable, unsigned int match);
3311 +void omap_dm_timer_set_pwm(struct omap_dm_timer *timer, int def_on, int toggle, int trigger);
3312 +void omap_dm_timer_set_prescaler(struct omap_dm_timer *timer, int prescaler);
3313 +
3314 +void omap_dm_timer_set_int_enable(struct omap_dm_timer *timer, unsigned int value);
3315 +
3316 +unsigned int omap_dm_timer_read_status(struct omap_dm_timer *timer);
3317 +void omap_dm_timer_write_status(struct omap_dm_timer *timer, unsigned int value);
3318 +unsigned int omap_dm_timer_read_counter(struct omap_dm_timer *timer);
3319 +void omap_dm_timer_write_counter(struct omap_dm_timer *timer, unsigned int value);
3320 +
3321 +int omap_dm_timers_active(void);
3322 +
3323 +
3324 +#endif /* __ASM_ARCH_DMTIMER_H */
3325 Index: linux-2.6.37-rc1/arch/arm/plat-omap/include/mach/dsp_common.h
3326 ===================================================================
3327 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
3328 +++ linux-2.6.37-rc1/arch/arm/plat-omap/include/mach/dsp_common.h 2010-11-05 17:36:26.173000001 +0100
3329 @@ -0,0 +1,40 @@
3330 +/*
3331 + * This file is part of OMAP DSP driver (DSP Gateway version 3.3.1)
3332 + *
3333 + * Copyright (C) 2004-2006 Nokia Corporation. All rights reserved.
3334 + *
3335 + * Contact: Toshihiro Kobayashi <toshihiro.kobayashi@nokia.com>
3336 + *
3337 + * This program is free software; you can redistribute it and/or
3338 + * modify it under the terms of the GNU General Public License
3339 + * version 2 as published by the Free Software Foundation.
3340 + *
3341 + * This program is distributed in the hope that it will be useful, but
3342 + * WITHOUT ANY WARRANTY; without even the implied warranty of
3343 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
3344 + * General Public License for more details.
3345 + *
3346 + * You should have received a copy of the GNU General Public License
3347 + * along with this program; if not, write to the Free Software
3348 + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
3349 + * 02110-1301 USA
3350 + *
3351 + */
3352 +
3353 +#ifndef ASM_ARCH_DSP_COMMON_H
3354 +#define ASM_ARCH_DSP_COMMON_H
3355 +
3356 +#if defined(CONFIG_ARCH_OMAP1) && defined(CONFIG_OMAP_MMU_FWK)
3357 +extern void omap_dsp_request_mpui(void);
3358 +extern void omap_dsp_release_mpui(void);
3359 +extern int omap_dsp_request_mem(void);
3360 +extern int omap_dsp_release_mem(void);
3361 +#else
3362 +static inline int omap_dsp_request_mem(void)
3363 +{
3364 + return 0;
3365 +}
3366 +#define omap_dsp_release_mem() do {} while (0)
3367 +#endif
3368 +
3369 +#endif /* ASM_ARCH_DSP_COMMON_H */
3370 Index: linux-2.6.37-rc1/arch/arm/plat-omap/include/mach/fpga.h
3371 ===================================================================
3372 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
3373 +++ linux-2.6.37-rc1/arch/arm/plat-omap/include/mach/fpga.h 2010-11-05 17:36:26.173000001 +0100
3374 @@ -0,0 +1,197 @@
3375 +/*
3376 + * arch/arm/plat-omap/include/mach/fpga.h
3377 + *
3378 + * Interrupt handler for OMAP-1510 FPGA
3379 + *
3380 + * Copyright (C) 2001 RidgeRun, Inc.
3381 + * Author: Greg Lonnon <glonnon@ridgerun.com>
3382 + *
3383 + * Copyright (C) 2002 MontaVista Software, Inc.
3384 + *
3385 + * Separated FPGA interrupts from innovator1510.c and cleaned up for 2.6
3386 + * Copyright (C) 2004 Nokia Corporation by Tony Lindrgen <tony@atomide.com>
3387 + *
3388 + * This program is free software; you can redistribute it and/or modify
3389 + * it under the terms of the GNU General Public License version 2 as
3390 + * published by the Free Software Foundation.
3391 + */
3392 +
3393 +#ifndef __ASM_ARCH_OMAP_FPGA_H
3394 +#define __ASM_ARCH_OMAP_FPGA_H
3395 +
3396 +#if defined(CONFIG_MACH_OMAP_INNOVATOR) && defined(CONFIG_ARCH_OMAP15XX)
3397 +extern void omap1510_fpga_init_irq(void);
3398 +#else
3399 +#define omap1510_fpga_init_irq() (0)
3400 +#endif
3401 +
3402 +#define fpga_read(reg) __raw_readb(reg)
3403 +#define fpga_write(val, reg) __raw_writeb(val, reg)
3404 +
3405 +/*
3406 + * ---------------------------------------------------------------------------
3407 + * H2/P2 Debug board FPGA
3408 + * ---------------------------------------------------------------------------
3409 + */
3410 +/* maps in the FPGA registers and the ETHR registers */
3411 +#define H2P2_DBG_FPGA_BASE IOMEM(0xE8000000) /* VA */
3412 +#define H2P2_DBG_FPGA_SIZE SZ_4K /* SIZE */
3413 +#define H2P2_DBG_FPGA_START 0x04000000 /* PA */
3414 +
3415 +#define H2P2_DBG_FPGA_ETHR_START (H2P2_DBG_FPGA_START + 0x300)
3416 +#define H2P2_DBG_FPGA_FPGA_REV (H2P2_DBG_FPGA_BASE + 0x10) /* FPGA Revision */
3417 +#define H2P2_DBG_FPGA_BOARD_REV (H2P2_DBG_FPGA_BASE + 0x12) /* Board Revision */
3418 +#define H2P2_DBG_FPGA_GPIO (H2P2_DBG_FPGA_BASE + 0x14) /* GPIO outputs */
3419 +#define H2P2_DBG_FPGA_LEDS (H2P2_DBG_FPGA_BASE + 0x16) /* LEDs outputs */
3420 +#define H2P2_DBG_FPGA_MISC_INPUTS (H2P2_DBG_FPGA_BASE + 0x18) /* Misc inputs */
3421 +#define H2P2_DBG_FPGA_LAN_STATUS (H2P2_DBG_FPGA_BASE + 0x1A) /* LAN Status line */
3422 +#define H2P2_DBG_FPGA_LAN_RESET (H2P2_DBG_FPGA_BASE + 0x1C) /* LAN Reset line */
3423 +
3424 +/* NOTE: most boards don't have a static mapping for the FPGA ... */
3425 +struct h2p2_dbg_fpga {
3426 + /* offset 0x00 */
3427 + u16 smc91x[8];
3428 + /* offset 0x10 */
3429 + u16 fpga_rev;
3430 + u16 board_rev;
3431 + u16 gpio_outputs;
3432 + u16 leds;
3433 + /* offset 0x18 */
3434 + u16 misc_inputs;
3435 + u16 lan_status;
3436 + u16 lan_reset;
3437 + u16 reserved0;
3438 + /* offset 0x20 */
3439 + u16 ps2_data;
3440 + u16 ps2_ctrl;
3441 + /* plus also 4 rs232 ports ... */
3442 +};
3443 +
3444 +/* LEDs definition on debug board (16 LEDs, all physically green) */
3445 +#define H2P2_DBG_FPGA_LED_GREEN (1 << 15)
3446 +#define H2P2_DBG_FPGA_LED_AMBER (1 << 14)
3447 +#define H2P2_DBG_FPGA_LED_RED (1 << 13)
3448 +#define H2P2_DBG_FPGA_LED_BLUE (1 << 12)
3449 +/* cpu0 load-meter LEDs */
3450 +#define H2P2_DBG_FPGA_LOAD_METER (1 << 0) // A bit of fun on our board ...
3451 +#define H2P2_DBG_FPGA_LOAD_METER_SIZE 11
3452 +#define H2P2_DBG_FPGA_LOAD_METER_MASK ((1 << H2P2_DBG_FPGA_LOAD_METER_SIZE) - 1)
3453 +
3454 +#define H2P2_DBG_FPGA_P2_LED_TIMER (1 << 0)
3455 +#define H2P2_DBG_FPGA_P2_LED_IDLE (1 << 1)
3456 +
3457 +/*
3458 + * ---------------------------------------------------------------------------
3459 + * OMAP-1510 FPGA
3460 + * ---------------------------------------------------------------------------
3461 + */
3462 +#define OMAP1510_FPGA_BASE IOMEM(0xE8000000) /* VA */
3463 +#define OMAP1510_FPGA_SIZE SZ_4K
3464 +#define OMAP1510_FPGA_START 0x08000000 /* PA */
3465 +
3466 +/* Revision */
3467 +#define OMAP1510_FPGA_REV_LOW (OMAP1510_FPGA_BASE + 0x0)
3468 +#define OMAP1510_FPGA_REV_HIGH (OMAP1510_FPGA_BASE + 0x1)
3469 +
3470 +#define OMAP1510_FPGA_LCD_PANEL_CONTROL (OMAP1510_FPGA_BASE + 0x2)
3471 +#define OMAP1510_FPGA_LED_DIGIT (OMAP1510_FPGA_BASE + 0x3)
3472 +#define INNOVATOR_FPGA_HID_SPI (OMAP1510_FPGA_BASE + 0x4)
3473 +#define OMAP1510_FPGA_POWER (OMAP1510_FPGA_BASE + 0x5)
3474 +
3475 +/* Interrupt status */
3476 +#define OMAP1510_FPGA_ISR_LO (OMAP1510_FPGA_BASE + 0x6)
3477 +#define OMAP1510_FPGA_ISR_HI (OMAP1510_FPGA_BASE + 0x7)
3478 +
3479 +/* Interrupt mask */
3480 +#define OMAP1510_FPGA_IMR_LO (OMAP1510_FPGA_BASE + 0x8)
3481 +#define OMAP1510_FPGA_IMR_HI (OMAP1510_FPGA_BASE + 0x9)
3482 +
3483 +/* Reset registers */
3484 +#define OMAP1510_FPGA_HOST_RESET (OMAP1510_FPGA_BASE + 0xa)
3485 +#define OMAP1510_FPGA_RST (OMAP1510_FPGA_BASE + 0xb)
3486 +
3487 +#define OMAP1510_FPGA_AUDIO (OMAP1510_FPGA_BASE + 0xc)
3488 +#define OMAP1510_FPGA_DIP (OMAP1510_FPGA_BASE + 0xe)
3489 +#define OMAP1510_FPGA_FPGA_IO (OMAP1510_FPGA_BASE + 0xf)
3490 +#define OMAP1510_FPGA_UART1 (OMAP1510_FPGA_BASE + 0x14)
3491 +#define OMAP1510_FPGA_UART2 (OMAP1510_FPGA_BASE + 0x15)
3492 +#define OMAP1510_FPGA_OMAP1510_STATUS (OMAP1510_FPGA_BASE + 0x16)
3493 +#define OMAP1510_FPGA_BOARD_REV (OMAP1510_FPGA_BASE + 0x18)
3494 +#define OMAP1510P1_PPT_DATA (OMAP1510_FPGA_BASE + 0x100)
3495 +#define OMAP1510P1_PPT_STATUS (OMAP1510_FPGA_BASE + 0x101)
3496 +#define OMAP1510P1_PPT_CONTROL (OMAP1510_FPGA_BASE + 0x102)
3497 +
3498 +#define OMAP1510_FPGA_TOUCHSCREEN (OMAP1510_FPGA_BASE + 0x204)
3499 +
3500 +#define INNOVATOR_FPGA_INFO (OMAP1510_FPGA_BASE + 0x205)
3501 +#define INNOVATOR_FPGA_LCD_BRIGHT_LO (OMAP1510_FPGA_BASE + 0x206)
3502 +#define INNOVATOR_FPGA_LCD_BRIGHT_HI (OMAP1510_FPGA_BASE + 0x207)
3503 +#define INNOVATOR_FPGA_LED_GRN_LO (OMAP1510_FPGA_BASE + 0x208)
3504 +#define INNOVATOR_FPGA_LED_GRN_HI (OMAP1510_FPGA_BASE + 0x209)
3505 +#define INNOVATOR_FPGA_LED_RED_LO (OMAP1510_FPGA_BASE + 0x20a)
3506 +#define INNOVATOR_FPGA_LED_RED_HI (OMAP1510_FPGA_BASE + 0x20b)
3507 +#define INNOVATOR_FPGA_CAM_USB_CONTROL (OMAP1510_FPGA_BASE + 0x20c)
3508 +#define INNOVATOR_FPGA_EXP_CONTROL (OMAP1510_FPGA_BASE + 0x20d)
3509 +#define INNOVATOR_FPGA_ISR2 (OMAP1510_FPGA_BASE + 0x20e)
3510 +#define INNOVATOR_FPGA_IMR2 (OMAP1510_FPGA_BASE + 0x210)
3511 +
3512 +#define OMAP1510_FPGA_ETHR_START (OMAP1510_FPGA_START + 0x300)
3513 +
3514 +/*
3515 + * Power up Giga UART driver, turn on HID clock.
3516 + * Turn off BT power, since we're not using it and it
3517 + * draws power.
3518 + */
3519 +#define OMAP1510_FPGA_RESET_VALUE 0x42
3520 +
3521 +#define OMAP1510_FPGA_PCR_IF_PD0 (1 << 7)
3522 +#define OMAP1510_FPGA_PCR_COM2_EN (1 << 6)
3523 +#define OMAP1510_FPGA_PCR_COM1_EN (1 << 5)
3524 +#define OMAP1510_FPGA_PCR_EXP_PD0 (1 << 4)
3525 +#define OMAP1510_FPGA_PCR_EXP_PD1 (1 << 3)
3526 +#define OMAP1510_FPGA_PCR_48MHZ_CLK (1 << 2)
3527 +#define OMAP1510_FPGA_PCR_4MHZ_CLK (1 << 1)
3528 +#define OMAP1510_FPGA_PCR_RSRVD_BIT0 (1 << 0)
3529 +
3530 +/*
3531 + * Innovator/OMAP1510 FPGA HID register bit definitions
3532 + */
3533 +#define OMAP1510_FPGA_HID_SCLK (1<<0) /* output */
3534 +#define OMAP1510_FPGA_HID_MOSI (1<<1) /* output */
3535 +#define OMAP1510_FPGA_HID_nSS (1<<2) /* output 0/1 chip idle/select */
3536 +#define OMAP1510_FPGA_HID_nHSUS (1<<3) /* output 0/1 host active/suspended */
3537 +#define OMAP1510_FPGA_HID_MISO (1<<4) /* input */
3538 +#define OMAP1510_FPGA_HID_ATN (1<<5) /* input 0/1 chip idle/ATN */
3539 +#define OMAP1510_FPGA_HID_rsrvd (1<<6)
3540 +#define OMAP1510_FPGA_HID_RESETn (1<<7) /* output - 0/1 USAR reset/run */
3541 +
3542 +/* The FPGA IRQ is cascaded through GPIO_13 */
3543 +#define OMAP1510_INT_FPGA (IH_GPIO_BASE + 13)
3544 +
3545 +/* IRQ Numbers for interrupts muxed through the FPGA */
3546 +#define OMAP1510_INT_FPGA_ATN (OMAP_FPGA_IRQ_BASE + 0)
3547 +#define OMAP1510_INT_FPGA_ACK (OMAP_FPGA_IRQ_BASE + 1)
3548 +#define OMAP1510_INT_FPGA2 (OMAP_FPGA_IRQ_BASE + 2)
3549 +#define OMAP1510_INT_FPGA3 (OMAP_FPGA_IRQ_BASE + 3)
3550 +#define OMAP1510_INT_FPGA4 (OMAP_FPGA_IRQ_BASE + 4)
3551 +#define OMAP1510_INT_FPGA5 (OMAP_FPGA_IRQ_BASE + 5)
3552 +#define OMAP1510_INT_FPGA6 (OMAP_FPGA_IRQ_BASE + 6)
3553 +#define OMAP1510_INT_FPGA7 (OMAP_FPGA_IRQ_BASE + 7)
3554 +#define OMAP1510_INT_FPGA8 (OMAP_FPGA_IRQ_BASE + 8)
3555 +#define OMAP1510_INT_FPGA9 (OMAP_FPGA_IRQ_BASE + 9)
3556 +#define OMAP1510_INT_FPGA10 (OMAP_FPGA_IRQ_BASE + 10)
3557 +#define OMAP1510_INT_FPGA11 (OMAP_FPGA_IRQ_BASE + 11)
3558 +#define OMAP1510_INT_FPGA12 (OMAP_FPGA_IRQ_BASE + 12)
3559 +#define OMAP1510_INT_ETHER (OMAP_FPGA_IRQ_BASE + 13)
3560 +#define OMAP1510_INT_FPGAUART1 (OMAP_FPGA_IRQ_BASE + 14)
3561 +#define OMAP1510_INT_FPGAUART2 (OMAP_FPGA_IRQ_BASE + 15)
3562 +#define OMAP1510_INT_FPGA_TS (OMAP_FPGA_IRQ_BASE + 16)
3563 +#define OMAP1510_INT_FPGA17 (OMAP_FPGA_IRQ_BASE + 17)
3564 +#define OMAP1510_INT_FPGA_CAM (OMAP_FPGA_IRQ_BASE + 18)
3565 +#define OMAP1510_INT_FPGA_RTC_A (OMAP_FPGA_IRQ_BASE + 19)
3566 +#define OMAP1510_INT_FPGA_RTC_B (OMAP_FPGA_IRQ_BASE + 20)
3567 +#define OMAP1510_INT_FPGA_CD (OMAP_FPGA_IRQ_BASE + 21)
3568 +#define OMAP1510_INT_FPGA22 (OMAP_FPGA_IRQ_BASE + 22)
3569 +#define OMAP1510_INT_FPGA23 (OMAP_FPGA_IRQ_BASE + 23)
3570 +
3571 +#endif
3572 Index: linux-2.6.37-rc1/arch/arm/plat-omap/include/mach/gpio.h
3573 ===================================================================
3574 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
3575 +++ linux-2.6.37-rc1/arch/arm/plat-omap/include/mach/gpio.h 2010-11-05 17:36:26.173000001 +0100
3576 @@ -0,0 +1,129 @@
3577 +/*
3578 + * arch/arm/plat-omap/include/mach/gpio.h
3579 + *
3580 + * OMAP GPIO handling defines and functions
3581 + *
3582 + * Copyright (C) 2003-2005 Nokia Corporation
3583 + *
3584 + * Written by Juha Yrjölä <juha.yrjola@nokia.com>
3585 + *
3586 + * This program is free software; you can redistribute it and/or modify
3587 + * it under the terms of the GNU General Public License as published by
3588 + * the Free Software Foundation; either version 2 of the License, or
3589 + * (at your option) any later version.
3590 + *
3591 + * This program is distributed in the hope that it will be useful,
3592 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
3593 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
3594 + * GNU General Public License for more details.
3595 + *
3596 + * You should have received a copy of the GNU General Public License
3597 + * along with this program; if not, write to the Free Software
3598 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
3599 + *
3600 + */
3601 +
3602 +#ifndef __ASM_ARCH_OMAP_GPIO_H
3603 +#define __ASM_ARCH_OMAP_GPIO_H
3604 +
3605 +#include <linux/io.h>
3606 +#include <mach/irqs.h>
3607 +
3608 +#define OMAP1_MPUIO_BASE 0xfffb5000
3609 +
3610 +#if (defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850))
3611 +
3612 +#define OMAP_MPUIO_INPUT_LATCH 0x00
3613 +#define OMAP_MPUIO_OUTPUT 0x02
3614 +#define OMAP_MPUIO_IO_CNTL 0x04
3615 +#define OMAP_MPUIO_KBR_LATCH 0x08
3616 +#define OMAP_MPUIO_KBC 0x0a
3617 +#define OMAP_MPUIO_GPIO_EVENT_MODE 0x0c
3618 +#define OMAP_MPUIO_GPIO_INT_EDGE 0x0e
3619 +#define OMAP_MPUIO_KBD_INT 0x10
3620 +#define OMAP_MPUIO_GPIO_INT 0x12
3621 +#define OMAP_MPUIO_KBD_MASKIT 0x14
3622 +#define OMAP_MPUIO_GPIO_MASKIT 0x16
3623 +#define OMAP_MPUIO_GPIO_DEBOUNCING 0x18
3624 +#define OMAP_MPUIO_LATCH 0x1a
3625 +#else
3626 +#define OMAP_MPUIO_INPUT_LATCH 0x00
3627 +#define OMAP_MPUIO_OUTPUT 0x04
3628 +#define OMAP_MPUIO_IO_CNTL 0x08
3629 +#define OMAP_MPUIO_KBR_LATCH 0x10
3630 +#define OMAP_MPUIO_KBC 0x14
3631 +#define OMAP_MPUIO_GPIO_EVENT_MODE 0x18
3632 +#define OMAP_MPUIO_GPIO_INT_EDGE 0x1c
3633 +#define OMAP_MPUIO_KBD_INT 0x20
3634 +#define OMAP_MPUIO_GPIO_INT 0x24
3635 +#define OMAP_MPUIO_KBD_MASKIT 0x28
3636 +#define OMAP_MPUIO_GPIO_MASKIT 0x2c
3637 +#define OMAP_MPUIO_GPIO_DEBOUNCING 0x30
3638 +#define OMAP_MPUIO_LATCH 0x34
3639 +#endif
3640 +
3641 +#define OMAP34XX_NR_GPIOS 6
3642 +
3643 +#define OMAP_MPUIO(nr) (OMAP_MAX_GPIO_LINES + (nr))
3644 +#define OMAP_GPIO_IS_MPUIO(nr) ((nr) >= OMAP_MAX_GPIO_LINES)
3645 +
3646 +#define OMAP_GPIO_IRQ(nr) (OMAP_GPIO_IS_MPUIO(nr) ? \
3647 + IH_MPUIO_BASE + ((nr) & 0x0f) : \
3648 + IH_GPIO_BASE + (nr))
3649 +
3650 +extern int omap_gpio_init(void); /* Call from board init only */
3651 +extern void omap2_gpio_prepare_for_retention(void);
3652 +extern void omap2_gpio_resume_after_retention(void);
3653 +extern void omap_set_gpio_debounce(int gpio, int enable);
3654 +extern void omap_set_gpio_debounce_time(int gpio, int enable);
3655 +extern void omap_gpio_save_context(void);
3656 +extern void omap_gpio_restore_context(void);
3657 +/*-------------------------------------------------------------------------*/
3658 +
3659 +/* Wrappers for "new style" GPIO calls, using the new infrastructure
3660 + * which lets us plug in FPGA, I2C, and other implementations.
3661 + * *
3662 + * The original OMAP-specfic calls should eventually be removed.
3663 + */
3664 +
3665 +#include <linux/errno.h>
3666 +#include <asm-generic/gpio.h>
3667 +
3668 +static inline int gpio_get_value(unsigned gpio)
3669 +{
3670 + return __gpio_get_value(gpio);
3671 +}
3672 +
3673 +static inline void gpio_set_value(unsigned gpio, int value)
3674 +{
3675 + __gpio_set_value(gpio, value);
3676 +}
3677 +
3678 +static inline int gpio_cansleep(unsigned gpio)
3679 +{
3680 + return __gpio_cansleep(gpio);
3681 +}
3682 +
3683 +static inline int gpio_to_irq(unsigned gpio)
3684 +{
3685 + return __gpio_to_irq(gpio);
3686 +}
3687 +
3688 +static inline int irq_to_gpio(unsigned irq)
3689 +{
3690 + int tmp;
3691 +
3692 + /* omap1 SOC mpuio */
3693 + if (cpu_class_is_omap1() && (irq < (IH_MPUIO_BASE + 16)))
3694 + return (irq - IH_MPUIO_BASE) + OMAP_MAX_GPIO_LINES;
3695 +
3696 + /* SOC gpio */
3697 + tmp = irq - IH_GPIO_BASE;
3698 + if (tmp < OMAP_MAX_GPIO_LINES)
3699 + return tmp;
3700 +
3701 + /* we don't supply reverse mappings for non-SOC gpios */
3702 + return -EIO;
3703 +}
3704 +
3705 +#endif
3706 Index: linux-2.6.37-rc1/arch/arm/plat-omap/include/mach/gpio-switch.h
3707 ===================================================================
3708 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
3709 +++ linux-2.6.37-rc1/arch/arm/plat-omap/include/mach/gpio-switch.h 2010-11-05 17:36:26.174000001 +0100
3710 @@ -0,0 +1,54 @@
3711 +/*
3712 + * GPIO switch definitions
3713 + *
3714 + * Copyright (C) 2006 Nokia Corporation
3715 + *
3716 + * This program is free software; you can redistribute it and/or modify
3717 + * it under the terms of the GNU General Public License version 2 as
3718 + * published by the Free Software Foundation.
3719 + */
3720 +
3721 +#ifndef __ASM_ARCH_OMAP_GPIO_SWITCH_H
3722 +#define __ASM_ARCH_OMAP_GPIO_SWITCH_H
3723 +
3724 +#include <linux/types.h>
3725 +
3726 +/* Cover:
3727 + * high -> closed
3728 + * low -> open
3729 + * Connection:
3730 + * high -> connected
3731 + * low -> disconnected
3732 + * Activity:
3733 + * high -> active
3734 + * low -> inactive
3735 + *
3736 + */
3737 +#define OMAP_GPIO_SWITCH_TYPE_COVER 0x0000
3738 +#define OMAP_GPIO_SWITCH_TYPE_CONNECTION 0x0001
3739 +#define OMAP_GPIO_SWITCH_TYPE_ACTIVITY 0x0002
3740 +#define OMAP_GPIO_SWITCH_FLAG_INVERTED 0x0001
3741 +#define OMAP_GPIO_SWITCH_FLAG_OUTPUT 0x0002
3742 +
3743 +struct omap_gpio_switch {
3744 + const char *name;
3745 + s16 gpio;
3746 + unsigned flags:4;
3747 + unsigned type:4;
3748 +
3749 + /* Time in ms to debounce when transitioning from
3750 + * inactive state to active state. */
3751 + u16 debounce_rising;
3752 + /* Same for transition from active to inactive state. */
3753 + u16 debounce_falling;
3754 +
3755 + /* notify board-specific code about state changes */
3756 + void (* notify)(void *data, int state);
3757 + void *notify_data;
3758 +};
3759 +
3760 +/* Call at init time only */
3761 +extern void omap_register_gpio_switches(const struct omap_gpio_switch *tbl,
3762 + int count);
3763 +
3764 +#endif
3765 Index: linux-2.6.37-rc1/arch/arm/plat-omap/include/mach/gpmc.h
3766 ===================================================================
3767 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
3768 +++ linux-2.6.37-rc1/arch/arm/plat-omap/include/mach/gpmc.h 2010-11-05 17:36:26.174000001 +0100
3769 @@ -0,0 +1,115 @@
3770 +/*
3771 + * General-Purpose Memory Controller for OMAP2
3772 + *
3773 + * Copyright (C) 2005-2006 Nokia Corporation
3774 + *
3775 + * This program is free software; you can redistribute it and/or modify
3776 + * it under the terms of the GNU General Public License version 2 as
3777 + * published by the Free Software Foundation.
3778 + */
3779 +
3780 +#ifndef __OMAP2_GPMC_H
3781 +#define __OMAP2_GPMC_H
3782 +
3783 +/* Maximum Number of Chip Selects */
3784 +#define GPMC_CS_NUM 8
3785 +
3786 +#define GPMC_CS_CONFIG1 0x00
3787 +#define GPMC_CS_CONFIG2 0x04
3788 +#define GPMC_CS_CONFIG3 0x08
3789 +#define GPMC_CS_CONFIG4 0x0c
3790 +#define GPMC_CS_CONFIG5 0x10
3791 +#define GPMC_CS_CONFIG6 0x14
3792 +#define GPMC_CS_CONFIG7 0x18
3793 +#define GPMC_CS_NAND_COMMAND 0x1c
3794 +#define GPMC_CS_NAND_ADDRESS 0x20
3795 +#define GPMC_CS_NAND_DATA 0x24
3796 +
3797 +#define GPMC_CONFIG 0x50
3798 +#define GPMC_STATUS 0x54
3799 +
3800 +#define GPMC_CONFIG1_WRAPBURST_SUPP (1 << 31)
3801 +#define GPMC_CONFIG1_READMULTIPLE_SUPP (1 << 30)
3802 +#define GPMC_CONFIG1_READTYPE_ASYNC (0 << 29)
3803 +#define GPMC_CONFIG1_READTYPE_SYNC (1 << 29)
3804 +#define GPMC_CONFIG1_WRITEMULTIPLE_SUPP (1 << 28)
3805 +#define GPMC_CONFIG1_WRITETYPE_ASYNC (0 << 27)
3806 +#define GPMC_CONFIG1_WRITETYPE_SYNC (1 << 27)
3807 +#define GPMC_CONFIG1_CLKACTIVATIONTIME(val) ((val & 3) << 25)
3808 +#define GPMC_CONFIG1_PAGE_LEN(val) ((val & 3) << 23)
3809 +#define GPMC_CONFIG1_WAIT_READ_MON (1 << 22)
3810 +#define GPMC_CONFIG1_WAIT_WRITE_MON (1 << 21)
3811 +#define GPMC_CONFIG1_WAIT_MON_IIME(val) ((val & 3) << 18)
3812 +#define GPMC_CONFIG1_WAIT_PIN_SEL(val) ((val & 3) << 16)
3813 +#define GPMC_CONFIG1_DEVICESIZE(val) ((val & 3) << 12)
3814 +#define GPMC_CONFIG1_DEVICESIZE_16 GPMC_CONFIG1_DEVICESIZE(1)
3815 +#define GPMC_CONFIG1_DEVICETYPE(val) ((val & 3) << 10)
3816 +#define GPMC_CONFIG1_DEVICETYPE_NOR GPMC_CONFIG1_DEVICETYPE(0)
3817 +#define GPMC_CONFIG1_DEVICETYPE_NAND GPMC_CONFIG1_DEVICETYPE(2)
3818 +#define GPMC_CONFIG1_MUXADDDATA (1 << 9)
3819 +#define GPMC_CONFIG1_TIME_PARA_GRAN (1 << 4)
3820 +#define GPMC_CONFIG1_FCLK_DIV(val) (val & 3)
3821 +#define GPMC_CONFIG1_FCLK_DIV2 (GPMC_CONFIG1_FCLK_DIV(1))
3822 +#define GPMC_CONFIG1_FCLK_DIV3 (GPMC_CONFIG1_FCLK_DIV(2))
3823 +#define GPMC_CONFIG1_FCLK_DIV4 (GPMC_CONFIG1_FCLK_DIV(3))
3824 +#define GPMC_CONFIG7_CSVALID (1 << 6)
3825 +
3826 +/*
3827 + * Note that all values in this struct are in nanoseconds, while
3828 + * the register values are in gpmc_fck cycles.
3829 + */
3830 +struct gpmc_timings {
3831 + /* Minimum clock period for synchronous mode */
3832 + u16 sync_clk;
3833 +
3834 + /* Chip-select signal timings corresponding to GPMC_CS_CONFIG2 */
3835 + u16 cs_on; /* Assertion time */
3836 + u16 cs_rd_off; /* Read deassertion time */
3837 + u16 cs_wr_off; /* Write deassertion time */
3838 +
3839 + /* ADV signal timings corresponding to GPMC_CONFIG3 */
3840 + u16 adv_on; /* Assertion time */
3841 + u16 adv_rd_off; /* Read deassertion time */
3842 + u16 adv_wr_off; /* Write deassertion time */
3843 +
3844 + /* WE signals timings corresponding to GPMC_CONFIG4 */
3845 + u16 we_on; /* WE assertion time */
3846 + u16 we_off; /* WE deassertion time */
3847 +
3848 + /* OE signals timings corresponding to GPMC_CONFIG4 */
3849 + u16 oe_on; /* OE assertion time */
3850 + u16 oe_off; /* OE deassertion time */
3851 +
3852 + /* Access time and cycle time timings corresponding to GPMC_CONFIG5 */
3853 + u16 page_burst_access; /* Multiple access word delay */
3854 + u16 access; /* Start-cycle to first data valid delay */
3855 + u16 rd_cycle; /* Total read cycle time */
3856 + u16 wr_cycle; /* Total write cycle time */
3857 +
3858 + /* The following are only on OMAP3430 */
3859 + u16 wr_access; /* WRACCESSTIME */
3860 + u16 wr_data_mux_bus; /* WRDATAONADMUXBUS */
3861 +};
3862 +
3863 +extern unsigned int gpmc_ns_to_ticks(unsigned int time_ns);
3864 +extern unsigned int gpmc_ticks_to_ns(unsigned int ticks);
3865 +extern unsigned int gpmc_round_ns_to_ticks(unsigned int time_ns);
3866 +extern unsigned long gpmc_get_fclk_period(void);
3867 +
3868 +extern void gpmc_cs_write_reg(int cs, int idx, u32 val);
3869 +extern u32 gpmc_cs_read_reg(int cs, int idx);
3870 +extern int gpmc_cs_calc_divider(int cs, unsigned int sync_clk);
3871 +extern int gpmc_cs_set_timings(int cs, const struct gpmc_timings *t);
3872 +extern int gpmc_cs_request(int cs, unsigned long size, unsigned long *base);
3873 +extern void gpmc_cs_free(int cs);
3874 +extern int gpmc_cs_set_reserved(int cs, int reserved);
3875 +extern int gpmc_cs_reserved(int cs);
3876 +extern int gpmc_prefetch_enable(int cs, int dma_mode,
3877 + unsigned int u32_count, int is_write);
3878 +extern void gpmc_prefetch_reset(void);
3879 +extern int gpmc_prefetch_status(void);
3880 +extern void omap3_gpmc_save_context(void);
3881 +extern void omap3_gpmc_restore_context(void);
3882 +extern void __init gpmc_init(void);
3883 +
3884 +#endif
3885 Index: linux-2.6.37-rc1/arch/arm/plat-omap/include/mach/gpmc-smc91x.h
3886 ===================================================================
3887 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
3888 +++ linux-2.6.37-rc1/arch/arm/plat-omap/include/mach/gpmc-smc91x.h 2010-11-05 17:36:26.174000001 +0100
3889 @@ -0,0 +1,42 @@
3890 +/*
3891 + * arch/arm/plat-omap/include/mach/gpmc-smc91x.h
3892 + *
3893 + * Copyright (C) 2009 Nokia Corporation
3894 + *
3895 + * This program is free software; you can redistribute it and/or modify
3896 + * it under the terms of the GNU General Public License version 2 as
3897 + * published by the Free Software Foundation.
3898 + */
3899 +
3900 +#ifndef __ASM_ARCH_OMAP_GPMC_SMC91X_H__
3901 +
3902 +#define GPMC_TIMINGS_SMC91C96 (1 << 4)
3903 +#define GPMC_MUX_ADD_DATA (1 << 5) /* GPMC_CONFIG1_MUXADDDATA */
3904 +#define GPMC_READ_MON (1 << 6) /* GPMC_CONFIG1_WAIT_READ_MON */
3905 +#define GPMC_WRITE_MON (1 << 7) /* GPMC_CONFIG1_WAIT_WRITE_MON */
3906 +
3907 +struct omap_smc91x_platform_data {
3908 + int cs;
3909 + int gpio_irq;
3910 + int gpio_pwrdwn;
3911 + int gpio_reset;
3912 + int wait_pin; /* Optional GPMC_CONFIG1_WAITPINSELECT */
3913 + u32 flags;
3914 + int (*retime)(void);
3915 +};
3916 +
3917 +#if defined(CONFIG_SMC91X) || \
3918 + defined(CONFIG_SMC91X_MODULE)
3919 +
3920 +extern void gpmc_smc91x_init(struct omap_smc91x_platform_data *d);
3921 +
3922 +#else
3923 +
3924 +#define board_smc91x_data NULL
3925 +
3926 +static inline void gpmc_smc91x_init(struct omap_smc91x_platform_data *d)
3927 +{
3928 +}
3929 +
3930 +#endif
3931 +#endif
3932 Index: linux-2.6.37-rc1/arch/arm/plat-omap/include/mach/hardware.h
3933 ===================================================================
3934 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
3935 +++ linux-2.6.37-rc1/arch/arm/plat-omap/include/mach/hardware.h 2010-11-05 17:36:26.174000001 +0100
3936 @@ -0,0 +1,290 @@
3937 +/*
3938 + * arch/arm/plat-omap/include/mach/hardware.h
3939 + *
3940 + * Hardware definitions for TI OMAP processors and boards
3941 + *
3942 + * NOTE: Please put device driver specific defines into a separate header
3943 + * file for each driver.
3944 + *
3945 + * Copyright (C) 2001 RidgeRun, Inc.
3946 + * Author: RidgeRun, Inc. Greg Lonnon <glonnon@ridgerun.com>
3947 + *
3948 + * Reorganized for Linux-2.6 by Tony Lindgren <tony@atomide.com>
3949 + * and Dirk Behme <dirk.behme@de.bosch.com>
3950 + *
3951 + * This program is free software; you can redistribute it and/or modify it
3952 + * under the terms of the GNU General Public License as published by the
3953 + * Free Software Foundation; either version 2 of the License, or (at your
3954 + * option) any later version.
3955 + *
3956 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
3957 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
3958 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
3959 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
3960 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
3961 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
3962 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
3963 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
3964 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
3965 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
3966 + *
3967 + * You should have received a copy of the GNU General Public License along
3968 + * with this program; if not, write to the Free Software Foundation, Inc.,
3969 + * 675 Mass Ave, Cambridge, MA 02139, USA.
3970 + */
3971 +
3972 +#ifndef __ASM_ARCH_OMAP_HARDWARE_H
3973 +#define __ASM_ARCH_OMAP_HARDWARE_H
3974 +
3975 +#include <asm/sizes.h>
3976 +#ifndef __ASSEMBLER__
3977 +#include <asm/types.h>
3978 +#include <plat/cpu.h>
3979 +#endif
3980 +#include <plat/serial.h>
3981 +
3982 +/*
3983 + * ---------------------------------------------------------------------------
3984 + * Common definitions for all OMAP processors
3985 + * NOTE: Put all processor or board specific parts to the special header
3986 + * files.
3987 + * ---------------------------------------------------------------------------
3988 + */
3989 +
3990 +/*
3991 + * ----------------------------------------------------------------------------
3992 + * Timers
3993 + * ----------------------------------------------------------------------------
3994 + */
3995 +#define OMAP_MPU_TIMER1_BASE (0xfffec500)
3996 +#define OMAP_MPU_TIMER2_BASE (0xfffec600)
3997 +#define OMAP_MPU_TIMER3_BASE (0xfffec700)
3998 +#define MPU_TIMER_FREE (1 << 6)
3999 +#define MPU_TIMER_CLOCK_ENABLE (1 << 5)
4000 +#define MPU_TIMER_AR (1 << 1)
4001 +#define MPU_TIMER_ST (1 << 0)
4002 +
4003 +/*
4004 + * ----------------------------------------------------------------------------
4005 + * Clocks
4006 + * ----------------------------------------------------------------------------
4007 + */
4008 +#define CLKGEN_REG_BASE (0xfffece00)
4009 +#define ARM_CKCTL (CLKGEN_REG_BASE + 0x0)
4010 +#define ARM_IDLECT1 (CLKGEN_REG_BASE + 0x4)
4011 +#define ARM_IDLECT2 (CLKGEN_REG_BASE + 0x8)
4012 +#define ARM_EWUPCT (CLKGEN_REG_BASE + 0xC)
4013 +#define ARM_RSTCT1 (CLKGEN_REG_BASE + 0x10)
4014 +#define ARM_RSTCT2 (CLKGEN_REG_BASE + 0x14)
4015 +#define ARM_SYSST (CLKGEN_REG_BASE + 0x18)
4016 +#define ARM_IDLECT3 (CLKGEN_REG_BASE + 0x24)
4017 +
4018 +#define CK_RATEF 1
4019 +#define CK_IDLEF 2
4020 +#define CK_ENABLEF 4
4021 +#define CK_SELECTF 8
4022 +#define SETARM_IDLE_SHIFT
4023 +
4024 +/* DPLL control registers */
4025 +#define DPLL_CTL (0xfffecf00)
4026 +
4027 +/* DSP clock control. Must use __raw_readw() and __raw_writew() with these */
4028 +#define DSP_CONFIG_REG_BASE IOMEM(0xe1008000)
4029 +#define DSP_CKCTL (DSP_CONFIG_REG_BASE + 0x0)
4030 +#define DSP_IDLECT1 (DSP_CONFIG_REG_BASE + 0x4)
4031 +#define DSP_IDLECT2 (DSP_CONFIG_REG_BASE + 0x8)
4032 +#define DSP_RSTCT2 (DSP_CONFIG_REG_BASE + 0x14)
4033 +
4034 +/*
4035 + * ---------------------------------------------------------------------------
4036 + * UPLD
4037 + * ---------------------------------------------------------------------------
4038 + */
4039 +#define ULPD_REG_BASE (0xfffe0800)
4040 +#define ULPD_IT_STATUS (ULPD_REG_BASE + 0x14)
4041 +#define ULPD_SETUP_ANALOG_CELL_3 (ULPD_REG_BASE + 0x24)
4042 +#define ULPD_CLOCK_CTRL (ULPD_REG_BASE + 0x30)
4043 +# define DIS_USB_PVCI_CLK (1 << 5) /* no USB/FAC synch */
4044 +# define USB_MCLK_EN (1 << 4) /* enable W4_USB_CLKO */
4045 +#define ULPD_SOFT_REQ (ULPD_REG_BASE + 0x34)
4046 +# define SOFT_UDC_REQ (1 << 4)
4047 +# define SOFT_USB_CLK_REQ (1 << 3)
4048 +# define SOFT_DPLL_REQ (1 << 0)
4049 +#define ULPD_DPLL_CTRL (ULPD_REG_BASE + 0x3c)
4050 +#define ULPD_STATUS_REQ (ULPD_REG_BASE + 0x40)
4051 +#define ULPD_APLL_CTRL (ULPD_REG_BASE + 0x4c)
4052 +#define ULPD_POWER_CTRL (ULPD_REG_BASE + 0x50)
4053 +#define ULPD_SOFT_DISABLE_REQ_REG (ULPD_REG_BASE + 0x68)
4054 +# define DIS_MMC2_DPLL_REQ (1 << 11)
4055 +# define DIS_MMC1_DPLL_REQ (1 << 10)
4056 +# define DIS_UART3_DPLL_REQ (1 << 9)
4057 +# define DIS_UART2_DPLL_REQ (1 << 8)
4058 +# define DIS_UART1_DPLL_REQ (1 << 7)
4059 +# define DIS_USB_HOST_DPLL_REQ (1 << 6)
4060 +#define ULPD_SDW_CLK_DIV_CTRL_SEL (ULPD_REG_BASE + 0x74)
4061 +#define ULPD_CAM_CLK_CTRL (ULPD_REG_BASE + 0x7c)
4062 +
4063 +/*
4064 + * ---------------------------------------------------------------------------
4065 + * Watchdog timer
4066 + * ---------------------------------------------------------------------------
4067 + */
4068 +
4069 +/* Watchdog timer within the OMAP3.2 gigacell */
4070 +#define OMAP_MPU_WATCHDOG_BASE (0xfffec800)
4071 +#define OMAP_WDT_TIMER (OMAP_MPU_WATCHDOG_BASE + 0x0)
4072 +#define OMAP_WDT_LOAD_TIM (OMAP_MPU_WATCHDOG_BASE + 0x4)
4073 +#define OMAP_WDT_READ_TIM (OMAP_MPU_WATCHDOG_BASE + 0x4)
4074 +#define OMAP_WDT_TIMER_MODE (OMAP_MPU_WATCHDOG_BASE + 0x8)
4075 +
4076 +/*
4077 + * ---------------------------------------------------------------------------
4078 + * Interrupts
4079 + * ---------------------------------------------------------------------------
4080 + */
4081 +#ifdef CONFIG_ARCH_OMAP1
4082 +
4083 +/*
4084 + * XXX: These probably want to be moved to arch/arm/mach-omap/omap1/irq.c
4085 + * or something similar.. -- PFM.
4086 + */
4087 +
4088 +#define OMAP_IH1_BASE 0xfffecb00
4089 +#define OMAP_IH2_BASE 0xfffe0000
4090 +
4091 +#define OMAP_IH1_ITR (OMAP_IH1_BASE + 0x00)
4092 +#define OMAP_IH1_MIR (OMAP_IH1_BASE + 0x04)
4093 +#define OMAP_IH1_SIR_IRQ (OMAP_IH1_BASE + 0x10)
4094 +#define OMAP_IH1_SIR_FIQ (OMAP_IH1_BASE + 0x14)
4095 +#define OMAP_IH1_CONTROL (OMAP_IH1_BASE + 0x18)
4096 +#define OMAP_IH1_ILR0 (OMAP_IH1_BASE + 0x1c)
4097 +#define OMAP_IH1_ISR (OMAP_IH1_BASE + 0x9c)
4098 +
4099 +#define OMAP_IH2_ITR (OMAP_IH2_BASE + 0x00)
4100 +#define OMAP_IH2_MIR (OMAP_IH2_BASE + 0x04)
4101 +#define OMAP_IH2_SIR_IRQ (OMAP_IH2_BASE + 0x10)
4102 +#define OMAP_IH2_SIR_FIQ (OMAP_IH2_BASE + 0x14)
4103 +#define OMAP_IH2_CONTROL (OMAP_IH2_BASE + 0x18)
4104 +#define OMAP_IH2_ILR0 (OMAP_IH2_BASE + 0x1c)
4105 +#define OMAP_IH2_ISR (OMAP_IH2_BASE + 0x9c)
4106 +
4107 +#define IRQ_ITR_REG_OFFSET 0x00
4108 +#define IRQ_MIR_REG_OFFSET 0x04
4109 +#define IRQ_SIR_IRQ_REG_OFFSET 0x10
4110 +#define IRQ_SIR_FIQ_REG_OFFSET 0x14
4111 +#define IRQ_CONTROL_REG_OFFSET 0x18
4112 +#define IRQ_ISR_REG_OFFSET 0x9c
4113 +#define IRQ_ILR0_REG_OFFSET 0x1c
4114 +#define IRQ_GMR_REG_OFFSET 0xa0
4115 +
4116 +#endif
4117 +
4118 +/*
4119 + * ----------------------------------------------------------------------------
4120 + * System control registers
4121 + * ----------------------------------------------------------------------------
4122 + */
4123 +#define MOD_CONF_CTRL_0 0xfffe1080
4124 +#define MOD_CONF_CTRL_1 0xfffe1110
4125 +
4126 +/*
4127 + * ----------------------------------------------------------------------------
4128 + * Pin multiplexing registers
4129 + * ----------------------------------------------------------------------------
4130 + */
4131 +#define FUNC_MUX_CTRL_0 0xfffe1000
4132 +#define FUNC_MUX_CTRL_1 0xfffe1004
4133 +#define FUNC_MUX_CTRL_2 0xfffe1008
4134 +#define COMP_MODE_CTRL_0 0xfffe100c
4135 +#define FUNC_MUX_CTRL_3 0xfffe1010
4136 +#define FUNC_MUX_CTRL_4 0xfffe1014
4137 +#define FUNC_MUX_CTRL_5 0xfffe1018
4138 +#define FUNC_MUX_CTRL_6 0xfffe101C
4139 +#define FUNC_MUX_CTRL_7 0xfffe1020
4140 +#define FUNC_MUX_CTRL_8 0xfffe1024
4141 +#define FUNC_MUX_CTRL_9 0xfffe1028
4142 +#define FUNC_MUX_CTRL_A 0xfffe102C
4143 +#define FUNC_MUX_CTRL_B 0xfffe1030
4144 +#define FUNC_MUX_CTRL_C 0xfffe1034
4145 +#define FUNC_MUX_CTRL_D 0xfffe1038
4146 +#define PULL_DWN_CTRL_0 0xfffe1040
4147 +#define PULL_DWN_CTRL_1 0xfffe1044
4148 +#define PULL_DWN_CTRL_2 0xfffe1048
4149 +#define PULL_DWN_CTRL_3 0xfffe104c
4150 +#define PULL_DWN_CTRL_4 0xfffe10ac
4151 +
4152 +/* OMAP-1610 specific multiplexing registers */
4153 +#define FUNC_MUX_CTRL_E 0xfffe1090
4154 +#define FUNC_MUX_CTRL_F 0xfffe1094
4155 +#define FUNC_MUX_CTRL_10 0xfffe1098
4156 +#define FUNC_MUX_CTRL_11 0xfffe109c
4157 +#define FUNC_MUX_CTRL_12 0xfffe10a0
4158 +#define PU_PD_SEL_0 0xfffe10b4
4159 +#define PU_PD_SEL_1 0xfffe10b8
4160 +#define PU_PD_SEL_2 0xfffe10bc
4161 +#define PU_PD_SEL_3 0xfffe10c0
4162 +#define PU_PD_SEL_4 0xfffe10c4
4163 +
4164 +/* Timer32K for 1610 and 1710*/
4165 +#define OMAP_TIMER32K_BASE 0xFFFBC400
4166 +
4167 +/*
4168 + * ---------------------------------------------------------------------------
4169 + * TIPB bus interface
4170 + * ---------------------------------------------------------------------------
4171 + */
4172 +#define TIPB_PUBLIC_CNTL_BASE 0xfffed300
4173 +#define MPU_PUBLIC_TIPB_CNTL (TIPB_PUBLIC_CNTL_BASE + 0x8)
4174 +#define TIPB_PRIVATE_CNTL_BASE 0xfffeca00
4175 +#define MPU_PRIVATE_TIPB_CNTL (TIPB_PRIVATE_CNTL_BASE + 0x8)
4176 +
4177 +/*
4178 + * ----------------------------------------------------------------------------
4179 + * MPUI interface
4180 + * ----------------------------------------------------------------------------
4181 + */
4182 +#define MPUI_BASE (0xfffec900)
4183 +#define MPUI_CTRL (MPUI_BASE + 0x0)
4184 +#define MPUI_DEBUG_ADDR (MPUI_BASE + 0x4)
4185 +#define MPUI_DEBUG_DATA (MPUI_BASE + 0x8)
4186 +#define MPUI_DEBUG_FLAG (MPUI_BASE + 0xc)
4187 +#define MPUI_STATUS_REG (MPUI_BASE + 0x10)
4188 +#define MPUI_DSP_STATUS (MPUI_BASE + 0x14)
4189 +#define MPUI_DSP_BOOT_CONFIG (MPUI_BASE + 0x18)
4190 +#define MPUI_DSP_API_CONFIG (MPUI_BASE + 0x1c)
4191 +
4192 +/*
4193 + * ----------------------------------------------------------------------------
4194 + * LED Pulse Generator
4195 + * ----------------------------------------------------------------------------
4196 + */
4197 +#define OMAP_LPG1_BASE 0xfffbd000
4198 +#define OMAP_LPG2_BASE 0xfffbd800
4199 +#define OMAP_LPG1_LCR (OMAP_LPG1_BASE + 0x00)
4200 +#define OMAP_LPG1_PMR (OMAP_LPG1_BASE + 0x04)
4201 +#define OMAP_LPG2_LCR (OMAP_LPG2_BASE + 0x00)
4202 +#define OMAP_LPG2_PMR (OMAP_LPG2_BASE + 0x04)
4203 +
4204 +/*
4205 + * ----------------------------------------------------------------------------
4206 + * Pulse-Width Light
4207 + * ----------------------------------------------------------------------------
4208 + */
4209 +#define OMAP_PWL_BASE 0xfffb5800
4210 +#define OMAP_PWL_ENABLE (OMAP_PWL_BASE + 0x00)
4211 +#define OMAP_PWL_CLK_ENABLE (OMAP_PWL_BASE + 0x04)
4212 +
4213 +/*
4214 + * ---------------------------------------------------------------------------
4215 + * Processor specific defines
4216 + * ---------------------------------------------------------------------------
4217 + */
4218 +
4219 +#include <plat/omap7xx.h>
4220 +#include <plat/omap1510.h>
4221 +#include <plat/omap16xx.h>
4222 +#include <plat/omap24xx.h>
4223 +#include <plat/omap34xx.h>
4224 +#include <plat/omap44xx.h>
4225 +
4226 +#endif /* __ASM_ARCH_OMAP_HARDWARE_H */
4227 Index: linux-2.6.37-rc1/arch/arm/plat-omap/include/mach/hwa742.h
4228 ===================================================================
4229 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
4230 +++ linux-2.6.37-rc1/arch/arm/plat-omap/include/mach/hwa742.h 2010-11-05 17:36:26.174000001 +0100
4231 @@ -0,0 +1,8 @@
4232 +#ifndef _HWA742_H
4233 +#define _HWA742_H
4234 +
4235 +struct hwa742_platform_data {
4236 + unsigned te_connected:1;
4237 +};
4238 +
4239 +#endif
4240 Index: linux-2.6.37-rc1/arch/arm/plat-omap/include/mach/i2c.h
4241 ===================================================================
4242 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
4243 +++ linux-2.6.37-rc1/arch/arm/plat-omap/include/mach/i2c.h 2010-11-05 17:36:26.174000001 +0100
4244 @@ -0,0 +1,39 @@
4245 +/*
4246 + * Helper module for board specific I2C bus registration
4247 + *
4248 + * Copyright (C) 2009 Nokia Corporation.
4249 + *
4250 + * This program is free software; you can redistribute it and/or
4251 + * modify it under the terms of the GNU General Public License
4252 + * version 2 as published by the Free Software Foundation.
4253 + *
4254 + * This program is distributed in the hope that it will be useful, but
4255 + * WITHOUT ANY WARRANTY; without even the implied warranty of
4256 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
4257 + * General Public License for more details.
4258 + *
4259 + * You should have received a copy of the GNU General Public License
4260 + * along with this program; if not, write to the Free Software
4261 + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
4262 + * 02110-1301 USA
4263 + *
4264 + */
4265 +
4266 +#include <linux/i2c.h>
4267 +
4268 +#if defined(CONFIG_I2C_OMAP) || defined(CONFIG_I2C_OMAP_MODULE)
4269 +extern int omap_register_i2c_bus(int bus_id, u32 clkrate,
4270 + struct i2c_board_info const *info,
4271 + unsigned len);
4272 +#else
4273 +static inline int omap_register_i2c_bus(int bus_id, u32 clkrate,
4274 + struct i2c_board_info const *info,
4275 + unsigned len)
4276 +{
4277 + return 0;
4278 +}
4279 +#endif
4280 +
4281 +int omap_plat_register_i2c_bus(int bus_id, u32 clkrate,
4282 + struct i2c_board_info const *info,
4283 + unsigned len);
4284 Index: linux-2.6.37-rc1/arch/arm/plat-omap/include/mach/io.h
4285 ===================================================================
4286 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
4287 +++ linux-2.6.37-rc1/arch/arm/plat-omap/include/mach/io.h 2010-11-05 17:36:26.174000001 +0100
4288 @@ -0,0 +1,287 @@
4289 +/*
4290 + * arch/arm/plat-omap/include/mach/io.h
4291 + *
4292 + * IO definitions for TI OMAP processors and boards
4293 + *
4294 + * Copied from arch/arm/mach-sa1100/include/mach/io.h
4295 + * Copyright (C) 1997-1999 Russell King
4296 + *
4297 + * Copyright (C) 2009 Texas Instruments
4298 + * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
4299 + *
4300 + * This program is free software; you can redistribute it and/or modify it
4301 + * under the terms of the GNU General Public License as published by the
4302 + * Free Software Foundation; either version 2 of the License, or (at your
4303 + * option) any later version.
4304 + *
4305 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
4306 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
4307 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
4308 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
4309 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
4310 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
4311 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
4312 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
4313 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
4314 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
4315 + *
4316 + * You should have received a copy of the GNU General Public License along
4317 + * with this program; if not, write to the Free Software Foundation, Inc.,
4318 + * 675 Mass Ave, Cambridge, MA 02139, USA.
4319 + *
4320 + * Modifications:
4321 + * 06-12-1997 RMK Created.
4322 + * 07-04-1999 RMK Major cleanup
4323 + */
4324 +
4325 +#ifndef __ASM_ARM_ARCH_IO_H
4326 +#define __ASM_ARM_ARCH_IO_H
4327 +
4328 +#include <mach/hardware.h>
4329 +
4330 +#define IO_SPACE_LIMIT 0xffffffff
4331 +
4332 +/*
4333 + * We don't actually have real ISA nor PCI buses, but there is so many
4334 + * drivers out there that might just work if we fake them...
4335 + */
4336 +#define __io(a) __typesafe_io(a)
4337 +#define __mem_pci(a) (a)
4338 +
4339 +/*
4340 + * ----------------------------------------------------------------------------
4341 + * I/O mapping
4342 + * ----------------------------------------------------------------------------
4343 + */
4344 +
4345 +#ifdef __ASSEMBLER__
4346 +#define IOMEM(x) (x)
4347 +#else
4348 +#define IOMEM(x) ((void __force __iomem *)(x))
4349 +#endif
4350 +
4351 +#define OMAP1_IO_OFFSET 0x01000000 /* Virtual IO = 0xfefb0000 */
4352 +#define OMAP1_IO_ADDRESS(pa) IOMEM((pa) - OMAP1_IO_OFFSET)
4353 +
4354 +#define OMAP2_L3_IO_OFFSET 0x90000000
4355 +#define OMAP2_L3_IO_ADDRESS(pa) IOMEM((pa) + OMAP2_L3_IO_OFFSET) /* L3 */
4356 +
4357 +
4358 +#define OMAP2_L4_IO_OFFSET 0xb2000000
4359 +#define OMAP2_L4_IO_ADDRESS(pa) IOMEM((pa) + OMAP2_L4_IO_OFFSET) /* L4 */
4360 +
4361 +#define OMAP4_L3_IO_OFFSET 0xb4000000
4362 +#define OMAP4_L3_IO_ADDRESS(pa) IOMEM((pa) + OMAP4_L3_IO_OFFSET) /* L3 */
4363 +
4364 +#define OMAP4_L3_PER_IO_OFFSET 0xb1100000
4365 +#define OMAP4_L3_PER_IO_ADDRESS(pa) IOMEM((pa) + OMAP4_L3_PER_IO_OFFSET)
4366 +
4367 +#define OMAP4_GPMC_IO_OFFSET 0xa9000000
4368 +#define OMAP4_GPMC_IO_ADDRESS(pa) IOMEM((pa) + OMAP4_GPMC_IO_OFFSET)
4369 +
4370 +#define OMAP2_EMU_IO_OFFSET 0xaa800000 /* Emulation */
4371 +#define OMAP2_EMU_IO_ADDRESS(pa) IOMEM((pa) + OMAP2_EMU_IO_OFFSET)
4372 +
4373 +/*
4374 + * ----------------------------------------------------------------------------
4375 + * Omap1 specific IO mapping
4376 + * ----------------------------------------------------------------------------
4377 + */
4378 +
4379 +#define OMAP1_IO_PHYS 0xFFFB0000
4380 +#define OMAP1_IO_SIZE 0x40000
4381 +#define OMAP1_IO_VIRT (OMAP1_IO_PHYS - OMAP1_IO_OFFSET)
4382 +
4383 +/*
4384 + * ----------------------------------------------------------------------------
4385 + * Omap2 specific IO mapping
4386 + * ----------------------------------------------------------------------------
4387 + */
4388 +
4389 +/* We map both L3 and L4 on OMAP2 */
4390 +#define L3_24XX_PHYS L3_24XX_BASE /* 0x68000000 --> 0xf8000000*/
4391 +#define L3_24XX_VIRT (L3_24XX_PHYS + OMAP2_L3_IO_OFFSET)
4392 +#define L3_24XX_SIZE SZ_1M /* 44kB of 128MB used, want 1MB sect */
4393 +#define L4_24XX_PHYS L4_24XX_BASE /* 0x48000000 --> 0xfa000000 */
4394 +#define L4_24XX_VIRT (L4_24XX_PHYS + OMAP2_L4_IO_OFFSET)
4395 +#define L4_24XX_SIZE SZ_1M /* 1MB of 128MB used, want 1MB sect */
4396 +
4397 +#define L4_WK_243X_PHYS L4_WK_243X_BASE /* 0x49000000 --> 0xfb000000 */
4398 +#define L4_WK_243X_VIRT (L4_WK_243X_PHYS + OMAP2_L4_IO_OFFSET)
4399 +#define L4_WK_243X_SIZE SZ_1M
4400 +#define OMAP243X_GPMC_PHYS OMAP243X_GPMC_BASE
4401 +#define OMAP243X_GPMC_VIRT (OMAP243X_GPMC_PHYS + OMAP2_L3_IO_OFFSET)
4402 + /* 0x6e000000 --> 0xfe000000 */
4403 +#define OMAP243X_GPMC_SIZE SZ_1M
4404 +#define OMAP243X_SDRC_PHYS OMAP243X_SDRC_BASE
4405 + /* 0x6D000000 --> 0xfd000000 */
4406 +#define OMAP243X_SDRC_VIRT (OMAP243X_SDRC_PHYS + OMAP2_L3_IO_OFFSET)
4407 +#define OMAP243X_SDRC_SIZE SZ_1M
4408 +#define OMAP243X_SMS_PHYS OMAP243X_SMS_BASE
4409 + /* 0x6c000000 --> 0xfc000000 */
4410 +#define OMAP243X_SMS_VIRT (OMAP243X_SMS_PHYS + OMAP2_L3_IO_OFFSET)
4411 +#define OMAP243X_SMS_SIZE SZ_1M
4412 +
4413 +/* DSP */
4414 +#define DSP_MEM_24XX_PHYS OMAP2420_DSP_MEM_BASE /* 0x58000000 */
4415 +#define DSP_MEM_24XX_VIRT 0xe0000000
4416 +#define DSP_MEM_24XX_SIZE 0x28000
4417 +#define DSP_IPI_24XX_PHYS OMAP2420_DSP_IPI_BASE /* 0x59000000 */
4418 +#define DSP_IPI_24XX_VIRT 0xe1000000
4419 +#define DSP_IPI_24XX_SIZE SZ_4K
4420 +#define DSP_MMU_24XX_PHYS OMAP2420_DSP_MMU_BASE /* 0x5a000000 */
4421 +#define DSP_MMU_24XX_VIRT 0xe2000000
4422 +#define DSP_MMU_24XX_SIZE SZ_4K
4423 +
4424 +/*
4425 + * ----------------------------------------------------------------------------
4426 + * Omap3 specific IO mapping
4427 + * ----------------------------------------------------------------------------
4428 + */
4429 +
4430 +/* We map both L3 and L4 on OMAP3 */
4431 +#define L3_34XX_PHYS L3_34XX_BASE /* 0x68000000 --> 0xf8000000 */
4432 +#define L3_34XX_VIRT (L3_34XX_PHYS + OMAP2_L3_IO_OFFSET)
4433 +#define L3_34XX_SIZE SZ_1M /* 44kB of 128MB used, want 1MB sect */
4434 +
4435 +#define L4_34XX_PHYS L4_34XX_BASE /* 0x48000000 --> 0xfa000000 */
4436 +#define L4_34XX_VIRT (L4_34XX_PHYS + OMAP2_L4_IO_OFFSET)
4437 +#define L4_34XX_SIZE SZ_4M /* 1MB of 128MB used, want 1MB sect */
4438 +
4439 +/*
4440 + * Need to look at the Size 4M for L4.
4441 + * VPOM3430 was not working for Int controller
4442 + */
4443 +
4444 +#define L4_WK_34XX_PHYS L4_WK_34XX_BASE /* 0x48300000 --> 0xfa300000 */
4445 +#define L4_WK_34XX_VIRT (L4_WK_34XX_PHYS + OMAP2_L4_IO_OFFSET)
4446 +#define L4_WK_34XX_SIZE SZ_1M
4447 +
4448 +#define L4_PER_34XX_PHYS L4_PER_34XX_BASE
4449 + /* 0x49000000 --> 0xfb000000 */
4450 +#define L4_PER_34XX_VIRT (L4_PER_34XX_PHYS + OMAP2_L4_IO_OFFSET)
4451 +#define L4_PER_34XX_SIZE SZ_1M
4452 +
4453 +#define L4_EMU_34XX_PHYS L4_EMU_34XX_BASE
4454 + /* 0x54000000 --> 0xfe800000 */
4455 +#define L4_EMU_34XX_VIRT (L4_EMU_34XX_PHYS + OMAP2_EMU_IO_OFFSET)
4456 +#define L4_EMU_34XX_SIZE SZ_8M
4457 +
4458 +#define OMAP34XX_GPMC_PHYS OMAP34XX_GPMC_BASE
4459 + /* 0x6e000000 --> 0xfe000000 */
4460 +#define OMAP34XX_GPMC_VIRT (OMAP34XX_GPMC_PHYS + OMAP2_L3_IO_OFFSET)
4461 +#define OMAP34XX_GPMC_SIZE SZ_1M
4462 +
4463 +#define OMAP343X_SMS_PHYS OMAP343X_SMS_BASE
4464 + /* 0x6c000000 --> 0xfc000000 */
4465 +#define OMAP343X_SMS_VIRT (OMAP343X_SMS_PHYS + OMAP2_L3_IO_OFFSET)
4466 +#define OMAP343X_SMS_SIZE SZ_1M
4467 +
4468 +#define OMAP343X_SDRC_PHYS OMAP343X_SDRC_BASE
4469 + /* 0x6D000000 --> 0xfd000000 */
4470 +#define OMAP343X_SDRC_VIRT (OMAP343X_SDRC_PHYS + OMAP2_L3_IO_OFFSET)
4471 +#define OMAP343X_SDRC_SIZE SZ_1M
4472 +
4473 +/* DSP */
4474 +#define DSP_MEM_34XX_PHYS OMAP34XX_DSP_MEM_BASE /* 0x58000000 */
4475 +#define DSP_MEM_34XX_VIRT 0xe0000000
4476 +#define DSP_MEM_34XX_SIZE 0x28000
4477 +#define DSP_IPI_34XX_PHYS OMAP34XX_DSP_IPI_BASE /* 0x59000000 */
4478 +#define DSP_IPI_34XX_VIRT 0xe1000000
4479 +#define DSP_IPI_34XX_SIZE SZ_4K
4480 +#define DSP_MMU_34XX_PHYS OMAP34XX_DSP_MMU_BASE /* 0x5a000000 */
4481 +#define DSP_MMU_34XX_VIRT 0xe2000000
4482 +#define DSP_MMU_34XX_SIZE SZ_4K
4483 +
4484 +/*
4485 + * ----------------------------------------------------------------------------
4486 + * Omap4 specific IO mapping
4487 + * ----------------------------------------------------------------------------
4488 + */
4489 +
4490 +/* We map both L3 and L4 on OMAP4 */
4491 +#define L3_44XX_PHYS L3_44XX_BASE /* 0x44000000 --> 0xf8000000 */
4492 +#define L3_44XX_VIRT (L3_44XX_PHYS + OMAP4_L3_IO_OFFSET)
4493 +#define L3_44XX_SIZE SZ_1M
4494 +
4495 +#define L4_44XX_PHYS L4_44XX_BASE /* 0x4a000000 --> 0xfc000000 */
4496 +#define L4_44XX_VIRT (L4_44XX_PHYS + OMAP2_L4_IO_OFFSET)
4497 +#define L4_44XX_SIZE SZ_4M
4498 +
4499 +
4500 +#define L4_WK_44XX_PHYS L4_WK_44XX_BASE /* 0x4a300000 --> 0xfc300000 */
4501 +#define L4_WK_44XX_VIRT (L4_WK_44XX_PHYS + OMAP2_L4_IO_OFFSET)
4502 +#define L4_WK_44XX_SIZE SZ_1M
4503 +
4504 +#define L4_PER_44XX_PHYS L4_PER_44XX_BASE
4505 + /* 0x48000000 --> 0xfa000000 */
4506 +#define L4_PER_44XX_VIRT (L4_PER_44XX_PHYS + OMAP2_L4_IO_OFFSET)
4507 +#define L4_PER_44XX_SIZE SZ_4M
4508 +
4509 +#define L4_ABE_44XX_PHYS L4_ABE_44XX_BASE
4510 + /* 0x49000000 --> 0xfb000000 */
4511 +#define L4_ABE_44XX_VIRT (L4_ABE_44XX_PHYS + OMAP2_L4_IO_OFFSET)
4512 +#define L4_ABE_44XX_SIZE SZ_1M
4513 +
4514 +#define L4_EMU_44XX_PHYS L4_EMU_44XX_BASE
4515 + /* 0x54000000 --> 0xfe800000 */
4516 +#define L4_EMU_44XX_VIRT (L4_EMU_44XX_PHYS + OMAP2_EMU_IO_OFFSET)
4517 +#define L4_EMU_44XX_SIZE SZ_8M
4518 +
4519 +#define OMAP44XX_GPMC_PHYS OMAP44XX_GPMC_BASE
4520 + /* 0x50000000 --> 0xf9000000 */
4521 +#define OMAP44XX_GPMC_VIRT (OMAP44XX_GPMC_PHYS + OMAP4_GPMC_IO_OFFSET)
4522 +#define OMAP44XX_GPMC_SIZE SZ_1M
4523 +
4524 +
4525 +#define OMAP44XX_EMIF1_PHYS OMAP44XX_EMIF1_BASE
4526 + /* 0x4c000000 --> 0xfd100000 */
4527 +#define OMAP44XX_EMIF1_VIRT (OMAP44XX_EMIF1_PHYS + OMAP4_L3_PER_IO_OFFSET)
4528 +#define OMAP44XX_EMIF1_SIZE SZ_1M
4529 +
4530 +#define OMAP44XX_EMIF2_PHYS OMAP44XX_EMIF2_BASE
4531 + /* 0x4d000000 --> 0xfd200000 */
4532 +#define OMAP44XX_EMIF2_VIRT (OMAP44XX_EMIF2_PHYS + OMAP4_L3_PER_IO_OFFSET)
4533 +#define OMAP44XX_EMIF2_SIZE SZ_1M
4534 +
4535 +#define OMAP44XX_DMM_PHYS OMAP44XX_DMM_BASE
4536 + /* 0x4e000000 --> 0xfd300000 */
4537 +#define OMAP44XX_DMM_VIRT (OMAP44XX_DMM_PHYS + OMAP4_L3_PER_IO_OFFSET)
4538 +#define OMAP44XX_DMM_SIZE SZ_1M
4539 +/*
4540 + * ----------------------------------------------------------------------------
4541 + * Omap specific register access
4542 + * ----------------------------------------------------------------------------
4543 + */
4544 +
4545 +#ifndef __ASSEMBLER__
4546 +
4547 +/*
4548 + * NOTE: Please use ioremap + __raw_read/write where possible instead of these
4549 + */
4550 +
4551 +extern u8 omap_readb(u32 pa);
4552 +extern u16 omap_readw(u32 pa);
4553 +extern u32 omap_readl(u32 pa);
4554 +extern void omap_writeb(u8 v, u32 pa);
4555 +extern void omap_writew(u16 v, u32 pa);
4556 +extern void omap_writel(u32 v, u32 pa);
4557 +
4558 +struct omap_sdrc_params;
4559 +
4560 +extern void omap1_map_common_io(void);
4561 +extern void omap1_init_common_hw(void);
4562 +
4563 +extern void omap2_map_common_io(void);
4564 +extern void omap2_init_common_hw(struct omap_sdrc_params *sdrc_cs0,
4565 + struct omap_sdrc_params *sdrc_cs1);
4566 +
4567 +#define __arch_ioremap(p,s,t) omap_ioremap(p,s,t)
4568 +#define __arch_iounmap(v) omap_iounmap(v)
4569 +
4570 +void __iomem *omap_ioremap(unsigned long phys, size_t size, unsigned int type);
4571 +void omap_iounmap(volatile void __iomem *addr);
4572 +
4573 +#endif
4574 +
4575 +#endif
4576 Index: linux-2.6.37-rc1/arch/arm/plat-omap/include/mach/iommu2.h
4577 ===================================================================
4578 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
4579 +++ linux-2.6.37-rc1/arch/arm/plat-omap/include/mach/iommu2.h 2010-11-05 17:36:26.174000001 +0100
4580 @@ -0,0 +1,96 @@
4581 +/*
4582 + * omap iommu: omap2 architecture specific definitions
4583 + *
4584 + * Copyright (C) 2008-2009 Nokia Corporation
4585 + *
4586 + * Written by Hiroshi DOYU <Hiroshi.DOYU@nokia.com>
4587 + *
4588 + * This program is free software; you can redistribute it and/or modify
4589 + * it under the terms of the GNU General Public License version 2 as
4590 + * published by the Free Software Foundation.
4591 + */
4592 +
4593 +#ifndef __MACH_IOMMU2_H
4594 +#define __MACH_IOMMU2_H
4595 +
4596 +#include <linux/io.h>
4597 +
4598 +/*
4599 + * MMU Register offsets
4600 + */
4601 +#define MMU_REVISION 0x00
4602 +#define MMU_SYSCONFIG 0x10
4603 +#define MMU_SYSSTATUS 0x14
4604 +#define MMU_IRQSTATUS 0x18
4605 +#define MMU_IRQENABLE 0x1c
4606 +#define MMU_WALKING_ST 0x40
4607 +#define MMU_CNTL 0x44
4608 +#define MMU_FAULT_AD 0x48
4609 +#define MMU_TTB 0x4c
4610 +#define MMU_LOCK 0x50
4611 +#define MMU_LD_TLB 0x54
4612 +#define MMU_CAM 0x58
4613 +#define MMU_RAM 0x5c
4614 +#define MMU_GFLUSH 0x60
4615 +#define MMU_FLUSH_ENTRY 0x64
4616 +#define MMU_READ_CAM 0x68
4617 +#define MMU_READ_RAM 0x6c
4618 +#define MMU_EMU_FAULT_AD 0x70
4619 +
4620 +#define MMU_REG_SIZE 256
4621 +
4622 +/*
4623 + * MMU Register bit definitions
4624 + */
4625 +#define MMU_LOCK_BASE_SHIFT 10
4626 +#define MMU_LOCK_BASE_MASK (0x1f << MMU_LOCK_BASE_SHIFT)
4627 +#define MMU_LOCK_BASE(x) \
4628 + ((x & MMU_LOCK_BASE_MASK) >> MMU_LOCK_BASE_SHIFT)
4629 +
4630 +#define MMU_LOCK_VICT_SHIFT 4
4631 +#define MMU_LOCK_VICT_MASK (0x1f << MMU_LOCK_VICT_SHIFT)
4632 +#define MMU_LOCK_VICT(x) \
4633 + ((x & MMU_LOCK_VICT_MASK) >> MMU_LOCK_VICT_SHIFT)
4634 +
4635 +#define MMU_CAM_VATAG_SHIFT 12
4636 +#define MMU_CAM_VATAG_MASK \
4637 + ((~0UL >> MMU_CAM_VATAG_SHIFT) << MMU_CAM_VATAG_SHIFT)
4638 +#define MMU_CAM_P (1 << 3)
4639 +#define MMU_CAM_V (1 << 2)
4640 +#define MMU_CAM_PGSZ_MASK 3
4641 +#define MMU_CAM_PGSZ_1M (0 << 0)
4642 +#define MMU_CAM_PGSZ_64K (1 << 0)
4643 +#define MMU_CAM_PGSZ_4K (2 << 0)
4644 +#define MMU_CAM_PGSZ_16M (3 << 0)
4645 +
4646 +#define MMU_RAM_PADDR_SHIFT 12
4647 +#define MMU_RAM_PADDR_MASK \
4648 + ((~0UL >> MMU_RAM_PADDR_SHIFT) << MMU_RAM_PADDR_SHIFT)
4649 +#define MMU_RAM_ENDIAN_SHIFT 9
4650 +#define MMU_RAM_ENDIAN_MASK (1 << MMU_RAM_ENDIAN_SHIFT)
4651 +#define MMU_RAM_ENDIAN_BIG (1 << MMU_RAM_ENDIAN_SHIFT)
4652 +#define MMU_RAM_ENDIAN_LITTLE (0 << MMU_RAM_ENDIAN_SHIFT)
4653 +#define MMU_RAM_ELSZ_SHIFT 7
4654 +#define MMU_RAM_ELSZ_MASK (3 << MMU_RAM_ELSZ_SHIFT)
4655 +#define MMU_RAM_ELSZ_8 (0 << MMU_RAM_ELSZ_SHIFT)
4656 +#define MMU_RAM_ELSZ_16 (1 << MMU_RAM_ELSZ_SHIFT)
4657 +#define MMU_RAM_ELSZ_32 (2 << MMU_RAM_ELSZ_SHIFT)
4658 +#define MMU_RAM_ELSZ_NONE (3 << MMU_RAM_ELSZ_SHIFT)
4659 +#define MMU_RAM_MIXED_SHIFT 6
4660 +#define MMU_RAM_MIXED_MASK (1 << MMU_RAM_MIXED_SHIFT)
4661 +#define MMU_RAM_MIXED MMU_RAM_MIXED_MASK
4662 +
4663 +/*
4664 + * register accessors
4665 + */
4666 +static inline u32 iommu_read_reg(struct iommu *obj, size_t offs)
4667 +{
4668 + return __raw_readl(obj->regbase + offs);
4669 +}
4670 +
4671 +static inline void iommu_write_reg(struct iommu *obj, u32 val, size_t offs)
4672 +{
4673 + __raw_writel(val, obj->regbase + offs);
4674 +}
4675 +
4676 +#endif /* __MACH_IOMMU2_H */
4677 Index: linux-2.6.37-rc1/arch/arm/plat-omap/include/mach/iommu.h
4678 ===================================================================
4679 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
4680 +++ linux-2.6.37-rc1/arch/arm/plat-omap/include/mach/iommu.h 2010-11-05 17:36:26.174000001 +0100
4681 @@ -0,0 +1,168 @@
4682 +/*
4683 + * omap iommu: main structures
4684 + *
4685 + * Copyright (C) 2008-2009 Nokia Corporation
4686 + *
4687 + * Written by Hiroshi DOYU <Hiroshi.DOYU@nokia.com>
4688 + *
4689 + * This program is free software; you can redistribute it and/or modify
4690 + * it under the terms of the GNU General Public License version 2 as
4691 + * published by the Free Software Foundation.
4692 + */
4693 +
4694 +#ifndef __MACH_IOMMU_H
4695 +#define __MACH_IOMMU_H
4696 +
4697 +struct iotlb_entry {
4698 + u32 da;
4699 + u32 pa;
4700 + u32 pgsz, prsvd, valid;
4701 + union {
4702 + u16 ap;
4703 + struct {
4704 + u32 endian, elsz, mixed;
4705 + };
4706 + };
4707 +};
4708 +
4709 +struct iommu {
4710 + const char *name;
4711 + struct module *owner;
4712 + struct clk *clk;
4713 + void __iomem *regbase;
4714 + struct device *dev;
4715 +
4716 + unsigned int refcount;
4717 + struct mutex iommu_lock; /* global for this whole object */
4718 +
4719 + /*
4720 + * We don't change iopgd for a situation like pgd for a task,
4721 + * but share it globally for each iommu.
4722 + */
4723 + u32 *iopgd;
4724 + spinlock_t page_table_lock; /* protect iopgd */
4725 +
4726 + int nr_tlb_entries;
4727 +
4728 + struct list_head mmap;
4729 + struct mutex mmap_lock; /* protect mmap */
4730 +
4731 + int (*isr)(struct iommu *obj);
4732 +
4733 + void *ctx; /* iommu context: registres saved area */
4734 +};
4735 +
4736 +struct cr_regs {
4737 + union {
4738 + struct {
4739 + u16 cam_l;
4740 + u16 cam_h;
4741 + };
4742 + u32 cam;
4743 + };
4744 + union {
4745 + struct {
4746 + u16 ram_l;
4747 + u16 ram_h;
4748 + };
4749 + u32 ram;
4750 + };
4751 +};
4752 +
4753 +struct iotlb_lock {
4754 + short base;
4755 + short vict;
4756 +};
4757 +
4758 +/* architecture specific functions */
4759 +struct iommu_functions {
4760 + unsigned long version;
4761 +
4762 + int (*enable)(struct iommu *obj);
4763 + void (*disable)(struct iommu *obj);
4764 + u32 (*fault_isr)(struct iommu *obj, u32 *ra);
4765 +
4766 + void (*tlb_read_cr)(struct iommu *obj, struct cr_regs *cr);
4767 + void (*tlb_load_cr)(struct iommu *obj, struct cr_regs *cr);
4768 +
4769 + struct cr_regs *(*alloc_cr)(struct iommu *obj, struct iotlb_entry *e);
4770 + int (*cr_valid)(struct cr_regs *cr);
4771 + u32 (*cr_to_virt)(struct cr_regs *cr);
4772 + void (*cr_to_e)(struct cr_regs *cr, struct iotlb_entry *e);
4773 + ssize_t (*dump_cr)(struct iommu *obj, struct cr_regs *cr, char *buf);
4774 +
4775 + u32 (*get_pte_attr)(struct iotlb_entry *e);
4776 +
4777 + void (*save_ctx)(struct iommu *obj);
4778 + void (*restore_ctx)(struct iommu *obj);
4779 + ssize_t (*dump_ctx)(struct iommu *obj, char *buf, ssize_t len);
4780 +};
4781 +
4782 +struct iommu_platform_data {
4783 + const char *name;
4784 + const char *clk_name;
4785 + const int nr_tlb_entries;
4786 +};
4787 +
4788 +#if defined(CONFIG_ARCH_OMAP1)
4789 +#error "iommu for this processor not implemented yet"
4790 +#else
4791 +#include <plat/iommu2.h>
4792 +#endif
4793 +
4794 +/*
4795 + * utilities for super page(16MB, 1MB, 64KB and 4KB)
4796 + */
4797 +
4798 +#define iopgsz_max(bytes) \
4799 + (((bytes) >= SZ_16M) ? SZ_16M : \
4800 + ((bytes) >= SZ_1M) ? SZ_1M : \
4801 + ((bytes) >= SZ_64K) ? SZ_64K : \
4802 + ((bytes) >= SZ_4K) ? SZ_4K : 0)
4803 +
4804 +#define bytes_to_iopgsz(bytes) \
4805 + (((bytes) == SZ_16M) ? MMU_CAM_PGSZ_16M : \
4806 + ((bytes) == SZ_1M) ? MMU_CAM_PGSZ_1M : \
4807 + ((bytes) == SZ_64K) ? MMU_CAM_PGSZ_64K : \
4808 + ((bytes) == SZ_4K) ? MMU_CAM_PGSZ_4K : -1)
4809 +
4810 +#define iopgsz_to_bytes(iopgsz) \
4811 + (((iopgsz) == MMU_CAM_PGSZ_16M) ? SZ_16M : \
4812 + ((iopgsz) == MMU_CAM_PGSZ_1M) ? SZ_1M : \
4813 + ((iopgsz) == MMU_CAM_PGSZ_64K) ? SZ_64K : \
4814 + ((iopgsz) == MMU_CAM_PGSZ_4K) ? SZ_4K : 0)
4815 +
4816 +#define iopgsz_ok(bytes) (bytes_to_iopgsz(bytes) >= 0)
4817 +
4818 +/*
4819 + * global functions
4820 + */
4821 +extern u32 iommu_arch_version(void);
4822 +
4823 +extern void iotlb_cr_to_e(struct cr_regs *cr, struct iotlb_entry *e);
4824 +extern u32 iotlb_cr_to_virt(struct cr_regs *cr);
4825 +
4826 +extern int load_iotlb_entry(struct iommu *obj, struct iotlb_entry *e);
4827 +extern void flush_iotlb_page(struct iommu *obj, u32 da);
4828 +extern void flush_iotlb_range(struct iommu *obj, u32 start, u32 end);
4829 +extern void flush_iotlb_all(struct iommu *obj);
4830 +
4831 +extern int iopgtable_store_entry(struct iommu *obj, struct iotlb_entry *e);
4832 +extern size_t iopgtable_clear_entry(struct iommu *obj, u32 iova);
4833 +
4834 +extern struct iommu *iommu_get(const char *name);
4835 +extern void iommu_put(struct iommu *obj);
4836 +
4837 +extern void iommu_save_ctx(struct iommu *obj);
4838 +extern void iommu_restore_ctx(struct iommu *obj);
4839 +
4840 +extern int install_iommu_arch(const struct iommu_functions *ops);
4841 +extern void uninstall_iommu_arch(const struct iommu_functions *ops);
4842 +
4843 +extern int foreach_iommu_device(void *data,
4844 + int (*fn)(struct device *, void *));
4845 +
4846 +extern ssize_t iommu_dump_ctx(struct iommu *obj, char *buf, ssize_t len);
4847 +extern size_t dump_tlb_entries(struct iommu *obj, char *buf, ssize_t len);
4848 +
4849 +#endif /* __MACH_IOMMU_H */
4850 Index: linux-2.6.37-rc1/arch/arm/plat-omap/include/mach/iovmm.h
4851 ===================================================================
4852 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
4853 +++ linux-2.6.37-rc1/arch/arm/plat-omap/include/mach/iovmm.h 2010-11-05 17:36:26.175000001 +0100
4854 @@ -0,0 +1,94 @@
4855 +/*
4856 + * omap iommu: simple virtual address space management
4857 + *
4858 + * Copyright (C) 2008-2009 Nokia Corporation
4859 + *
4860 + * Written by Hiroshi DOYU <Hiroshi.DOYU@nokia.com>
4861 + *
4862 + * This program is free software; you can redistribute it and/or modify
4863 + * it under the terms of the GNU General Public License version 2 as
4864 + * published by the Free Software Foundation.
4865 + */
4866 +
4867 +#ifndef __IOMMU_MMAP_H
4868 +#define __IOMMU_MMAP_H
4869 +
4870 +struct iovm_struct {
4871 + struct iommu *iommu; /* iommu object which this belongs to */
4872 + u32 da_start; /* area definition */
4873 + u32 da_end;
4874 + u32 flags; /* IOVMF_: see below */
4875 + struct list_head list; /* linked in ascending order */
4876 + const struct sg_table *sgt; /* keep 'page' <-> 'da' mapping */
4877 + void *va; /* mpu side mapped address */
4878 +};
4879 +
4880 +/*
4881 + * IOVMF_FLAGS: attribute for iommu virtual memory area(iovma)
4882 + *
4883 + * lower 16 bit is used for h/w and upper 16 bit is for s/w.
4884 + */
4885 +#define IOVMF_SW_SHIFT 16
4886 +#define IOVMF_HW_SIZE (1 << IOVMF_SW_SHIFT)
4887 +#define IOVMF_HW_MASK (IOVMF_HW_SIZE - 1)
4888 +#define IOVMF_SW_MASK (~IOVMF_HW_MASK)UL
4889 +
4890 +/*
4891 + * iovma: h/w flags derived from cam and ram attribute
4892 + */
4893 +#define IOVMF_CAM_MASK (~((1 << 10) - 1))
4894 +#define IOVMF_RAM_MASK (~IOVMF_CAM_MASK)
4895 +
4896 +#define IOVMF_PGSZ_MASK (3 << 0)
4897 +#define IOVMF_PGSZ_1M MMU_CAM_PGSZ_1M
4898 +#define IOVMF_PGSZ_64K MMU_CAM_PGSZ_64K
4899 +#define IOVMF_PGSZ_4K MMU_CAM_PGSZ_4K
4900 +#define IOVMF_PGSZ_16M MMU_CAM_PGSZ_16M
4901 +
4902 +#define IOVMF_ENDIAN_MASK (1 << 9)
4903 +#define IOVMF_ENDIAN_BIG MMU_RAM_ENDIAN_BIG
4904 +#define IOVMF_ENDIAN_LITTLE MMU_RAM_ENDIAN_LITTLE
4905 +
4906 +#define IOVMF_ELSZ_MASK (3 << 7)
4907 +#define IOVMF_ELSZ_8 MMU_RAM_ELSZ_8
4908 +#define IOVMF_ELSZ_16 MMU_RAM_ELSZ_16
4909 +#define IOVMF_ELSZ_32 MMU_RAM_ELSZ_32
4910 +#define IOVMF_ELSZ_NONE MMU_RAM_ELSZ_NONE
4911 +
4912 +#define IOVMF_MIXED_MASK (1 << 6)
4913 +#define IOVMF_MIXED MMU_RAM_MIXED
4914 +
4915 +/*
4916 + * iovma: s/w flags, used for mapping and umapping internally.
4917 + */
4918 +#define IOVMF_MMIO (1 << IOVMF_SW_SHIFT)
4919 +#define IOVMF_ALLOC (2 << IOVMF_SW_SHIFT)
4920 +#define IOVMF_ALLOC_MASK (3 << IOVMF_SW_SHIFT)
4921 +
4922 +/* "superpages" is supported just with physically linear pages */
4923 +#define IOVMF_DISCONT (1 << (2 + IOVMF_SW_SHIFT))
4924 +#define IOVMF_LINEAR (2 << (2 + IOVMF_SW_SHIFT))
4925 +#define IOVMF_LINEAR_MASK (3 << (2 + IOVMF_SW_SHIFT))
4926 +
4927 +#define IOVMF_DA_FIXED (1 << (4 + IOVMF_SW_SHIFT))
4928 +#define IOVMF_DA_ANON (2 << (4 + IOVMF_SW_SHIFT))
4929 +#define IOVMF_DA_MASK (3 << (4 + IOVMF_SW_SHIFT))
4930 +
4931 +
4932 +extern struct iovm_struct *find_iovm_area(struct iommu *obj, u32 da);
4933 +extern u32 iommu_vmap(struct iommu *obj, u32 da,
4934 + const struct sg_table *sgt, u32 flags);
4935 +extern struct sg_table *iommu_vunmap(struct iommu *obj, u32 da);
4936 +extern u32 iommu_vmalloc(struct iommu *obj, u32 da, size_t bytes,
4937 + u32 flags);
4938 +extern void iommu_vfree(struct iommu *obj, const u32 da);
4939 +extern u32 iommu_kmap(struct iommu *obj, u32 da, u32 pa, size_t bytes,
4940 + u32 flags);
4941 +extern void iommu_kunmap(struct iommu *obj, u32 da);
4942 +extern u32 iommu_kmalloc(struct iommu *obj, u32 da, size_t bytes,
4943 + u32 flags);
4944 +extern void iommu_kfree(struct iommu *obj, u32 da);
4945 +
4946 +extern void *da_to_va(struct iommu *obj, u32 da);
4947 +
4948 +#endif /* __IOMMU_MMAP_H */
4949 Index: linux-2.6.37-rc1/arch/arm/plat-omap/include/mach/irda.h
4950 ===================================================================
4951 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
4952 +++ linux-2.6.37-rc1/arch/arm/plat-omap/include/mach/irda.h 2010-11-05 17:36:26.175000001 +0100
4953 @@ -0,0 +1,33 @@
4954 +/*
4955 + * arch/arm/plat-omap/include/mach/irda.h
4956 + *
4957 + * Copyright (C) 2005-2006 Komal Shah <komal_shah802003@yahoo.com>
4958 + *
4959 + * This program is free software; you can redistribute it and/or modify
4960 + * it under the terms of the GNU General Public License version 2 as
4961 + * published by the Free Software Foundation.
4962 + */
4963 +#ifndef ASMARM_ARCH_IRDA_H
4964 +#define ASMARM_ARCH_IRDA_H
4965 +
4966 +/* board specific transceiver capabilities */
4967 +
4968 +#define IR_SEL 1 /* Selects IrDA */
4969 +#define IR_SIRMODE 2
4970 +#define IR_FIRMODE 4
4971 +#define IR_MIRMODE 8
4972 +
4973 +struct omap_irda_config {
4974 + int transceiver_cap;
4975 + int (*transceiver_mode)(struct device *dev, int mode);
4976 + int (*select_irda)(struct device *dev, int state);
4977 + int rx_channel;
4978 + int tx_channel;
4979 + unsigned long dest_start;
4980 + unsigned long src_start;
4981 + int tx_trigger;
4982 + int rx_trigger;
4983 + int mode;
4984 +};
4985 +
4986 +#endif
4987 Index: linux-2.6.37-rc1/arch/arm/plat-omap/include/mach/irqs.h
4988 ===================================================================
4989 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
4990 +++ linux-2.6.37-rc1/arch/arm/plat-omap/include/mach/irqs.h 2010-11-05 17:36:26.175000001 +0100
4991 @@ -0,0 +1,506 @@
4992 +/*
4993 + * arch/arm/plat-omap/include/mach/irqs.h
4994 + *
4995 + * Copyright (C) Greg Lonnon 2001
4996 + * Updated for OMAP-1610 by Tony Lindgren <tony@atomide.com>
4997 + *
4998 + * Copyright (C) 2009 Texas Instruments
4999 + * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
5000 + *
5001 + * This program is free software; you can redistribute it and/or modify
5002 + * it under the terms of the GNU General Public License as published by
5003 + * the Free Software Foundation; either version 2 of the License, or
5004 + * (at your option) any later version.
5005 + *
5006 + * This program is distributed in the hope that it will be useful,
5007 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
5008 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
5009 + * GNU General Public License for more details.
5010 + *
5011 + * You should have received a copy of the GNU General Public License
5012 + * along with this program; if not, write to the Free Software
5013 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
5014 + *
5015 + * NOTE: The interrupt vectors for the OMAP-1509, OMAP-1510, and OMAP-1610
5016 + * are different.
5017 + */
5018 +
5019 +#ifndef __ASM_ARCH_OMAP15XX_IRQS_H
5020 +#define __ASM_ARCH_OMAP15XX_IRQS_H
5021 +
5022 +/*
5023 + * IRQ numbers for interrupt handler 1
5024 + *
5025 + * NOTE: See also the OMAP-1510 and 1610 specific IRQ numbers below
5026 + *
5027 + */
5028 +#define INT_CAMERA 1
5029 +#define INT_FIQ 3
5030 +#define INT_RTDX 6
5031 +#define INT_DSP_MMU_ABORT 7
5032 +#define INT_HOST 8
5033 +#define INT_ABORT 9
5034 +#define INT_BRIDGE_PRIV 13
5035 +#define INT_GPIO_BANK1 14
5036 +#define INT_UART3 15
5037 +#define INT_TIMER3 16
5038 +#define INT_DMA_CH0_6 19
5039 +#define INT_DMA_CH1_7 20
5040 +#define INT_DMA_CH2_8 21
5041 +#define INT_DMA_CH3 22
5042 +#define INT_DMA_CH4 23
5043 +#define INT_DMA_CH5 24
5044 +#define INT_DMA_LCD 25
5045 +#define INT_TIMER1 26
5046 +#define INT_WD_TIMER 27
5047 +#define INT_BRIDGE_PUB 28
5048 +#define INT_TIMER2 30
5049 +#define INT_LCD_CTRL 31
5050 +
5051 +/*
5052 + * OMAP-1510 specific IRQ numbers for interrupt handler 1
5053 + */
5054 +#define INT_1510_IH2_IRQ 0
5055 +#define INT_1510_RES2 2
5056 +#define INT_1510_SPI_TX 4
5057 +#define INT_1510_SPI_RX 5
5058 +#define INT_1510_DSP_MAILBOX1 10
5059 +#define INT_1510_DSP_MAILBOX2 11
5060 +#define INT_1510_RES12 12
5061 +#define INT_1510_LB_MMU 17
5062 +#define INT_1510_RES18 18
5063 +#define INT_1510_LOCAL_BUS 29
5064 +
5065 +/*
5066 + * OMAP-1610 specific IRQ numbers for interrupt handler 1
5067 + */
5068 +#define INT_1610_IH2_IRQ 0
5069 +#define INT_1610_IH2_FIQ 2
5070 +#define INT_1610_McBSP2_TX 4
5071 +#define INT_1610_McBSP2_RX 5
5072 +#define INT_1610_DSP_MAILBOX1 10
5073 +#define INT_1610_DSP_MAILBOX2 11
5074 +#define INT_1610_LCD_LINE 12
5075 +#define INT_1610_GPTIMER1 17
5076 +#define INT_1610_GPTIMER2 18
5077 +#define INT_1610_SSR_FIFO_0 29
5078 +
5079 +/*
5080 + * OMAP-7xx specific IRQ numbers for interrupt handler 1
5081 + */
5082 +#define INT_7XX_IH2_FIQ 0
5083 +#define INT_7XX_IH2_IRQ 1
5084 +#define INT_7XX_USB_NON_ISO 2
5085 +#define INT_7XX_USB_ISO 3
5086 +#define INT_7XX_ICR 4
5087 +#define INT_7XX_EAC 5
5088 +#define INT_7XX_GPIO_BANK1 6
5089 +#define INT_7XX_GPIO_BANK2 7
5090 +#define INT_7XX_GPIO_BANK3 8
5091 +#define INT_7XX_McBSP2TX 10
5092 +#define INT_7XX_McBSP2RX 11
5093 +#define INT_7XX_McBSP2RX_OVF 12
5094 +#define INT_7XX_LCD_LINE 14
5095 +#define INT_7XX_GSM_PROTECT 15
5096 +#define INT_7XX_TIMER3 16
5097 +#define INT_7XX_GPIO_BANK5 17
5098 +#define INT_7XX_GPIO_BANK6 18
5099 +#define INT_7XX_SPGIO_WR 29
5100 +
5101 +/*
5102 + * IRQ numbers for interrupt handler 2
5103 + *
5104 + * NOTE: See also the OMAP-1510 and 1610 specific IRQ numbers below
5105 + */
5106 +#define IH2_BASE 32
5107 +
5108 +#define INT_KEYBOARD (1 + IH2_BASE)
5109 +#define INT_uWireTX (2 + IH2_BASE)
5110 +#define INT_uWireRX (3 + IH2_BASE)
5111 +#define INT_I2C (4 + IH2_BASE)
5112 +#define INT_MPUIO (5 + IH2_BASE)
5113 +#define INT_USB_HHC_1 (6 + IH2_BASE)
5114 +#define INT_McBSP3TX (10 + IH2_BASE)
5115 +#define INT_McBSP3RX (11 + IH2_BASE)
5116 +#define INT_McBSP1TX (12 + IH2_BASE)
5117 +#define INT_McBSP1RX (13 + IH2_BASE)
5118 +#define INT_UART1 (14 + IH2_BASE)
5119 +#define INT_UART2 (15 + IH2_BASE)
5120 +#define INT_BT_MCSI1TX (16 + IH2_BASE)
5121 +#define INT_BT_MCSI1RX (17 + IH2_BASE)
5122 +#define INT_SOSSI_MATCH (19 + IH2_BASE)
5123 +#define INT_USB_W2FC (20 + IH2_BASE)
5124 +#define INT_1WIRE (21 + IH2_BASE)
5125 +#define INT_OS_TIMER (22 + IH2_BASE)
5126 +#define INT_MMC (23 + IH2_BASE)
5127 +#define INT_GAUGE_32K (24 + IH2_BASE)
5128 +#define INT_RTC_TIMER (25 + IH2_BASE)
5129 +#define INT_RTC_ALARM (26 + IH2_BASE)
5130 +#define INT_MEM_STICK (27 + IH2_BASE)
5131 +
5132 +/*
5133 + * OMAP-1510 specific IRQ numbers for interrupt handler 2
5134 + */
5135 +#define INT_1510_DSP_MMU (28 + IH2_BASE)
5136 +#define INT_1510_COM_SPI_RO (31 + IH2_BASE)
5137 +
5138 +/*
5139 + * OMAP-1610 specific IRQ numbers for interrupt handler 2
5140 + */
5141 +#define INT_1610_FAC (0 + IH2_BASE)
5142 +#define INT_1610_USB_HHC_2 (7 + IH2_BASE)
5143 +#define INT_1610_USB_OTG (8 + IH2_BASE)
5144 +#define INT_1610_SoSSI (9 + IH2_BASE)
5145 +#define INT_1610_SoSSI_MATCH (19 + IH2_BASE)
5146 +#define INT_1610_DSP_MMU (28 + IH2_BASE)
5147 +#define INT_1610_McBSP2RX_OF (31 + IH2_BASE)
5148 +#define INT_1610_STI (32 + IH2_BASE)
5149 +#define INT_1610_STI_WAKEUP (33 + IH2_BASE)
5150 +#define INT_1610_GPTIMER3 (34 + IH2_BASE)
5151 +#define INT_1610_GPTIMER4 (35 + IH2_BASE)
5152 +#define INT_1610_GPTIMER5 (36 + IH2_BASE)
5153 +#define INT_1610_GPTIMER6 (37 + IH2_BASE)
5154 +#define INT_1610_GPTIMER7 (38 + IH2_BASE)
5155 +#define INT_1610_GPTIMER8 (39 + IH2_BASE)
5156 +#define INT_1610_GPIO_BANK2 (40 + IH2_BASE)
5157 +#define INT_1610_GPIO_BANK3 (41 + IH2_BASE)
5158 +#define INT_1610_MMC2 (42 + IH2_BASE)
5159 +#define INT_1610_CF (43 + IH2_BASE)
5160 +#define INT_1610_WAKE_UP_REQ (46 + IH2_BASE)
5161 +#define INT_1610_GPIO_BANK4 (48 + IH2_BASE)
5162 +#define INT_1610_SPI (49 + IH2_BASE)
5163 +#define INT_1610_DMA_CH6 (53 + IH2_BASE)
5164 +#define INT_1610_DMA_CH7 (54 + IH2_BASE)
5165 +#define INT_1610_DMA_CH8 (55 + IH2_BASE)
5166 +#define INT_1610_DMA_CH9 (56 + IH2_BASE)
5167 +#define INT_1610_DMA_CH10 (57 + IH2_BASE)
5168 +#define INT_1610_DMA_CH11 (58 + IH2_BASE)
5169 +#define INT_1610_DMA_CH12 (59 + IH2_BASE)
5170 +#define INT_1610_DMA_CH13 (60 + IH2_BASE)
5171 +#define INT_1610_DMA_CH14 (61 + IH2_BASE)
5172 +#define INT_1610_DMA_CH15 (62 + IH2_BASE)
5173 +#define INT_1610_NAND (63 + IH2_BASE)
5174 +#define INT_1610_SHA1MD5 (91 + IH2_BASE)
5175 +
5176 +/*
5177 + * OMAP-7xx specific IRQ numbers for interrupt handler 2
5178 + */
5179 +#define INT_7XX_HW_ERRORS (0 + IH2_BASE)
5180 +#define INT_7XX_NFIQ_PWR_FAIL (1 + IH2_BASE)
5181 +#define INT_7XX_CFCD (2 + IH2_BASE)
5182 +#define INT_7XX_CFIREQ (3 + IH2_BASE)
5183 +#define INT_7XX_I2C (4 + IH2_BASE)
5184 +#define INT_7XX_PCC (5 + IH2_BASE)
5185 +#define INT_7XX_MPU_EXT_NIRQ (6 + IH2_BASE)
5186 +#define INT_7XX_SPI_100K_1 (7 + IH2_BASE)
5187 +#define INT_7XX_SYREN_SPI (8 + IH2_BASE)
5188 +#define INT_7XX_VLYNQ (9 + IH2_BASE)
5189 +#define INT_7XX_GPIO_BANK4 (10 + IH2_BASE)
5190 +#define INT_7XX_McBSP1TX (11 + IH2_BASE)
5191 +#define INT_7XX_McBSP1RX (12 + IH2_BASE)
5192 +#define INT_7XX_McBSP1RX_OF (13 + IH2_BASE)
5193 +#define INT_7XX_UART_MODEM_IRDA_2 (14 + IH2_BASE)
5194 +#define INT_7XX_UART_MODEM_1 (15 + IH2_BASE)
5195 +#define INT_7XX_MCSI (16 + IH2_BASE)
5196 +#define INT_7XX_uWireTX (17 + IH2_BASE)
5197 +#define INT_7XX_uWireRX (18 + IH2_BASE)
5198 +#define INT_7XX_SMC_CD (19 + IH2_BASE)
5199 +#define INT_7XX_SMC_IREQ (20 + IH2_BASE)
5200 +#define INT_7XX_HDQ_1WIRE (21 + IH2_BASE)
5201 +#define INT_7XX_TIMER32K (22 + IH2_BASE)
5202 +#define INT_7XX_MMC_SDIO (23 + IH2_BASE)
5203 +#define INT_7XX_UPLD (24 + IH2_BASE)
5204 +#define INT_7XX_USB_HHC_1 (27 + IH2_BASE)
5205 +#define INT_7XX_USB_HHC_2 (28 + IH2_BASE)
5206 +#define INT_7XX_USB_GENI (29 + IH2_BASE)
5207 +#define INT_7XX_USB_OTG (30 + IH2_BASE)
5208 +#define INT_7XX_CAMERA_IF (31 + IH2_BASE)
5209 +#define INT_7XX_RNG (32 + IH2_BASE)
5210 +#define INT_7XX_DUAL_MODE_TIMER (33 + IH2_BASE)
5211 +#define INT_7XX_DBB_RF_EN (34 + IH2_BASE)
5212 +#define INT_7XX_MPUIO_KEYPAD (35 + IH2_BASE)
5213 +#define INT_7XX_SHA1_MD5 (36 + IH2_BASE)
5214 +#define INT_7XX_SPI_100K_2 (37 + IH2_BASE)
5215 +#define INT_7XX_RNG_IDLE (38 + IH2_BASE)
5216 +#define INT_7XX_MPUIO (39 + IH2_BASE)
5217 +#define INT_7XX_LLPC_LCD_CTRL_CAN_BE_OFF (40 + IH2_BASE)
5218 +#define INT_7XX_LLPC_OE_FALLING (41 + IH2_BASE)
5219 +#define INT_7XX_LLPC_OE_RISING (42 + IH2_BASE)
5220 +#define INT_7XX_LLPC_VSYNC (43 + IH2_BASE)
5221 +#define INT_7XX_WAKE_UP_REQ (46 + IH2_BASE)
5222 +#define INT_7XX_DMA_CH6 (53 + IH2_BASE)
5223 +#define INT_7XX_DMA_CH7 (54 + IH2_BASE)
5224 +#define INT_7XX_DMA_CH8 (55 + IH2_BASE)
5225 +#define INT_7XX_DMA_CH9 (56 + IH2_BASE)
5226 +#define INT_7XX_DMA_CH10 (57 + IH2_BASE)
5227 +#define INT_7XX_DMA_CH11 (58 + IH2_BASE)
5228 +#define INT_7XX_DMA_CH12 (59 + IH2_BASE)
5229 +#define INT_7XX_DMA_CH13 (60 + IH2_BASE)
5230 +#define INT_7XX_DMA_CH14 (61 + IH2_BASE)
5231 +#define INT_7XX_DMA_CH15 (62 + IH2_BASE)
5232 +#define INT_7XX_NAND (63 + IH2_BASE)
5233 +
5234 +#define INT_24XX_SYS_NIRQ 7
5235 +#define INT_24XX_SDMA_IRQ0 12
5236 +#define INT_24XX_SDMA_IRQ1 13
5237 +#define INT_24XX_SDMA_IRQ2 14
5238 +#define INT_24XX_SDMA_IRQ3 15
5239 +#define INT_24XX_CAM_IRQ 24
5240 +#define INT_24XX_DSS_IRQ 25
5241 +#define INT_24XX_MAIL_U0_MPU 26
5242 +#define INT_24XX_DSP_UMA 27
5243 +#define INT_24XX_DSP_MMU 28
5244 +#define INT_24XX_GPIO_BANK1 29
5245 +#define INT_24XX_GPIO_BANK2 30
5246 +#define INT_24XX_GPIO_BANK3 31
5247 +#define INT_24XX_GPIO_BANK4 32
5248 +#define INT_24XX_GPIO_BANK5 33
5249 +#define INT_24XX_MAIL_U3_MPU 34
5250 +#define INT_24XX_GPTIMER1 37
5251 +#define INT_24XX_GPTIMER2 38
5252 +#define INT_24XX_GPTIMER3 39
5253 +#define INT_24XX_GPTIMER4 40
5254 +#define INT_24XX_GPTIMER5 41
5255 +#define INT_24XX_GPTIMER6 42
5256 +#define INT_24XX_GPTIMER7 43
5257 +#define INT_24XX_GPTIMER8 44
5258 +#define INT_24XX_GPTIMER9 45
5259 +#define INT_24XX_GPTIMER10 46
5260 +#define INT_24XX_GPTIMER11 47
5261 +#define INT_24XX_GPTIMER12 48
5262 +#define INT_24XX_SHA1MD5 51
5263 +#define INT_24XX_MCBSP4_IRQ_TX 54
5264 +#define INT_24XX_MCBSP4_IRQ_RX 55
5265 +#define INT_24XX_I2C1_IRQ 56
5266 +#define INT_24XX_I2C2_IRQ 57
5267 +#define INT_24XX_HDQ_IRQ 58
5268 +#define INT_24XX_MCBSP1_IRQ_TX 59
5269 +#define INT_24XX_MCBSP1_IRQ_RX 60
5270 +#define INT_24XX_MCBSP2_IRQ_TX 62
5271 +#define INT_24XX_MCBSP2_IRQ_RX 63
5272 +#define INT_24XX_SPI1_IRQ 65
5273 +#define INT_24XX_SPI2_IRQ 66
5274 +#define INT_24XX_UART1_IRQ 72
5275 +#define INT_24XX_UART2_IRQ 73
5276 +#define INT_24XX_UART3_IRQ 74
5277 +#define INT_24XX_USB_IRQ_GEN 75
5278 +#define INT_24XX_USB_IRQ_NISO 76
5279 +#define INT_24XX_USB_IRQ_ISO 77
5280 +#define INT_24XX_USB_IRQ_HGEN 78
5281 +#define INT_24XX_USB_IRQ_HSOF 79
5282 +#define INT_24XX_USB_IRQ_OTG 80
5283 +#define INT_24XX_MCBSP5_IRQ_TX 81
5284 +#define INT_24XX_MCBSP5_IRQ_RX 82
5285 +#define INT_24XX_MMC_IRQ 83
5286 +#define INT_24XX_MMC2_IRQ 86
5287 +#define INT_24XX_MCBSP3_IRQ_TX 89
5288 +#define INT_24XX_MCBSP3_IRQ_RX 90
5289 +#define INT_24XX_SPI3_IRQ 91
5290 +
5291 +#define INT_243X_MCBSP2_IRQ 16
5292 +#define INT_243X_MCBSP3_IRQ 17
5293 +#define INT_243X_MCBSP4_IRQ 18
5294 +#define INT_243X_MCBSP5_IRQ 19
5295 +#define INT_243X_MCBSP1_IRQ 64
5296 +#define INT_243X_HS_USB_MC 92
5297 +#define INT_243X_HS_USB_DMA 93
5298 +#define INT_243X_CARKIT_IRQ 94
5299 +
5300 +#define INT_34XX_BENCH_MPU_EMUL 3
5301 +#define INT_34XX_ST_MCBSP2_IRQ 4
5302 +#define INT_34XX_ST_MCBSP3_IRQ 5
5303 +#define INT_34XX_SSM_ABORT_IRQ 6
5304 +#define INT_34XX_SYS_NIRQ 7
5305 +#define INT_34XX_D2D_FW_IRQ 8
5306 +#define INT_34XX_PRCM_MPU_IRQ 11
5307 +#define INT_34XX_MCBSP1_IRQ 16
5308 +#define INT_34XX_MCBSP2_IRQ 17
5309 +#define INT_34XX_MCBSP3_IRQ 22
5310 +#define INT_34XX_MCBSP4_IRQ 23
5311 +#define INT_34XX_CAM_IRQ 24
5312 +#define INT_34XX_MCBSP5_IRQ 27
5313 +#define INT_34XX_GPIO_BANK1 29
5314 +#define INT_34XX_GPIO_BANK2 30
5315 +#define INT_34XX_GPIO_BANK3 31
5316 +#define INT_34XX_GPIO_BANK4 32
5317 +#define INT_34XX_GPIO_BANK5 33
5318 +#define INT_34XX_GPIO_BANK6 34
5319 +#define INT_34XX_USIM_IRQ 35
5320 +#define INT_34XX_WDT3_IRQ 36
5321 +#define INT_34XX_SPI4_IRQ 48
5322 +#define INT_34XX_SHA1MD52_IRQ 49
5323 +#define INT_34XX_FPKA_READY_IRQ 50
5324 +#define INT_34XX_SHA1MD51_IRQ 51
5325 +#define INT_34XX_RNG_IRQ 52
5326 +#define INT_34XX_I2C3_IRQ 61
5327 +#define INT_34XX_FPKA_ERROR_IRQ 64
5328 +#define INT_34XX_PBIAS_IRQ 75
5329 +#define INT_34XX_OHCI_IRQ 76
5330 +#define INT_34XX_EHCI_IRQ 77
5331 +#define INT_34XX_TLL_IRQ 78
5332 +#define INT_34XX_PARTHASH_IRQ 79
5333 +#define INT_34XX_MMC3_IRQ 94
5334 +#define INT_34XX_GPT12_IRQ 95
5335 +
5336 +#define INT_34XX_BENCH_MPU_EMUL 3
5337 +
5338 +
5339 +#define IRQ_GIC_START 32
5340 +#define INT_44XX_LOCALTIMER_IRQ 29
5341 +#define INT_44XX_LOCALWDT_IRQ 30
5342 +
5343 +#define INT_44XX_BENCH_MPU_EMUL (3 + IRQ_GIC_START)
5344 +#define INT_44XX_SSM_ABORT_IRQ (6 + IRQ_GIC_START)
5345 +#define INT_44XX_SYS_NIRQ (7 + IRQ_GIC_START)
5346 +#define INT_44XX_D2D_FW_IRQ (8 + IRQ_GIC_START)
5347 +#define INT_44XX_PRCM_MPU_IRQ (11 + IRQ_GIC_START)
5348 +#define INT_44XX_SDMA_IRQ0 (12 + IRQ_GIC_START)
5349 +#define INT_44XX_SDMA_IRQ1 (13 + IRQ_GIC_START)
5350 +#define INT_44XX_SDMA_IRQ2 (14 + IRQ_GIC_START)
5351 +#define INT_44XX_SDMA_IRQ3 (15 + IRQ_GIC_START)
5352 +#define INT_44XX_ISS_IRQ (24 + IRQ_GIC_START)
5353 +#define INT_44XX_DSS_IRQ (25 + IRQ_GIC_START)
5354 +#define INT_44XX_MAIL_U0_MPU (26 + IRQ_GIC_START)
5355 +#define INT_44XX_DSP_MMU (28 + IRQ_GIC_START)
5356 +#define INT_44XX_GPTIMER1 (37 + IRQ_GIC_START)
5357 +#define INT_44XX_GPTIMER2 (38 + IRQ_GIC_START)
5358 +#define INT_44XX_GPTIMER3 (39 + IRQ_GIC_START)
5359 +#define INT_44XX_GPTIMER4 (40 + IRQ_GIC_START)
5360 +#define INT_44XX_GPTIMER5 (41 + IRQ_GIC_START)
5361 +#define INT_44XX_GPTIMER6 (42 + IRQ_GIC_START)
5362 +#define INT_44XX_GPTIMER7 (43 + IRQ_GIC_START)
5363 +#define INT_44XX_GPTIMER8 (44 + IRQ_GIC_START)
5364 +#define INT_44XX_GPTIMER9 (45 + IRQ_GIC_START)
5365 +#define INT_44XX_GPTIMER10 (46 + IRQ_GIC_START)
5366 +#define INT_44XX_GPTIMER11 (47 + IRQ_GIC_START)
5367 +#define INT_44XX_GPTIMER12 (95 + IRQ_GIC_START)
5368 +#define INT_44XX_SHA1MD5 (51 + IRQ_GIC_START)
5369 +#define INT_44XX_I2C1_IRQ (56 + IRQ_GIC_START)
5370 +#define INT_44XX_I2C2_IRQ (57 + IRQ_GIC_START)
5371 +#define INT_44XX_HDQ_IRQ (58 + IRQ_GIC_START)
5372 +#define INT_44XX_SPI1_IRQ (65 + IRQ_GIC_START)
5373 +#define INT_44XX_SPI2_IRQ (66 + IRQ_GIC_START)
5374 +#define INT_44XX_HSI_1_IRQ0 (67 + IRQ_GIC_START)
5375 +#define INT_44XX_HSI_2_IRQ1 (68 + IRQ_GIC_START)
5376 +#define INT_44XX_HSI_1_DMAIRQ (71 + IRQ_GIC_START)
5377 +#define INT_44XX_UART1_IRQ (72 + IRQ_GIC_START)
5378 +#define INT_44XX_UART2_IRQ (73 + IRQ_GIC_START)
5379 +#define INT_44XX_UART3_IRQ (74 + IRQ_GIC_START)
5380 +#define INT_44XX_UART4_IRQ (70 + IRQ_GIC_START)
5381 +#define INT_44XX_USB_IRQ_NISO (76 + IRQ_GIC_START)
5382 +#define INT_44XX_USB_IRQ_ISO (77 + IRQ_GIC_START)
5383 +#define INT_44XX_USB_IRQ_HGEN (78 + IRQ_GIC_START)
5384 +#define INT_44XX_USB_IRQ_HSOF (79 + IRQ_GIC_START)
5385 +#define INT_44XX_USB_IRQ_OTG (80 + IRQ_GIC_START)
5386 +#define INT_44XX_MCBSP4_IRQ_TX (81 + IRQ_GIC_START)
5387 +#define INT_44XX_MCBSP4_IRQ_RX (82 + IRQ_GIC_START)
5388 +#define INT_44XX_MMC_IRQ (83 + IRQ_GIC_START)
5389 +#define INT_44XX_MMC2_IRQ (86 + IRQ_GIC_START)
5390 +#define INT_44XX_MCBSP2_IRQ_TX (89 + IRQ_GIC_START)
5391 +#define INT_44XX_MCBSP2_IRQ_RX (90 + IRQ_GIC_START)
5392 +#define INT_44XX_SPI3_IRQ (91 + IRQ_GIC_START)
5393 +#define INT_44XX_SPI5_IRQ (69 + IRQ_GIC_START)
5394 +
5395 +#define INT_44XX_MCBSP5_IRQ (16 + IRQ_GIC_START)
5396 +#define INT_44xX_MCBSP1_IRQ (17 + IRQ_GIC_START)
5397 +#define INT_44XX_MCBSP2_IRQ (22 + IRQ_GIC_START)
5398 +#define INT_44XX_MCBSP3_IRQ (23 + IRQ_GIC_START)
5399 +#define INT_44XX_MCBSP4_IRQ (27 + IRQ_GIC_START)
5400 +#define INT_44XX_HS_USB_MC (92 + IRQ_GIC_START)
5401 +#define INT_44XX_HS_USB_DMA (93 + IRQ_GIC_START)
5402 +
5403 +#define INT_44XX_GPIO_BANK1 (29 + IRQ_GIC_START)
5404 +#define INT_44XX_GPIO_BANK2 (30 + IRQ_GIC_START)
5405 +#define INT_44XX_GPIO_BANK3 (31 + IRQ_GIC_START)
5406 +#define INT_44XX_GPIO_BANK4 (32 + IRQ_GIC_START)
5407 +#define INT_44XX_GPIO_BANK5 (33 + IRQ_GIC_START)
5408 +#define INT_44XX_GPIO_BANK6 (34 + IRQ_GIC_START)
5409 +#define INT_44XX_USIM_IRQ (35 + IRQ_GIC_START)
5410 +#define INT_44XX_WDT3_IRQ (36 + IRQ_GIC_START)
5411 +#define INT_44XX_SPI4_IRQ (48 + IRQ_GIC_START)
5412 +#define INT_44XX_SHA1MD52_IRQ (49 + IRQ_GIC_START)
5413 +#define INT_44XX_FPKA_READY_IRQ (50 + IRQ_GIC_START)
5414 +#define INT_44XX_SHA1MD51_IRQ (51 + IRQ_GIC_START)
5415 +#define INT_44XX_RNG_IRQ (52 + IRQ_GIC_START)
5416 +#define INT_44XX_MMC5_IRQ (59 + IRQ_GIC_START)
5417 +#define INT_44XX_I2C3_IRQ (61 + IRQ_GIC_START)
5418 +#define INT_44XX_FPKA_ERROR_IRQ (64 + IRQ_GIC_START)
5419 +#define INT_44XX_PBIAS_IRQ (75 + IRQ_GIC_START)
5420 +#define INT_44XX_OHCI_IRQ (76 + IRQ_GIC_START)
5421 +#define INT_44XX_EHCI_IRQ (77 + IRQ_GIC_START)
5422 +#define INT_44XX_TLL_IRQ (78 + IRQ_GIC_START)
5423 +#define INT_44XX_PARTHASH_IRQ (79 + IRQ_GIC_START)
5424 +#define INT_44XX_MMC3_IRQ (94 + IRQ_GIC_START)
5425 +#define INT_44XX_MMC4_IRQ (96 + IRQ_GIC_START)
5426 +
5427 +
5428 +/* Max. 128 level 2 IRQs (OMAP1610), 192 GPIOs (OMAP730/850) and
5429 + * 16 MPUIO lines */
5430 +#define OMAP_MAX_GPIO_LINES 192
5431 +#define IH_GPIO_BASE (128 + IH2_BASE)
5432 +#define IH_MPUIO_BASE (OMAP_MAX_GPIO_LINES + IH_GPIO_BASE)
5433 +#define OMAP_IRQ_END (IH_MPUIO_BASE + 16)
5434 +
5435 +/* External FPGA handles interrupts on Innovator boards */
5436 +#define OMAP_FPGA_IRQ_BASE (OMAP_IRQ_END)
5437 +#ifdef CONFIG_MACH_OMAP_INNOVATOR
5438 +#define OMAP_FPGA_NR_IRQS 24
5439 +#else
5440 +#define OMAP_FPGA_NR_IRQS 0
5441 +#endif
5442 +#define OMAP_FPGA_IRQ_END (OMAP_FPGA_IRQ_BASE + OMAP_FPGA_NR_IRQS)
5443 +
5444 +/* External TWL4030 can handle interrupts on 2430 and 34xx boards */
5445 +#define TWL4030_IRQ_BASE (OMAP_FPGA_IRQ_END)
5446 +#ifdef CONFIG_TWL4030_CORE
5447 +#define TWL4030_BASE_NR_IRQS 8
5448 +#define TWL4030_PWR_NR_IRQS 8
5449 +#else
5450 +#define TWL4030_BASE_NR_IRQS 0
5451 +#define TWL4030_PWR_NR_IRQS 0
5452 +#endif
5453 +#define TWL4030_IRQ_END (TWL4030_IRQ_BASE + TWL4030_BASE_NR_IRQS)
5454 +#define TWL4030_PWR_IRQ_BASE TWL4030_IRQ_END
5455 +#define TWL4030_PWR_IRQ_END (TWL4030_PWR_IRQ_BASE + TWL4030_PWR_NR_IRQS)
5456 +
5457 +/* External TWL4030 gpio interrupts are optional */
5458 +#define TWL4030_GPIO_IRQ_BASE TWL4030_PWR_IRQ_END
5459 +#ifdef CONFIG_GPIO_TWL4030
5460 +#define TWL4030_GPIO_NR_IRQS 18
5461 +#else
5462 +#define TWL4030_GPIO_NR_IRQS 0
5463 +#endif
5464 +#define TWL4030_GPIO_IRQ_END (TWL4030_GPIO_IRQ_BASE + TWL4030_GPIO_NR_IRQS)
5465 +
5466 +#define TWL6030_IRQ_BASE (OMAP_FPGA_IRQ_END)
5467 +#ifdef CONFIG_TWL4030_CORE
5468 +#define TWL6030_BASE_NR_IRQS 20
5469 +#else
5470 +#define TWL6030_BASE_NR_IRQS 0
5471 +#endif
5472 +#define TWL6030_IRQ_END (TWL6030_IRQ_BASE + TWL6030_BASE_NR_IRQS)
5473 +
5474 +/* Total number of interrupts depends on the enabled blocks above */
5475 +#if (TWL4030_GPIO_IRQ_END > TWL6030_IRQ_END)
5476 +#define TWL_IRQ_END TWL4030_GPIO_IRQ_END
5477 +#else
5478 +#define TWL_IRQ_END TWL6030_IRQ_END
5479 +#endif
5480 +
5481 +#define NR_IRQS TWL_IRQ_END
5482 +
5483 +#define OMAP_IRQ_BIT(irq) (1 << ((irq) % 32))
5484 +
5485 +#define INTCPS_NR_MIR_REGS 3
5486 +#define INTCPS_NR_IRQS 96
5487 +
5488 +#ifndef __ASSEMBLY__
5489 +extern void omap_init_irq(void);
5490 +extern int omap_irq_pending(void);
5491 +void omap_intc_save_context(void);
5492 +void omap_intc_restore_context(void);
5493 +#endif
5494 +
5495 +#include <mach/hardware.h>
5496 +
5497 +#endif
5498 Index: linux-2.6.37-rc1/arch/arm/plat-omap/include/mach/keypad.h
5499 ===================================================================
5500 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
5501 +++ linux-2.6.37-rc1/arch/arm/plat-omap/include/mach/keypad.h 2010-11-05 17:36:26.175000001 +0100
5502 @@ -0,0 +1,45 @@
5503 +/*
5504 + * arch/arm/plat-omap/include/mach/keypad.h
5505 + *
5506 + * Copyright (C) 2006 Komal Shah <komal_shah802003@yahoo.com>
5507 + *
5508 + * This program is free software; you can redistribute it and/or modify
5509 + * it under the terms of the GNU General Public License version 2 as
5510 + * published by the Free Software Foundation.
5511 + */
5512 +#ifndef ASMARM_ARCH_KEYPAD_H
5513 +#define ASMARM_ARCH_KEYPAD_H
5514 +
5515 +#warning: Please update the board to use matrix_keypad.h instead
5516 +
5517 +struct omap_kp_platform_data {
5518 + int rows;
5519 + int cols;
5520 + int *keymap;
5521 + unsigned int keymapsize;
5522 + unsigned int rep:1;
5523 + unsigned long delay;
5524 + unsigned int dbounce:1;
5525 + /* specific to OMAP242x*/
5526 + unsigned int *row_gpios;
5527 + unsigned int *col_gpios;
5528 +};
5529 +
5530 +/* Group (0..3) -- when multiple keys are pressed, only the
5531 + * keys pressed in the same group are considered as pressed. This is
5532 + * in order to workaround certain crappy HW designs that produce ghost
5533 + * keypresses. */
5534 +#define GROUP_0 (0 << 16)
5535 +#define GROUP_1 (1 << 16)
5536 +#define GROUP_2 (2 << 16)
5537 +#define GROUP_3 (3 << 16)
5538 +#define GROUP_MASK GROUP_3
5539 +
5540 +#define KEY_PERSISTENT 0x00800000
5541 +#define KEYNUM_MASK 0x00EFFFFF
5542 +#define KEY(col, row, val) (((col) << 28) | ((row) << 24) | (val))
5543 +#define PERSISTENT_KEY(col, row) (((col) << 28) | ((row) << 24) | \
5544 + KEY_PERSISTENT)
5545 +
5546 +#endif
5547 +
5548 Index: linux-2.6.37-rc1/arch/arm/plat-omap/include/mach/lcd_mipid.h
5549 ===================================================================
5550 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
5551 +++ linux-2.6.37-rc1/arch/arm/plat-omap/include/mach/lcd_mipid.h 2010-11-05 17:36:26.175000001 +0100
5552 @@ -0,0 +1,29 @@
5553 +#ifndef __LCD_MIPID_H
5554 +#define __LCD_MIPID_H
5555 +
5556 +enum mipid_test_num {
5557 + MIPID_TEST_RGB_LINES,
5558 +};
5559 +
5560 +enum mipid_test_result {
5561 + MIPID_TEST_SUCCESS,
5562 + MIPID_TEST_INVALID,
5563 + MIPID_TEST_FAILED,
5564 +};
5565 +
5566 +#ifdef __KERNEL__
5567 +
5568 +struct mipid_platform_data {
5569 + int nreset_gpio;
5570 + int data_lines;
5571 +
5572 + void (*shutdown)(struct mipid_platform_data *pdata);
5573 + void (*set_bklight_level)(struct mipid_platform_data *pdata,
5574 + int level);
5575 + int (*get_bklight_level)(struct mipid_platform_data *pdata);
5576 + int (*get_bklight_max)(struct mipid_platform_data *pdata);
5577 +};
5578 +
5579 +#endif
5580 +
5581 +#endif
5582 Index: linux-2.6.37-rc1/arch/arm/plat-omap/include/mach/led.h
5583 ===================================================================
5584 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
5585 +++ linux-2.6.37-rc1/arch/arm/plat-omap/include/mach/led.h 2010-11-05 17:36:26.175000001 +0100
5586 @@ -0,0 +1,24 @@
5587 +/*
5588 + * arch/arm/plat-omap/include/mach/led.h
5589 + *
5590 + * Copyright (C) 2006 Samsung Electronics
5591 + * Kyungmin Park <kyungmin.park@samsung.com>
5592 + *
5593 + * This program is free software; you can redistribute it and/or modify
5594 + * it under the terms of the GNU General Public License version 2 as
5595 + * published by the Free Software Foundation.
5596 + */
5597 +#ifndef ASMARM_ARCH_LED_H
5598 +#define ASMARM_ARCH_LED_H
5599 +
5600 +struct omap_led_config {
5601 + struct led_classdev cdev;
5602 + s16 gpio;
5603 +};
5604 +
5605 +struct omap_led_platform_data {
5606 + s16 nr_leds;
5607 + struct omap_led_config *leds;
5608 +};
5609 +
5610 +#endif
5611 Index: linux-2.6.37-rc1/arch/arm/plat-omap/include/mach/mailbox.h
5612 ===================================================================
5613 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
5614 +++ linux-2.6.37-rc1/arch/arm/plat-omap/include/mach/mailbox.h 2010-11-05 17:36:26.175000001 +0100
5615 @@ -0,0 +1,111 @@
5616 +/* mailbox.h */
5617 +
5618 +#ifndef MAILBOX_H
5619 +#define MAILBOX_H
5620 +
5621 +#include <linux/wait.h>
5622 +#include <linux/workqueue.h>
5623 +#include <linux/blkdev.h>
5624 +#include <linux/interrupt.h>
5625 +
5626 +typedef u32 mbox_msg_t;
5627 +struct omap_mbox;
5628 +
5629 +typedef int __bitwise omap_mbox_irq_t;
5630 +#define IRQ_TX ((__force omap_mbox_irq_t) 1)
5631 +#define IRQ_RX ((__force omap_mbox_irq_t) 2)
5632 +
5633 +typedef int __bitwise omap_mbox_type_t;
5634 +#define OMAP_MBOX_TYPE1 ((__force omap_mbox_type_t) 1)
5635 +#define OMAP_MBOX_TYPE2 ((__force omap_mbox_type_t) 2)
5636 +
5637 +struct omap_mbox_ops {
5638 + omap_mbox_type_t type;
5639 + int (*startup)(struct omap_mbox *mbox);
5640 + void (*shutdown)(struct omap_mbox *mbox);
5641 + /* fifo */
5642 + mbox_msg_t (*fifo_read)(struct omap_mbox *mbox);
5643 + void (*fifo_write)(struct omap_mbox *mbox, mbox_msg_t msg);
5644 + int (*fifo_empty)(struct omap_mbox *mbox);
5645 + int (*fifo_full)(struct omap_mbox *mbox);
5646 + /* irq */
5647 + void (*enable_irq)(struct omap_mbox *mbox,
5648 + omap_mbox_irq_t irq);
5649 + void (*disable_irq)(struct omap_mbox *mbox,
5650 + omap_mbox_irq_t irq);
5651 + void (*ack_irq)(struct omap_mbox *mbox, omap_mbox_irq_t irq);
5652 + int (*is_irq)(struct omap_mbox *mbox, omap_mbox_irq_t irq);
5653 + /* ctx */
5654 + void (*save_ctx)(struct omap_mbox *mbox);
5655 + void (*restore_ctx)(struct omap_mbox *mbox);
5656 +};
5657 +
5658 +struct omap_mbox_queue {
5659 + spinlock_t lock;
5660 + struct request_queue *queue;
5661 + struct work_struct work;
5662 + struct tasklet_struct tasklet;
5663 + int (*callback)(void *);
5664 + struct omap_mbox *mbox;
5665 +};
5666 +
5667 +struct omap_mbox {
5668 + char *name;
5669 + unsigned int irq;
5670 +
5671 + struct omap_mbox_queue *txq, *rxq;
5672 +
5673 + struct omap_mbox_ops *ops;
5674 +
5675 + mbox_msg_t seq_snd, seq_rcv;
5676 +
5677 + struct device *dev;
5678 +
5679 + struct omap_mbox *next;
5680 + void *priv;
5681 +
5682 + void (*err_notify)(void);
5683 +};
5684 +
5685 +int omap_mbox_msg_send(struct omap_mbox *, mbox_msg_t msg);
5686 +void omap_mbox_init_seq(struct omap_mbox *);
5687 +
5688 +struct omap_mbox *omap_mbox_get(const char *);
5689 +void omap_mbox_put(struct omap_mbox *);
5690 +
5691 +int omap_mbox_register(struct device *parent, struct omap_mbox *);
5692 +int omap_mbox_unregister(struct omap_mbox *);
5693 +
5694 +static inline void omap_mbox_save_ctx(struct omap_mbox *mbox)
5695 +{
5696 + if (!mbox->ops->save_ctx) {
5697 + dev_err(mbox->dev, "%s:\tno save\n", __func__);
5698 + return;
5699 + }
5700 +
5701 + mbox->ops->save_ctx(mbox);
5702 +}
5703 +
5704 +static inline void omap_mbox_restore_ctx(struct omap_mbox *mbox)
5705 +{
5706 + if (!mbox->ops->restore_ctx) {
5707 + dev_err(mbox->dev, "%s:\tno restore\n", __func__);
5708 + return;
5709 + }
5710 +
5711 + mbox->ops->restore_ctx(mbox);
5712 +}
5713 +
5714 +static inline void omap_mbox_enable_irq(struct omap_mbox *mbox,
5715 + omap_mbox_irq_t irq)
5716 +{
5717 + mbox->ops->enable_irq(mbox, irq);
5718 +}
5719 +
5720 +static inline void omap_mbox_disable_irq(struct omap_mbox *mbox,
5721 + omap_mbox_irq_t irq)
5722 +{
5723 + mbox->ops->disable_irq(mbox, irq);
5724 +}
5725 +
5726 +#endif /* MAILBOX_H */
5727 Index: linux-2.6.37-rc1/arch/arm/plat-omap/include/mach/mcbsp.h
5728 ===================================================================
5729 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
5730 +++ linux-2.6.37-rc1/arch/arm/plat-omap/include/mach/mcbsp.h 2010-11-05 17:36:26.175000001 +0100
5731 @@ -0,0 +1,462 @@
5732 +/*
5733 + * arch/arm/plat-omap/include/mach/mcbsp.h
5734 + *
5735 + * Defines for Multi-Channel Buffered Serial Port
5736 + *
5737 + * Copyright (C) 2002 RidgeRun, Inc.
5738 + * Author: Steve Johnson
5739 + *
5740 + * This program is free software; you can redistribute it and/or modify
5741 + * it under the terms of the GNU General Public License as published by
5742 + * the Free Software Foundation; either version 2 of the License, or
5743 + * (at your option) any later version.
5744 + *
5745 + * This program is distributed in the hope that it will be useful,
5746 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
5747 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
5748 + * GNU General Public License for more details.
5749 + *
5750 + * You should have received a copy of the GNU General Public License
5751 + * along with this program; if not, write to the Free Software
5752 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
5753 + *
5754 + */
5755 +#ifndef __ASM_ARCH_OMAP_MCBSP_H
5756 +#define __ASM_ARCH_OMAP_MCBSP_H
5757 +
5758 +#include <linux/completion.h>
5759 +#include <linux/spinlock.h>
5760 +
5761 +#include <mach/hardware.h>
5762 +#include <plat/clock.h>
5763 +
5764 +#define OMAP7XX_MCBSP1_BASE 0xfffb1000
5765 +#define OMAP7XX_MCBSP2_BASE 0xfffb1800
5766 +
5767 +#define OMAP1510_MCBSP1_BASE 0xe1011800
5768 +#define OMAP1510_MCBSP2_BASE 0xfffb1000
5769 +#define OMAP1510_MCBSP3_BASE 0xe1017000
5770 +
5771 +#define OMAP1610_MCBSP1_BASE 0xe1011800
5772 +#define OMAP1610_MCBSP2_BASE 0xfffb1000
5773 +#define OMAP1610_MCBSP3_BASE 0xe1017000
5774 +
5775 +#define OMAP24XX_MCBSP1_BASE 0x48074000
5776 +#define OMAP24XX_MCBSP2_BASE 0x48076000
5777 +#define OMAP2430_MCBSP3_BASE 0x4808c000
5778 +#define OMAP2430_MCBSP4_BASE 0x4808e000
5779 +#define OMAP2430_MCBSP5_BASE 0x48096000
5780 +
5781 +#define OMAP34XX_MCBSP1_BASE 0x48074000
5782 +#define OMAP34XX_MCBSP2_BASE 0x49022000
5783 +#define OMAP34XX_MCBSP3_BASE 0x49024000
5784 +#define OMAP34XX_MCBSP4_BASE 0x49026000
5785 +#define OMAP34XX_MCBSP5_BASE 0x48096000
5786 +
5787 +#define OMAP44XX_MCBSP1_BASE 0x49022000
5788 +#define OMAP44XX_MCBSP2_BASE 0x49024000
5789 +#define OMAP44XX_MCBSP3_BASE 0x49026000
5790 +#define OMAP44XX_MCBSP4_BASE 0x48074000
5791 +
5792 +#if defined(CONFIG_ARCH_OMAP15XX) || defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
5793 +
5794 +#define OMAP_MCBSP_REG_DRR2 0x00
5795 +#define OMAP_MCBSP_REG_DRR1 0x02
5796 +#define OMAP_MCBSP_REG_DXR2 0x04
5797 +#define OMAP_MCBSP_REG_DXR1 0x06
5798 +#define OMAP_MCBSP_REG_SPCR2 0x08
5799 +#define OMAP_MCBSP_REG_SPCR1 0x0a
5800 +#define OMAP_MCBSP_REG_RCR2 0x0c
5801 +#define OMAP_MCBSP_REG_RCR1 0x0e
5802 +#define OMAP_MCBSP_REG_XCR2 0x10
5803 +#define OMAP_MCBSP_REG_XCR1 0x12
5804 +#define OMAP_MCBSP_REG_SRGR2 0x14
5805 +#define OMAP_MCBSP_REG_SRGR1 0x16
5806 +#define OMAP_MCBSP_REG_MCR2 0x18
5807 +#define OMAP_MCBSP_REG_MCR1 0x1a
5808 +#define OMAP_MCBSP_REG_RCERA 0x1c
5809 +#define OMAP_MCBSP_REG_RCERB 0x1e
5810 +#define OMAP_MCBSP_REG_XCERA 0x20
5811 +#define OMAP_MCBSP_REG_XCERB 0x22
5812 +#define OMAP_MCBSP_REG_PCR0 0x24
5813 +#define OMAP_MCBSP_REG_RCERC 0x26
5814 +#define OMAP_MCBSP_REG_RCERD 0x28
5815 +#define OMAP_MCBSP_REG_XCERC 0x2A
5816 +#define OMAP_MCBSP_REG_XCERD 0x2C
5817 +#define OMAP_MCBSP_REG_RCERE 0x2E
5818 +#define OMAP_MCBSP_REG_RCERF 0x30
5819 +#define OMAP_MCBSP_REG_XCERE 0x32
5820 +#define OMAP_MCBSP_REG_XCERF 0x34
5821 +#define OMAP_MCBSP_REG_RCERG 0x36
5822 +#define OMAP_MCBSP_REG_RCERH 0x38
5823 +#define OMAP_MCBSP_REG_XCERG 0x3A
5824 +#define OMAP_MCBSP_REG_XCERH 0x3C
5825 +
5826 +/* Dummy defines, these are not available on omap1 */
5827 +#define OMAP_MCBSP_REG_XCCR 0x00
5828 +#define OMAP_MCBSP_REG_RCCR 0x00
5829 +
5830 +#define AUDIO_MCBSP_DATAWRITE (OMAP1510_MCBSP1_BASE + OMAP_MCBSP_REG_DXR1)
5831 +#define AUDIO_MCBSP_DATAREAD (OMAP1510_MCBSP1_BASE + OMAP_MCBSP_REG_DRR1)
5832 +
5833 +#define AUDIO_MCBSP OMAP_MCBSP1
5834 +#define AUDIO_DMA_TX OMAP_DMA_MCBSP1_TX
5835 +#define AUDIO_DMA_RX OMAP_DMA_MCBSP1_RX
5836 +
5837 +#elif defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) || \
5838 + defined(CONFIG_ARCH_OMAP4)
5839 +
5840 +#define OMAP_MCBSP_REG_DRR2 0x00
5841 +#define OMAP_MCBSP_REG_DRR1 0x04
5842 +#define OMAP_MCBSP_REG_DXR2 0x08
5843 +#define OMAP_MCBSP_REG_DXR1 0x0C
5844 +#define OMAP_MCBSP_REG_DRR 0x00
5845 +#define OMAP_MCBSP_REG_DXR 0x08
5846 +#define OMAP_MCBSP_REG_SPCR2 0x10
5847 +#define OMAP_MCBSP_REG_SPCR1 0x14
5848 +#define OMAP_MCBSP_REG_RCR2 0x18
5849 +#define OMAP_MCBSP_REG_RCR1 0x1C
5850 +#define OMAP_MCBSP_REG_XCR2 0x20
5851 +#define OMAP_MCBSP_REG_XCR1 0x24
5852 +#define OMAP_MCBSP_REG_SRGR2 0x28
5853 +#define OMAP_MCBSP_REG_SRGR1 0x2C
5854 +#define OMAP_MCBSP_REG_MCR2 0x30
5855 +#define OMAP_MCBSP_REG_MCR1 0x34
5856 +#define OMAP_MCBSP_REG_RCERA 0x38
5857 +#define OMAP_MCBSP_REG_RCERB 0x3C
5858 +#define OMAP_MCBSP_REG_XCERA 0x40
5859 +#define OMAP_MCBSP_REG_XCERB 0x44
5860 +#define OMAP_MCBSP_REG_PCR0 0x48
5861 +#define OMAP_MCBSP_REG_RCERC 0x4C
5862 +#define OMAP_MCBSP_REG_RCERD 0x50
5863 +#define OMAP_MCBSP_REG_XCERC 0x54
5864 +#define OMAP_MCBSP_REG_XCERD 0x58
5865 +#define OMAP_MCBSP_REG_RCERE 0x5C
5866 +#define OMAP_MCBSP_REG_RCERF 0x60
5867 +#define OMAP_MCBSP_REG_XCERE 0x64
5868 +#define OMAP_MCBSP_REG_XCERF 0x68
5869 +#define OMAP_MCBSP_REG_RCERG 0x6C
5870 +#define OMAP_MCBSP_REG_RCERH 0x70
5871 +#define OMAP_MCBSP_REG_XCERG 0x74
5872 +#define OMAP_MCBSP_REG_XCERH 0x78
5873 +#define OMAP_MCBSP_REG_SYSCON 0x8C
5874 +#define OMAP_MCBSP_REG_THRSH2 0x90
5875 +#define OMAP_MCBSP_REG_THRSH1 0x94
5876 +#define OMAP_MCBSP_REG_IRQST 0xA0
5877 +#define OMAP_MCBSP_REG_IRQEN 0xA4
5878 +#define OMAP_MCBSP_REG_WAKEUPEN 0xA8
5879 +#define OMAP_MCBSP_REG_XCCR 0xAC
5880 +#define OMAP_MCBSP_REG_RCCR 0xB0
5881 +
5882 +#define AUDIO_MCBSP_DATAWRITE (OMAP24XX_MCBSP2_BASE + OMAP_MCBSP_REG_DXR1)
5883 +#define AUDIO_MCBSP_DATAREAD (OMAP24XX_MCBSP2_BASE + OMAP_MCBSP_REG_DRR1)
5884 +
5885 +#define AUDIO_MCBSP OMAP_MCBSP2
5886 +#define AUDIO_DMA_TX OMAP24XX_DMA_MCBSP2_TX
5887 +#define AUDIO_DMA_RX OMAP24XX_DMA_MCBSP2_RX
5888 +
5889 +#endif
5890 +
5891 +/************************** McBSP SPCR1 bit definitions ***********************/
5892 +#define RRST 0x0001
5893 +#define RRDY 0x0002
5894 +#define RFULL 0x0004
5895 +#define RSYNC_ERR 0x0008
5896 +#define RINTM(value) ((value)<<4) /* bits 4:5 */
5897 +#define ABIS 0x0040
5898 +#define DXENA 0x0080
5899 +#define CLKSTP(value) ((value)<<11) /* bits 11:12 */
5900 +#define RJUST(value) ((value)<<13) /* bits 13:14 */
5901 +#define ALB 0x8000
5902 +#define DLB 0x8000
5903 +
5904 +/************************** McBSP SPCR2 bit definitions ***********************/
5905 +#define XRST 0x0001
5906 +#define XRDY 0x0002
5907 +#define XEMPTY 0x0004
5908 +#define XSYNC_ERR 0x0008
5909 +#define XINTM(value) ((value)<<4) /* bits 4:5 */
5910 +#define GRST 0x0040
5911 +#define FRST 0x0080
5912 +#define SOFT 0x0100
5913 +#define FREE 0x0200
5914 +
5915 +/************************** McBSP PCR bit definitions *************************/
5916 +#define CLKRP 0x0001
5917 +#define CLKXP 0x0002
5918 +#define FSRP 0x0004
5919 +#define FSXP 0x0008
5920 +#define DR_STAT 0x0010
5921 +#define DX_STAT 0x0020
5922 +#define CLKS_STAT 0x0040
5923 +#define SCLKME 0x0080
5924 +#define CLKRM 0x0100
5925 +#define CLKXM 0x0200
5926 +#define FSRM 0x0400
5927 +#define FSXM 0x0800
5928 +#define RIOEN 0x1000
5929 +#define XIOEN 0x2000
5930 +#define IDLE_EN 0x4000
5931 +
5932 +/************************** McBSP RCR1 bit definitions ************************/
5933 +#define RWDLEN1(value) ((value)<<5) /* Bits 5:7 */
5934 +#define RFRLEN1(value) ((value)<<8) /* Bits 8:14 */
5935 +
5936 +/************************** McBSP XCR1 bit definitions ************************/
5937 +#define XWDLEN1(value) ((value)<<5) /* Bits 5:7 */
5938 +#define XFRLEN1(value) ((value)<<8) /* Bits 8:14 */
5939 +
5940 +/*************************** McBSP RCR2 bit definitions ***********************/
5941 +#define RDATDLY(value) (value) /* Bits 0:1 */
5942 +#define RFIG 0x0004
5943 +#define RCOMPAND(value) ((value)<<3) /* Bits 3:4 */
5944 +#define RWDLEN2(value) ((value)<<5) /* Bits 5:7 */
5945 +#define RFRLEN2(value) ((value)<<8) /* Bits 8:14 */
5946 +#define RPHASE 0x8000
5947 +
5948 +/*************************** McBSP XCR2 bit definitions ***********************/
5949 +#define XDATDLY(value) (value) /* Bits 0:1 */
5950 +#define XFIG 0x0004
5951 +#define XCOMPAND(value) ((value)<<3) /* Bits 3:4 */
5952 +#define XWDLEN2(value) ((value)<<5) /* Bits 5:7 */
5953 +#define XFRLEN2(value) ((value)<<8) /* Bits 8:14 */
5954 +#define XPHASE 0x8000
5955 +
5956 +/************************* McBSP SRGR1 bit definitions ************************/
5957 +#define CLKGDV(value) (value) /* Bits 0:7 */
5958 +#define FWID(value) ((value)<<8) /* Bits 8:15 */
5959 +
5960 +/************************* McBSP SRGR2 bit definitions ************************/
5961 +#define FPER(value) (value) /* Bits 0:11 */
5962 +#define FSGM 0x1000
5963 +#define CLKSM 0x2000
5964 +#define CLKSP 0x4000
5965 +#define GSYNC 0x8000
5966 +
5967 +/************************* McBSP MCR1 bit definitions *************************/
5968 +#define RMCM 0x0001
5969 +#define RCBLK(value) ((value)<<2) /* Bits 2:4 */
5970 +#define RPABLK(value) ((value)<<5) /* Bits 5:6 */
5971 +#define RPBBLK(value) ((value)<<7) /* Bits 7:8 */
5972 +
5973 +/************************* McBSP MCR2 bit definitions *************************/
5974 +#define XMCM(value) (value) /* Bits 0:1 */
5975 +#define XCBLK(value) ((value)<<2) /* Bits 2:4 */
5976 +#define XPABLK(value) ((value)<<5) /* Bits 5:6 */
5977 +#define XPBBLK(value) ((value)<<7) /* Bits 7:8 */
5978 +
5979 +/*********************** McBSP XCCR bit definitions *************************/
5980 +#define EXTCLKGATE 0x8000
5981 +#define PPCONNECT 0x4000
5982 +#define DXENDLY(value) ((value)<<12) /* Bits 12:13 */
5983 +#define XFULL_CYCLE 0x0800
5984 +#define DILB 0x0020
5985 +#define XDMAEN 0x0008
5986 +#define XDISABLE 0x0001
5987 +
5988 +/********************** McBSP RCCR bit definitions *************************/
5989 +#define RFULL_CYCLE 0x0800
5990 +#define RDMAEN 0x0008
5991 +#define RDISABLE 0x0001
5992 +
5993 +/********************** McBSP SYSCONFIG bit definitions ********************/
5994 +#define CLOCKACTIVITY(value) ((value)<<8)
5995 +#define SIDLEMODE(value) ((value)<<3)
5996 +#define ENAWAKEUP 0x0004
5997 +#define SOFTRST 0x0002
5998 +
5999 +/********************** McBSP DMA operating modes **************************/
6000 +#define MCBSP_DMA_MODE_ELEMENT 0
6001 +#define MCBSP_DMA_MODE_THRESHOLD 1
6002 +#define MCBSP_DMA_MODE_FRAME 2
6003 +
6004 +/********************** McBSP WAKEUPEN bit definitions *********************/
6005 +#define XEMPTYEOFEN 0x4000
6006 +#define XRDYEN 0x0400
6007 +#define XEOFEN 0x0200
6008 +#define XFSXEN 0x0100
6009 +#define XSYNCERREN 0x0080
6010 +#define RRDYEN 0x0008
6011 +#define REOFEN 0x0004
6012 +#define RFSREN 0x0002
6013 +#define RSYNCERREN 0x0001
6014 +
6015 +/* we don't do multichannel for now */
6016 +struct omap_mcbsp_reg_cfg {
6017 + u16 spcr2;
6018 + u16 spcr1;
6019 + u16 rcr2;
6020 + u16 rcr1;
6021 + u16 xcr2;
6022 + u16 xcr1;
6023 + u16 srgr2;
6024 + u16 srgr1;
6025 + u16 mcr2;
6026 + u16 mcr1;
6027 + u16 pcr0;
6028 + u16 rcerc;
6029 + u16 rcerd;
6030 + u16 xcerc;
6031 + u16 xcerd;
6032 + u16 rcere;
6033 + u16 rcerf;
6034 + u16 xcere;
6035 + u16 xcerf;
6036 + u16 rcerg;
6037 + u16 rcerh;
6038 + u16 xcerg;
6039 + u16 xcerh;
6040 + u16 xccr;
6041 + u16 rccr;
6042 +};
6043 +
6044 +typedef enum {
6045 + OMAP_MCBSP1 = 0,
6046 + OMAP_MCBSP2,
6047 + OMAP_MCBSP3,
6048 + OMAP_MCBSP4,
6049 + OMAP_MCBSP5
6050 +} omap_mcbsp_id;
6051 +
6052 +typedef int __bitwise omap_mcbsp_io_type_t;
6053 +#define OMAP_MCBSP_IRQ_IO ((__force omap_mcbsp_io_type_t) 1)
6054 +#define OMAP_MCBSP_POLL_IO ((__force omap_mcbsp_io_type_t) 2)
6055 +
6056 +typedef enum {
6057 + OMAP_MCBSP_WORD_8 = 0,
6058 + OMAP_MCBSP_WORD_12,
6059 + OMAP_MCBSP_WORD_16,
6060 + OMAP_MCBSP_WORD_20,
6061 + OMAP_MCBSP_WORD_24,
6062 + OMAP_MCBSP_WORD_32,
6063 +} omap_mcbsp_word_length;
6064 +
6065 +typedef enum {
6066 + OMAP_MCBSP_CLK_RISING = 0,
6067 + OMAP_MCBSP_CLK_FALLING,
6068 +} omap_mcbsp_clk_polarity;
6069 +
6070 +typedef enum {
6071 + OMAP_MCBSP_FS_ACTIVE_HIGH = 0,
6072 + OMAP_MCBSP_FS_ACTIVE_LOW,
6073 +} omap_mcbsp_fs_polarity;
6074 +
6075 +typedef enum {
6076 + OMAP_MCBSP_CLK_STP_MODE_NO_DELAY = 0,
6077 + OMAP_MCBSP_CLK_STP_MODE_DELAY,
6078 +} omap_mcbsp_clk_stp_mode;
6079 +
6080 +
6081 +/******* SPI specific mode **********/
6082 +typedef enum {
6083 + OMAP_MCBSP_SPI_MASTER = 0,
6084 + OMAP_MCBSP_SPI_SLAVE,
6085 +} omap_mcbsp_spi_mode;
6086 +
6087 +struct omap_mcbsp_spi_cfg {
6088 + omap_mcbsp_spi_mode spi_mode;
6089 + omap_mcbsp_clk_polarity rx_clock_polarity;
6090 + omap_mcbsp_clk_polarity tx_clock_polarity;
6091 + omap_mcbsp_fs_polarity fsx_polarity;
6092 + u8 clk_div;
6093 + omap_mcbsp_clk_stp_mode clk_stp_mode;
6094 + omap_mcbsp_word_length word_length;
6095 +};
6096 +
6097 +/* Platform specific configuration */
6098 +struct omap_mcbsp_ops {
6099 + void (*request)(unsigned int);
6100 + void (*free)(unsigned int);
6101 +};
6102 +
6103 +struct omap_mcbsp_platform_data {
6104 + unsigned long phys_base;
6105 + u8 dma_rx_sync, dma_tx_sync;
6106 + u16 rx_irq, tx_irq;
6107 + struct omap_mcbsp_ops *ops;
6108 +#ifdef CONFIG_ARCH_OMAP34XX
6109 + u16 buffer_size;
6110 +#endif
6111 +};
6112 +
6113 +struct omap_mcbsp {
6114 + struct device *dev;
6115 + unsigned long phys_base;
6116 + void __iomem *io_base;
6117 + u8 id;
6118 + u8 free;
6119 + omap_mcbsp_word_length rx_word_length;
6120 + omap_mcbsp_word_length tx_word_length;
6121 +
6122 + omap_mcbsp_io_type_t io_type; /* IRQ or poll */
6123 + /* IRQ based TX/RX */
6124 + int rx_irq;
6125 + int tx_irq;
6126 +
6127 + /* DMA stuff */
6128 + u8 dma_rx_sync;
6129 + short dma_rx_lch;
6130 + u8 dma_tx_sync;
6131 + short dma_tx_lch;
6132 +
6133 + /* Completion queues */
6134 + struct completion tx_irq_completion;
6135 + struct completion rx_irq_completion;
6136 + struct completion tx_dma_completion;
6137 + struct completion rx_dma_completion;
6138 +
6139 + /* Protect the field .free, while checking if the mcbsp is in use */
6140 + spinlock_t lock;
6141 + struct omap_mcbsp_platform_data *pdata;
6142 + struct clk *iclk;
6143 + struct clk *fclk;
6144 +#ifdef CONFIG_ARCH_OMAP34XX
6145 + int dma_op_mode;
6146 + u16 max_tx_thres;
6147 + u16 max_rx_thres;
6148 +#endif
6149 +};
6150 +extern struct omap_mcbsp **mcbsp_ptr;
6151 +extern int omap_mcbsp_count;
6152 +
6153 +int omap_mcbsp_init(void);
6154 +void omap_mcbsp_register_board_cfg(struct omap_mcbsp_platform_data *config,
6155 + int size);
6156 +void omap_mcbsp_config(unsigned int id, const struct omap_mcbsp_reg_cfg * config);
6157 +#ifdef CONFIG_ARCH_OMAP34XX
6158 +void omap_mcbsp_set_tx_threshold(unsigned int id, u16 threshold);
6159 +void omap_mcbsp_set_rx_threshold(unsigned int id, u16 threshold);
6160 +u16 omap_mcbsp_get_max_tx_threshold(unsigned int id);
6161 +u16 omap_mcbsp_get_max_rx_threshold(unsigned int id);
6162 +int omap_mcbsp_get_dma_op_mode(unsigned int id);
6163 +#else
6164 +static inline void omap_mcbsp_set_tx_threshold(unsigned int id, u16 threshold)
6165 +{ }
6166 +static inline void omap_mcbsp_set_rx_threshold(unsigned int id, u16 threshold)
6167 +{ }
6168 +static inline u16 omap_mcbsp_get_max_tx_threshold(unsigned int id) { return 0; }
6169 +static inline u16 omap_mcbsp_get_max_rx_threshold(unsigned int id) { return 0; }
6170 +static inline int omap_mcbsp_get_dma_op_mode(unsigned int id) { return 0; }
6171 +#endif
6172 +int omap_mcbsp_request(unsigned int id);
6173 +void omap_mcbsp_free(unsigned int id);
6174 +void omap_mcbsp_start(unsigned int id, int tx, int rx);
6175 +void omap_mcbsp_stop(unsigned int id, int tx, int rx);
6176 +void omap_mcbsp_xmit_word(unsigned int id, u32 word);
6177 +u32 omap_mcbsp_recv_word(unsigned int id);
6178 +
6179 +int omap_mcbsp_xmit_buffer(unsigned int id, dma_addr_t buffer, unsigned int length);
6180 +int omap_mcbsp_recv_buffer(unsigned int id, dma_addr_t buffer, unsigned int length);
6181 +int omap_mcbsp_spi_master_xmit_word_poll(unsigned int id, u32 word);
6182 +int omap_mcbsp_spi_master_recv_word_poll(unsigned int id, u32 * word);
6183 +
6184 +
6185 +/* SPI specific API */
6186 +void omap_mcbsp_set_spi_mode(unsigned int id, const struct omap_mcbsp_spi_cfg * spi_cfg);
6187 +
6188 +/* Polled read/write functions */
6189 +int omap_mcbsp_pollread(unsigned int id, u16 * buf);
6190 +int omap_mcbsp_pollwrite(unsigned int id, u16 buf);
6191 +int omap_mcbsp_set_io_type(unsigned int id, omap_mcbsp_io_type_t io_type);
6192 +
6193 +#endif
6194 Index: linux-2.6.37-rc1/arch/arm/plat-omap/include/mach/mcspi.h
6195 ===================================================================
6196 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
6197 +++ linux-2.6.37-rc1/arch/arm/plat-omap/include/mach/mcspi.h 2010-11-05 17:36:26.176000001 +0100
6198 @@ -0,0 +1,15 @@
6199 +#ifndef _OMAP2_MCSPI_H
6200 +#define _OMAP2_MCSPI_H
6201 +
6202 +struct omap2_mcspi_platform_config {
6203 + unsigned short num_cs;
6204 +};
6205 +
6206 +struct omap2_mcspi_device_config {
6207 + unsigned turbo_mode:1;
6208 +
6209 + /* Do we want one channel enabled at the same time? */
6210 + unsigned single_channel:1;
6211 +};
6212 +
6213 +#endif
6214 Index: linux-2.6.37-rc1/arch/arm/plat-omap/include/mach/memory.h
6215 ===================================================================
6216 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
6217 +++ linux-2.6.37-rc1/arch/arm/plat-omap/include/mach/memory.h 2010-11-05 17:36:26.176000001 +0100
6218 @@ -0,0 +1,103 @@
6219 +/*
6220 + * arch/arm/plat-omap/include/mach/memory.h
6221 + *
6222 + * Memory map for OMAP-1510 and 1610
6223 + *
6224 + * Copyright (C) 2000 RidgeRun, Inc.
6225 + * Author: Greg Lonnon <glonnon@ridgerun.com>
6226 + *
6227 + * This file was derived from arch/arm/mach-intergrator/include/mach/memory.h
6228 + * Copyright (C) 1999 ARM Limited
6229 + *
6230 + * This program is free software; you can redistribute it and/or modify it
6231 + * under the terms of the GNU General Public License as published by the
6232 + * Free Software Foundation; either version 2 of the License, or (at your
6233 + * option) any later version.
6234 + *
6235 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
6236 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
6237 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
6238 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
6239 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
6240 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
6241 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
6242 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
6243 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
6244 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
6245 + *
6246 + * You should have received a copy of the GNU General Public License along
6247 + * with this program; if not, write to the Free Software Foundation, Inc.,
6248 + * 675 Mass Ave, Cambridge, MA 02139, USA.
6249 + */
6250 +
6251 +#ifndef __ASM_ARCH_MEMORY_H
6252 +#define __ASM_ARCH_MEMORY_H
6253 +
6254 +/*
6255 + * Physical DRAM offset.
6256 + */
6257 +#if defined(CONFIG_ARCH_OMAP1)
6258 +#define PHYS_OFFSET UL(0x10000000)
6259 +#elif defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) || \
6260 + defined(CONFIG_ARCH_OMAP4)
6261 +#define PHYS_OFFSET UL(0x80000000)
6262 +#endif
6263 +
6264 +/*
6265 + * Bus address is physical address, except for OMAP-1510 Local Bus.
6266 + * OMAP-1510 bus address is translated into a Local Bus address if the
6267 + * OMAP bus type is lbus. We do the address translation based on the
6268 + * device overriding the defaults used in the dma-mapping API.
6269 + * Note that the is_lbus_device() test is not very efficient on 1510
6270 + * because of the strncmp().
6271 + */
6272 +#ifdef CONFIG_ARCH_OMAP15XX
6273 +
6274 +/*
6275 + * OMAP-1510 Local Bus address offset
6276 + */
6277 +#define OMAP1510_LB_OFFSET UL(0x30000000)
6278 +
6279 +#define virt_to_lbus(x) ((x) - PAGE_OFFSET + OMAP1510_LB_OFFSET)
6280 +#define lbus_to_virt(x) ((x) - OMAP1510_LB_OFFSET + PAGE_OFFSET)
6281 +#define is_lbus_device(dev) (cpu_is_omap15xx() && dev && (strncmp(dev_name(dev), "ohci", 4) == 0))
6282 +
6283 +#define __arch_page_to_dma(dev, page) \
6284 + ({ dma_addr_t __dma = page_to_phys(page); \
6285 + if (is_lbus_device(dev)) \
6286 + __dma = __dma - PHYS_OFFSET + OMAP1510_LB_OFFSET; \
6287 + __dma; })
6288 +
6289 +#define __arch_dma_to_page(dev, addr) \
6290 + ({ dma_addr_t __dma = addr; \
6291 + if (is_lbus_device(dev)) \
6292 + __dma += PHYS_OFFSET - OMAP1510_LB_OFFSET; \
6293 + phys_to_page(__dma); \
6294 + })
6295 +
6296 +#define __arch_dma_to_virt(dev, addr) ({ (void *) (is_lbus_device(dev) ? \
6297 + lbus_to_virt(addr) : \
6298 + __phys_to_virt(addr)); })
6299 +
6300 +#define __arch_virt_to_dma(dev, addr) ({ unsigned long __addr = (unsigned long)(addr); \
6301 + (dma_addr_t) (is_lbus_device(dev) ? \
6302 + virt_to_lbus(__addr) : \
6303 + __virt_to_phys(__addr)); })
6304 +
6305 +#endif /* CONFIG_ARCH_OMAP15XX */
6306 +
6307 +/* Override the ARM default */
6308 +#ifdef CONFIG_FB_OMAP_CONSISTENT_DMA_SIZE
6309 +
6310 +#if (CONFIG_FB_OMAP_CONSISTENT_DMA_SIZE == 0)
6311 +#undef CONFIG_FB_OMAP_CONSISTENT_DMA_SIZE
6312 +#define CONFIG_FB_OMAP_CONSISTENT_DMA_SIZE 2
6313 +#endif
6314 +
6315 +#define CONSISTENT_DMA_SIZE \
6316 + (((CONFIG_FB_OMAP_CONSISTENT_DMA_SIZE + 1) & ~1) * 1024 * 1024)
6317 +
6318 +#endif
6319 +
6320 +#endif
6321 +
6322 Index: linux-2.6.37-rc1/arch/arm/plat-omap/include/mach/menelaus.h
6323 ===================================================================
6324 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
6325 +++ linux-2.6.37-rc1/arch/arm/plat-omap/include/mach/menelaus.h 2010-11-05 17:36:26.176000001 +0100
6326 @@ -0,0 +1,49 @@
6327 +/*
6328 + * arch/arm/plat-omap/include/mach/menelaus.h
6329 + *
6330 + * Functions to access Menelaus power management chip
6331 + */
6332 +
6333 +#ifndef __ASM_ARCH_MENELAUS_H
6334 +#define __ASM_ARCH_MENELAUS_H
6335 +
6336 +struct device;
6337 +
6338 +struct menelaus_platform_data {
6339 + int (* late_init)(struct device *dev);
6340 +};
6341 +
6342 +extern int menelaus_register_mmc_callback(void (*callback)(void *data, u8 card_mask),
6343 + void *data);
6344 +extern void menelaus_unregister_mmc_callback(void);
6345 +extern int menelaus_set_mmc_opendrain(int slot, int enable);
6346 +extern int menelaus_set_mmc_slot(int slot, int enable, int power, int cd_on);
6347 +
6348 +extern int menelaus_set_vmem(unsigned int mV);
6349 +extern int menelaus_set_vio(unsigned int mV);
6350 +extern int menelaus_set_vmmc(unsigned int mV);
6351 +extern int menelaus_set_vaux(unsigned int mV);
6352 +extern int menelaus_set_vdcdc(int dcdc, unsigned int mV);
6353 +extern int menelaus_set_slot_sel(int enable);
6354 +extern int menelaus_get_slot_pin_states(void);
6355 +extern int menelaus_set_vcore_sw(unsigned int mV);
6356 +extern int menelaus_set_vcore_hw(unsigned int roof_mV, unsigned int floor_mV);
6357 +
6358 +#define EN_VPLL_SLEEP (1 << 7)
6359 +#define EN_VMMC_SLEEP (1 << 6)
6360 +#define EN_VAUX_SLEEP (1 << 5)
6361 +#define EN_VIO_SLEEP (1 << 4)
6362 +#define EN_VMEM_SLEEP (1 << 3)
6363 +#define EN_DC3_SLEEP (1 << 2)
6364 +#define EN_DC2_SLEEP (1 << 1)
6365 +#define EN_VC_SLEEP (1 << 0)
6366 +
6367 +extern int menelaus_set_regulator_sleep(int enable, u32 val);
6368 +
6369 +#if defined(CONFIG_ARCH_OMAP24XX) && defined(CONFIG_MENELAUS)
6370 +#define omap_has_menelaus() 1
6371 +#else
6372 +#define omap_has_menelaus() 0
6373 +#endif
6374 +
6375 +#endif
6376 Index: linux-2.6.37-rc1/arch/arm/plat-omap/include/mach/mmc.h
6377 ===================================================================
6378 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
6379 +++ linux-2.6.37-rc1/arch/arm/plat-omap/include/mach/mmc.h 2010-11-05 17:36:26.176000001 +0100
6380 @@ -0,0 +1,157 @@
6381 +/*
6382 + * MMC definitions for OMAP2
6383 + *
6384 + * Copyright (C) 2006 Nokia Corporation
6385 + *
6386 + * This program is free software; you can redistribute it and/or modify
6387 + * it under the terms of the GNU General Public License version 2 as
6388 + * published by the Free Software Foundation.
6389 + */
6390 +
6391 +#ifndef __OMAP2_MMC_H
6392 +#define __OMAP2_MMC_H
6393 +
6394 +#include <linux/types.h>
6395 +#include <linux/device.h>
6396 +#include <linux/mmc/host.h>
6397 +
6398 +#include <plat/board.h>
6399 +
6400 +#define OMAP15XX_NR_MMC 1
6401 +#define OMAP16XX_NR_MMC 2
6402 +#define OMAP1_MMC_SIZE 0x080
6403 +#define OMAP1_MMC1_BASE 0xfffb7800
6404 +#define OMAP1_MMC2_BASE 0xfffb7c00 /* omap16xx only */
6405 +
6406 +#define OMAP24XX_NR_MMC 2
6407 +#define OMAP34XX_NR_MMC 3
6408 +#define OMAP44XX_NR_MMC 5
6409 +#define OMAP2420_MMC_SIZE OMAP1_MMC_SIZE
6410 +#define OMAP3_HSMMC_SIZE 0x200
6411 +#define OMAP4_HSMMC_SIZE 0x1000
6412 +#define OMAP2_MMC1_BASE 0x4809c000
6413 +#define OMAP2_MMC2_BASE 0x480b4000
6414 +#define OMAP3_MMC3_BASE 0x480ad000
6415 +#define OMAP4_MMC4_BASE 0x480d1000
6416 +#define OMAP4_MMC5_BASE 0x480d5000
6417 +#define OMAP4_MMC_REG_OFFSET 0x100
6418 +#define HSMMC5 (1 << 4)
6419 +#define HSMMC4 (1 << 3)
6420 +#define HSMMC3 (1 << 2)
6421 +#define HSMMC2 (1 << 1)
6422 +#define HSMMC1 (1 << 0)
6423 +
6424 +#define OMAP_MMC_MAX_SLOTS 2
6425 +
6426 +struct omap_mmc_platform_data {
6427 + /* back-link to device */
6428 + struct device *dev;
6429 +
6430 + /* number of slots per controller */
6431 + unsigned nr_slots:2;
6432 +
6433 + /* set if your board has components or wiring that limits the
6434 + * maximum frequency on the MMC bus */
6435 + unsigned int max_freq;
6436 +
6437 + /* switch the bus to a new slot */
6438 + int (* switch_slot)(struct device *dev, int slot);
6439 + /* initialize board-specific MMC functionality, can be NULL if
6440 + * not supported */
6441 + int (* init)(struct device *dev);
6442 + void (* cleanup)(struct device *dev);
6443 + void (* shutdown)(struct device *dev);
6444 +
6445 + /* To handle board related suspend/resume functionality for MMC */
6446 + int (*suspend)(struct device *dev, int slot);
6447 + int (*resume)(struct device *dev, int slot);
6448 +
6449 + /* Return context loss count due to PM states changing */
6450 + int (*get_context_loss_count)(struct device *dev);
6451 +
6452 + u64 dma_mask;
6453 +
6454 + struct omap_mmc_slot_data {
6455 +
6456 + /* 4 wire signaling is optional, and is used for SD/SDIO/HSMMC;
6457 + * 8 wire signaling is also optional, and is used with HSMMC
6458 + */
6459 + u8 wires;
6460 +
6461 + /*
6462 + * nomux means "standard" muxing is wrong on this board, and
6463 + * that board-specific code handled it before common init logic.
6464 + */
6465 + unsigned nomux:1;
6466 +
6467 + /* switch pin can be for card detect (default) or card cover */
6468 + unsigned cover:1;
6469 +
6470 + /* use the internal clock */
6471 + unsigned internal_clock:1;
6472 +
6473 + /* nonremovable e.g. eMMC */
6474 + unsigned nonremovable:1;
6475 +
6476 + /* Try to sleep or power off when possible */
6477 + unsigned power_saving:1;
6478 +
6479 + int switch_pin; /* gpio (card detect) */
6480 + int gpio_wp; /* gpio (write protect) */
6481 +
6482 + int (* set_bus_mode)(struct device *dev, int slot, int bus_mode);
6483 + int (* set_power)(struct device *dev, int slot, int power_on, int vdd);
6484 + int (* get_ro)(struct device *dev, int slot);
6485 + int (*set_sleep)(struct device *dev, int slot, int sleep,
6486 + int vdd, int cardsleep);
6487 +
6488 + /* return MMC cover switch state, can be NULL if not supported.
6489 + *
6490 + * possible return values:
6491 + * 0 - closed
6492 + * 1 - open
6493 + */
6494 + int (* get_cover_state)(struct device *dev, int slot);
6495 +
6496 + const char *name;
6497 + u32 ocr_mask;
6498 +
6499 + /* Card detection IRQs */
6500 + int card_detect_irq;
6501 + int (* card_detect)(int irq);
6502 +
6503 + unsigned int ban_openended:1;
6504 +
6505 + } slots[OMAP_MMC_MAX_SLOTS];
6506 +};
6507 +
6508 +/* called from board-specific card detection service routine */
6509 +extern void omap_mmc_notify_cover_event(struct device *dev, int slot, int is_closed);
6510 +
6511 +#if defined(CONFIG_MMC_OMAP) || defined(CONFIG_MMC_OMAP_MODULE) || \
6512 + defined(CONFIG_MMC_OMAP_HS) || defined(CONFIG_MMC_OMAP_HS_MODULE)
6513 +void omap1_init_mmc(struct omap_mmc_platform_data **mmc_data,
6514 + int nr_controllers);
6515 +void omap2_init_mmc(struct omap_mmc_platform_data **mmc_data,
6516 + int nr_controllers);
6517 +int omap_mmc_add(const char *name, int id, unsigned long base,
6518 + unsigned long size, unsigned int irq,
6519 + struct omap_mmc_platform_data *data);
6520 +#else
6521 +static inline void omap1_init_mmc(struct omap_mmc_platform_data **mmc_data,
6522 + int nr_controllers)
6523 +{
6524 +}
6525 +static inline void omap2_init_mmc(struct omap_mmc_platform_data **mmc_data,
6526 + int nr_controllers)
6527 +{
6528 +}
6529 +static inline int omap_mmc_add(const char *name, int id, unsigned long base,
6530 + unsigned long size, unsigned int irq,
6531 + struct omap_mmc_platform_data *data)
6532 +{
6533 + return 0;
6534 +}
6535 +
6536 +#endif
6537 +#endif
6538 Index: linux-2.6.37-rc1/arch/arm/plat-omap/include/mach/mux.h
6539 ===================================================================
6540 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
6541 +++ linux-2.6.37-rc1/arch/arm/plat-omap/include/mach/mux.h 2010-11-05 17:36:26.176000001 +0100
6542 @@ -0,0 +1,662 @@
6543 +/*
6544 + * arch/arm/plat-omap/include/mach/mux.h
6545 + *
6546 + * Table of the Omap register configurations for the FUNC_MUX and
6547 + * PULL_DWN combinations.
6548 + *
6549 + * Copyright (C) 2004 - 2008 Texas Instruments Inc.
6550 + * Copyright (C) 2003 - 2008 Nokia Corporation
6551 + *
6552 + * Written by Tony Lindgren
6553 + *
6554 + * This program is free software; you can redistribute it and/or modify
6555 + * it under the terms of the GNU General Public License as published by
6556 + * the Free Software Foundation; either version 2 of the License, or
6557 + * (at your option) any later version.
6558 + *
6559 + * This program is distributed in the hope that it will be useful,
6560 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
6561 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
6562 + * GNU General Public License for more details.
6563 + *
6564 + * You should have received a copy of the GNU General Public License
6565 + * along with this program; if not, write to the Free Software
6566 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
6567 + *
6568 + * NOTE: Please use the following naming style for new pin entries.
6569 + * For example, W8_1610_MMC2_DAT0, where:
6570 + * - W8 = ball
6571 + * - 1610 = 1510 or 1610, none if common for both 1510 and 1610
6572 + * - MMC2_DAT0 = function
6573 + */
6574 +
6575 +#ifndef __ASM_ARCH_MUX_H
6576 +#define __ASM_ARCH_MUX_H
6577 +
6578 +#define PU_PD_SEL_NA 0 /* No pu_pd reg available */
6579 +#define PULL_DWN_CTRL_NA 0 /* No pull-down control needed */
6580 +
6581 +#ifdef CONFIG_OMAP_MUX_DEBUG
6582 +#define MUX_REG(reg, mode_offset, mode) .mux_reg_name = "FUNC_MUX_CTRL_"#reg, \
6583 + .mux_reg = FUNC_MUX_CTRL_##reg, \
6584 + .mask_offset = mode_offset, \
6585 + .mask = mode,
6586 +
6587 +#define PULL_REG(reg, bit, status) .pull_name = "PULL_DWN_CTRL_"#reg, \
6588 + .pull_reg = PULL_DWN_CTRL_##reg, \
6589 + .pull_bit = bit, \
6590 + .pull_val = status,
6591 +
6592 +#define PU_PD_REG(reg, status) .pu_pd_name = "PU_PD_SEL_"#reg, \
6593 + .pu_pd_reg = PU_PD_SEL_##reg, \
6594 + .pu_pd_val = status,
6595 +
6596 +#define MUX_REG_7XX(reg, mode_offset, mode) .mux_reg_name = "OMAP7XX_IO_CONF_"#reg, \
6597 + .mux_reg = OMAP7XX_IO_CONF_##reg, \
6598 + .mask_offset = mode_offset, \
6599 + .mask = mode,
6600 +
6601 +#define PULL_REG_7XX(reg, bit, status) .pull_name = "OMAP7XX_IO_CONF_"#reg, \
6602 + .pull_reg = OMAP7XX_IO_CONF_##reg, \
6603 + .pull_bit = bit, \
6604 + .pull_val = status,
6605 +
6606 +#else
6607 +
6608 +#define MUX_REG(reg, mode_offset, mode) .mux_reg = FUNC_MUX_CTRL_##reg, \
6609 + .mask_offset = mode_offset, \
6610 + .mask = mode,
6611 +
6612 +#define PULL_REG(reg, bit, status) .pull_reg = PULL_DWN_CTRL_##reg, \
6613 + .pull_bit = bit, \
6614 + .pull_val = status,
6615 +
6616 +#define PU_PD_REG(reg, status) .pu_pd_reg = PU_PD_SEL_##reg, \
6617 + .pu_pd_val = status,
6618 +
6619 +#define MUX_REG_7XX(reg, mode_offset, mode) \
6620 + .mux_reg = OMAP7XX_IO_CONF_##reg, \
6621 + .mask_offset = mode_offset, \
6622 + .mask = mode,
6623 +
6624 +#define PULL_REG_7XX(reg, bit, status) .pull_reg = OMAP7XX_IO_CONF_##reg, \
6625 + .pull_bit = bit, \
6626 + .pull_val = status,
6627 +
6628 +#endif /* CONFIG_OMAP_MUX_DEBUG */
6629 +
6630 +#define MUX_CFG(desc, mux_reg, mode_offset, mode, \
6631 + pull_reg, pull_bit, pull_status, \
6632 + pu_pd_reg, pu_pd_status, debug_status) \
6633 +{ \
6634 + .name = desc, \
6635 + .debug = debug_status, \
6636 + MUX_REG(mux_reg, mode_offset, mode) \
6637 + PULL_REG(pull_reg, pull_bit, pull_status) \
6638 + PU_PD_REG(pu_pd_reg, pu_pd_status) \
6639 +},
6640 +
6641 +
6642 +/*
6643 + * OMAP730/850 has a slightly different config for the pin mux.
6644 + * - config regs are the OMAP7XX_IO_CONF_x regs (see omap730.h) regs and
6645 + * not the FUNC_MUX_CTRL_x regs from hardware.h
6646 + * - for pull-up/down, only has one enable bit which is is in the same register
6647 + * as mux config
6648 + */
6649 +#define MUX_CFG_7XX(desc, mux_reg, mode_offset, mode, \
6650 + pull_bit, pull_status, debug_status)\
6651 +{ \
6652 + .name = desc, \
6653 + .debug = debug_status, \
6654 + MUX_REG_7XX(mux_reg, mode_offset, mode) \
6655 + PULL_REG_7XX(mux_reg, pull_bit, pull_status) \
6656 + PU_PD_REG(NA, 0) \
6657 +},
6658 +
6659 +#define MUX_CFG_24XX(desc, reg_offset, mode, \
6660 + pull_en, pull_mode, dbg) \
6661 +{ \
6662 + .name = desc, \
6663 + .debug = dbg, \
6664 + .mux_reg = reg_offset, \
6665 + .mask = mode, \
6666 + .pull_val = pull_en, \
6667 + .pu_pd_val = pull_mode, \
6668 +},
6669 +
6670 +/* 24xx/34xx mux bit defines */
6671 +#define OMAP2_PULL_ENA (1 << 3)
6672 +#define OMAP2_PULL_UP (1 << 4)
6673 +#define OMAP2_ALTELECTRICALSEL (1 << 5)
6674 +
6675 +struct pin_config {
6676 + char *name;
6677 + const unsigned int mux_reg;
6678 + unsigned char debug;
6679 +
6680 +#if defined(CONFIG_ARCH_OMAP1) || defined(CONFIG_ARCH_OMAP24XX)
6681 + const unsigned char mask_offset;
6682 + const unsigned char mask;
6683 +
6684 + const char *pull_name;
6685 + const unsigned int pull_reg;
6686 + const unsigned char pull_val;
6687 + const unsigned char pull_bit;
6688 +
6689 + const char *pu_pd_name;
6690 + const unsigned int pu_pd_reg;
6691 + const unsigned char pu_pd_val;
6692 +#endif
6693 +
6694 +#if defined(CONFIG_OMAP_MUX_DEBUG) || defined(CONFIG_OMAP_MUX_WARNINGS)
6695 + const char *mux_reg_name;
6696 +#endif
6697 +
6698 +};
6699 +
6700 +enum omap7xx_index {
6701 + /* OMAP 730 keyboard */
6702 + E2_7XX_KBR0,
6703 + J7_7XX_KBR1,
6704 + E1_7XX_KBR2,
6705 + F3_7XX_KBR3,
6706 + D2_7XX_KBR4,
6707 + C2_7XX_KBC0,
6708 + D3_7XX_KBC1,
6709 + E4_7XX_KBC2,
6710 + F4_7XX_KBC3,
6711 + E3_7XX_KBC4,
6712 +
6713 + /* USB */
6714 + AA17_7XX_USB_DM,
6715 + W16_7XX_USB_PU_EN,
6716 + W17_7XX_USB_VBUSI,
6717 + W18_7XX_USB_DMCK_OUT,
6718 + W19_7XX_USB_DCRST,
6719 +
6720 + /* MMC */
6721 + MMC_7XX_CMD,
6722 + MMC_7XX_CLK,
6723 + MMC_7XX_DAT0,
6724 +
6725 + /* I2C */
6726 + I2C_7XX_SCL,
6727 + I2C_7XX_SDA,
6728 +};
6729 +
6730 +enum omap1xxx_index {
6731 + /* UART1 (BT_UART_GATING)*/
6732 + UART1_TX = 0,
6733 + UART1_RTS,
6734 +
6735 + /* UART2 (COM_UART_GATING)*/
6736 + UART2_TX,
6737 + UART2_RX,
6738 + UART2_CTS,
6739 + UART2_RTS,
6740 +
6741 + /* UART3 (GIGA_UART_GATING) */
6742 + UART3_TX,
6743 + UART3_RX,
6744 + UART3_CTS,
6745 + UART3_RTS,
6746 + UART3_CLKREQ,
6747 + UART3_BCLK, /* 12MHz clock out */
6748 + Y15_1610_UART3_RTS,
6749 +
6750 + /* PWT & PWL */
6751 + PWT,
6752 + PWL,
6753 +
6754 + /* USB master generic */
6755 + R18_USB_VBUS,
6756 + R18_1510_USB_GPIO0,
6757 + W4_USB_PUEN,
6758 + W4_USB_CLKO,
6759 + W4_USB_HIGHZ,
6760 + W4_GPIO58,
6761 +
6762 + /* USB1 master */
6763 + USB1_SUSP,
6764 + USB1_SEO,
6765 + W13_1610_USB1_SE0,
6766 + USB1_TXEN,
6767 + USB1_TXD,
6768 + USB1_VP,
6769 + USB1_VM,
6770 + USB1_RCV,
6771 + USB1_SPEED,
6772 + R13_1610_USB1_SPEED,
6773 + R13_1710_USB1_SE0,
6774 +
6775 + /* USB2 master */
6776 + USB2_SUSP,
6777 + USB2_VP,
6778 + USB2_TXEN,
6779 + USB2_VM,
6780 + USB2_RCV,
6781 + USB2_SEO,
6782 + USB2_TXD,
6783 +
6784 + /* OMAP-1510 GPIO */
6785 + R18_1510_GPIO0,
6786 + R19_1510_GPIO1,
6787 + M14_1510_GPIO2,
6788 +
6789 + /* OMAP1610 GPIO */
6790 + P18_1610_GPIO3,
6791 + Y15_1610_GPIO17,
6792 +
6793 + /* OMAP-1710 GPIO */
6794 + R18_1710_GPIO0,
6795 + V2_1710_GPIO10,
6796 + N21_1710_GPIO14,
6797 + W15_1710_GPIO40,
6798 +
6799 + /* MPUIO */
6800 + MPUIO2,
6801 + N15_1610_MPUIO2,
6802 + MPUIO4,
6803 + MPUIO5,
6804 + T20_1610_MPUIO5,
6805 + W11_1610_MPUIO6,
6806 + V10_1610_MPUIO7,
6807 + W11_1610_MPUIO9,
6808 + V10_1610_MPUIO10,
6809 + W10_1610_MPUIO11,
6810 + E20_1610_MPUIO13,
6811 + U20_1610_MPUIO14,
6812 + E19_1610_MPUIO15,
6813 +
6814 + /* MCBSP2 */
6815 + MCBSP2_CLKR,
6816 + MCBSP2_CLKX,
6817 + MCBSP2_DR,
6818 + MCBSP2_DX,
6819 + MCBSP2_FSR,
6820 + MCBSP2_FSX,
6821 +
6822 + /* MCBSP3 */
6823 + MCBSP3_CLKX,
6824 +
6825 + /* Misc ballouts */
6826 + BALLOUT_V8_ARMIO3,
6827 + N20_HDQ,
6828 +
6829 + /* OMAP-1610 MMC2 */
6830 + W8_1610_MMC2_DAT0,
6831 + V8_1610_MMC2_DAT1,
6832 + W15_1610_MMC2_DAT2,
6833 + R10_1610_MMC2_DAT3,
6834 + Y10_1610_MMC2_CLK,
6835 + Y8_1610_MMC2_CMD,
6836 + V9_1610_MMC2_CMDDIR,
6837 + V5_1610_MMC2_DATDIR0,
6838 + W19_1610_MMC2_DATDIR1,
6839 + R18_1610_MMC2_CLKIN,
6840 +
6841 + /* OMAP-1610 External Trace Interface */
6842 + M19_1610_ETM_PSTAT0,
6843 + L15_1610_ETM_PSTAT1,
6844 + L18_1610_ETM_PSTAT2,
6845 + L19_1610_ETM_D0,
6846 + J19_1610_ETM_D6,
6847 + J18_1610_ETM_D7,
6848 +
6849 + /* OMAP16XX GPIO */
6850 + P20_1610_GPIO4,
6851 + V9_1610_GPIO7,
6852 + W8_1610_GPIO9,
6853 + N20_1610_GPIO11,
6854 + N19_1610_GPIO13,
6855 + P10_1610_GPIO22,
6856 + V5_1610_GPIO24,
6857 + AA20_1610_GPIO_41,
6858 + W19_1610_GPIO48,
6859 + M7_1610_GPIO62,
6860 + V14_16XX_GPIO37,
6861 + R9_16XX_GPIO18,
6862 + L14_16XX_GPIO49,
6863 +
6864 + /* OMAP-1610 uWire */
6865 + V19_1610_UWIRE_SCLK,
6866 + U18_1610_UWIRE_SDI,
6867 + W21_1610_UWIRE_SDO,
6868 + N14_1610_UWIRE_CS0,
6869 + P15_1610_UWIRE_CS3,
6870 + N15_1610_UWIRE_CS1,
6871 +
6872 + /* OMAP-1610 SPI */
6873 + U19_1610_SPIF_SCK,
6874 + U18_1610_SPIF_DIN,
6875 + P20_1610_SPIF_DIN,
6876 + W21_1610_SPIF_DOUT,
6877 + R18_1610_SPIF_DOUT,
6878 + N14_1610_SPIF_CS0,
6879 + N15_1610_SPIF_CS1,
6880 + T19_1610_SPIF_CS2,
6881 + P15_1610_SPIF_CS3,
6882 +
6883 + /* OMAP-1610 Flash */
6884 + L3_1610_FLASH_CS2B_OE,
6885 + M8_1610_FLASH_CS2B_WE,
6886 +
6887 + /* First MMC */
6888 + MMC_CMD,
6889 + MMC_DAT1,
6890 + MMC_DAT2,
6891 + MMC_DAT0,
6892 + MMC_CLK,
6893 + MMC_DAT3,
6894 +
6895 + /* OMAP-1710 MMC CMDDIR and DATDIR0 */
6896 + M15_1710_MMC_CLKI,
6897 + P19_1710_MMC_CMDDIR,
6898 + P20_1710_MMC_DATDIR0,
6899 +
6900 + /* OMAP-1610 USB0 alternate pin configuration */
6901 + W9_USB0_TXEN,
6902 + AA9_USB0_VP,
6903 + Y5_USB0_RCV,
6904 + R9_USB0_VM,
6905 + V6_USB0_TXD,
6906 + W5_USB0_SE0,
6907 + V9_USB0_SPEED,
6908 + V9_USB0_SUSP,
6909 +
6910 + /* USB2 */
6911 + W9_USB2_TXEN,
6912 + AA9_USB2_VP,
6913 + Y5_USB2_RCV,
6914 + R9_USB2_VM,
6915 + V6_USB2_TXD,
6916 + W5_USB2_SE0,
6917 +
6918 + /* 16XX UART */
6919 + R13_1610_UART1_TX,
6920 + V14_16XX_UART1_RX,
6921 + R14_1610_UART1_CTS,
6922 + AA15_1610_UART1_RTS,
6923 + R9_16XX_UART2_RX,
6924 + L14_16XX_UART3_RX,
6925 +
6926 + /* I2C OMAP-1610 */
6927 + I2C_SCL,
6928 + I2C_SDA,
6929 +
6930 + /* Keypad */
6931 + F18_1610_KBC0,
6932 + D20_1610_KBC1,
6933 + D19_1610_KBC2,
6934 + E18_1610_KBC3,
6935 + C21_1610_KBC4,
6936 + G18_1610_KBR0,
6937 + F19_1610_KBR1,
6938 + H14_1610_KBR2,
6939 + E20_1610_KBR3,
6940 + E19_1610_KBR4,
6941 + N19_1610_KBR5,
6942 +
6943 + /* Power management */
6944 + T20_1610_LOW_PWR,
6945 +
6946 + /* MCLK Settings */
6947 + V5_1710_MCLK_ON,
6948 + V5_1710_MCLK_OFF,
6949 + R10_1610_MCLK_ON,
6950 + R10_1610_MCLK_OFF,
6951 +
6952 + /* CompactFlash controller */
6953 + P11_1610_CF_CD2,
6954 + R11_1610_CF_IOIS16,
6955 + V10_1610_CF_IREQ,
6956 + W10_1610_CF_RESET,
6957 + W11_1610_CF_CD1,
6958 +
6959 + /* parallel camera */
6960 + J15_1610_CAM_LCLK,
6961 + J18_1610_CAM_D7,
6962 + J19_1610_CAM_D6,
6963 + J14_1610_CAM_D5,
6964 + K18_1610_CAM_D4,
6965 + K19_1610_CAM_D3,
6966 + K15_1610_CAM_D2,
6967 + K14_1610_CAM_D1,
6968 + L19_1610_CAM_D0,
6969 + L18_1610_CAM_VS,
6970 + L15_1610_CAM_HS,
6971 + M19_1610_CAM_RSTZ,
6972 + Y15_1610_CAM_OUTCLK,
6973 +
6974 + /* serial camera */
6975 + H19_1610_CAM_EXCLK,
6976 + Y12_1610_CCP_CLKP,
6977 + W13_1610_CCP_CLKM,
6978 + W14_1610_CCP_DATAP,
6979 + Y14_1610_CCP_DATAM,
6980 +
6981 +};
6982 +
6983 +enum omap24xx_index {
6984 + /* 24xx I2C */
6985 + M19_24XX_I2C1_SCL,
6986 + L15_24XX_I2C1_SDA,
6987 + J15_24XX_I2C2_SCL,
6988 + H19_24XX_I2C2_SDA,
6989 +
6990 + /* 24xx Menelaus interrupt */
6991 + W19_24XX_SYS_NIRQ,
6992 +
6993 + /* 24xx clock */
6994 + W14_24XX_SYS_CLKOUT,
6995 +
6996 + /* 24xx GPMC chipselects, wait pin monitoring */
6997 + E2_GPMC_NCS2,
6998 + L2_GPMC_NCS7,
6999 + L3_GPMC_WAIT0,
7000 + N7_GPMC_WAIT1,
7001 + M1_GPMC_WAIT2,
7002 + P1_GPMC_WAIT3,
7003 +
7004 + /* 242X McBSP */
7005 + Y15_24XX_MCBSP2_CLKX,
7006 + R14_24XX_MCBSP2_FSX,
7007 + W15_24XX_MCBSP2_DR,
7008 + V15_24XX_MCBSP2_DX,
7009 +
7010 + /* 24xx GPIO */
7011 + M21_242X_GPIO11,
7012 + P21_242X_GPIO12,
7013 + AA10_242X_GPIO13,
7014 + AA6_242X_GPIO14,
7015 + AA4_242X_GPIO15,
7016 + Y11_242X_GPIO16,
7017 + AA12_242X_GPIO17,
7018 + AA8_242X_GPIO58,
7019 + Y20_24XX_GPIO60,
7020 + W4__24XX_GPIO74,
7021 + N15_24XX_GPIO85,
7022 + M15_24XX_GPIO92,
7023 + P20_24XX_GPIO93,
7024 + P18_24XX_GPIO95,
7025 + M18_24XX_GPIO96,
7026 + L14_24XX_GPIO97,
7027 + J15_24XX_GPIO99,
7028 + V14_24XX_GPIO117,
7029 + P14_24XX_GPIO125,
7030 +
7031 + /* 242x DBG GPIO */
7032 + V4_242X_GPIO49,
7033 + W2_242X_GPIO50,
7034 + U4_242X_GPIO51,
7035 + V3_242X_GPIO52,
7036 + V2_242X_GPIO53,
7037 + V6_242X_GPIO53,
7038 + T4_242X_GPIO54,
7039 + Y4_242X_GPIO54,
7040 + T3_242X_GPIO55,
7041 + U2_242X_GPIO56,
7042 +
7043 + /* 24xx external DMA requests */
7044 + AA10_242X_DMAREQ0,
7045 + AA6_242X_DMAREQ1,
7046 + E4_242X_DMAREQ2,
7047 + G4_242X_DMAREQ3,
7048 + D3_242X_DMAREQ4,
7049 + E3_242X_DMAREQ5,
7050 +
7051 + /* UART3 */
7052 + K15_24XX_UART3_TX,
7053 + K14_24XX_UART3_RX,
7054 +
7055 + /* MMC/SDIO */
7056 + G19_24XX_MMC_CLKO,
7057 + H18_24XX_MMC_CMD,
7058 + F20_24XX_MMC_DAT0,
7059 + H14_24XX_MMC_DAT1,
7060 + E19_24XX_MMC_DAT2,
7061 + D19_24XX_MMC_DAT3,
7062 + F19_24XX_MMC_DAT_DIR0,
7063 + E20_24XX_MMC_DAT_DIR1,
7064 + F18_24XX_MMC_DAT_DIR2,
7065 + E18_24XX_MMC_DAT_DIR3,
7066 + G18_24XX_MMC_CMD_DIR,
7067 + H15_24XX_MMC_CLKI,
7068 +
7069 + /* Full speed USB */
7070 + J20_24XX_USB0_PUEN,
7071 + J19_24XX_USB0_VP,
7072 + K20_24XX_USB0_VM,
7073 + J18_24XX_USB0_RCV,
7074 + K19_24XX_USB0_TXEN,
7075 + J14_24XX_USB0_SE0,
7076 + K18_24XX_USB0_DAT,
7077 +
7078 + N14_24XX_USB1_SE0,
7079 + W12_24XX_USB1_SE0,
7080 + P15_24XX_USB1_DAT,
7081 + R13_24XX_USB1_DAT,
7082 + W20_24XX_USB1_TXEN,
7083 + P13_24XX_USB1_TXEN,
7084 + V19_24XX_USB1_RCV,
7085 + V12_24XX_USB1_RCV,
7086 +
7087 + AA10_24XX_USB2_SE0,
7088 + Y11_24XX_USB2_DAT,
7089 + AA12_24XX_USB2_TXEN,
7090 + AA6_24XX_USB2_RCV,
7091 + AA4_24XX_USB2_TLLSE0,
7092 +
7093 + /* Keypad GPIO*/
7094 + T19_24XX_KBR0,
7095 + R19_24XX_KBR1,
7096 + V18_24XX_KBR2,
7097 + M21_24XX_KBR3,
7098 + E5__24XX_KBR4,
7099 + M18_24XX_KBR5,
7100 + R20_24XX_KBC0,
7101 + M14_24XX_KBC1,
7102 + H19_24XX_KBC2,
7103 + V17_24XX_KBC3,
7104 + P21_24XX_KBC4,
7105 + L14_24XX_KBC5,
7106 + N19_24XX_KBC6,
7107 +
7108 + /* 24xx Menelaus Keypad GPIO */
7109 + B3__24XX_KBR5,
7110 + AA4_24XX_KBC2,
7111 + B13_24XX_KBC6,
7112 +
7113 + /* 2430 USB */
7114 + AD9_2430_USB0_PUEN,
7115 + Y11_2430_USB0_VP,
7116 + AD7_2430_USB0_VM,
7117 + AE7_2430_USB0_RCV,
7118 + AD4_2430_USB0_TXEN,
7119 + AF9_2430_USB0_SE0,
7120 + AE6_2430_USB0_DAT,
7121 + AD24_2430_USB1_SE0,
7122 + AB24_2430_USB1_RCV,
7123 + Y25_2430_USB1_TXEN,
7124 + AA26_2430_USB1_DAT,
7125 +
7126 + /* 2430 HS-USB */
7127 + AD9_2430_USB0HS_DATA3,
7128 + Y11_2430_USB0HS_DATA4,
7129 + AD7_2430_USB0HS_DATA5,
7130 + AE7_2430_USB0HS_DATA6,
7131 + AD4_2430_USB0HS_DATA2,
7132 + AF9_2430_USB0HS_DATA0,
7133 + AE6_2430_USB0HS_DATA1,
7134 + AE8_2430_USB0HS_CLK,
7135 + AD8_2430_USB0HS_DIR,
7136 + AE5_2430_USB0HS_STP,
7137 + AE9_2430_USB0HS_NXT,
7138 + AC7_2430_USB0HS_DATA7,
7139 +
7140 + /* 2430 McBSP */
7141 + AD6_2430_MCBSP_CLKS,
7142 +
7143 + AB2_2430_MCBSP1_CLKR,
7144 + AD5_2430_MCBSP1_FSR,
7145 + AA1_2430_MCBSP1_DX,
7146 + AF3_2430_MCBSP1_DR,
7147 + AB3_2430_MCBSP1_FSX,
7148 + Y9_2430_MCBSP1_CLKX,
7149 +
7150 + AC10_2430_MCBSP2_FSX,
7151 + AD16_2430_MCBSP2_CLX,
7152 + AE13_2430_MCBSP2_DX,
7153 + AD13_2430_MCBSP2_DR,
7154 + AC10_2430_MCBSP2_FSX_OFF,
7155 + AD16_2430_MCBSP2_CLX_OFF,
7156 + AE13_2430_MCBSP2_DX_OFF,
7157 + AD13_2430_MCBSP2_DR_OFF,
7158 +
7159 + AC9_2430_MCBSP3_CLKX,
7160 + AE4_2430_MCBSP3_FSX,
7161 + AE2_2430_MCBSP3_DR,
7162 + AF4_2430_MCBSP3_DX,
7163 +
7164 + N3_2430_MCBSP4_CLKX,
7165 + AD23_2430_MCBSP4_DR,
7166 + AB25_2430_MCBSP4_DX,
7167 + AC25_2430_MCBSP4_FSX,
7168 +
7169 + AE16_2430_MCBSP5_CLKX,
7170 + AF12_2430_MCBSP5_FSX,
7171 + K7_2430_MCBSP5_DX,
7172 + M1_2430_MCBSP5_DR,
7173 +
7174 + /* 2430 McSPI*/
7175 + Y18_2430_MCSPI1_CLK,
7176 + AD15_2430_MCSPI1_SIMO,
7177 + AE17_2430_MCSPI1_SOMI,
7178 + U1_2430_MCSPI1_CS0,
7179 +
7180 + /* Touchscreen GPIO */
7181 + AF19_2430_GPIO_85,
7182 +
7183 +};
7184 +
7185 +struct omap_mux_cfg {
7186 + struct pin_config *pins;
7187 + unsigned long size;
7188 + int (*cfg_reg)(const struct pin_config *cfg);
7189 +};
7190 +
7191 +#ifdef CONFIG_OMAP_MUX
7192 +/* setup pin muxing in Linux */
7193 +extern int omap1_mux_init(void);
7194 +extern int omap_mux_register(struct omap_mux_cfg *);
7195 +extern int omap_cfg_reg(unsigned long reg_cfg);
7196 +#else
7197 +/* boot loader does it all (no warnings from CONFIG_OMAP_MUX_WARNINGS) */
7198 +static inline int omap1_mux_init(void) { return 0; }
7199 +static inline int omap_cfg_reg(unsigned long reg_cfg) { return 0; }
7200 +#endif
7201 +
7202 +extern int omap2_mux_init(void);
7203 +
7204 +#endif
7205 Index: linux-2.6.37-rc1/arch/arm/plat-omap/include/mach/nand.h
7206 ===================================================================
7207 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
7208 +++ linux-2.6.37-rc1/arch/arm/plat-omap/include/mach/nand.h 2010-11-05 17:36:26.176000001 +0100
7209 @@ -0,0 +1,24 @@
7210 +/*
7211 + * arch/arm/plat-omap/include/mach/nand.h
7212 + *
7213 + * Copyright (C) 2006 Micron Technology Inc.
7214 + *
7215 + * This program is free software; you can redistribute it and/or modify
7216 + * it under the terms of the GNU General Public License version 2 as
7217 + * published by the Free Software Foundation.
7218 + */
7219 +
7220 +#include <linux/mtd/partitions.h>
7221 +
7222 +struct omap_nand_platform_data {
7223 + unsigned int options;
7224 + int cs;
7225 + int gpio_irq;
7226 + struct mtd_partition *parts;
7227 + int nr_parts;
7228 + int (*nand_setup)(void __iomem *);
7229 + int (*dev_ready)(struct omap_nand_platform_data *);
7230 + int dma_channel;
7231 + void __iomem *gpmc_cs_baseaddr;
7232 + void __iomem *gpmc_baseaddr;
7233 +};
7234 Index: linux-2.6.37-rc1/arch/arm/plat-omap/include/mach/omap1510.h
7235 ===================================================================
7236 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
7237 +++ linux-2.6.37-rc1/arch/arm/plat-omap/include/mach/omap1510.h 2010-11-05 17:36:26.176000001 +0100
7238 @@ -0,0 +1,50 @@
7239 +/* arch/arm/plat-omap/include/mach/omap1510.h
7240 + *
7241 + * Hardware definitions for TI OMAP1510 processor.
7242 + *
7243 + * Cleanup for Linux-2.6 by Dirk Behme <dirk.behme@de.bosch.com>
7244 + *
7245 + * This program is free software; you can redistribute it and/or modify it
7246 + * under the terms of the GNU General Public License as published by the
7247 + * Free Software Foundation; either version 2 of the License, or (at your
7248 + * option) any later version.
7249 + *
7250 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
7251 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
7252 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
7253 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
7254 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
7255 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
7256 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
7257 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
7258 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
7259 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
7260 + *
7261 + * You should have received a copy of the GNU General Public License along
7262 + * with this program; if not, write to the Free Software Foundation, Inc.,
7263 + * 675 Mass Ave, Cambridge, MA 02139, USA.
7264 + */
7265 +
7266 +#ifndef __ASM_ARCH_OMAP15XX_H
7267 +#define __ASM_ARCH_OMAP15XX_H
7268 +
7269 +/*
7270 + * ----------------------------------------------------------------------------
7271 + * Base addresses
7272 + * ----------------------------------------------------------------------------
7273 + */
7274 +
7275 +/* Syntax: XX_BASE = Virtual base address, XX_START = Physical base address */
7276 +
7277 +#define OMAP1510_DSP_BASE 0xE0000000
7278 +#define OMAP1510_DSP_SIZE 0x28000
7279 +#define OMAP1510_DSP_START 0xE0000000
7280 +
7281 +#define OMAP1510_DSPREG_BASE 0xE1000000
7282 +#define OMAP1510_DSPREG_SIZE SZ_128K
7283 +#define OMAP1510_DSPREG_START 0xE1000000
7284 +
7285 +#define OMAP1510_DSP_MMU_BASE (0xfffed200)
7286 +
7287 +#endif /* __ASM_ARCH_OMAP15XX_H */
7288 +
7289 Index: linux-2.6.37-rc1/arch/arm/plat-omap/include/mach/omap16xx.h
7290 ===================================================================
7291 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
7292 +++ linux-2.6.37-rc1/arch/arm/plat-omap/include/mach/omap16xx.h 2010-11-05 17:36:26.176000001 +0100
7293 @@ -0,0 +1,202 @@
7294 +/* arch/arm/plat-omap/include/mach/omap16xx.h
7295 + *
7296 + * Hardware definitions for TI OMAP1610/5912/1710 processors.
7297 + *
7298 + * Cleanup for Linux-2.6 by Dirk Behme <dirk.behme@de.bosch.com>
7299 + *
7300 + * This program is free software; you can redistribute it and/or modify it
7301 + * under the terms of the GNU General Public License as published by the
7302 + * Free Software Foundation; either version 2 of the License, or (at your
7303 + * option) any later version.
7304 + *
7305 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
7306 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
7307 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
7308 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
7309 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
7310 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
7311 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
7312 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
7313 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
7314 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
7315 + *
7316 + * You should have received a copy of the GNU General Public License along
7317 + * with this program; if not, write to the Free Software Foundation, Inc.,
7318 + * 675 Mass Ave, Cambridge, MA 02139, USA.
7319 + */
7320 +
7321 +#ifndef __ASM_ARCH_OMAP16XX_H
7322 +#define __ASM_ARCH_OMAP16XX_H
7323 +
7324 +/*
7325 + * ----------------------------------------------------------------------------
7326 + * Base addresses
7327 + * ----------------------------------------------------------------------------
7328 + */
7329 +
7330 +/* Syntax: XX_BASE = Virtual base address, XX_START = Physical base address */
7331 +
7332 +#define OMAP16XX_DSP_BASE 0xE0000000
7333 +#define OMAP16XX_DSP_SIZE 0x28000
7334 +#define OMAP16XX_DSP_START 0xE0000000
7335 +
7336 +#define OMAP16XX_DSPREG_BASE 0xE1000000
7337 +#define OMAP16XX_DSPREG_SIZE SZ_128K
7338 +#define OMAP16XX_DSPREG_START 0xE1000000
7339 +
7340 +#define OMAP16XX_SEC_BASE 0xFFFE4000
7341 +#define OMAP16XX_SEC_DES (OMAP16XX_SEC_BASE + 0x0000)
7342 +#define OMAP16XX_SEC_SHA1MD5 (OMAP16XX_SEC_BASE + 0x0800)
7343 +#define OMAP16XX_SEC_RNG (OMAP16XX_SEC_BASE + 0x1000)
7344 +
7345 +/*
7346 + * ---------------------------------------------------------------------------
7347 + * Interrupts
7348 + * ---------------------------------------------------------------------------
7349 + */
7350 +#define OMAP_IH2_0_BASE (0xfffe0000)
7351 +#define OMAP_IH2_1_BASE (0xfffe0100)
7352 +#define OMAP_IH2_2_BASE (0xfffe0200)
7353 +#define OMAP_IH2_3_BASE (0xfffe0300)
7354 +
7355 +#define OMAP_IH2_0_ITR (OMAP_IH2_0_BASE + 0x00)
7356 +#define OMAP_IH2_0_MIR (OMAP_IH2_0_BASE + 0x04)
7357 +#define OMAP_IH2_0_SIR_IRQ (OMAP_IH2_0_BASE + 0x10)
7358 +#define OMAP_IH2_0_SIR_FIQ (OMAP_IH2_0_BASE + 0x14)
7359 +#define OMAP_IH2_0_CONTROL (OMAP_IH2_0_BASE + 0x18)
7360 +#define OMAP_IH2_0_ILR0 (OMAP_IH2_0_BASE + 0x1c)
7361 +#define OMAP_IH2_0_ISR (OMAP_IH2_0_BASE + 0x9c)
7362 +
7363 +#define OMAP_IH2_1_ITR (OMAP_IH2_1_BASE + 0x00)
7364 +#define OMAP_IH2_1_MIR (OMAP_IH2_1_BASE + 0x04)
7365 +#define OMAP_IH2_1_SIR_IRQ (OMAP_IH2_1_BASE + 0x10)
7366 +#define OMAP_IH2_1_SIR_FIQ (OMAP_IH2_1_BASE + 0x14)
7367 +#define OMAP_IH2_1_CONTROL (OMAP_IH2_1_BASE + 0x18)
7368 +#define OMAP_IH2_1_ILR1 (OMAP_IH2_1_BASE + 0x1c)
7369 +#define OMAP_IH2_1_ISR (OMAP_IH2_1_BASE + 0x9c)
7370 +
7371 +#define OMAP_IH2_2_ITR (OMAP_IH2_2_BASE + 0x00)
7372 +#define OMAP_IH2_2_MIR (OMAP_IH2_2_BASE + 0x04)
7373 +#define OMAP_IH2_2_SIR_IRQ (OMAP_IH2_2_BASE + 0x10)
7374 +#define OMAP_IH2_2_SIR_FIQ (OMAP_IH2_2_BASE + 0x14)
7375 +#define OMAP_IH2_2_CONTROL (OMAP_IH2_2_BASE + 0x18)
7376 +#define OMAP_IH2_2_ILR2 (OMAP_IH2_2_BASE + 0x1c)
7377 +#define OMAP_IH2_2_ISR (OMAP_IH2_2_BASE + 0x9c)
7378 +
7379 +#define OMAP_IH2_3_ITR (OMAP_IH2_3_BASE + 0x00)
7380 +#define OMAP_IH2_3_MIR (OMAP_IH2_3_BASE + 0x04)
7381 +#define OMAP_IH2_3_SIR_IRQ (OMAP_IH2_3_BASE + 0x10)
7382 +#define OMAP_IH2_3_SIR_FIQ (OMAP_IH2_3_BASE + 0x14)
7383 +#define OMAP_IH2_3_CONTROL (OMAP_IH2_3_BASE + 0x18)
7384 +#define OMAP_IH2_3_ILR3 (OMAP_IH2_3_BASE + 0x1c)
7385 +#define OMAP_IH2_3_ISR (OMAP_IH2_3_BASE + 0x9c)
7386 +
7387 +/*
7388 + * ----------------------------------------------------------------------------
7389 + * Clocks
7390 + * ----------------------------------------------------------------------------
7391 + */
7392 +#define OMAP16XX_ARM_IDLECT3 (CLKGEN_REG_BASE + 0x24)
7393 +
7394 +/*
7395 + * ----------------------------------------------------------------------------
7396 + * Pin configuration registers
7397 + * ----------------------------------------------------------------------------
7398 + */
7399 +#define OMAP16XX_CONF_VOLTAGE_VDDSHV6 (1 << 8)
7400 +#define OMAP16XX_CONF_VOLTAGE_VDDSHV7 (1 << 9)
7401 +#define OMAP16XX_CONF_VOLTAGE_VDDSHV8 (1 << 10)
7402 +#define OMAP16XX_CONF_VOLTAGE_VDDSHV9 (1 << 11)
7403 +#define OMAP16XX_SUBLVDS_CONF_VALID (1 << 13)
7404 +
7405 +/*
7406 + * ----------------------------------------------------------------------------
7407 + * System control registers
7408 + * ----------------------------------------------------------------------------
7409 + */
7410 +#define OMAP1610_RESET_CONTROL 0xfffe1140
7411 +
7412 +/*
7413 + * ---------------------------------------------------------------------------
7414 + * TIPB bus interface
7415 + * ---------------------------------------------------------------------------
7416 + */
7417 +#define TIPB_SWITCH_BASE (0xfffbc800)
7418 +#define OMAP16XX_MMCSD2_SSW_MPU_CONF (TIPB_SWITCH_BASE + 0x160)
7419 +
7420 +/* UART3 Registers Mapping through MPU bus */
7421 +#define UART3_RHR (OMAP_UART3_BASE + 0)
7422 +#define UART3_THR (OMAP_UART3_BASE + 0)
7423 +#define UART3_DLL (OMAP_UART3_BASE + 0)
7424 +#define UART3_IER (OMAP_UART3_BASE + 4)
7425 +#define UART3_DLH (OMAP_UART3_BASE + 4)
7426 +#define UART3_IIR (OMAP_UART3_BASE + 8)
7427 +#define UART3_FCR (OMAP_UART3_BASE + 8)
7428 +#define UART3_EFR (OMAP_UART3_BASE + 8)
7429 +#define UART3_LCR (OMAP_UART3_BASE + 0x0C)
7430 +#define UART3_MCR (OMAP_UART3_BASE + 0x10)
7431 +#define UART3_XON1_ADDR1 (OMAP_UART3_BASE + 0x10)
7432 +#define UART3_XON2_ADDR2 (OMAP_UART3_BASE + 0x14)
7433 +#define UART3_LSR (OMAP_UART3_BASE + 0x14)
7434 +#define UART3_TCR (OMAP_UART3_BASE + 0x18)
7435 +#define UART3_MSR (OMAP_UART3_BASE + 0x18)
7436 +#define UART3_XOFF1 (OMAP_UART3_BASE + 0x18)
7437 +#define UART3_XOFF2 (OMAP_UART3_BASE + 0x1C)
7438 +#define UART3_SPR (OMAP_UART3_BASE + 0x1C)
7439 +#define UART3_TLR (OMAP_UART3_BASE + 0x1C)
7440 +#define UART3_MDR1 (OMAP_UART3_BASE + 0x20)
7441 +#define UART3_MDR2 (OMAP_UART3_BASE + 0x24)
7442 +#define UART3_SFLSR (OMAP_UART3_BASE + 0x28)
7443 +#define UART3_TXFLL (OMAP_UART3_BASE + 0x28)
7444 +#define UART3_RESUME (OMAP_UART3_BASE + 0x2C)
7445 +#define UART3_TXFLH (OMAP_UART3_BASE + 0x2C)
7446 +#define UART3_SFREGL (OMAP_UART3_BASE + 0x30)
7447 +#define UART3_RXFLL (OMAP_UART3_BASE + 0x30)
7448 +#define UART3_SFREGH (OMAP_UART3_BASE + 0x34)
7449 +#define UART3_RXFLH (OMAP_UART3_BASE + 0x34)
7450 +#define UART3_BLR (OMAP_UART3_BASE + 0x38)
7451 +#define UART3_ACREG (OMAP_UART3_BASE + 0x3C)
7452 +#define UART3_DIV16 (OMAP_UART3_BASE + 0x3C)
7453 +#define UART3_SCR (OMAP_UART3_BASE + 0x40)
7454 +#define UART3_SSR (OMAP_UART3_BASE + 0x44)
7455 +#define UART3_EBLR (OMAP_UART3_BASE + 0x48)
7456 +#define UART3_OSC_12M_SEL (OMAP_UART3_BASE + 0x4C)
7457 +#define UART3_MVR (OMAP_UART3_BASE + 0x50)
7458 +
7459 +/*
7460 + * ---------------------------------------------------------------------------
7461 + * Watchdog timer
7462 + * ---------------------------------------------------------------------------
7463 + */
7464 +
7465 +/* 32-bit Watchdog timer in OMAP 16XX */
7466 +#define OMAP_16XX_WATCHDOG_BASE (0xfffeb000)
7467 +#define OMAP_16XX_WIDR (OMAP_16XX_WATCHDOG_BASE + 0x00)
7468 +#define OMAP_16XX_WD_SYSCONFIG (OMAP_16XX_WATCHDOG_BASE + 0x10)
7469 +#define OMAP_16XX_WD_SYSSTATUS (OMAP_16XX_WATCHDOG_BASE + 0x14)
7470 +#define OMAP_16XX_WCLR (OMAP_16XX_WATCHDOG_BASE + 0x24)
7471 +#define OMAP_16XX_WCRR (OMAP_16XX_WATCHDOG_BASE + 0x28)
7472 +#define OMAP_16XX_WLDR (OMAP_16XX_WATCHDOG_BASE + 0x2c)
7473 +#define OMAP_16XX_WTGR (OMAP_16XX_WATCHDOG_BASE + 0x30)
7474 +#define OMAP_16XX_WWPS (OMAP_16XX_WATCHDOG_BASE + 0x34)
7475 +#define OMAP_16XX_WSPR (OMAP_16XX_WATCHDOG_BASE + 0x48)
7476 +
7477 +#define WCLR_PRE_SHIFT 5
7478 +#define WCLR_PTV_SHIFT 2
7479 +
7480 +#define WWPS_W_PEND_WSPR (1 << 4)
7481 +#define WWPS_W_PEND_WTGR (1 << 3)
7482 +#define WWPS_W_PEND_WLDR (1 << 2)
7483 +#define WWPS_W_PEND_WCRR (1 << 1)
7484 +#define WWPS_W_PEND_WCLR (1 << 0)
7485 +
7486 +#define WSPR_ENABLE_0 (0x0000bbbb)
7487 +#define WSPR_ENABLE_1 (0x00004444)
7488 +#define WSPR_DISABLE_0 (0x0000aaaa)
7489 +#define WSPR_DISABLE_1 (0x00005555)
7490 +
7491 +#define OMAP16XX_DSP_MMU_BASE (0xfffed200)
7492 +#define OMAP16XX_MAILBOX_BASE (0xfffcf000)
7493 +
7494 +#endif /* __ASM_ARCH_OMAP16XX_H */
7495 +
7496 Index: linux-2.6.37-rc1/arch/arm/plat-omap/include/mach/omap24xx.h
7497 ===================================================================
7498 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
7499 +++ linux-2.6.37-rc1/arch/arm/plat-omap/include/mach/omap24xx.h 2010-11-05 17:36:26.177000001 +0100
7500 @@ -0,0 +1,89 @@
7501 +/*
7502 + * arch/arm/plat-omap/include/mach/omap24xx.h
7503 + *
7504 + * This file contains the processor specific definitions
7505 + * of the TI OMAP24XX.
7506 + *
7507 + * Copyright (C) 2007 Texas Instruments.
7508 + * Copyright (C) 2007 Nokia Corporation.
7509 + *
7510 + * This program is free software; you can redistribute it and/or modify
7511 + * it under the terms of the GNU General Public License as published by
7512 + * the Free Software Foundation; either version 2 of the License, or
7513 + * (at your option) any later version.
7514 + *
7515 + * This program is distributed in the hope that it will be useful,
7516 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
7517 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
7518 + * GNU General Public License for more details.
7519 + *
7520 + * You should have received a copy of the GNU General Public License
7521 + * along with this program; if not, write to the Free Software
7522 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
7523 + *
7524 + */
7525 +
7526 +#ifndef __ASM_ARCH_OMAP24XX_H
7527 +#define __ASM_ARCH_OMAP24XX_H
7528 +
7529 +/*
7530 + * Please place only base defines here and put the rest in device
7531 + * specific headers. Note also that some of these defines are needed
7532 + * for omap1 to compile without adding ifdefs.
7533 + */
7534 +
7535 +#define L4_24XX_BASE 0x48000000
7536 +#define L4_WK_243X_BASE 0x49000000
7537 +#define L3_24XX_BASE 0x68000000
7538 +
7539 +/* interrupt controller */
7540 +#define OMAP24XX_IC_BASE (L4_24XX_BASE + 0xfe000)
7541 +#define OMAP24XX_IVA_INTC_BASE 0x40000000
7542 +
7543 +#define OMAP2420_CTRL_BASE L4_24XX_BASE
7544 +#define OMAP2420_32KSYNCT_BASE (L4_24XX_BASE + 0x4000)
7545 +#define OMAP2420_PRCM_BASE (L4_24XX_BASE + 0x8000)
7546 +#define OMAP2420_CM_BASE (L4_24XX_BASE + 0x8000)
7547 +#define OMAP2420_PRM_BASE OMAP2420_CM_BASE
7548 +#define OMAP2420_SDRC_BASE (L3_24XX_BASE + 0x9000)
7549 +#define OMAP2420_SMS_BASE 0x68008000
7550 +#define OMAP2420_GPMC_BASE 0x6800a000
7551 +
7552 +#define OMAP2430_32KSYNCT_BASE (L4_WK_243X_BASE + 0x20000)
7553 +#define OMAP2430_PRCM_BASE (L4_WK_243X_BASE + 0x6000)
7554 +#define OMAP2430_CM_BASE (L4_WK_243X_BASE + 0x6000)
7555 +#define OMAP2430_PRM_BASE OMAP2430_CM_BASE
7556 +
7557 +#define OMAP243X_SMS_BASE 0x6C000000
7558 +#define OMAP243X_SDRC_BASE 0x6D000000
7559 +#define OMAP243X_GPMC_BASE 0x6E000000
7560 +#define OMAP243X_SCM_BASE (L4_WK_243X_BASE + 0x2000)
7561 +#define OMAP243X_CTRL_BASE OMAP243X_SCM_BASE
7562 +#define OMAP243X_HS_BASE (L4_24XX_BASE + 0x000ac000)
7563 +
7564 +/* DSP SS */
7565 +#define OMAP2420_DSP_BASE 0x58000000
7566 +#define OMAP2420_DSP_MEM_BASE (OMAP2420_DSP_BASE + 0x0)
7567 +#define OMAP2420_DSP_IPI_BASE (OMAP2420_DSP_BASE + 0x1000000)
7568 +#define OMAP2420_DSP_MMU_BASE (OMAP2420_DSP_BASE + 0x2000000)
7569 +
7570 +#define OMAP243X_DSP_BASE 0x5C000000
7571 +#define OMAP243X_DSP_MEM_BASE (OMAP243X_DSP_BASE + 0x0)
7572 +#define OMAP243X_DSP_MMU_BASE (OMAP243X_DSP_BASE + 0x1000000)
7573 +
7574 +/* Mailbox */
7575 +#define OMAP24XX_MAILBOX_BASE (L4_24XX_BASE + 0x94000)
7576 +
7577 +/* Camera */
7578 +#define OMAP24XX_CAMERA_BASE (L4_24XX_BASE + 0x52000)
7579 +
7580 +/* Security */
7581 +#define OMAP24XX_SEC_BASE (L4_24XX_BASE + 0xA0000)
7582 +#define OMAP24XX_SEC_RNG_BASE (OMAP24XX_SEC_BASE + 0x0000)
7583 +#define OMAP24XX_SEC_DES_BASE (OMAP24XX_SEC_BASE + 0x2000)
7584 +#define OMAP24XX_SEC_SHA1MD5_BASE (OMAP24XX_SEC_BASE + 0x4000)
7585 +#define OMAP24XX_SEC_AES_BASE (OMAP24XX_SEC_BASE + 0x6000)
7586 +#define OMAP24XX_SEC_PKA_BASE (OMAP24XX_SEC_BASE + 0x8000)
7587 +
7588 +#endif /* __ASM_ARCH_OMAP24XX_H */
7589 +
7590 Index: linux-2.6.37-rc1/arch/arm/plat-omap/include/mach/omap34xx.h
7591 ===================================================================
7592 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
7593 +++ linux-2.6.37-rc1/arch/arm/plat-omap/include/mach/omap34xx.h 2010-11-05 17:36:26.177000001 +0100
7594 @@ -0,0 +1,86 @@
7595 +/*
7596 + * arch/arm/plat-omap/include/mach/omap34xx.h
7597 + *
7598 + * This file contains the processor specific definitions of the TI OMAP34XX.
7599 + *
7600 + * Copyright (C) 2007 Texas Instruments.
7601 + * Copyright (C) 2007 Nokia Corporation.
7602 + *
7603 + * This program is free software; you can redistribute it and/or modify
7604 + * it under the terms of the GNU General Public License as published by
7605 + * the Free Software Foundation; either version 2 of the License, or
7606 + * (at your option) any later version.
7607 + *
7608 + * This program is distributed in the hope that it will be useful,
7609 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
7610 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
7611 + * GNU General Public License for more details.
7612 + *
7613 + * You should have received a copy of the GNU General Public License
7614 + * along with this program; if not, write to the Free Software
7615 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
7616 + */
7617 +
7618 +#ifndef __ASM_ARCH_OMAP34XX_H
7619 +#define __ASM_ARCH_OMAP34XX_H
7620 +
7621 +/*
7622 + * Please place only base defines here and put the rest in device
7623 + * specific headers.
7624 + */
7625 +
7626 +#define L4_34XX_BASE 0x48000000
7627 +#define L4_WK_34XX_BASE 0x48300000
7628 +#define L4_PER_34XX_BASE 0x49000000
7629 +#define L4_EMU_34XX_BASE 0x54000000
7630 +#define L3_34XX_BASE 0x68000000
7631 +
7632 +#define OMAP3430_32KSYNCT_BASE 0x48320000
7633 +#define OMAP3430_CM_BASE 0x48004800
7634 +#define OMAP3430_PRM_BASE 0x48306800
7635 +#define OMAP343X_SMS_BASE 0x6C000000
7636 +#define OMAP343X_SDRC_BASE 0x6D000000
7637 +#define OMAP34XX_GPMC_BASE 0x6E000000
7638 +#define OMAP343X_SCM_BASE 0x48002000
7639 +#define OMAP343X_CTRL_BASE OMAP343X_SCM_BASE
7640 +
7641 +#define OMAP34XX_IC_BASE 0x48200000
7642 +
7643 +#define OMAP3430_ISP_BASE (L4_34XX_BASE + 0xBC000)
7644 +#define OMAP3430_ISP_CBUFF_BASE (OMAP3430_ISP_BASE + 0x0100)
7645 +#define OMAP3430_ISP_CCP2_BASE (OMAP3430_ISP_BASE + 0x0400)
7646 +#define OMAP3430_ISP_CCDC_BASE (OMAP3430_ISP_BASE + 0x0600)
7647 +#define OMAP3430_ISP_HIST_BASE (OMAP3430_ISP_BASE + 0x0A00)
7648 +#define OMAP3430_ISP_H3A_BASE (OMAP3430_ISP_BASE + 0x0C00)
7649 +#define OMAP3430_ISP_PREV_BASE (OMAP3430_ISP_BASE + 0x0E00)
7650 +#define OMAP3430_ISP_RESZ_BASE (OMAP3430_ISP_BASE + 0x1000)
7651 +#define OMAP3430_ISP_SBL_BASE (OMAP3430_ISP_BASE + 0x1200)
7652 +#define OMAP3430_ISP_MMU_BASE (OMAP3430_ISP_BASE + 0x1400)
7653 +#define OMAP3430_ISP_CSI2A_BASE (OMAP3430_ISP_BASE + 0x1800)
7654 +#define OMAP3430_ISP_CSI2PHY_BASE (OMAP3430_ISP_BASE + 0x1970)
7655 +
7656 +#define OMAP3430_ISP_END (OMAP3430_ISP_BASE + 0x06F)
7657 +#define OMAP3430_ISP_CBUFF_END (OMAP3430_ISP_CBUFF_BASE + 0x077)
7658 +#define OMAP3430_ISP_CCP2_END (OMAP3430_ISP_CCP2_BASE + 0x1EF)
7659 +#define OMAP3430_ISP_CCDC_END (OMAP3430_ISP_CCDC_BASE + 0x0A7)
7660 +#define OMAP3430_ISP_HIST_END (OMAP3430_ISP_HIST_BASE + 0x047)
7661 +#define OMAP3430_ISP_H3A_END (OMAP3430_ISP_H3A_BASE + 0x05F)
7662 +#define OMAP3430_ISP_PREV_END (OMAP3430_ISP_PREV_BASE + 0x09F)
7663 +#define OMAP3430_ISP_RESZ_END (OMAP3430_ISP_RESZ_BASE + 0x0AB)
7664 +#define OMAP3430_ISP_SBL_END (OMAP3430_ISP_SBL_BASE + 0x0FB)
7665 +#define OMAP3430_ISP_MMU_END (OMAP3430_ISP_MMU_BASE + 0x06F)
7666 +#define OMAP3430_ISP_CSI2A_END (OMAP3430_ISP_CSI2A_BASE + 0x16F)
7667 +#define OMAP3430_ISP_CSI2PHY_END (OMAP3430_ISP_CSI2PHY_BASE + 0x007)
7668 +
7669 +#define OMAP34XX_HSUSB_OTG_BASE (L4_34XX_BASE + 0xAB000)
7670 +#define OMAP34XX_USBTLL_BASE (L4_34XX_BASE + 0x62000)
7671 +#define OMAP34XX_UHH_CONFIG_BASE (L4_34XX_BASE + 0x64000)
7672 +#define OMAP34XX_OHCI_BASE (L4_34XX_BASE + 0x64400)
7673 +#define OMAP34XX_EHCI_BASE (L4_34XX_BASE + 0x64800)
7674 +#define OMAP34XX_SR1_BASE 0x480C9000
7675 +#define OMAP34XX_SR2_BASE 0x480CB000
7676 +
7677 +#define OMAP34XX_MAILBOX_BASE (L4_34XX_BASE + 0x94000)
7678 +
7679 +#endif /* __ASM_ARCH_OMAP34XX_H */
7680 +
7681 Index: linux-2.6.37-rc1/arch/arm/plat-omap/include/mach/omap44xx.h
7682 ===================================================================
7683 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
7684 +++ linux-2.6.37-rc1/arch/arm/plat-omap/include/mach/omap44xx.h 2010-11-05 17:36:26.177000001 +0100
7685 @@ -0,0 +1,48 @@
7686 +/*:
7687 + * Address mappings and base address for OMAP4 interconnects
7688 + * and peripherals.
7689 + *
7690 + * Copyright (C) 2009 Texas Instruments
7691 + *
7692 + * Author: Santosh Shilimkar <santosh.shilimkar@ti.com>
7693 + *
7694 + * This program is free software; you can redistribute it and/or modify
7695 + * it under the terms of the GNU General Public License version 2 as
7696 + * published by the Free Software Foundation.
7697 + */
7698 +#ifndef __ASM_ARCH_OMAP44XX_H
7699 +#define __ASM_ARCH_OMAP44XX_H
7700 +
7701 +/*
7702 + * Please place only base defines here and put the rest in device
7703 + * specific headers.
7704 + */
7705 +#define L4_44XX_BASE 0x4a000000
7706 +#define L4_WK_44XX_BASE 0x4a300000
7707 +#define L4_PER_44XX_BASE 0x48000000
7708 +#define L4_EMU_44XX_BASE 0x54000000
7709 +#define L3_44XX_BASE 0x44000000
7710 +#define OMAP44XX_EMIF1_BASE 0x4c000000
7711 +#define OMAP44XX_EMIF2_BASE 0x4d000000
7712 +#define OMAP44XX_DMM_BASE 0x4e000000
7713 +#define OMAP4430_32KSYNCT_BASE 0x4a304000
7714 +#define OMAP4430_CM1_BASE 0x4a004000
7715 +#define OMAP4430_CM_BASE OMAP4430_CM1_BASE
7716 +#define OMAP4430_CM2_BASE 0x4a008000
7717 +#define OMAP4430_PRM_BASE 0x4a306000
7718 +#define OMAP44XX_GPMC_BASE 0x50000000
7719 +#define OMAP443X_SCM_BASE 0x4a002000
7720 +#define OMAP443X_CTRL_BASE OMAP443X_SCM_BASE
7721 +#define OMAP44XX_IC_BASE 0x48200000
7722 +#define OMAP44XX_IVA_INTC_BASE 0x40000000
7723 +#define IRQ_SIR_IRQ 0x0040
7724 +#define OMAP44XX_GIC_DIST_BASE 0x48241000
7725 +#define OMAP44XX_GIC_CPU_BASE 0x48240100
7726 +#define OMAP44XX_SCU_BASE 0x48240000
7727 +#define OMAP44XX_LOCAL_TWD_BASE 0x48240600
7728 +#define OMAP44XX_WKUPGEN_BASE 0x48281000
7729 +
7730 +#define OMAP44XX_MAILBOX_BASE (L4_44XX_BASE + 0xF4000)
7731 +
7732 +#endif /* __ASM_ARCH_OMAP44XX_H */
7733 +
7734 Index: linux-2.6.37-rc1/arch/arm/plat-omap/include/mach/omap730.h
7735 ===================================================================
7736 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
7737 +++ linux-2.6.37-rc1/arch/arm/plat-omap/include/mach/omap730.h 2010-11-05 17:36:26.177000001 +0100
7738 @@ -0,0 +1,102 @@
7739 +/* arch/arm/plat-omap/include/mach/omap730.h
7740 + *
7741 + * Hardware definitions for TI OMAP730 processor.
7742 + *
7743 + * Cleanup for Linux-2.6 by Dirk Behme <dirk.behme@de.bosch.com>
7744 + *
7745 + * This program is free software; you can redistribute it and/or modify it
7746 + * under the terms of the GNU General Public License as published by the
7747 + * Free Software Foundation; either version 2 of the License, or (at your
7748 + * option) any later version.
7749 + *
7750 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
7751 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
7752 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
7753 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
7754 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
7755 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
7756 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
7757 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
7758 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
7759 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
7760 + *
7761 + * You should have received a copy of the GNU General Public License along
7762 + * with this program; if not, write to the Free Software Foundation, Inc.,
7763 + * 675 Mass Ave, Cambridge, MA 02139, USA.
7764 + */
7765 +
7766 +#ifndef __ASM_ARCH_OMAP730_H
7767 +#define __ASM_ARCH_OMAP730_H
7768 +
7769 +/*
7770 + * ----------------------------------------------------------------------------
7771 + * Base addresses
7772 + * ----------------------------------------------------------------------------
7773 + */
7774 +
7775 +/* Syntax: XX_BASE = Virtual base address, XX_START = Physical base address */
7776 +
7777 +#define OMAP730_DSP_BASE 0xE0000000
7778 +#define OMAP730_DSP_SIZE 0x50000
7779 +#define OMAP730_DSP_START 0xE0000000
7780 +
7781 +#define OMAP730_DSPREG_BASE 0xE1000000
7782 +#define OMAP730_DSPREG_SIZE SZ_128K
7783 +#define OMAP730_DSPREG_START 0xE1000000
7784 +
7785 +/*
7786 + * ----------------------------------------------------------------------------
7787 + * OMAP730 specific configuration registers
7788 + * ----------------------------------------------------------------------------
7789 + */
7790 +#define OMAP730_CONFIG_BASE 0xfffe1000
7791 +#define OMAP730_IO_CONF_0 0xfffe1070
7792 +#define OMAP730_IO_CONF_1 0xfffe1074
7793 +#define OMAP730_IO_CONF_2 0xfffe1078
7794 +#define OMAP730_IO_CONF_3 0xfffe107c
7795 +#define OMAP730_IO_CONF_4 0xfffe1080
7796 +#define OMAP730_IO_CONF_5 0xfffe1084
7797 +#define OMAP730_IO_CONF_6 0xfffe1088
7798 +#define OMAP730_IO_CONF_7 0xfffe108c
7799 +#define OMAP730_IO_CONF_8 0xfffe1090
7800 +#define OMAP730_IO_CONF_9 0xfffe1094
7801 +#define OMAP730_IO_CONF_10 0xfffe1098
7802 +#define OMAP730_IO_CONF_11 0xfffe109c
7803 +#define OMAP730_IO_CONF_12 0xfffe10a0
7804 +#define OMAP730_IO_CONF_13 0xfffe10a4
7805 +
7806 +#define OMAP730_MODE_1 0xfffe1010
7807 +#define OMAP730_MODE_2 0xfffe1014
7808 +
7809 +/* CSMI specials: in terms of base + offset */
7810 +#define OMAP730_MODE2_OFFSET 0x14
7811 +
7812 +/*
7813 + * ----------------------------------------------------------------------------
7814 + * OMAP730 traffic controller configuration registers
7815 + * ----------------------------------------------------------------------------
7816 + */
7817 +#define OMAP730_FLASH_CFG_0 0xfffecc10
7818 +#define OMAP730_FLASH_ACFG_0 0xfffecc50
7819 +#define OMAP730_FLASH_CFG_1 0xfffecc14
7820 +#define OMAP730_FLASH_ACFG_1 0xfffecc54
7821 +
7822 +/*
7823 + * ----------------------------------------------------------------------------
7824 + * OMAP730 DSP control registers
7825 + * ----------------------------------------------------------------------------
7826 + */
7827 +#define OMAP730_ICR_BASE 0xfffbb800
7828 +#define OMAP730_DSP_M_CTL 0xfffbb804
7829 +#define OMAP730_DSP_MMU_BASE 0xfffed200
7830 +
7831 +/*
7832 + * ----------------------------------------------------------------------------
7833 + * OMAP730 PCC_UPLD configuration registers
7834 + * ----------------------------------------------------------------------------
7835 + */
7836 +#define OMAP730_PCC_UPLD_CTRL_BASE (0xfffe0900)
7837 +#define OMAP730_PCC_UPLD_CTRL (OMAP730_PCC_UPLD_CTRL_BASE + 0x00)
7838 +
7839 +#endif /* __ASM_ARCH_OMAP730_H */
7840 +
7841 Index: linux-2.6.37-rc1/arch/arm/plat-omap/include/mach/omap7xx.h
7842 ===================================================================
7843 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
7844 +++ linux-2.6.37-rc1/arch/arm/plat-omap/include/mach/omap7xx.h 2010-11-05 17:36:26.177000001 +0100
7845 @@ -0,0 +1,104 @@
7846 +/* arch/arm/plat-omap/include/mach/omap7xx.h
7847 + *
7848 + * Hardware definitions for TI OMAP7XX processor.
7849 + *
7850 + * Cleanup for Linux-2.6 by Dirk Behme <dirk.behme@de.bosch.com>
7851 + * Adapted for omap850 by Zebediah C. McClure <zmc@lurian.net>
7852 + * Adapted for omap7xx by Alistair Buxton <a.j.buxton@gmail.com>
7853 + *
7854 + * This program is free software; you can redistribute it and/or modify it
7855 + * under the terms of the GNU General Public License as published by the
7856 + * Free Software Foundation; either version 2 of the License, or (at your
7857 + * option) any later version.
7858 + *
7859 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
7860 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
7861 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
7862 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
7863 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
7864 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
7865 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
7866 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
7867 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
7868 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
7869 + *
7870 + * You should have received a copy of the GNU General Public License along
7871 + * with this program; if not, write to the Free Software Foundation, Inc.,
7872 + * 675 Mass Ave, Cambridge, MA 02139, USA.
7873 + */
7874 +
7875 +#ifndef __ASM_ARCH_OMAP7XX_H
7876 +#define __ASM_ARCH_OMAP7XX_H
7877 +
7878 +/*
7879 + * ----------------------------------------------------------------------------
7880 + * Base addresses
7881 + * ----------------------------------------------------------------------------
7882 + */
7883 +
7884 +/* Syntax: XX_BASE = Virtual base address, XX_START = Physical base address */
7885 +
7886 +#define OMAP7XX_DSP_BASE 0xE0000000
7887 +#define OMAP7XX_DSP_SIZE 0x50000
7888 +#define OMAP7XX_DSP_START 0xE0000000
7889 +
7890 +#define OMAP7XX_DSPREG_BASE 0xE1000000
7891 +#define OMAP7XX_DSPREG_SIZE SZ_128K
7892 +#define OMAP7XX_DSPREG_START 0xE1000000
7893 +
7894 +/*
7895 + * ----------------------------------------------------------------------------
7896 + * OMAP7XX specific configuration registers
7897 + * ----------------------------------------------------------------------------
7898 + */
7899 +#define OMAP7XX_CONFIG_BASE 0xfffe1000
7900 +#define OMAP7XX_IO_CONF_0 0xfffe1070
7901 +#define OMAP7XX_IO_CONF_1 0xfffe1074
7902 +#define OMAP7XX_IO_CONF_2 0xfffe1078
7903 +#define OMAP7XX_IO_CONF_3 0xfffe107c
7904 +#define OMAP7XX_IO_CONF_4 0xfffe1080
7905 +#define OMAP7XX_IO_CONF_5 0xfffe1084
7906 +#define OMAP7XX_IO_CONF_6 0xfffe1088
7907 +#define OMAP7XX_IO_CONF_7 0xfffe108c
7908 +#define OMAP7XX_IO_CONF_8 0xfffe1090
7909 +#define OMAP7XX_IO_CONF_9 0xfffe1094
7910 +#define OMAP7XX_IO_CONF_10 0xfffe1098
7911 +#define OMAP7XX_IO_CONF_11 0xfffe109c
7912 +#define OMAP7XX_IO_CONF_12 0xfffe10a0
7913 +#define OMAP7XX_IO_CONF_13 0xfffe10a4
7914 +
7915 +#define OMAP7XX_MODE_1 0xfffe1010
7916 +#define OMAP7XX_MODE_2 0xfffe1014
7917 +
7918 +/* CSMI specials: in terms of base + offset */
7919 +#define OMAP7XX_MODE2_OFFSET 0x14
7920 +
7921 +/*
7922 + * ----------------------------------------------------------------------------
7923 + * OMAP7XX traffic controller configuration registers
7924 + * ----------------------------------------------------------------------------
7925 + */
7926 +#define OMAP7XX_FLASH_CFG_0 0xfffecc10
7927 +#define OMAP7XX_FLASH_ACFG_0 0xfffecc50
7928 +#define OMAP7XX_FLASH_CFG_1 0xfffecc14
7929 +#define OMAP7XX_FLASH_ACFG_1 0xfffecc54
7930 +
7931 +/*
7932 + * ----------------------------------------------------------------------------
7933 + * OMAP7XX DSP control registers
7934 + * ----------------------------------------------------------------------------
7935 + */
7936 +#define OMAP7XX_ICR_BASE 0xfffbb800
7937 +#define OMAP7XX_DSP_M_CTL 0xfffbb804
7938 +#define OMAP7XX_DSP_MMU_BASE 0xfffed200
7939 +
7940 +/*
7941 + * ----------------------------------------------------------------------------
7942 + * OMAP7XX PCC_UPLD configuration registers
7943 + * ----------------------------------------------------------------------------
7944 + */
7945 +#define OMAP7XX_PCC_UPLD_CTRL_BASE (0xfffe0900)
7946 +#define OMAP7XX_PCC_UPLD_CTRL (OMAP7XX_PCC_UPLD_CTRL_BASE + 0x00)
7947 +
7948 +#endif /* __ASM_ARCH_OMAP7XX_H */
7949 +
7950 Index: linux-2.6.37-rc1/arch/arm/plat-omap/include/mach/omap850.h
7951 ===================================================================
7952 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
7953 +++ linux-2.6.37-rc1/arch/arm/plat-omap/include/mach/omap850.h 2010-11-05 17:36:26.177000001 +0100
7954 @@ -0,0 +1,102 @@
7955 +/* arch/arm/plat-omap/include/mach/omap850.h
7956 + *
7957 + * Hardware definitions for TI OMAP850 processor.
7958 + *
7959 + * Derived from omap730.h by Zebediah C. McClure <zmc@lurian.net>
7960 + *
7961 + * This program is free software; you can redistribute it and/or modify it
7962 + * under the terms of the GNU General Public License as published by the
7963 + * Free Software Foundation; either version 2 of the License, or (at your
7964 + * option) any later version.
7965 + *
7966 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
7967 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
7968 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
7969 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
7970 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
7971 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
7972 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
7973 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
7974 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
7975 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
7976 + *
7977 + * You should have received a copy of the GNU General Public License along
7978 + * with this program; if not, write to the Free Software Foundation, Inc.,
7979 + * 675 Mass Ave, Cambridge, MA 02139, USA.
7980 + */
7981 +
7982 +#ifndef __ASM_ARCH_OMAP850_H
7983 +#define __ASM_ARCH_OMAP850_H
7984 +
7985 +/*
7986 + * ----------------------------------------------------------------------------
7987 + * Base addresses
7988 + * ----------------------------------------------------------------------------
7989 + */
7990 +
7991 +/* Syntax: XX_BASE = Virtual base address, XX_START = Physical base address */
7992 +
7993 +#define OMAP850_DSP_BASE 0xE0000000
7994 +#define OMAP850_DSP_SIZE 0x50000
7995 +#define OMAP850_DSP_START 0xE0000000
7996 +
7997 +#define OMAP850_DSPREG_BASE 0xE1000000
7998 +#define OMAP850_DSPREG_SIZE SZ_128K
7999 +#define OMAP850_DSPREG_START 0xE1000000
8000 +
8001 +/*
8002 + * ----------------------------------------------------------------------------
8003 + * OMAP850 specific configuration registers
8004 + * ----------------------------------------------------------------------------
8005 + */
8006 +#define OMAP850_CONFIG_BASE 0xfffe1000
8007 +#define OMAP850_IO_CONF_0 0xfffe1070
8008 +#define OMAP850_IO_CONF_1 0xfffe1074
8009 +#define OMAP850_IO_CONF_2 0xfffe1078
8010 +#define OMAP850_IO_CONF_3 0xfffe107c
8011 +#define OMAP850_IO_CONF_4 0xfffe1080
8012 +#define OMAP850_IO_CONF_5 0xfffe1084
8013 +#define OMAP850_IO_CONF_6 0xfffe1088
8014 +#define OMAP850_IO_CONF_7 0xfffe108c
8015 +#define OMAP850_IO_CONF_8 0xfffe1090
8016 +#define OMAP850_IO_CONF_9 0xfffe1094
8017 +#define OMAP850_IO_CONF_10 0xfffe1098
8018 +#define OMAP850_IO_CONF_11 0xfffe109c
8019 +#define OMAP850_IO_CONF_12 0xfffe10a0
8020 +#define OMAP850_IO_CONF_13 0xfffe10a4
8021 +
8022 +#define OMAP850_MODE_1 0xfffe1010
8023 +#define OMAP850_MODE_2 0xfffe1014
8024 +
8025 +/* CSMI specials: in terms of base + offset */
8026 +#define OMAP850_MODE2_OFFSET 0x14
8027 +
8028 +/*
8029 + * ----------------------------------------------------------------------------
8030 + * OMAP850 traffic controller configuration registers
8031 + * ----------------------------------------------------------------------------
8032 + */
8033 +#define OMAP850_FLASH_CFG_0 0xfffecc10
8034 +#define OMAP850_FLASH_ACFG_0 0xfffecc50
8035 +#define OMAP850_FLASH_CFG_1 0xfffecc14
8036 +#define OMAP850_FLASH_ACFG_1 0xfffecc54
8037 +
8038 +/*
8039 + * ----------------------------------------------------------------------------
8040 + * OMAP850 DSP control registers
8041 + * ----------------------------------------------------------------------------
8042 + */
8043 +#define OMAP850_ICR_BASE 0xfffbb800
8044 +#define OMAP850_DSP_M_CTL 0xfffbb804
8045 +#define OMAP850_DSP_MMU_BASE 0xfffed200
8046 +
8047 +/*
8048 + * ----------------------------------------------------------------------------
8049 + * OMAP850 PCC_UPLD configuration registers
8050 + * ----------------------------------------------------------------------------
8051 + */
8052 +#define OMAP850_PCC_UPLD_CTRL_BASE (0xfffe0900)
8053 +#define OMAP850_PCC_UPLD_CTRL (OMAP850_PCC_UPLD_CTRL_BASE + 0x00)
8054 +
8055 +#endif /* __ASM_ARCH_OMAP850_H */
8056 +
8057 Index: linux-2.6.37-rc1/arch/arm/plat-omap/include/mach/omap-alsa.h
8058 ===================================================================
8059 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
8060 +++ linux-2.6.37-rc1/arch/arm/plat-omap/include/mach/omap-alsa.h 2010-11-05 17:36:26.177000001 +0100
8061 @@ -0,0 +1,123 @@
8062 +/*
8063 + * arch/arm/plat-omap/include/mach/omap-alsa.h
8064 + *
8065 + * Alsa Driver for AIC23 and TSC2101 codecs on OMAP platform boards.
8066 + *
8067 + * Copyright (C) 2006 Mika Laitio <lamikr@cc.jyu.fi>
8068 + *
8069 + * Copyright (C) 2005 Instituto Nokia de Tecnologia - INdT - Manaus Brazil
8070 + * Written by Daniel Petrini, David Cohen, Anderson Briglia
8071 + * {daniel.petrini, david.cohen, anderson.briglia}@indt.org.br
8072 + *
8073 + * This program is free software; you can redistribute it and/or modify it
8074 + * under the terms of the GNU General Public License as published by the
8075 + * Free Software Foundation; either version 2 of the License, or (at your
8076 + * option) any later version.
8077 + *
8078 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
8079 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
8080 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
8081 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
8082 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
8083 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
8084 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
8085 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
8086 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
8087 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
8088 + *
8089 + * You should have received a copy of the GNU General Public License along
8090 + * with this program; if not, write to the Free Software Foundation, Inc.,
8091 + * 675 Mass Ave, Cambridge, MA 02139, USA.
8092 + *
8093 + * History
8094 + * -------
8095 + *
8096 + * 2005/07/25 INdT-10LE Kernel Team - Alsa driver for omap osk,
8097 + * original version based in sa1100 driver
8098 + * and omap oss driver.
8099 + */
8100 +
8101 +#ifndef __OMAP_ALSA_H
8102 +#define __OMAP_ALSA_H
8103 +
8104 +#include <plat/dma.h>
8105 +#include <sound/core.h>
8106 +#include <sound/pcm.h>
8107 +#include <plat/mcbsp.h>
8108 +#include <linux/platform_device.h>
8109 +
8110 +#define DMA_BUF_SIZE (1024 * 8)
8111 +
8112 +/*
8113 + * Buffer management for alsa and dma
8114 + */
8115 +struct audio_stream {
8116 + char *id; /* identification string */
8117 + int stream_id; /* numeric identification */
8118 + int dma_dev; /* dma number of that device */
8119 + int *lch; /* Chain of channels this stream is linked to */
8120 + char started; /* to store if the chain was started or not */
8121 + int dma_q_head; /* DMA Channel Q Head */
8122 + int dma_q_tail; /* DMA Channel Q Tail */
8123 + char dma_q_count; /* DMA Channel Q Count */
8124 + int active:1; /* we are using this stream for transfer now */
8125 + int period; /* current transfer period */
8126 + int periods; /* current count of periods registerd in the DMA engine */
8127 + spinlock_t dma_lock; /* for locking in DMA operations */
8128 + struct snd_pcm_substream *stream; /* the pcm stream */
8129 + unsigned linked:1; /* dma channels linked */
8130 + int offset; /* store start position of the last period in the alsa buffer */
8131 + int (*hw_start)(void); /* interface to start HW interface, e.g. McBSP */
8132 + int (*hw_stop)(void); /* interface to stop HW interface, e.g. McBSP */
8133 +};
8134 +
8135 +/*
8136 + * Alsa card structure for aic23
8137 + */
8138 +struct snd_card_omap_codec {
8139 + struct snd_card *card;
8140 + struct snd_pcm *pcm;
8141 + long samplerate;
8142 + struct audio_stream s[2]; /* playback & capture */
8143 +};
8144 +
8145 +/* Codec specific information and function pointers.
8146 + * Codec (omap-alsa-aic23.c and omap-alsa-tsc2101.c)
8147 + * are responsible for defining the function pointers.
8148 + */
8149 +struct omap_alsa_codec_config {
8150 + char *name;
8151 + struct omap_mcbsp_reg_cfg *mcbsp_regs_alsa;
8152 + struct snd_pcm_hw_constraint_list *hw_constraints_rates;
8153 + struct snd_pcm_hardware *snd_omap_alsa_playback;
8154 + struct snd_pcm_hardware *snd_omap_alsa_capture;
8155 + void (*codec_configure_dev)(void);
8156 + void (*codec_set_samplerate)(long);
8157 + void (*codec_clock_setup)(void);
8158 + int (*codec_clock_on)(void);
8159 + int (*codec_clock_off)(void);
8160 + int (*get_default_samplerate)(void);
8161 +};
8162 +
8163 +/*********** Mixer function prototypes *************************/
8164 +int snd_omap_mixer(struct snd_card_omap_codec *);
8165 +void snd_omap_init_mixer(void);
8166 +
8167 +#ifdef CONFIG_PM
8168 +void snd_omap_suspend_mixer(void);
8169 +void snd_omap_resume_mixer(void);
8170 +#endif
8171 +
8172 +int snd_omap_alsa_post_probe(struct platform_device *pdev, struct omap_alsa_codec_config *config);
8173 +int snd_omap_alsa_remove(struct platform_device *pdev);
8174 +#ifdef CONFIG_PM
8175 +int snd_omap_alsa_suspend(struct platform_device *pdev, pm_message_t state);
8176 +int snd_omap_alsa_resume(struct platform_device *pdev);
8177 +#else
8178 +#define snd_omap_alsa_suspend NULL
8179 +#define snd_omap_alsa_resume NULL
8180 +#endif
8181 +
8182 +void callback_omap_alsa_sound_dma(void *);
8183 +
8184 +#endif
8185 Index: linux-2.6.37-rc1/arch/arm/plat-omap/include/mach/omap_device.h
8186 ===================================================================
8187 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
8188 +++ linux-2.6.37-rc1/arch/arm/plat-omap/include/mach/omap_device.h 2010-11-05 17:36:26.177000001 +0100
8189 @@ -0,0 +1,143 @@
8190 +/*
8191 + * omap_device headers
8192 + *
8193 + * Copyright (C) 2009 Nokia Corporation
8194 + * Paul Walmsley
8195 + *
8196 + * Developed in collaboration with (alphabetical order): Benoit
8197 + * Cousson, Kevin Hilman, Tony Lindgren, Rajendra Nayak, Vikram
8198 + * Pandita, Sakari Poussa, Anand Sawant, Santosh Shilimkar, Richard
8199 + * Woodruff
8200 + *
8201 + * This program is free software; you can redistribute it and/or modify
8202 + * it under the terms of the GNU General Public License version 2 as
8203 + * published by the Free Software Foundation.
8204 + *
8205 + * Eventually this type of functionality should either be
8206 + * a) implemented via arch-specific pointers in platform_device
8207 + * or
8208 + * b) implemented as a proper omap_bus/omap_device in Linux, no more
8209 + * platform_device
8210 + *
8211 + * omap_device differs from omap_hwmod in that it includes external
8212 + * (e.g., board- and system-level) integration details. omap_hwmod
8213 + * stores hardware data that is invariant for a given OMAP chip.
8214 + *
8215 + * To do:
8216 + * - GPIO integration
8217 + * - regulator integration
8218 + *
8219 + */
8220 +#ifndef __ARCH_ARM_PLAT_OMAP_INCLUDE_MACH_OMAP_DEVICE_H
8221 +#define __ARCH_ARM_PLAT_OMAP_INCLUDE_MACH_OMAP_DEVICE_H
8222 +
8223 +#include <linux/kernel.h>
8224 +#include <linux/platform_device.h>
8225 +
8226 +#include <plat/omap_hwmod.h>
8227 +
8228 +/* omap_device._state values */
8229 +#define OMAP_DEVICE_STATE_UNKNOWN 0
8230 +#define OMAP_DEVICE_STATE_ENABLED 1
8231 +#define OMAP_DEVICE_STATE_IDLE 2
8232 +#define OMAP_DEVICE_STATE_SHUTDOWN 3
8233 +
8234 +/**
8235 + * struct omap_device - omap_device wrapper for platform_devices
8236 + * @pdev: platform_device
8237 + * @hwmods: (one .. many per omap_device)
8238 + * @hwmods_cnt: ARRAY_SIZE() of @hwmods
8239 + * @pm_lats: ptr to an omap_device_pm_latency table
8240 + * @pm_lats_cnt: ARRAY_SIZE() of what is passed to @pm_lats
8241 + * @pm_lat_level: array index of the last odpl entry executed - -1 if never
8242 + * @dev_wakeup_lat: dev wakeup latency in nanoseconds
8243 + * @_dev_wakeup_lat_limit: dev wakeup latency limit in nsec - set by OMAP PM
8244 + * @_state: one of OMAP_DEVICE_STATE_* (see above)
8245 + * @flags: device flags
8246 + *
8247 + * Integrates omap_hwmod data into Linux platform_device.
8248 + *
8249 + * Field names beginning with underscores are for the internal use of
8250 + * the omap_device code.
8251 + *
8252 + */
8253 +struct omap_device {
8254 + struct platform_device pdev;
8255 + struct omap_hwmod **hwmods;
8256 + struct omap_device_pm_latency *pm_lats;
8257 + u32 dev_wakeup_lat;
8258 + u32 _dev_wakeup_lat_limit;
8259 + u8 pm_lats_cnt;
8260 + s8 pm_lat_level;
8261 + u8 hwmods_cnt;
8262 + u8 _state;
8263 +};
8264 +
8265 +/* Device driver interface (call via platform_data fn ptrs) */
8266 +
8267 +int omap_device_enable(struct platform_device *pdev);
8268 +int omap_device_idle(struct platform_device *pdev);
8269 +int omap_device_shutdown(struct platform_device *pdev);
8270 +
8271 +/* Core code interface */
8272 +
8273 +int omap_device_count_resources(struct omap_device *od);
8274 +int omap_device_fill_resources(struct omap_device *od, struct resource *res);
8275 +
8276 +struct omap_device *omap_device_build(const char *pdev_name, int pdev_id,
8277 + struct omap_hwmod *oh, void *pdata,
8278 + int pdata_len,
8279 + struct omap_device_pm_latency *pm_lats,
8280 + int pm_lats_cnt);
8281 +
8282 +struct omap_device *omap_device_build_ss(const char *pdev_name, int pdev_id,
8283 + struct omap_hwmod **oh, int oh_cnt,
8284 + void *pdata, int pdata_len,
8285 + struct omap_device_pm_latency *pm_lats,
8286 + int pm_lats_cnt);
8287 +
8288 +int omap_device_register(struct omap_device *od);
8289 +
8290 +/* OMAP PM interface */
8291 +int omap_device_align_pm_lat(struct platform_device *pdev,
8292 + u32 new_wakeup_lat_limit);
8293 +struct powerdomain *omap_device_get_pwrdm(struct omap_device *od);
8294 +
8295 +/* Other */
8296 +
8297 +int omap_device_idle_hwmods(struct omap_device *od);
8298 +int omap_device_enable_hwmods(struct omap_device *od);
8299 +
8300 +int omap_device_disable_clocks(struct omap_device *od);
8301 +int omap_device_enable_clocks(struct omap_device *od);
8302 +
8303 +
8304 +/*
8305 + * Entries should be kept in latency order ascending
8306 + *
8307 + * deact_lat is the maximum number of microseconds required to complete
8308 + * deactivate_func() at the device's slowest OPP.
8309 + *
8310 + * act_lat is the maximum number of microseconds required to complete
8311 + * activate_func() at the device's slowest OPP.
8312 + *
8313 + * This will result in some suboptimal power management decisions at fast
8314 + * OPPs, but avoids having to recompute all device power management decisions
8315 + * if the system shifts from a fast OPP to a slow OPP (in order to meet
8316 + * latency requirements).
8317 + *
8318 + * XXX should deactivate_func/activate_func() take platform_device pointers
8319 + * rather than omap_device pointers?
8320 + */
8321 +struct omap_device_pm_latency {
8322 + u32 deactivate_lat;
8323 + int (*deactivate_func)(struct omap_device *od);
8324 + u32 activate_lat;
8325 + int (*activate_func)(struct omap_device *od);
8326 +};
8327 +
8328 +
8329 +/* Get omap_device pointer from platform_device pointer */
8330 +#define to_omap_device(x) container_of((x), struct omap_device, pdev)
8331 +
8332 +#endif
8333 Index: linux-2.6.37-rc1/arch/arm/plat-omap/include/mach/omap_hwmod.h
8334 ===================================================================
8335 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
8336 +++ linux-2.6.37-rc1/arch/arm/plat-omap/include/mach/omap_hwmod.h 2010-11-05 17:36:26.178000001 +0100
8337 @@ -0,0 +1,467 @@
8338 +/*
8339 + * omap_hwmod macros, structures
8340 + *
8341 + * Copyright (C) 2009 Nokia Corporation
8342 + * Paul Walmsley
8343 + *
8344 + * Created in collaboration with (alphabetical order): Benoit Cousson,
8345 + * Kevin Hilman, Tony Lindgren, Rajendra Nayak, Vikram Pandita, Sakari
8346 + * Poussa, Anand Sawant, Santosh Shilimkar, Richard Woodruff
8347 + *
8348 + * This program is free software; you can redistribute it and/or modify
8349 + * it under the terms of the GNU General Public License version 2 as
8350 + * published by the Free Software Foundation.
8351 + *
8352 + * These headers and macros are used to define OMAP on-chip module
8353 + * data and their integration with other OMAP modules and Linux.
8354 + *
8355 + * References:
8356 + * - OMAP2420 Multimedia Processor Silicon Revision 2.1.1, 2.2 (SWPU064)
8357 + * - OMAP2430 Multimedia Device POP Silicon Revision 2.1 (SWPU090)
8358 + * - OMAP34xx Multimedia Device Silicon Revision 3.1 (SWPU108)
8359 + * - OMAP4430 Multimedia Device Silicon Revision 1.0 (SWPU140)
8360 + * - Open Core Protocol Specification 2.2
8361 + *
8362 + * To do:
8363 + * - add interconnect error log structures
8364 + * - add pinmuxing
8365 + * - init_conn_id_bit (CONNID_BIT_VECTOR)
8366 + * - implement default hwmod SMS/SDRC flags?
8367 + *
8368 + */
8369 +#ifndef __ARCH_ARM_PLAT_OMAP_INCLUDE_MACH_OMAP_HWMOD_H
8370 +#define __ARCH_ARM_PLAT_OMAP_INCLUDE_MACH_OMAP_HWMOD_H
8371 +
8372 +#include <linux/kernel.h>
8373 +#include <linux/ioport.h>
8374 +
8375 +#include <plat/cpu.h>
8376 +
8377 +struct omap_device;
8378 +
8379 +/* OCP SYSCONFIG bit shifts/masks */
8380 +#define SYSC_MIDLEMODE_SHIFT 12
8381 +#define SYSC_MIDLEMODE_MASK (0x3 << SYSC_MIDLEMODE_SHIFT)
8382 +#define SYSC_CLOCKACTIVITY_SHIFT 8
8383 +#define SYSC_CLOCKACTIVITY_MASK (0x3 << SYSC_CLOCKACTIVITY_SHIFT)
8384 +#define SYSC_SIDLEMODE_SHIFT 3
8385 +#define SYSC_SIDLEMODE_MASK (0x3 << SYSC_SIDLEMODE_SHIFT)
8386 +#define SYSC_ENAWAKEUP_SHIFT 2
8387 +#define SYSC_ENAWAKEUP_MASK (1 << SYSC_ENAWAKEUP_SHIFT)
8388 +#define SYSC_SOFTRESET_SHIFT 1
8389 +#define SYSC_SOFTRESET_MASK (1 << SYSC_SOFTRESET_SHIFT)
8390 +#define SYSC_AUTOIDLE_SHIFT 0
8391 +#define SYSC_AUTOIDLE_MASK (1 << SYSC_AUTOIDLE_SHIFT)
8392 +
8393 +/* OCP SYSSTATUS bit shifts/masks */
8394 +#define SYSS_RESETDONE_SHIFT 0
8395 +#define SYSS_RESETDONE_MASK (1 << SYSS_RESETDONE_SHIFT)
8396 +
8397 +/* Master standby/slave idle mode flags */
8398 +#define HWMOD_IDLEMODE_FORCE (1 << 0)
8399 +#define HWMOD_IDLEMODE_NO (1 << 1)
8400 +#define HWMOD_IDLEMODE_SMART (1 << 2)
8401 +
8402 +
8403 +/**
8404 + * struct omap_hwmod_irq_info - MPU IRQs used by the hwmod
8405 + * @name: name of the IRQ channel (module local name)
8406 + * @irq_ch: IRQ channel ID
8407 + *
8408 + * @name should be something short, e.g., "tx" or "rx". It is for use
8409 + * by platform_get_resource_byname(). It is defined locally to the
8410 + * hwmod.
8411 + */
8412 +struct omap_hwmod_irq_info {
8413 + const char *name;
8414 + u16 irq;
8415 +};
8416 +
8417 +/**
8418 + * struct omap_hwmod_dma_info - DMA channels used by the hwmod
8419 + * @name: name of the DMA channel (module local name)
8420 + * @dma_ch: DMA channel ID
8421 + *
8422 + * @name should be something short, e.g., "tx" or "rx". It is for use
8423 + * by platform_get_resource_byname(). It is defined locally to the
8424 + * hwmod.
8425 + */
8426 +struct omap_hwmod_dma_info {
8427 + const char *name;
8428 + u16 dma_ch;
8429 +};
8430 +
8431 +/**
8432 + * struct omap_hwmod_opt_clk - optional clocks used by this hwmod
8433 + * @role: "sys", "32k", "tv", etc -- for use in clk_get()
8434 + * @clkdev_dev_id: opt clock: clkdev dev_id string
8435 + * @clkdev_con_id: opt clock: clkdev con_id string
8436 + * @_clk: pointer to the struct clk (filled in at runtime)
8437 + *
8438 + * The module's interface clock and main functional clock should not
8439 + * be added as optional clocks.
8440 + */
8441 +struct omap_hwmod_opt_clk {
8442 + const char *role;
8443 + const char *clkdev_dev_id;
8444 + const char *clkdev_con_id;
8445 + struct clk *_clk;
8446 +};
8447 +
8448 +
8449 +/* omap_hwmod_omap2_firewall.flags bits */
8450 +#define OMAP_FIREWALL_L3 (1 << 0)
8451 +#define OMAP_FIREWALL_L4 (1 << 1)
8452 +
8453 +/**
8454 + * struct omap_hwmod_omap2_firewall - OMAP2/3 device firewall data
8455 + * @l3_perm_bit: bit shift for L3_PM_*_PERMISSION_*
8456 + * @l4_fw_region: L4 firewall region ID
8457 + * @l4_prot_group: L4 protection group ID
8458 + * @flags: (see omap_hwmod_omap2_firewall.flags macros above)
8459 + */
8460 +struct omap_hwmod_omap2_firewall {
8461 + u8 l3_perm_bit;
8462 + u8 l4_fw_region;
8463 + u8 l4_prot_group;
8464 + u8 flags;
8465 +};
8466 +
8467 +
8468 +/*
8469 + * omap_hwmod_addr_space.flags bits
8470 + *
8471 + * ADDR_MAP_ON_INIT: Map this address space during omap_hwmod init.
8472 + * ADDR_TYPE_RT: Address space contains module register target data.
8473 + */
8474 +#define ADDR_MAP_ON_INIT (1 << 0)
8475 +#define ADDR_TYPE_RT (1 << 1)
8476 +
8477 +/**
8478 + * struct omap_hwmod_addr_space - MPU address space handled by the hwmod
8479 + * @pa_start: starting physical address
8480 + * @pa_end: ending physical address
8481 + * @flags: (see omap_hwmod_addr_space.flags macros above)
8482 + *
8483 + * Address space doesn't necessarily follow physical interconnect
8484 + * structure. GPMC is one example.
8485 + */
8486 +struct omap_hwmod_addr_space {
8487 + u32 pa_start;
8488 + u32 pa_end;
8489 + u8 flags;
8490 +};
8491 +
8492 +
8493 +/*
8494 + * omap_hwmod_ocp_if.user bits: these indicate the initiators that use this
8495 + * interface to interact with the hwmod. Used to add sleep dependencies
8496 + * when the module is enabled or disabled.
8497 + */
8498 +#define OCP_USER_MPU (1 << 0)
8499 +#define OCP_USER_SDMA (1 << 1)
8500 +
8501 +/* omap_hwmod_ocp_if.flags bits */
8502 +#define OCPIF_HAS_IDLEST (1 << 0)
8503 +#define OCPIF_SWSUP_IDLE (1 << 1)
8504 +#define OCPIF_CAN_BURST (1 << 2)
8505 +
8506 +/**
8507 + * struct omap_hwmod_ocp_if - OCP interface data
8508 + * @master: struct omap_hwmod that initiates OCP transactions on this link
8509 + * @slave: struct omap_hwmod that responds to OCP transactions on this link
8510 + * @addr: address space associated with this link
8511 + * @clkdev_dev_id: interface clock: clkdev dev_id string
8512 + * @clkdev_con_id: interface clock: clkdev con_id string
8513 + * @_clk: pointer to the interface struct clk (filled in at runtime)
8514 + * @fw: interface firewall data
8515 + * @addr_cnt: ARRAY_SIZE(@addr)
8516 + * @width: OCP data width
8517 + * @thread_cnt: number of threads
8518 + * @max_burst_len: maximum burst length in @width sized words (0 if unlimited)
8519 + * @user: initiators using this interface (see OCP_USER_* macros above)
8520 + * @flags: OCP interface flags (see OCPIF_* macros above)
8521 + *
8522 + * It may also be useful to add a tag_cnt field for OCP2.x devices.
8523 + *
8524 + * Parameter names beginning with an underscore are managed internally by
8525 + * the omap_hwmod code and should not be set during initialization.
8526 + */
8527 +struct omap_hwmod_ocp_if {
8528 + struct omap_hwmod *master;
8529 + struct omap_hwmod *slave;
8530 + struct omap_hwmod_addr_space *addr;
8531 + const char *clkdev_dev_id;
8532 + const char *clkdev_con_id;
8533 + struct clk *_clk;
8534 + union {
8535 + struct omap_hwmod_omap2_firewall omap2;
8536 + } fw;
8537 + u8 addr_cnt;
8538 + u8 width;
8539 + u8 thread_cnt;
8540 + u8 max_burst_len;
8541 + u8 user;
8542 + u8 flags;
8543 +};
8544 +
8545 +
8546 +/* Macros for use in struct omap_hwmod_sysconfig */
8547 +
8548 +/* Flags for use in omap_hwmod_sysconfig.idlemodes */
8549 +#define MASTER_STANDBY_SHIFT 2
8550 +#define SLAVE_IDLE_SHIFT 0
8551 +#define SIDLE_FORCE (HWMOD_IDLEMODE_FORCE << SLAVE_IDLE_SHIFT)
8552 +#define SIDLE_NO (HWMOD_IDLEMODE_NO << SLAVE_IDLE_SHIFT)
8553 +#define SIDLE_SMART (HWMOD_IDLEMODE_SMART << SLAVE_IDLE_SHIFT)
8554 +#define MSTANDBY_FORCE (HWMOD_IDLEMODE_FORCE << MASTER_STANDBY_SHIFT)
8555 +#define MSTANDBY_NO (HWMOD_IDLEMODE_NO << MASTER_STANDBY_SHIFT)
8556 +#define MSTANDBY_SMART (HWMOD_IDLEMODE_SMART << MASTER_STANDBY_SHIFT)
8557 +
8558 +/* omap_hwmod_sysconfig.sysc_flags capability flags */
8559 +#define SYSC_HAS_AUTOIDLE (1 << 0)
8560 +#define SYSC_HAS_SOFTRESET (1 << 1)
8561 +#define SYSC_HAS_ENAWAKEUP (1 << 2)
8562 +#define SYSC_HAS_EMUFREE (1 << 3)
8563 +#define SYSC_HAS_CLOCKACTIVITY (1 << 4)
8564 +#define SYSC_HAS_SIDLEMODE (1 << 5)
8565 +#define SYSC_HAS_MIDLEMODE (1 << 6)
8566 +#define SYSS_MISSING (1 << 7)
8567 +
8568 +/* omap_hwmod_sysconfig.clockact flags */
8569 +#define CLOCKACT_TEST_BOTH 0x0
8570 +#define CLOCKACT_TEST_MAIN 0x1
8571 +#define CLOCKACT_TEST_ICLK 0x2
8572 +#define CLOCKACT_TEST_NONE 0x3
8573 +
8574 +/**
8575 + * struct omap_hwmod_sysconfig - hwmod OCP_SYSCONFIG/OCP_SYSSTATUS data
8576 + * @rev_offs: IP block revision register offset (from module base addr)
8577 + * @sysc_offs: OCP_SYSCONFIG register offset (from module base addr)
8578 + * @syss_offs: OCP_SYSSTATUS register offset (from module base addr)
8579 + * @idlemodes: One or more of {SIDLE,MSTANDBY}_{OFF,FORCE,SMART}
8580 + * @sysc_flags: SYS{C,S}_HAS* flags indicating SYSCONFIG bits supported
8581 + * @clockact: the default value of the module CLOCKACTIVITY bits
8582 + *
8583 + * @clockact describes to the module which clocks are likely to be
8584 + * disabled when the PRCM issues its idle request to the module. Some
8585 + * modules have separate clockdomains for the interface clock and main
8586 + * functional clock, and can check whether they should acknowledge the
8587 + * idle request based on the internal module functionality that has
8588 + * been associated with the clocks marked in @clockact. This field is
8589 + * only used if HWMOD_SET_DEFAULT_CLOCKACT is set (see below)
8590 + *
8591 + */
8592 +struct omap_hwmod_sysconfig {
8593 + u16 rev_offs;
8594 + u16 sysc_offs;
8595 + u16 syss_offs;
8596 + u8 idlemodes;
8597 + u8 sysc_flags;
8598 + u8 clockact;
8599 +};
8600 +
8601 +/**
8602 + * struct omap_hwmod_omap2_prcm - OMAP2/3-specific PRCM data
8603 + * @module_offs: PRCM submodule offset from the start of the PRM/CM
8604 + * @prcm_reg_id: PRCM register ID (e.g., 3 for CM_AUTOIDLE3)
8605 + * @module_bit: register bit shift for AUTOIDLE, WKST, WKEN, GRPSEL regs
8606 + * @idlest_reg_id: IDLEST register ID (e.g., 3 for CM_IDLEST3)
8607 + * @idlest_idle_bit: register bit shift for CM_IDLEST slave idle bit
8608 + * @idlest_stdby_bit: register bit shift for CM_IDLEST master standby bit
8609 + *
8610 + * @prcm_reg_id and @module_bit are specific to the AUTOIDLE, WKST,
8611 + * WKEN, GRPSEL registers. In an ideal world, no extra information
8612 + * would be needed for IDLEST information, but alas, there are some
8613 + * exceptions, so @idlest_reg_id, @idlest_idle_bit, @idlest_stdby_bit
8614 + * are needed for the IDLEST registers (c.f. 2430 I2CHS, 3430 USBHOST)
8615 + */
8616 +struct omap_hwmod_omap2_prcm {
8617 + s16 module_offs;
8618 + u8 prcm_reg_id;
8619 + u8 module_bit;
8620 + u8 idlest_reg_id;
8621 + u8 idlest_idle_bit;
8622 + u8 idlest_stdby_bit;
8623 +};
8624 +
8625 +
8626 +/**
8627 + * struct omap_hwmod_omap4_prcm - OMAP4-specific PRCM data
8628 + * @module_offs: PRCM submodule offset from the start of the PRM/CM1/CM2
8629 + * @device_offs: device register offset from @module_offs
8630 + * @submodule_wkdep_bit: bit shift of the WKDEP range
8631 + */
8632 +struct omap_hwmod_omap4_prcm {
8633 + u32 module_offs;
8634 + u16 device_offs;
8635 + u8 submodule_wkdep_bit;
8636 +};
8637 +
8638 +
8639 +/*
8640 + * omap_hwmod.flags definitions
8641 + *
8642 + * HWMOD_SWSUP_SIDLE: omap_hwmod code should manually bring module in and out
8643 + * of idle, rather than relying on module smart-idle
8644 + * HWMOD_SWSUP_MSTDBY: omap_hwmod code should manually bring module in and out
8645 + * of standby, rather than relying on module smart-standby
8646 + * HWMOD_INIT_NO_RESET: don't reset this module at boot - important for
8647 + * SDRAM controller, etc.
8648 + * HWMOD_INIT_NO_IDLE: don't idle this module at boot - important for SDRAM
8649 + * controller, etc.
8650 + * HWMOD_NO_AUTOIDLE: disable module autoidle (OCP_SYSCONFIG.AUTOIDLE)
8651 + * when module is enabled, rather than the default, which is to
8652 + * enable autoidle
8653 + * HWMOD_SET_DEFAULT_CLOCKACT: program CLOCKACTIVITY bits at startup
8654 + */
8655 +#define HWMOD_SWSUP_SIDLE (1 << 0)
8656 +#define HWMOD_SWSUP_MSTANDBY (1 << 1)
8657 +#define HWMOD_INIT_NO_RESET (1 << 2)
8658 +#define HWMOD_INIT_NO_IDLE (1 << 3)
8659 +#define HWMOD_NO_OCP_AUTOIDLE (1 << 4)
8660 +#define HWMOD_SET_DEFAULT_CLOCKACT (1 << 5)
8661 +
8662 +/*
8663 + * omap_hwmod._int_flags definitions
8664 + * These are for internal use only and are managed by the omap_hwmod code.
8665 + *
8666 + * _HWMOD_NO_MPU_PORT: no path exists for the MPU to write to this module
8667 + * _HWMOD_WAKEUP_ENABLED: set when the omap_hwmod code has enabled ENAWAKEUP
8668 + * _HWMOD_SYSCONFIG_LOADED: set when the OCP_SYSCONFIG value has been cached
8669 + */
8670 +#define _HWMOD_NO_MPU_PORT (1 << 0)
8671 +#define _HWMOD_WAKEUP_ENABLED (1 << 1)
8672 +#define _HWMOD_SYSCONFIG_LOADED (1 << 2)
8673 +
8674 +/*
8675 + * omap_hwmod._state definitions
8676 + *
8677 + * INITIALIZED: reset (optionally), initialized, enabled, disabled
8678 + * (optionally)
8679 + *
8680 + *
8681 + */
8682 +#define _HWMOD_STATE_UNKNOWN 0
8683 +#define _HWMOD_STATE_REGISTERED 1
8684 +#define _HWMOD_STATE_CLKS_INITED 2
8685 +#define _HWMOD_STATE_INITIALIZED 3
8686 +#define _HWMOD_STATE_ENABLED 4
8687 +#define _HWMOD_STATE_IDLE 5
8688 +#define _HWMOD_STATE_DISABLED 6
8689 +
8690 +/**
8691 + * struct omap_hwmod - integration data for OMAP hardware "modules" (IP blocks)
8692 + * @name: name of the hwmod
8693 + * @od: struct omap_device currently associated with this hwmod (internal use)
8694 + * @mpu_irqs: ptr to an array of MPU IRQs (see also mpu_irqs_cnt)
8695 + * @sdma_chs: ptr to an array of SDMA channel IDs (see also sdma_chs_cnt)
8696 + * @prcm: PRCM data pertaining to this hwmod
8697 + * @clkdev_dev_id: main clock: clkdev dev_id string
8698 + * @clkdev_con_id: main clock: clkdev con_id string
8699 + * @_clk: pointer to the main struct clk (filled in at runtime)
8700 + * @opt_clks: other device clocks that drivers can request (0..*)
8701 + * @masters: ptr to array of OCP ifs that this hwmod can initiate on
8702 + * @slaves: ptr to array of OCP ifs that this hwmod can respond on
8703 + * @sysconfig: device SYSCONFIG/SYSSTATUS register data
8704 + * @dev_attr: arbitrary device attributes that can be passed to the driver
8705 + * @_sysc_cache: internal-use hwmod flags
8706 + * @_rt_va: cached register target start address (internal use)
8707 + * @_mpu_port_index: cached MPU register target slave ID (internal use)
8708 + * @msuspendmux_reg_id: CONTROL_MSUSPENDMUX register ID (1-6)
8709 + * @msuspendmux_shift: CONTROL_MSUSPENDMUX register bit shift
8710 + * @mpu_irqs_cnt: number of @mpu_irqs
8711 + * @sdma_chs_cnt: number of @sdma_chs
8712 + * @opt_clks_cnt: number of @opt_clks
8713 + * @master_cnt: number of @master entries
8714 + * @slaves_cnt: number of @slave entries
8715 + * @response_lat: device OCP response latency (in interface clock cycles)
8716 + * @_int_flags: internal-use hwmod flags
8717 + * @_state: internal-use hwmod state
8718 + * @flags: hwmod flags (documented below)
8719 + * @omap_chip: OMAP chips this hwmod is present on
8720 + * @node: list node for hwmod list (internal use)
8721 + *
8722 + * @clkdev_dev_id, @clkdev_con_id, and @clk all refer to this module's "main
8723 + * clock," which for our purposes is defined as "the functional clock needed
8724 + * for register accesses to complete." Modules may not have a main clock if
8725 + * the interface clock also serves as a main clock.
8726 + *
8727 + * Parameter names beginning with an underscore are managed internally by
8728 + * the omap_hwmod code and should not be set during initialization.
8729 + */
8730 +struct omap_hwmod {
8731 + const char *name;
8732 + struct omap_device *od;
8733 + struct omap_hwmod_irq_info *mpu_irqs;
8734 + struct omap_hwmod_dma_info *sdma_chs;
8735 + union {
8736 + struct omap_hwmod_omap2_prcm omap2;
8737 + struct omap_hwmod_omap4_prcm omap4;
8738 + } prcm;
8739 + const char *clkdev_dev_id;
8740 + const char *clkdev_con_id;
8741 + struct clk *_clk;
8742 + struct omap_hwmod_opt_clk *opt_clks;
8743 + struct omap_hwmod_ocp_if **masters; /* connect to *_IA */
8744 + struct omap_hwmod_ocp_if **slaves; /* connect to *_TA */
8745 + struct omap_hwmod_sysconfig *sysconfig;
8746 + void *dev_attr;
8747 + u32 _sysc_cache;
8748 + void __iomem *_rt_va;
8749 + struct list_head node;
8750 + u16 flags;
8751 + u8 _mpu_port_index;
8752 + u8 msuspendmux_reg_id;
8753 + u8 msuspendmux_shift;
8754 + u8 response_lat;
8755 + u8 mpu_irqs_cnt;
8756 + u8 sdma_chs_cnt;
8757 + u8 opt_clks_cnt;
8758 + u8 masters_cnt;
8759 + u8 slaves_cnt;
8760 + u8 hwmods_cnt;
8761 + u8 _int_flags;
8762 + u8 _state;
8763 + const struct omap_chip_id omap_chip;
8764 +};
8765 +
8766 +int omap_hwmod_init(struct omap_hwmod **ohs);
8767 +int omap_hwmod_register(struct omap_hwmod *oh);
8768 +int omap_hwmod_unregister(struct omap_hwmod *oh);
8769 +struct omap_hwmod *omap_hwmod_lookup(const char *name);
8770 +int omap_hwmod_for_each(int (*fn)(struct omap_hwmod *oh));
8771 +int omap_hwmod_late_init(void);
8772 +
8773 +int omap_hwmod_enable(struct omap_hwmod *oh);
8774 +int omap_hwmod_idle(struct omap_hwmod *oh);
8775 +int omap_hwmod_shutdown(struct omap_hwmod *oh);
8776 +
8777 +int omap_hwmod_enable_clocks(struct omap_hwmod *oh);
8778 +int omap_hwmod_disable_clocks(struct omap_hwmod *oh);
8779 +
8780 +int omap_hwmod_reset(struct omap_hwmod *oh);
8781 +void omap_hwmod_ocp_barrier(struct omap_hwmod *oh);
8782 +
8783 +void omap_hwmod_writel(u32 v, struct omap_hwmod *oh, u16 reg_offs);
8784 +u32 omap_hwmod_readl(struct omap_hwmod *oh, u16 reg_offs);
8785 +
8786 +int omap_hwmod_count_resources(struct omap_hwmod *oh);
8787 +int omap_hwmod_fill_resources(struct omap_hwmod *oh, struct resource *res);
8788 +
8789 +struct powerdomain *omap_hwmod_get_pwrdm(struct omap_hwmod *oh);
8790 +
8791 +int omap_hwmod_add_initiator_dep(struct omap_hwmod *oh,
8792 + struct omap_hwmod *init_oh);
8793 +int omap_hwmod_del_initiator_dep(struct omap_hwmod *oh,
8794 + struct omap_hwmod *init_oh);
8795 +
8796 +int omap_hwmod_set_clockact_both(struct omap_hwmod *oh);
8797 +int omap_hwmod_set_clockact_main(struct omap_hwmod *oh);
8798 +int omap_hwmod_set_clockact_iclk(struct omap_hwmod *oh);
8799 +int omap_hwmod_set_clockact_none(struct omap_hwmod *oh);
8800 +
8801 +int omap_hwmod_enable_wakeup(struct omap_hwmod *oh);
8802 +int omap_hwmod_disable_wakeup(struct omap_hwmod *oh);
8803 +
8804 +#endif
8805 Index: linux-2.6.37-rc1/arch/arm/plat-omap/include/mach/omap-pm.h
8806 ===================================================================
8807 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
8808 +++ linux-2.6.37-rc1/arch/arm/plat-omap/include/mach/omap-pm.h 2010-11-05 17:36:26.178000001 +0100
8809 @@ -0,0 +1,301 @@
8810 +/*
8811 + * omap-pm.h - OMAP power management interface
8812 + *
8813 + * Copyright (C) 2008-2009 Texas Instruments, Inc.
8814 + * Copyright (C) 2008-2009 Nokia Corporation
8815 + * Paul Walmsley
8816 + *
8817 + * Interface developed by (in alphabetical order): Karthik Dasu, Jouni
8818 + * Högander, Tony Lindgren, Rajendra Nayak, Sakari Poussa,
8819 + * Veeramanikandan Raju, Anand Sawant, Igor Stoppa, Paul Walmsley,
8820 + * Richard Woodruff
8821 + */
8822 +
8823 +#ifndef ASM_ARM_ARCH_OMAP_OMAP_PM_H
8824 +#define ASM_ARM_ARCH_OMAP_OMAP_PM_H
8825 +
8826 +#include <linux/device.h>
8827 +#include <linux/cpufreq.h>
8828 +
8829 +#include "powerdomain.h"
8830 +
8831 +/**
8832 + * struct omap_opp - clock frequency-to-OPP ID table for DSP, MPU
8833 + * @rate: target clock rate
8834 + * @opp_id: OPP ID
8835 + * @min_vdd: minimum VDD1 voltage (in millivolts) for this OPP
8836 + *
8837 + * Operating performance point data. Can vary by OMAP chip and board.
8838 + */
8839 +struct omap_opp {
8840 + unsigned long rate;
8841 + u8 opp_id;
8842 + u16 min_vdd;
8843 +};
8844 +
8845 +extern struct omap_opp *mpu_opps;
8846 +extern struct omap_opp *dsp_opps;
8847 +extern struct omap_opp *l3_opps;
8848 +
8849 +/*
8850 + * agent_id values for use with omap_pm_set_min_bus_tput():
8851 + *
8852 + * OCP_INITIATOR_AGENT is only valid for devices that can act as
8853 + * initiators -- it represents the device's L3 interconnect
8854 + * connection. OCP_TARGET_AGENT represents the device's L4
8855 + * interconnect connection.
8856 + */
8857 +#define OCP_TARGET_AGENT 1
8858 +#define OCP_INITIATOR_AGENT 2
8859 +
8860 +/**
8861 + * omap_pm_if_early_init - OMAP PM init code called before clock fw init
8862 + * @mpu_opp_table: array ptr to struct omap_opp for MPU
8863 + * @dsp_opp_table: array ptr to struct omap_opp for DSP
8864 + * @l3_opp_table : array ptr to struct omap_opp for CORE
8865 + *
8866 + * Initialize anything that must be configured before the clock
8867 + * framework starts. The "_if_" is to avoid name collisions with the
8868 + * PM idle-loop code.
8869 + */
8870 +int __init omap_pm_if_early_init(struct omap_opp *mpu_opp_table,
8871 + struct omap_opp *dsp_opp_table,
8872 + struct omap_opp *l3_opp_table);
8873 +
8874 +/**
8875 + * omap_pm_if_init - OMAP PM init code called after clock fw init
8876 + *
8877 + * The main initialization code. OPP tables are passed in here. The
8878 + * "_if_" is to avoid name collisions with the PM idle-loop code.
8879 + */
8880 +int __init omap_pm_if_init(void);
8881 +
8882 +/**
8883 + * omap_pm_if_exit - OMAP PM exit code
8884 + *
8885 + * Exit code; currently unused. The "_if_" is to avoid name
8886 + * collisions with the PM idle-loop code.
8887 + */
8888 +void omap_pm_if_exit(void);
8889 +
8890 +/*
8891 + * Device-driver-originated constraints (via board-*.c files, platform_data)
8892 + */
8893 +
8894 +
8895 +/**
8896 + * omap_pm_set_max_mpu_wakeup_lat - set the maximum MPU wakeup latency
8897 + * @dev: struct device * requesting the constraint
8898 + * @t: maximum MPU wakeup latency in microseconds
8899 + *
8900 + * Request that the maximum interrupt latency for the MPU to be no
8901 + * greater than 't' microseconds. "Interrupt latency" in this case is
8902 + * defined as the elapsed time from the occurrence of a hardware or
8903 + * timer interrupt to the time when the device driver's interrupt
8904 + * service routine has been entered by the MPU.
8905 + *
8906 + * It is intended that underlying PM code will use this information to
8907 + * determine what power state to put the MPU powerdomain into, and
8908 + * possibly the CORE powerdomain as well, since interrupt handling
8909 + * code currently runs from SDRAM. Advanced PM or board*.c code may
8910 + * also configure interrupt controller priorities, OCP bus priorities,
8911 + * CPU speed(s), etc.
8912 + *
8913 + * This function will not affect device wakeup latency, e.g., time
8914 + * elapsed from when a device driver enables a hardware device with
8915 + * clk_enable(), to when the device is ready for register access or
8916 + * other use. To control this device wakeup latency, use
8917 + * set_max_dev_wakeup_lat()
8918 + *
8919 + * Multiple calls to set_max_mpu_wakeup_lat() will replace the
8920 + * previous t value. To remove the latency target for the MPU, call
8921 + * with t = -1.
8922 + *
8923 + * No return value.
8924 + */
8925 +void omap_pm_set_max_mpu_wakeup_lat(struct device *dev, long t);
8926 +
8927 +
8928 +/**
8929 + * omap_pm_set_min_bus_tput - set minimum bus throughput needed by device
8930 + * @dev: struct device * requesting the constraint
8931 + * @tbus_id: interconnect to operate on (OCP_{INITIATOR,TARGET}_AGENT)
8932 + * @r: minimum throughput (in KiB/s)
8933 + *
8934 + * Request that the minimum data throughput on the OCP interconnect
8935 + * attached to device 'dev' interconnect agent 'tbus_id' be no less
8936 + * than 'r' KiB/s.
8937 + *
8938 + * It is expected that the OMAP PM or bus code will use this
8939 + * information to set the interconnect clock to run at the lowest
8940 + * possible speed that satisfies all current system users. The PM or
8941 + * bus code will adjust the estimate based on its model of the bus, so
8942 + * device driver authors should attempt to specify an accurate
8943 + * quantity for their device use case, and let the PM or bus code
8944 + * overestimate the numbers as necessary to handle request/response
8945 + * latency, other competing users on the system, etc. On OMAP2/3, if
8946 + * a driver requests a minimum L4 interconnect speed constraint, the
8947 + * code will also need to add an minimum L3 interconnect speed
8948 + * constraint,
8949 + *
8950 + * Multiple calls to set_min_bus_tput() will replace the previous rate
8951 + * value for this device. To remove the interconnect throughput
8952 + * restriction for this device, call with r = 0.
8953 + *
8954 + * No return value.
8955 + */
8956 +void omap_pm_set_min_bus_tput(struct device *dev, u8 agent_id, unsigned long r);
8957 +
8958 +
8959 +/**
8960 + * omap_pm_set_max_dev_wakeup_lat - set the maximum device enable latency
8961 + * @dev: struct device *
8962 + * @t: maximum device wakeup latency in microseconds
8963 + *
8964 + * Request that the maximum amount of time necessary for a device to
8965 + * become accessible after its clocks are enabled should be no greater
8966 + * than 't' microseconds. Specifically, this represents the time from
8967 + * when a device driver enables device clocks with clk_enable(), to
8968 + * when the register reads and writes on the device will succeed.
8969 + * This function should be called before clk_disable() is called,
8970 + * since the power state transition decision may be made during
8971 + * clk_disable().
8972 + *
8973 + * It is intended that underlying PM code will use this information to
8974 + * determine what power state to put the powerdomain enclosing this
8975 + * device into.
8976 + *
8977 + * Multiple calls to set_max_dev_wakeup_lat() will replace the
8978 + * previous wakeup latency values for this device. To remove the wakeup
8979 + * latency restriction for this device, call with t = -1.
8980 + *
8981 + * No return value.
8982 + */
8983 +void omap_pm_set_max_dev_wakeup_lat(struct device *dev, long t);
8984 +
8985 +
8986 +/**
8987 + * omap_pm_set_max_sdma_lat - set the maximum system DMA transfer start latency
8988 + * @dev: struct device *
8989 + * @t: maximum DMA transfer start latency in microseconds
8990 + *
8991 + * Request that the maximum system DMA transfer start latency for this
8992 + * device 'dev' should be no greater than 't' microseconds. "DMA
8993 + * transfer start latency" here is defined as the elapsed time from
8994 + * when a device (e.g., McBSP) requests that a system DMA transfer
8995 + * start or continue, to the time at which data starts to flow into
8996 + * that device from the system DMA controller.
8997 + *
8998 + * It is intended that underlying PM code will use this information to
8999 + * determine what power state to put the CORE powerdomain into.
9000 + *
9001 + * Since system DMA transfers may not involve the MPU, this function
9002 + * will not affect MPU wakeup latency. Use set_max_cpu_lat() to do
9003 + * so. Similarly, this function will not affect device wakeup latency
9004 + * -- use set_max_dev_wakeup_lat() to affect that.
9005 + *
9006 + * Multiple calls to set_max_sdma_lat() will replace the previous t
9007 + * value for this device. To remove the maximum DMA latency for this
9008 + * device, call with t = -1.
9009 + *
9010 + * No return value.
9011 + */
9012 +void omap_pm_set_max_sdma_lat(struct device *dev, long t);
9013 +
9014 +
9015 +/*
9016 + * DSP Bridge-specific constraints
9017 + */
9018 +
9019 +/**
9020 + * omap_pm_dsp_get_opp_table - get OPP->DSP clock frequency table
9021 + *
9022 + * Intended for use by DSPBridge. Returns an array of OPP->DSP clock
9023 + * frequency entries. The final item in the array should have .rate =
9024 + * .opp_id = 0.
9025 + */
9026 +const struct omap_opp *omap_pm_dsp_get_opp_table(void);
9027 +
9028 +/**
9029 + * omap_pm_dsp_set_min_opp - receive desired OPP target ID from DSP Bridge
9030 + * @opp_id: target DSP OPP ID
9031 + *
9032 + * Set a minimum OPP ID for the DSP. This is intended to be called
9033 + * only from the DSP Bridge MPU-side driver. Unfortunately, the only
9034 + * information that code receives from the DSP/BIOS load estimator is the
9035 + * target OPP ID; hence, this interface. No return value.
9036 + */
9037 +void omap_pm_dsp_set_min_opp(u8 opp_id);
9038 +
9039 +/**
9040 + * omap_pm_dsp_get_opp - report the current DSP OPP ID
9041 + *
9042 + * Report the current OPP for the DSP. Since on OMAP3, the DSP and
9043 + * MPU share a single voltage domain, the OPP ID returned back may
9044 + * represent a higher DSP speed than the OPP requested via
9045 + * omap_pm_dsp_set_min_opp().
9046 + *
9047 + * Returns the current VDD1 OPP ID, or 0 upon error.
9048 + */
9049 +u8 omap_pm_dsp_get_opp(void);
9050 +
9051 +
9052 +/*
9053 + * CPUFreq-originated constraint
9054 + *
9055 + * In the future, this should be handled by custom OPP clocktype
9056 + * functions.
9057 + */
9058 +
9059 +/**
9060 + * omap_pm_cpu_get_freq_table - return a cpufreq_frequency_table array ptr
9061 + *
9062 + * Provide a frequency table usable by CPUFreq for the current chip/board.
9063 + * Returns a pointer to a struct cpufreq_frequency_table array or NULL
9064 + * upon error.
9065 + */
9066 +struct cpufreq_frequency_table **omap_pm_cpu_get_freq_table(void);
9067 +
9068 +/**
9069 + * omap_pm_cpu_set_freq - set the current minimum MPU frequency
9070 + * @f: MPU frequency in Hz
9071 + *
9072 + * Set the current minimum CPU frequency. The actual CPU frequency
9073 + * used could end up higher if the DSP requested a higher OPP.
9074 + * Intended to be called by plat-omap/cpu_omap.c:omap_target(). No
9075 + * return value.
9076 + */
9077 +void omap_pm_cpu_set_freq(unsigned long f);
9078 +
9079 +/**
9080 + * omap_pm_cpu_get_freq - report the current CPU frequency
9081 + *
9082 + * Returns the current MPU frequency, or 0 upon error.
9083 + */
9084 +unsigned long omap_pm_cpu_get_freq(void);
9085 +
9086 +
9087 +/*
9088 + * Device context loss tracking
9089 + */
9090 +
9091 +/**
9092 + * omap_pm_get_dev_context_loss_count - return count of times dev has lost ctx
9093 + * @dev: struct device *
9094 + *
9095 + * This function returns the number of times that the device @dev has
9096 + * lost its internal context. This generally occurs on a powerdomain
9097 + * transition to OFF. Drivers use this as an optimization to avoid restoring
9098 + * context if the device hasn't lost it. To use, drivers should initially
9099 + * call this in their context save functions and store the result. Early in
9100 + * the driver's context restore function, the driver should call this function
9101 + * again, and compare the result to the stored counter. If they differ, the
9102 + * driver must restore device context. If the number of context losses
9103 + * exceeds the maximum positive integer, the function will wrap to 0 and
9104 + * continue counting. Returns the number of context losses for this device,
9105 + * or -EINVAL upon error.
9106 + */
9107 +int omap_pm_get_dev_context_loss_count(struct device *dev);
9108 +
9109 +
9110 +#endif
9111 Index: linux-2.6.37-rc1/arch/arm/plat-omap/include/mach/onenand.h
9112 ===================================================================
9113 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
9114 +++ linux-2.6.37-rc1/arch/arm/plat-omap/include/mach/onenand.h 2010-11-05 17:36:26.178000001 +0100
9115 @@ -0,0 +1,43 @@
9116 +/*
9117 + * arch/arm/plat-omap/include/mach/onenand.h
9118 + *
9119 + * Copyright (C) 2006 Nokia Corporation
9120 + * Author: Juha Yrjola
9121 + *
9122 + * This program is free software; you can redistribute it and/or modify
9123 + * it under the terms of the GNU General Public License version 2 as
9124 + * published by the Free Software Foundation.
9125 + */
9126 +
9127 +#include <linux/mtd/mtd.h>
9128 +#include <linux/mtd/partitions.h>
9129 +
9130 +#define ONENAND_SYNC_READ (1 << 0)
9131 +#define ONENAND_SYNC_READWRITE (1 << 1)
9132 +
9133 +struct omap_onenand_platform_data {
9134 + int cs;
9135 + int gpio_irq;
9136 + struct mtd_partition *parts;
9137 + int nr_parts;
9138 + int (*onenand_setup)(void __iomem *, int freq);
9139 + int dma_channel;
9140 + u8 flags;
9141 +};
9142 +
9143 +#define ONENAND_MAX_PARTITIONS 8
9144 +
9145 +#if defined(CONFIG_MTD_ONENAND_OMAP2) || \
9146 + defined(CONFIG_MTD_ONENAND_OMAP2_MODULE)
9147 +
9148 +extern void gpmc_onenand_init(struct omap_onenand_platform_data *d);
9149 +
9150 +#else
9151 +
9152 +#define board_onenand_data NULL
9153 +
9154 +static inline void gpmc_onenand_init(struct omap_onenand_platform_data *d)
9155 +{
9156 +}
9157 +
9158 +#endif
9159 Index: linux-2.6.37-rc1/arch/arm/plat-omap/include/mach/param.h
9160 ===================================================================
9161 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
9162 +++ linux-2.6.37-rc1/arch/arm/plat-omap/include/mach/param.h 2010-11-05 17:36:26.178000001 +0100
9163 @@ -0,0 +1,8 @@
9164 +/*
9165 + * arch/arm/plat-omap/include/mach/param.h
9166 + *
9167 + */
9168 +
9169 +#ifdef CONFIG_OMAP_32K_TIMER_HZ
9170 +#define HZ CONFIG_OMAP_32K_TIMER_HZ
9171 +#endif
9172 Index: linux-2.6.37-rc1/arch/arm/plat-omap/include/mach/powerdomain.h
9173 ===================================================================
9174 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
9175 +++ linux-2.6.37-rc1/arch/arm/plat-omap/include/mach/powerdomain.h 2010-11-05 17:36:26.178000001 +0100
9176 @@ -0,0 +1,187 @@
9177 +/*
9178 + * OMAP2/3 powerdomain control
9179 + *
9180 + * Copyright (C) 2007-8 Texas Instruments, Inc.
9181 + * Copyright (C) 2007-8 Nokia Corporation
9182 + *
9183 + * Written by Paul Walmsley
9184 + *
9185 + * This program is free software; you can redistribute it and/or modify
9186 + * it under the terms of the GNU General Public License version 2 as
9187 + * published by the Free Software Foundation.
9188 + */
9189 +
9190 +#ifndef ASM_ARM_ARCH_OMAP_POWERDOMAIN
9191 +#define ASM_ARM_ARCH_OMAP_POWERDOMAIN
9192 +
9193 +#include <linux/types.h>
9194 +#include <linux/list.h>
9195 +
9196 +#include <asm/atomic.h>
9197 +
9198 +#include <plat/cpu.h>
9199 +
9200 +
9201 +/* Powerdomain basic power states */
9202 +#define PWRDM_POWER_OFF 0x0
9203 +#define PWRDM_POWER_RET 0x1
9204 +#define PWRDM_POWER_INACTIVE 0x2
9205 +#define PWRDM_POWER_ON 0x3
9206 +
9207 +#define PWRDM_MAX_PWRSTS 4
9208 +
9209 +/* Powerdomain allowable state bitfields */
9210 +#define PWRSTS_OFF_ON ((1 << PWRDM_POWER_OFF) | \
9211 + (1 << PWRDM_POWER_ON))
9212 +
9213 +#define PWRSTS_OFF_RET ((1 << PWRDM_POWER_OFF) | \
9214 + (1 << PWRDM_POWER_RET))
9215 +
9216 +#define PWRSTS_OFF_RET_ON (PWRSTS_OFF_RET | (1 << PWRDM_POWER_ON))
9217 +
9218 +
9219 +/* Powerdomain flags */
9220 +#define PWRDM_HAS_HDWR_SAR (1 << 0) /* hardware save-and-restore support */
9221 +#define PWRDM_HAS_MPU_QUIRK (1 << 1) /* MPU pwr domain has MEM bank 0 bits
9222 + * in MEM bank 1 position. This is
9223 + * true for OMAP3430
9224 + */
9225 +
9226 +/*
9227 + * Number of memory banks that are power-controllable. On OMAP3430, the
9228 + * maximum is 4.
9229 + */
9230 +#define PWRDM_MAX_MEM_BANKS 4
9231 +
9232 +/*
9233 + * Maximum number of clockdomains that can be associated with a powerdomain.
9234 + * CORE powerdomain on OMAP3 is the worst case
9235 + */
9236 +#define PWRDM_MAX_CLKDMS 4
9237 +
9238 +/* XXX A completely arbitrary number. What is reasonable here? */
9239 +#define PWRDM_TRANSITION_BAILOUT 100000
9240 +
9241 +struct clockdomain;
9242 +struct powerdomain;
9243 +
9244 +/* Encodes dependencies between powerdomains - statically defined */
9245 +struct pwrdm_dep {
9246 +
9247 + /* Powerdomain name */
9248 + const char *pwrdm_name;
9249 +
9250 + /* Powerdomain pointer - resolved by the powerdomain code */
9251 + struct powerdomain *pwrdm;
9252 +
9253 + /* Flags to mark OMAP chip restrictions, etc. */
9254 + const struct omap_chip_id omap_chip;
9255 +
9256 +};
9257 +
9258 +struct powerdomain {
9259 +
9260 + /* Powerdomain name */
9261 + const char *name;
9262 +
9263 + /* the address offset from CM_BASE/PRM_BASE */
9264 + const s16 prcm_offs;
9265 +
9266 + /* Used to represent the OMAP chip types containing this pwrdm */
9267 + const struct omap_chip_id omap_chip;
9268 +
9269 + /* Powerdomains that can be told to wake this powerdomain up */
9270 + struct pwrdm_dep *wkdep_srcs;
9271 +
9272 + /* Powerdomains that can be told to keep this pwrdm from inactivity */
9273 + struct pwrdm_dep *sleepdep_srcs;
9274 +
9275 + /* Bit shift of this powerdomain's PM_WKDEP/CM_SLEEPDEP bit */
9276 + const u8 dep_bit;
9277 +
9278 + /* Possible powerdomain power states */
9279 + const u8 pwrsts;
9280 +
9281 + /* Possible logic power states when pwrdm in RETENTION */
9282 + const u8 pwrsts_logic_ret;
9283 +
9284 + /* Powerdomain flags */
9285 + const u8 flags;
9286 +
9287 + /* Number of software-controllable memory banks in this powerdomain */
9288 + const u8 banks;
9289 +
9290 + /* Possible memory bank pwrstates when pwrdm in RETENTION */
9291 + const u8 pwrsts_mem_ret[PWRDM_MAX_MEM_BANKS];
9292 +
9293 + /* Possible memory bank pwrstates when pwrdm is ON */
9294 + const u8 pwrsts_mem_on[PWRDM_MAX_MEM_BANKS];
9295 +
9296 + /* Clockdomains in this powerdomain */
9297 + struct clockdomain *pwrdm_clkdms[PWRDM_MAX_CLKDMS];
9298 +
9299 + struct list_head node;
9300 +
9301 + int state;
9302 + unsigned state_counter[PWRDM_MAX_PWRSTS];
9303 +
9304 +#ifdef CONFIG_PM_DEBUG
9305 + s64 timer;
9306 + s64 state_timer[PWRDM_MAX_PWRSTS];
9307 +#endif
9308 +};
9309 +
9310 +
9311 +void pwrdm_init(struct powerdomain **pwrdm_list);
9312 +
9313 +int pwrdm_register(struct powerdomain *pwrdm);
9314 +int pwrdm_unregister(struct powerdomain *pwrdm);
9315 +struct powerdomain *pwrdm_lookup(const char *name);
9316 +
9317 +int pwrdm_for_each(int (*fn)(struct powerdomain *pwrdm, void *user),
9318 + void *user);
9319 +int pwrdm_for_each_nolock(int (*fn)(struct powerdomain *pwrdm, void *user),
9320 + void *user);
9321 +
9322 +int pwrdm_add_clkdm(struct powerdomain *pwrdm, struct clockdomain *clkdm);
9323 +int pwrdm_del_clkdm(struct powerdomain *pwrdm, struct clockdomain *clkdm);
9324 +int pwrdm_for_each_clkdm(struct powerdomain *pwrdm,
9325 + int (*fn)(struct powerdomain *pwrdm,
9326 + struct clockdomain *clkdm));
9327 +
9328 +int pwrdm_add_wkdep(struct powerdomain *pwrdm1, struct powerdomain *pwrdm2);
9329 +int pwrdm_del_wkdep(struct powerdomain *pwrdm1, struct powerdomain *pwrdm2);
9330 +int pwrdm_read_wkdep(struct powerdomain *pwrdm1, struct powerdomain *pwrdm2);
9331 +int pwrdm_add_sleepdep(struct powerdomain *pwrdm1, struct powerdomain *pwrdm2);
9332 +int pwrdm_del_sleepdep(struct powerdomain *pwrdm1, struct powerdomain *pwrdm2);
9333 +int pwrdm_read_sleepdep(struct powerdomain *pwrdm1, struct powerdomain *pwrdm2);
9334 +
9335 +int pwrdm_get_mem_bank_count(struct powerdomain *pwrdm);
9336 +
9337 +int pwrdm_set_next_pwrst(struct powerdomain *pwrdm, u8 pwrst);
9338 +int pwrdm_read_next_pwrst(struct powerdomain *pwrdm);
9339 +int pwrdm_read_pwrst(struct powerdomain *pwrdm);
9340 +int pwrdm_read_prev_pwrst(struct powerdomain *pwrdm);
9341 +int pwrdm_clear_all_prev_pwrst(struct powerdomain *pwrdm);
9342 +
9343 +int pwrdm_set_logic_retst(struct powerdomain *pwrdm, u8 pwrst);
9344 +int pwrdm_set_mem_onst(struct powerdomain *pwrdm, u8 bank, u8 pwrst);
9345 +int pwrdm_set_mem_retst(struct powerdomain *pwrdm, u8 bank, u8 pwrst);
9346 +
9347 +int pwrdm_read_logic_pwrst(struct powerdomain *pwrdm);
9348 +int pwrdm_read_prev_logic_pwrst(struct powerdomain *pwrdm);
9349 +int pwrdm_read_mem_pwrst(struct powerdomain *pwrdm, u8 bank);
9350 +int pwrdm_read_prev_mem_pwrst(struct powerdomain *pwrdm, u8 bank);
9351 +
9352 +int pwrdm_enable_hdwr_sar(struct powerdomain *pwrdm);
9353 +int pwrdm_disable_hdwr_sar(struct powerdomain *pwrdm);
9354 +bool pwrdm_has_hdwr_sar(struct powerdomain *pwrdm);
9355 +
9356 +int pwrdm_wait_transition(struct powerdomain *pwrdm);
9357 +
9358 +int pwrdm_state_switch(struct powerdomain *pwrdm);
9359 +int pwrdm_clkdm_state_switch(struct clockdomain *clkdm);
9360 +int pwrdm_pre_transition(void);
9361 +int pwrdm_post_transition(void);
9362 +
9363 +#endif
9364 Index: linux-2.6.37-rc1/arch/arm/plat-omap/include/mach/prcm.h
9365 ===================================================================
9366 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
9367 +++ linux-2.6.37-rc1/arch/arm/plat-omap/include/mach/prcm.h 2010-11-05 17:36:26.178000001 +0100
9368 @@ -0,0 +1,39 @@
9369 +/*
9370 + * arch/arm/plat-omap/include/mach/prcm.h
9371 + *
9372 + * Access definations for use in OMAP24XX clock and power management
9373 + *
9374 + * Copyright (C) 2005 Texas Instruments, Inc.
9375 + *
9376 + * This program is free software; you can redistribute it and/or modify
9377 + * it under the terms of the GNU General Public License as published by
9378 + * the Free Software Foundation; either version 2 of the License, or
9379 + * (at your option) any later version.
9380 + *
9381 + * This program is distributed in the hope that it will be useful,
9382 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
9383 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
9384 + * GNU General Public License for more details.
9385 + *
9386 + * You should have received a copy of the GNU General Public License
9387 + * along with this program; if not, write to the Free Software
9388 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
9389 + */
9390 +
9391 +#ifndef __ASM_ARM_ARCH_OMAP_PRCM_H
9392 +#define __ASM_ARM_ARCH_OMAP_PRCM_H
9393 +
9394 +u32 omap_prcm_get_reset_sources(void);
9395 +void omap_prcm_arch_reset(char mode);
9396 +int omap2_cm_wait_idlest(void __iomem *reg, u32 mask, const char *name);
9397 +
9398 +#define START_PADCONF_SAVE 0x2
9399 +#define PADCONF_SAVE_DONE 0x1
9400 +
9401 +void omap3_prcm_save_context(void);
9402 +void omap3_prcm_restore_context(void);
9403 +
9404 +#endif
9405 +
9406 +
9407 +
9408 Index: linux-2.6.37-rc1/arch/arm/plat-omap/include/mach/sdrc.h
9409 ===================================================================
9410 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
9411 +++ linux-2.6.37-rc1/arch/arm/plat-omap/include/mach/sdrc.h 2010-11-05 17:36:26.178000001 +0100
9412 @@ -0,0 +1,158 @@
9413 +#ifndef ____ASM_ARCH_SDRC_H
9414 +#define ____ASM_ARCH_SDRC_H
9415 +
9416 +/*
9417 + * OMAP2/3 SDRC/SMS register definitions
9418 + *
9419 + * Copyright (C) 2007-2008 Texas Instruments, Inc.
9420 + * Copyright (C) 2007-2008 Nokia Corporation
9421 + *
9422 + * Tony Lindgren
9423 + * Paul Walmsley
9424 + * Richard Woodruff
9425 + *
9426 + * This program is free software; you can redistribute it and/or modify
9427 + * it under the terms of the GNU General Public License version 2 as
9428 + * published by the Free Software Foundation.
9429 + */
9430 +
9431 +#include <mach/io.h>
9432 +
9433 +/* SDRC register offsets - read/write with sdrc_{read,write}_reg() */
9434 +
9435 +#define SDRC_SYSCONFIG 0x010
9436 +#define SDRC_CS_CFG 0x040
9437 +#define SDRC_SHARING 0x044
9438 +#define SDRC_ERR_TYPE 0x04C
9439 +#define SDRC_DLLA_CTRL 0x060
9440 +#define SDRC_DLLA_STATUS 0x064
9441 +#define SDRC_DLLB_CTRL 0x068
9442 +#define SDRC_DLLB_STATUS 0x06C
9443 +#define SDRC_POWER 0x070
9444 +#define SDRC_MCFG_0 0x080
9445 +#define SDRC_MR_0 0x084
9446 +#define SDRC_EMR2_0 0x08c
9447 +#define SDRC_ACTIM_CTRL_A_0 0x09c
9448 +#define SDRC_ACTIM_CTRL_B_0 0x0a0
9449 +#define SDRC_RFR_CTRL_0 0x0a4
9450 +#define SDRC_MANUAL_0 0x0a8
9451 +#define SDRC_MCFG_1 0x0B0
9452 +#define SDRC_MR_1 0x0B4
9453 +#define SDRC_EMR2_1 0x0BC
9454 +#define SDRC_ACTIM_CTRL_A_1 0x0C4
9455 +#define SDRC_ACTIM_CTRL_B_1 0x0C8
9456 +#define SDRC_RFR_CTRL_1 0x0D4
9457 +#define SDRC_MANUAL_1 0x0D8
9458 +
9459 +#define SDRC_POWER_AUTOCOUNT_SHIFT 8
9460 +#define SDRC_POWER_AUTOCOUNT_MASK (0xffff << SDRC_POWER_AUTOCOUNT_SHIFT)
9461 +#define SDRC_POWER_CLKCTRL_SHIFT 4
9462 +#define SDRC_POWER_CLKCTRL_MASK (0x3 << SDRC_POWER_CLKCTRL_SHIFT)
9463 +#define SDRC_SELF_REFRESH_ON_AUTOCOUNT (0x2 << SDRC_POWER_CLKCTRL_SHIFT)
9464 +
9465 +/*
9466 + * These values represent the number of memory clock cycles between
9467 + * autorefresh initiation. They assume 1 refresh per 64 ms (JEDEC), 8192
9468 + * rows per device, and include a subtraction of a 50 cycle window in the
9469 + * event that the autorefresh command is delayed due to other SDRC activity.
9470 + * The '| 1' sets the ARE field to send one autorefresh when the autorefresh
9471 + * counter reaches 0.
9472 + *
9473 + * These represent optimal values for common parts, it won't work for all.
9474 + * As long as you scale down, most parameters are still work, they just
9475 + * become sub-optimal. The RFR value goes in the opposite direction. If you
9476 + * don't adjust it down as your clock period increases the refresh interval
9477 + * will not be met. Setting all parameters for complete worst case may work,
9478 + * but may cut memory performance by 2x. Due to errata the DLLs need to be
9479 + * unlocked and their value needs run time calibration. A dynamic call is
9480 + * need for that as no single right value exists acorss production samples.
9481 + *
9482 + * Only the FULL speed values are given. Current code is such that rate
9483 + * changes must be made at DPLLoutx2. The actual value adjustment for low
9484 + * frequency operation will be handled by omap_set_performance()
9485 + *
9486 + * By having the boot loader boot up in the fastest L4 speed available likely
9487 + * will result in something which you can switch between.
9488 + */
9489 +#define SDRC_RFR_CTRL_165MHz (0x00044c00 | 1)
9490 +#define SDRC_RFR_CTRL_133MHz (0x0003de00 | 1)
9491 +#define SDRC_RFR_CTRL_100MHz (0x0002da01 | 1)
9492 +#define SDRC_RFR_CTRL_110MHz (0x0002da01 | 1) /* Need to calc */
9493 +#define SDRC_RFR_CTRL_BYPASS (0x00005000 | 1) /* Need to calc */
9494 +
9495 +
9496 +/*
9497 + * SMS register access
9498 + */
9499 +
9500 +#define OMAP242X_SMS_REGADDR(reg) \
9501 + (void __iomem *)OMAP2_L3_IO_ADDRESS(OMAP2420_SMS_BASE + reg)
9502 +#define OMAP243X_SMS_REGADDR(reg) \
9503 + (void __iomem *)OMAP2_L3_IO_ADDRESS(OMAP243X_SMS_BASE + reg)
9504 +#define OMAP343X_SMS_REGADDR(reg) \
9505 + (void __iomem *)OMAP2_L3_IO_ADDRESS(OMAP343X_SMS_BASE + reg)
9506 +
9507 +/* SMS register offsets - read/write with sms_{read,write}_reg() */
9508 +
9509 +#define SMS_SYSCONFIG 0x010
9510 +#define SMS_ROT_CONTROL(context) (0x180 + 0x10 * context)
9511 +#define SMS_ROT_SIZE(context) (0x184 + 0x10 * context)
9512 +#define SMS_ROT_PHYSICAL_BA(context) (0x188 + 0x10 * context)
9513 +/* REVISIT: fill in other SMS registers here */
9514 +
9515 +
9516 +#ifndef __ASSEMBLER__
9517 +
9518 +/**
9519 + * struct omap_sdrc_params - SDRC parameters for a given SDRC clock rate
9520 + * @rate: SDRC clock rate (in Hz)
9521 + * @actim_ctrla: Value to program to SDRC_ACTIM_CTRLA for this rate
9522 + * @actim_ctrlb: Value to program to SDRC_ACTIM_CTRLB for this rate
9523 + * @rfr_ctrl: Value to program to SDRC_RFR_CTRL for this rate
9524 + * @mr: Value to program to SDRC_MR for this rate
9525 + *
9526 + * This structure holds a pre-computed set of register values for the
9527 + * SDRC for a given SDRC clock rate and SDRAM chip. These are
9528 + * intended to be pre-computed and specified in an array in the board-*.c
9529 + * files. The structure is keyed off the 'rate' field.
9530 + */
9531 +struct omap_sdrc_params {
9532 + unsigned long rate;
9533 + u32 actim_ctrla;
9534 + u32 actim_ctrlb;
9535 + u32 rfr_ctrl;
9536 + u32 mr;
9537 +};
9538 +
9539 +void __init omap2_sdrc_init(struct omap_sdrc_params *sdrc_cs0,
9540 + struct omap_sdrc_params *sdrc_cs1);
9541 +int omap2_sdrc_get_params(unsigned long r,
9542 + struct omap_sdrc_params **sdrc_cs0,
9543 + struct omap_sdrc_params **sdrc_cs1);
9544 +void omap2_sms_save_context(void);
9545 +void omap2_sms_restore_context(void);
9546 +
9547 +void omap2_sms_write_rot_control(u32 val, unsigned ctx);
9548 +void omap2_sms_write_rot_size(u32 val, unsigned ctx);
9549 +void omap2_sms_write_rot_physical_ba(u32 val, unsigned ctx);
9550 +
9551 +#ifdef CONFIG_ARCH_OMAP2
9552 +
9553 +struct memory_timings {
9554 + u32 m_type; /* ddr = 1, sdr = 0 */
9555 + u32 dll_mode; /* use lock mode = 1, unlock mode = 0 */
9556 + u32 slow_dll_ctrl; /* unlock mode, dll value for slow speed */
9557 + u32 fast_dll_ctrl; /* unlock mode, dll value for fast speed */
9558 + u32 base_cs; /* base chip select to use for calculations */
9559 +};
9560 +
9561 +extern void omap2xxx_sdrc_init_params(u32 force_lock_to_unlock_mode);
9562 +
9563 +u32 omap2xxx_sdrc_dll_is_unlocked(void);
9564 +u32 omap2xxx_sdrc_reprogram(u32 level, u32 force);
9565 +
9566 +#endif /* CONFIG_ARCH_OMAP2 */
9567 +
9568 +#endif /* __ASSEMBLER__ */
9569 +
9570 +#endif
9571 Index: linux-2.6.37-rc1/arch/arm/plat-omap/include/mach/serial.h
9572 ===================================================================
9573 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
9574 +++ linux-2.6.37-rc1/arch/arm/plat-omap/include/mach/serial.h 2010-11-05 17:36:26.178000001 +0100
9575 @@ -0,0 +1,65 @@
9576 +/*
9577 + * arch/arm/plat-omap/include/mach/serial.h
9578 + *
9579 + * Copyright (C) 2009 Texas Instruments
9580 + * Addded OMAP4 support- Santosh Shilimkar <santosh.shilimkar@ti.com>
9581 + *
9582 + * This program is distributed in the hope that it will be useful,
9583 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
9584 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
9585 + * GNU General Public License for more details.
9586 + */
9587 +
9588 +#ifndef __ASM_ARCH_SERIAL_H
9589 +#define __ASM_ARCH_SERIAL_H
9590 +
9591 +#include <linux/init.h>
9592 +
9593 +#if defined(CONFIG_ARCH_OMAP1)
9594 +/* OMAP1 serial ports */
9595 +#define OMAP_UART1_BASE 0xfffb0000
9596 +#define OMAP_UART2_BASE 0xfffb0800
9597 +#define OMAP_UART3_BASE 0xfffb9800
9598 +#elif defined(CONFIG_ARCH_OMAP2)
9599 +/* OMAP2 serial ports */
9600 +#define OMAP_UART1_BASE 0x4806a000
9601 +#define OMAP_UART2_BASE 0x4806c000
9602 +#define OMAP_UART3_BASE 0x4806e000
9603 +#elif defined(CONFIG_ARCH_OMAP3)
9604 +/* OMAP3 serial ports */
9605 +#define OMAP_UART1_BASE 0x4806a000
9606 +#define OMAP_UART2_BASE 0x4806c000
9607 +#define OMAP_UART3_BASE 0x49020000
9608 +#elif defined(CONFIG_ARCH_OMAP4)
9609 +/* OMAP4 serial ports */
9610 +#define OMAP_UART1_BASE 0x4806a000
9611 +#define OMAP_UART2_BASE 0x4806c000
9612 +#define OMAP_UART3_BASE 0x48020000
9613 +#define OMAP_UART4_BASE 0x4806e000
9614 +#endif
9615 +
9616 +#define OMAP1510_BASE_BAUD (12000000/16)
9617 +#define OMAP16XX_BASE_BAUD (48000000/16)
9618 +#define OMAP24XX_BASE_BAUD (48000000/16)
9619 +
9620 +#define is_omap_port(pt) ({int __ret = 0; \
9621 + if ((pt)->port.mapbase == OMAP_UART1_BASE || \
9622 + (pt)->port.mapbase == OMAP_UART2_BASE || \
9623 + (pt)->port.mapbase == OMAP_UART3_BASE) \
9624 + __ret = 1; \
9625 + __ret; \
9626 + })
9627 +
9628 +#ifndef __ASSEMBLER__
9629 +extern void __init omap_serial_early_init(void);
9630 +extern void omap_serial_init(void);
9631 +extern void omap_serial_init_port(int port);
9632 +extern int omap_uart_can_sleep(void);
9633 +extern void omap_uart_check_wakeup(void);
9634 +extern void omap_uart_prepare_suspend(void);
9635 +extern void omap_uart_prepare_idle(int num);
9636 +extern void omap_uart_resume_idle(int num);
9637 +extern void omap_uart_enable_irqs(int enable);
9638 +#endif
9639 +
9640 +#endif
9641 Index: linux-2.6.37-rc1/arch/arm/plat-omap/include/mach/smp.h
9642 ===================================================================
9643 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
9644 +++ linux-2.6.37-rc1/arch/arm/plat-omap/include/mach/smp.h 2010-11-05 17:36:26.178000001 +0100
9645 @@ -0,0 +1,53 @@
9646 +/*
9647 + * OMAP4 machine specific smp.h
9648 + *
9649 + * Copyright (C) 2009 Texas Instruments, Inc.
9650 + *
9651 + * Author:
9652 + * Santosh Shilimkar <santosh.shilimkar@ti.com>
9653 + *
9654 + * Interface functions needed for the SMP. This file is based on arm
9655 + * realview smp platform.
9656 + * Copyright (c) 2003 ARM Limited.
9657 + *
9658 + * This program is free software; you can redistribute it and/or modify
9659 + * it under the terms of the GNU General Public License version 2 as
9660 + * published by the Free Software Foundation.
9661 + */
9662 +#ifndef OMAP_ARCH_SMP_H
9663 +#define OMAP_ARCH_SMP_H
9664 +
9665 +#include <asm/hardware/gic.h>
9666 +
9667 +/*
9668 + * set_event() is used to wake up secondary core from wfe using sev. ROM
9669 + * code puts the second core into wfe(standby).
9670 + *
9671 + */
9672 +#define set_event() __asm__ __volatile__ ("sev" : : : "memory")
9673 +
9674 +/* Needed for secondary core boot */
9675 +extern void omap_secondary_startup(void);
9676 +extern u32 omap_modify_auxcoreboot0(u32 set_mask, u32 clear_mask);
9677 +extern void omap_auxcoreboot_addr(u32 cpu_addr);
9678 +
9679 +/*
9680 + * We use Soft IRQ1 as the IPI
9681 + */
9682 +static inline void smp_cross_call(const struct cpumask *mask)
9683 +{
9684 + gic_raise_softirq(mask, 1);
9685 +}
9686 +
9687 +/*
9688 + * Read MPIDR: Multiprocessor affinity register
9689 + */
9690 +#define hard_smp_processor_id() \
9691 + ({ \
9692 + unsigned int cpunum; \
9693 + __asm__("mrc p15, 0, %0, c0, c0, 5" \
9694 + : "=r" (cpunum)); \
9695 + cpunum &= 0x0F; \
9696 + })
9697 +
9698 +#endif
9699 Index: linux-2.6.37-rc1/arch/arm/plat-omap/include/mach/sram.h
9700 ===================================================================
9701 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
9702 +++ linux-2.6.37-rc1/arch/arm/plat-omap/include/mach/sram.h 2010-11-05 17:36:26.178000001 +0100
9703 @@ -0,0 +1,78 @@
9704 +/*
9705 + * arch/arm/plat-omap/include/mach/sram.h
9706 + *
9707 + * Interface for functions that need to be run in internal SRAM
9708 + *
9709 + * This program is free software; you can redistribute it and/or modify
9710 + * it under the terms of the GNU General Public License version 2 as
9711 + * published by the Free Software Foundation.
9712 + */
9713 +
9714 +#ifndef __ARCH_ARM_OMAP_SRAM_H
9715 +#define __ARCH_ARM_OMAP_SRAM_H
9716 +
9717 +extern int __init omap_sram_init(void);
9718 +extern void * omap_sram_push(void * start, unsigned long size);
9719 +extern void omap_sram_reprogram_clock(u32 dpllctl, u32 ckctl);
9720 +
9721 +extern void omap2_sram_ddr_init(u32 *slow_dll_ctrl, u32 fast_dll_ctrl,
9722 + u32 base_cs, u32 force_unlock);
9723 +extern void omap2_sram_reprogram_sdrc(u32 perf_level, u32 dll_val,
9724 + u32 mem_type);
9725 +extern u32 omap2_set_prcm(u32 dpll_ctrl_val, u32 sdrc_rfr_val, int bypass);
9726 +
9727 +extern u32 omap3_configure_core_dpll(
9728 + u32 m2, u32 unlock_dll, u32 f, u32 inc,
9729 + u32 sdrc_rfr_ctrl_0, u32 sdrc_actim_ctrl_a_0,
9730 + u32 sdrc_actim_ctrl_b_0, u32 sdrc_mr_0,
9731 + u32 sdrc_rfr_ctrl_1, u32 sdrc_actim_ctrl_a_1,
9732 + u32 sdrc_actim_ctrl_b_1, u32 sdrc_mr_1);
9733 +extern void omap3_sram_restore_context(void);
9734 +
9735 +/* Do not use these */
9736 +extern void omap1_sram_reprogram_clock(u32 ckctl, u32 dpllctl);
9737 +extern unsigned long omap1_sram_reprogram_clock_sz;
9738 +
9739 +extern void omap24xx_sram_reprogram_clock(u32 ckctl, u32 dpllctl);
9740 +extern unsigned long omap24xx_sram_reprogram_clock_sz;
9741 +
9742 +extern void omap242x_sram_ddr_init(u32 *slow_dll_ctrl, u32 fast_dll_ctrl,
9743 + u32 base_cs, u32 force_unlock);
9744 +extern unsigned long omap242x_sram_ddr_init_sz;
9745 +
9746 +extern u32 omap242x_sram_set_prcm(u32 dpll_ctrl_val, u32 sdrc_rfr_val,
9747 + int bypass);
9748 +extern unsigned long omap242x_sram_set_prcm_sz;
9749 +
9750 +extern void omap242x_sram_reprogram_sdrc(u32 perf_level, u32 dll_val,
9751 + u32 mem_type);
9752 +extern unsigned long omap242x_sram_reprogram_sdrc_sz;
9753 +
9754 +
9755 +extern void omap243x_sram_ddr_init(u32 *slow_dll_ctrl, u32 fast_dll_ctrl,
9756 + u32 base_cs, u32 force_unlock);
9757 +extern unsigned long omap243x_sram_ddr_init_sz;
9758 +
9759 +extern u32 omap243x_sram_set_prcm(u32 dpll_ctrl_val, u32 sdrc_rfr_val,
9760 + int bypass);
9761 +extern unsigned long omap243x_sram_set_prcm_sz;
9762 +
9763 +extern void omap243x_sram_reprogram_sdrc(u32 perf_level, u32 dll_val,
9764 + u32 mem_type);
9765 +extern unsigned long omap243x_sram_reprogram_sdrc_sz;
9766 +
9767 +extern u32 omap3_sram_configure_core_dpll(
9768 + u32 m2, u32 unlock_dll, u32 f, u32 inc,
9769 + u32 sdrc_rfr_ctrl_0, u32 sdrc_actim_ctrl_a_0,
9770 + u32 sdrc_actim_ctrl_b_0, u32 sdrc_mr_0,
9771 + u32 sdrc_rfr_ctrl_1, u32 sdrc_actim_ctrl_a_1,
9772 + u32 sdrc_actim_ctrl_b_1, u32 sdrc_mr_1);
9773 +extern unsigned long omap3_sram_configure_core_dpll_sz;
9774 +
9775 +#ifdef CONFIG_PM
9776 +extern void omap_push_sram_idle(void);
9777 +#else
9778 +static inline void omap_push_sram_idle(void) {}
9779 +#endif /* CONFIG_PM */
9780 +
9781 +#endif
9782 Index: linux-2.6.37-rc1/arch/arm/plat-omap/include/mach/system.h
9783 ===================================================================
9784 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
9785 +++ linux-2.6.37-rc1/arch/arm/plat-omap/include/mach/system.h 2010-11-05 17:36:26.179000001 +0100
9786 @@ -0,0 +1,51 @@
9787 +/*
9788 + * Copied from arch/arm/mach-sa1100/include/mach/system.h
9789 + * Copyright (c) 1999 Nicolas Pitre <nico@fluxnic.net>
9790 + */
9791 +#ifndef __ASM_ARCH_SYSTEM_H
9792 +#define __ASM_ARCH_SYSTEM_H
9793 +#include <linux/clk.h>
9794 +
9795 +#include <asm/mach-types.h>
9796 +#include <mach/hardware.h>
9797 +
9798 +#include <plat/prcm.h>
9799 +
9800 +#ifndef CONFIG_MACH_VOICEBLUE
9801 +#define voiceblue_reset() do {} while (0)
9802 +#else
9803 +extern void voiceblue_reset(void);
9804 +#endif
9805 +
9806 +static inline void arch_idle(void)
9807 +{
9808 + cpu_do_idle();
9809 +}
9810 +
9811 +static inline void omap1_arch_reset(char mode)
9812 +{
9813 + /*
9814 + * Workaround for 5912/1611b bug mentioned in sprz209d.pdf p. 28
9815 + * "Global Software Reset Affects Traffic Controller Frequency".
9816 + */
9817 + if (cpu_is_omap5912()) {
9818 + omap_writew(omap_readw(DPLL_CTL) & ~(1 << 4),
9819 + DPLL_CTL);
9820 + omap_writew(0x8, ARM_RSTCT1);
9821 + }
9822 +
9823 + if (machine_is_voiceblue())
9824 + voiceblue_reset();
9825 + else
9826 + omap_writew(1, ARM_RSTCT1);
9827 +}
9828 +
9829 +static inline void arch_reset(char mode, const char *cmd)
9830 +{
9831 + if (!cpu_class_is_omap2())
9832 + omap1_arch_reset(mode);
9833 + else
9834 + omap_prcm_arch_reset(mode);
9835 +}
9836 +
9837 +#endif
9838 Index: linux-2.6.37-rc1/arch/arm/plat-omap/include/mach/tc.h
9839 ===================================================================
9840 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
9841 +++ linux-2.6.37-rc1/arch/arm/plat-omap/include/mach/tc.h 2010-11-05 17:36:26.179000001 +0100
9842 @@ -0,0 +1,106 @@
9843 +/*
9844 + * arch/arm/plat-omap/include/mach/tc.h
9845 + *
9846 + * OMAP Traffic Controller
9847 + *
9848 + * Copyright (C) 2004 Nokia Corporation
9849 + * Author: Imre Deak <imre.deak@nokia.com>
9850 + *
9851 + * This program is free software; you can redistribute it and/or modify it
9852 + * under the terms of the GNU General Public License as published by the
9853 + * Free Software Foundation; either version 2 of the License, or (at your
9854 + * option) any later version.
9855 + *
9856 + * This program is distributed in the hope that it will be useful, but
9857 + * WITHOUT ANY WARRANTY; without even the implied warranty of
9858 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
9859 + * General Public License for more details.
9860 + *
9861 + * You should have received a copy of the GNU General Public License along
9862 + * with this program; if not, write to the Free Software Foundation, Inc.,
9863 + * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
9864 + */
9865 +
9866 +#ifndef __ASM_ARCH_TC_H
9867 +#define __ASM_ARCH_TC_H
9868 +
9869 +#define TCMIF_BASE 0xfffecc00
9870 +#define OMAP_TC_OCPT1_PRIOR (TCMIF_BASE + 0x00)
9871 +#define OMAP_TC_EMIFS_PRIOR (TCMIF_BASE + 0x04)
9872 +#define OMAP_TC_EMIFF_PRIOR (TCMIF_BASE + 0x08)
9873 +#define EMIFS_CONFIG (TCMIF_BASE + 0x0c)
9874 +#define EMIFS_CS0_CONFIG (TCMIF_BASE + 0x10)
9875 +#define EMIFS_CS1_CONFIG (TCMIF_BASE + 0x14)
9876 +#define EMIFS_CS2_CONFIG (TCMIF_BASE + 0x18)
9877 +#define EMIFS_CS3_CONFIG (TCMIF_BASE + 0x1c)
9878 +#define EMIFF_SDRAM_CONFIG (TCMIF_BASE + 0x20)
9879 +#define EMIFF_MRS (TCMIF_BASE + 0x24)
9880 +#define TC_TIMEOUT1 (TCMIF_BASE + 0x28)
9881 +#define TC_TIMEOUT2 (TCMIF_BASE + 0x2c)
9882 +#define TC_TIMEOUT3 (TCMIF_BASE + 0x30)
9883 +#define TC_ENDIANISM (TCMIF_BASE + 0x34)
9884 +#define EMIFF_SDRAM_CONFIG_2 (TCMIF_BASE + 0x3c)
9885 +#define EMIF_CFG_DYNAMIC_WS (TCMIF_BASE + 0x40)
9886 +#define EMIFS_ACS0 (TCMIF_BASE + 0x50)
9887 +#define EMIFS_ACS1 (TCMIF_BASE + 0x54)
9888 +#define EMIFS_ACS2 (TCMIF_BASE + 0x58)
9889 +#define EMIFS_ACS3 (TCMIF_BASE + 0x5c)
9890 +#define OMAP_TC_OCPT2_PRIOR (TCMIF_BASE + 0xd0)
9891 +
9892 +/* external EMIFS chipselect regions */
9893 +#define OMAP_CS0_PHYS 0x00000000
9894 +#define OMAP_CS0_SIZE SZ_64M
9895 +
9896 +#define OMAP_CS1_PHYS 0x04000000
9897 +#define OMAP_CS1_SIZE SZ_64M
9898 +
9899 +#define OMAP_CS1A_PHYS OMAP_CS1_PHYS
9900 +#define OMAP_CS1A_SIZE SZ_32M
9901 +
9902 +#define OMAP_CS1B_PHYS (OMAP_CS1A_PHYS + OMAP_CS1A_SIZE)
9903 +#define OMAP_CS1B_SIZE SZ_32M
9904 +
9905 +#define OMAP_CS2_PHYS 0x08000000
9906 +#define OMAP_CS2_SIZE SZ_64M
9907 +
9908 +#define OMAP_CS2A_PHYS OMAP_CS2_PHYS
9909 +#define OMAP_CS2A_SIZE SZ_32M
9910 +
9911 +#define OMAP_CS2B_PHYS (OMAP_CS2A_PHYS + OMAP_CS2A_SIZE)
9912 +#define OMAP_CS2B_SIZE SZ_32M
9913 +
9914 +#define OMAP_CS3_PHYS 0x0c000000
9915 +#define OMAP_CS3_SIZE SZ_64M
9916 +
9917 +#ifndef __ASSEMBLER__
9918 +
9919 +/* EMIF Slow Interface Configuration Register */
9920 +#define OMAP_EMIFS_CONFIG_FR (1 << 4)
9921 +#define OMAP_EMIFS_CONFIG_PDE (1 << 3)
9922 +#define OMAP_EMIFS_CONFIG_PWD_EN (1 << 2)
9923 +#define OMAP_EMIFS_CONFIG_BM (1 << 1)
9924 +#define OMAP_EMIFS_CONFIG_WP (1 << 0)
9925 +
9926 +#define EMIFS_CCS(n) (EMIFS_CS0_CONFIG + (4 * (n)))
9927 +#define EMIFS_ACS(n) (EMIFS_ACS0 + (4 * (n)))
9928 +
9929 +/* Almost all documentation for chip and board memory maps assumes
9930 + * BM is clear. Most devel boards have a switch to control booting
9931 + * from NOR flash (using external chipselect 3) rather than mask ROM,
9932 + * which uses BM to interchange the physical CS0 and CS3 addresses.
9933 + */
9934 +static inline u32 omap_cs0_phys(void)
9935 +{
9936 + return (omap_readl(EMIFS_CONFIG) & OMAP_EMIFS_CONFIG_BM)
9937 + ? OMAP_CS3_PHYS : 0;
9938 +}
9939 +
9940 +static inline u32 omap_cs3_phys(void)
9941 +{
9942 + return (omap_readl(EMIFS_CONFIG) & OMAP_EMIFS_CONFIG_BM)
9943 + ? 0 : OMAP_CS3_PHYS;
9944 +}
9945 +
9946 +#endif /* __ASSEMBLER__ */
9947 +
9948 +#endif /* __ASM_ARCH_TC_H */
9949 Index: linux-2.6.37-rc1/arch/arm/plat-omap/include/mach/timer-gp.h
9950 ===================================================================
9951 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
9952 +++ linux-2.6.37-rc1/arch/arm/plat-omap/include/mach/timer-gp.h 2010-11-05 17:36:26.179000001 +0100
9953 @@ -0,0 +1,17 @@
9954 +/*
9955 + * OMAP2/3 GPTIMER support.headers
9956 + *
9957 + * Copyright (C) 2009 Nokia Corporation
9958 + *
9959 + * This file is subject to the terms and conditions of the GNU General Public
9960 + * License. See the file "COPYING" in the main directory of this archive
9961 + * for more details.
9962 + */
9963 +
9964 +#ifndef __ARCH_ARM_PLAT_OMAP_INCLUDE_MACH_TIMER_GP_H
9965 +#define __ARCH_ARM_PLAT_OMAP_INCLUDE_MACH_TIMER_GP_H
9966 +
9967 +int __init omap2_gp_clockevent_set_gptimer(u8 id);
9968 +
9969 +#endif
9970 +
9971 Index: linux-2.6.37-rc1/arch/arm/plat-omap/include/mach/timex.h
9972 ===================================================================
9973 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
9974 +++ linux-2.6.37-rc1/arch/arm/plat-omap/include/mach/timex.h 2010-11-05 17:36:26.179000001 +0100
9975 @@ -0,0 +1,41 @@
9976 +/*
9977 + * arch/arm/plat-omap/include/mach/timex.h
9978 + *
9979 + * Copyright (C) 2000 RidgeRun, Inc.
9980 + * Author: Greg Lonnon <glonnon@ridgerun.com>
9981 + *
9982 + * This program is free software; you can redistribute it and/or modify it
9983 + * under the terms of the GNU General Public License as published by the
9984 + * Free Software Foundation; either version 2 of the License, or (at your
9985 + * option) any later version.
9986 + *
9987 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
9988 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
9989 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
9990 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
9991 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
9992 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
9993 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
9994 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
9995 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
9996 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
9997 + *
9998 + * You should have received a copy of the GNU General Public License along
9999 + * with this program; if not, write to the Free Software Foundation, Inc.,
10000 + * 675 Mass Ave, Cambridge, MA 02139, USA.
10001 + */
10002 +
10003 +#if !defined(__ASM_ARCH_OMAP_TIMEX_H)
10004 +#define __ASM_ARCH_OMAP_TIMEX_H
10005 +
10006 +/*
10007 + * OMAP 32KHz timer updates time one jiffie at a time from a secondary timer,
10008 + * and that's why the CLOCK_TICK_RATE is not 32768.
10009 + */
10010 +#ifdef CONFIG_OMAP_32K_TIMER
10011 +#define CLOCK_TICK_RATE (CONFIG_OMAP_32K_TIMER_HZ)
10012 +#else
10013 +#define CLOCK_TICK_RATE (HZ * 100000UL)
10014 +#endif
10015 +
10016 +#endif /* __ASM_ARCH_OMAP_TIMEX_H */
10017 Index: linux-2.6.37-rc1/arch/arm/plat-omap/include/mach/uncompress.h
10018 ===================================================================
10019 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
10020 +++ linux-2.6.37-rc1/arch/arm/plat-omap/include/mach/uncompress.h 2010-11-05 17:36:26.179000001 +0100
10021 @@ -0,0 +1,88 @@
10022 +/*
10023 + * arch/arm/plat-omap/include/mach/uncompress.h
10024 + *
10025 + * Serial port stubs for kernel decompress status messages
10026 + *
10027 + * Initially based on:
10028 + * linux-2.4.15-rmk1-dsplinux1.6/arch/arm/plat-omap/include/mach1510/uncompress.h
10029 + * Copyright (C) 2000 RidgeRun, Inc.
10030 + * Author: Greg Lonnon <glonnon@ridgerun.com>
10031 + *
10032 + * Rewritten by:
10033 + * Author: <source@mvista.com>
10034 + * 2004 (c) MontaVista Software, Inc.
10035 + *
10036 + * This file is licensed under the terms of the GNU General Public License
10037 + * version 2. This program is licensed "as is" without any warranty of any
10038 + * kind, whether express or implied.
10039 + */
10040 +
10041 +#include <linux/types.h>
10042 +#include <linux/serial_reg.h>
10043 +#include <plat/serial.h>
10044 +
10045 +unsigned int system_rev;
10046 +
10047 +#define UART_OMAP_MDR1 0x08 /* mode definition register */
10048 +#define OMAP_ID_730 0x355F
10049 +#define OMAP_ID_850 0x362C
10050 +#define ID_MASK 0x7fff
10051 +#define check_port(base, shift) ((base[UART_OMAP_MDR1 << shift] & 7) == 0)
10052 +#define omap_get_id() ((*(volatile unsigned int *)(0xfffed404)) >> 12) & ID_MASK
10053 +
10054 +static void putc(int c)
10055 +{
10056 + volatile u8 * uart = 0;
10057 + int shift = 2;
10058 +
10059 +#ifdef CONFIG_MACH_OMAP_PALMTE
10060 + return;
10061 +#endif
10062 +
10063 +#ifdef CONFIG_ARCH_OMAP
10064 +#ifdef CONFIG_OMAP_LL_DEBUG_UART3
10065 + uart = (volatile u8 *)(OMAP_UART3_BASE);
10066 +#elif defined(CONFIG_OMAP_LL_DEBUG_UART2)
10067 + uart = (volatile u8 *)(OMAP_UART2_BASE);
10068 +#elif defined(CONFIG_OMAP_LL_DEBUG_UART1)
10069 + uart = (volatile u8 *)(OMAP_UART1_BASE);
10070 +#elif defined(CONFIG_OMAP_LL_DEBUG_NONE)
10071 + return;
10072 +#else
10073 + return;
10074 +#endif
10075 +
10076 +#ifdef CONFIG_ARCH_OMAP1
10077 + /* Determine which serial port to use */
10078 + do {
10079 + /* MMU is not on, so cpu_is_omapXXXX() won't work here */
10080 + unsigned int omap_id = omap_get_id();
10081 +
10082 + if (omap_id == OMAP_ID_730 || omap_id == OMAP_ID_850)
10083 + shift = 0;
10084 +
10085 + if (check_port(uart, shift))
10086 + break;
10087 + /* Silent boot if no serial ports are enabled. */
10088 + return;
10089 + } while (0);
10090 +#endif /* CONFIG_ARCH_OMAP1 */
10091 +#endif
10092 +
10093 + /*
10094 + * Now, xmit each character
10095 + */
10096 + while (!(uart[UART_LSR << shift] & UART_LSR_THRE))
10097 + barrier();
10098 + uart[UART_TX << shift] = c;
10099 +}
10100 +
10101 +static inline void flush(void)
10102 +{
10103 +}
10104 +
10105 +/*
10106 + * nothing to do
10107 + */
10108 +#define arch_decomp_setup()
10109 +#define arch_decomp_wdog()
10110 Index: linux-2.6.37-rc1/arch/arm/plat-omap/include/mach/usb.h
10111 ===================================================================
10112 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
10113 +++ linux-2.6.37-rc1/arch/arm/plat-omap/include/mach/usb.h 2010-11-05 17:36:26.179000001 +0100
10114 @@ -0,0 +1,162 @@
10115 +// include/asm-arm/mach-omap/usb.h
10116 +
10117 +#ifndef __ASM_ARCH_OMAP_USB_H
10118 +#define __ASM_ARCH_OMAP_USB_H
10119 +
10120 +#include <plat/board.h>
10121 +
10122 +#define OMAP3_HS_USB_PORTS 3
10123 +enum ehci_hcd_omap_mode {
10124 + EHCI_HCD_OMAP_MODE_UNKNOWN,
10125 + EHCI_HCD_OMAP_MODE_PHY,
10126 + EHCI_HCD_OMAP_MODE_TLL,
10127 +};
10128 +
10129 +struct ehci_hcd_omap_platform_data {
10130 + enum ehci_hcd_omap_mode port_mode[OMAP3_HS_USB_PORTS];
10131 + unsigned phy_reset:1;
10132 +
10133 + /* have to be valid if phy_reset is true and portx is in phy mode */
10134 + int reset_gpio_port[OMAP3_HS_USB_PORTS];
10135 +};
10136 +
10137 +/*-------------------------------------------------------------------------*/
10138 +
10139 +#define OMAP1_OTG_BASE 0xfffb0400
10140 +#define OMAP1_UDC_BASE 0xfffb4000
10141 +#define OMAP1_OHCI_BASE 0xfffba000
10142 +
10143 +#define OMAP2_OHCI_BASE 0x4805e000
10144 +#define OMAP2_UDC_BASE 0x4805e200
10145 +#define OMAP2_OTG_BASE 0x4805e300
10146 +
10147 +#ifdef CONFIG_ARCH_OMAP1
10148 +
10149 +#define OTG_BASE OMAP1_OTG_BASE
10150 +#define UDC_BASE OMAP1_UDC_BASE
10151 +#define OMAP_OHCI_BASE OMAP1_OHCI_BASE
10152 +
10153 +#else
10154 +
10155 +#define OTG_BASE OMAP2_OTG_BASE
10156 +#define UDC_BASE OMAP2_UDC_BASE
10157 +#define OMAP_OHCI_BASE OMAP2_OHCI_BASE
10158 +
10159 +extern void usb_musb_init(void);
10160 +
10161 +extern void usb_ehci_init(struct ehci_hcd_omap_platform_data *pdata);
10162 +
10163 +#endif
10164 +
10165 +void omap_usb_init(struct omap_usb_config *pdata);
10166 +
10167 +/*-------------------------------------------------------------------------*/
10168 +
10169 +/*
10170 + * OTG and transceiver registers, for OMAPs starting with ARM926
10171 + */
10172 +#define OTG_REV (OTG_BASE + 0x00)
10173 +#define OTG_SYSCON_1 (OTG_BASE + 0x04)
10174 +# define USB2_TRX_MODE(w) (((w)>>24)&0x07)
10175 +# define USB1_TRX_MODE(w) (((w)>>20)&0x07)
10176 +# define USB0_TRX_MODE(w) (((w)>>16)&0x07)
10177 +# define OTG_IDLE_EN (1 << 15)
10178 +# define HST_IDLE_EN (1 << 14)
10179 +# define DEV_IDLE_EN (1 << 13)
10180 +# define OTG_RESET_DONE (1 << 2)
10181 +# define OTG_SOFT_RESET (1 << 1)
10182 +#define OTG_SYSCON_2 (OTG_BASE + 0x08)
10183 +# define OTG_EN (1 << 31)
10184 +# define USBX_SYNCHRO (1 << 30)
10185 +# define OTG_MST16 (1 << 29)
10186 +# define SRP_GPDATA (1 << 28)
10187 +# define SRP_GPDVBUS (1 << 27)
10188 +# define SRP_GPUVBUS(w) (((w)>>24)&0x07)
10189 +# define A_WAIT_VRISE(w) (((w)>>20)&0x07)
10190 +# define B_ASE_BRST(w) (((w)>>16)&0x07)
10191 +# define SRP_DPW (1 << 14)
10192 +# define SRP_DATA (1 << 13)
10193 +# define SRP_VBUS (1 << 12)
10194 +# define OTG_PADEN (1 << 10)
10195 +# define HMC_PADEN (1 << 9)
10196 +# define UHOST_EN (1 << 8)
10197 +# define HMC_TLLSPEED (1 << 7)
10198 +# define HMC_TLLATTACH (1 << 6)
10199 +# define OTG_HMC(w) (((w)>>0)&0x3f)
10200 +#define OTG_CTRL (OTG_BASE + 0x0c)
10201 +# define OTG_USB2_EN (1 << 29)
10202 +# define OTG_USB2_DP (1 << 28)
10203 +# define OTG_USB2_DM (1 << 27)
10204 +# define OTG_USB1_EN (1 << 26)
10205 +# define OTG_USB1_DP (1 << 25)
10206 +# define OTG_USB1_DM (1 << 24)
10207 +# define OTG_USB0_EN (1 << 23)
10208 +# define OTG_USB0_DP (1 << 22)
10209 +# define OTG_USB0_DM (1 << 21)
10210 +# define OTG_ASESSVLD (1 << 20)
10211 +# define OTG_BSESSEND (1 << 19)
10212 +# define OTG_BSESSVLD (1 << 18)
10213 +# define OTG_VBUSVLD (1 << 17)
10214 +# define OTG_ID (1 << 16)
10215 +# define OTG_DRIVER_SEL (1 << 15)
10216 +# define OTG_A_SETB_HNPEN (1 << 12)
10217 +# define OTG_A_BUSREQ (1 << 11)
10218 +# define OTG_B_HNPEN (1 << 9)
10219 +# define OTG_B_BUSREQ (1 << 8)
10220 +# define OTG_BUSDROP (1 << 7)
10221 +# define OTG_PULLDOWN (1 << 5)
10222 +# define OTG_PULLUP (1 << 4)
10223 +# define OTG_DRV_VBUS (1 << 3)
10224 +# define OTG_PD_VBUS (1 << 2)
10225 +# define OTG_PU_VBUS (1 << 1)
10226 +# define OTG_PU_ID (1 << 0)
10227 +#define OTG_IRQ_EN (OTG_BASE + 0x10) /* 16-bit */
10228 +# define DRIVER_SWITCH (1 << 15)
10229 +# define A_VBUS_ERR (1 << 13)
10230 +# define A_REQ_TMROUT (1 << 12)
10231 +# define A_SRP_DETECT (1 << 11)
10232 +# define B_HNP_FAIL (1 << 10)
10233 +# define B_SRP_TMROUT (1 << 9)
10234 +# define B_SRP_DONE (1 << 8)
10235 +# define B_SRP_STARTED (1 << 7)
10236 +# define OPRT_CHG (1 << 0)
10237 +#define OTG_IRQ_SRC (OTG_BASE + 0x14) /* 16-bit */
10238 + // same bits as in IRQ_EN
10239 +#define OTG_OUTCTRL (OTG_BASE + 0x18) /* 16-bit */
10240 +# define OTGVPD (1 << 14)
10241 +# define OTGVPU (1 << 13)
10242 +# define OTGPUID (1 << 12)
10243 +# define USB2VDR (1 << 10)
10244 +# define USB2PDEN (1 << 9)
10245 +# define USB2PUEN (1 << 8)
10246 +# define USB1VDR (1 << 6)
10247 +# define USB1PDEN (1 << 5)
10248 +# define USB1PUEN (1 << 4)
10249 +# define USB0VDR (1 << 2)
10250 +# define USB0PDEN (1 << 1)
10251 +# define USB0PUEN (1 << 0)
10252 +#define OTG_TEST (OTG_BASE + 0x20) /* 16-bit */
10253 +#define OTG_VENDOR_CODE (OTG_BASE + 0xfc) /* 16-bit */
10254 +
10255 +/*-------------------------------------------------------------------------*/
10256 +
10257 +/* OMAP1 */
10258 +#define USB_TRANSCEIVER_CTRL (0xfffe1000 + 0x0064)
10259 +# define CONF_USB2_UNI_R (1 << 8)
10260 +# define CONF_USB1_UNI_R (1 << 7)
10261 +# define CONF_USB_PORT0_R(x) (((x)>>4)&0x7)
10262 +# define CONF_USB0_ISOLATE_R (1 << 3)
10263 +# define CONF_USB_PWRDN_DM_R (1 << 2)
10264 +# define CONF_USB_PWRDN_DP_R (1 << 1)
10265 +
10266 +/* OMAP2 */
10267 +# define USB_UNIDIR 0x0
10268 +# define USB_UNIDIR_TLL 0x1
10269 +# define USB_BIDIR 0x2
10270 +# define USB_BIDIR_TLL 0x3
10271 +# define USBTXWRMODEI(port, x) ((x) << (22 - (port * 2)))
10272 +# define USBT2TLL5PI (1 << 17)
10273 +# define USB0PUENACTLOI (1 << 16)
10274 +# define USBSTANDBYCTRL (1 << 15)
10275 +
10276 +#endif /* __ASM_ARCH_OMAP_USB_H */
10277 Index: linux-2.6.37-rc1/arch/arm/plat-omap/include/mach/vram.h
10278 ===================================================================
10279 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
10280 +++ linux-2.6.37-rc1/arch/arm/plat-omap/include/mach/vram.h 2010-11-05 17:36:26.179000001 +0100
10281 @@ -0,0 +1,62 @@
10282 +/*
10283 + * VRAM manager for OMAP
10284 + *
10285 + * Copyright (C) 2009 Nokia Corporation
10286 + * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
10287 + *
10288 + * This program is free software; you can redistribute it and/or modify
10289 + * it under the terms of the GNU General Public License version 2 as
10290 + * published by the Free Software Foundation.
10291 + *
10292 + * This program is distributed in the hope that it will be useful, but
10293 + * WITHOUT ANY WARRANTY; without even the implied warranty of
10294 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
10295 + * General Public License for more details.
10296 + *
10297 + * You should have received a copy of the GNU General Public License along
10298 + * with this program; if not, write to the Free Software Foundation, Inc.,
10299 + * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
10300 + */
10301 +
10302 +#ifndef __OMAP_VRAM_H__
10303 +#define __OMAP_VRAM_H__
10304 +
10305 +#include <linux/types.h>
10306 +
10307 +#define OMAP_VRAM_MEMTYPE_SDRAM 0
10308 +#define OMAP_VRAM_MEMTYPE_SRAM 1
10309 +#define OMAP_VRAM_MEMTYPE_MAX 1
10310 +
10311 +extern int omap_vram_add_region(unsigned long paddr, size_t size);
10312 +extern int omap_vram_free(unsigned long paddr, size_t size);
10313 +extern int omap_vram_alloc(int mtype, size_t size, unsigned long *paddr);
10314 +extern int omap_vram_reserve(unsigned long paddr, size_t size);
10315 +extern void omap_vram_get_info(unsigned long *vram, unsigned long *free_vram,
10316 + unsigned long *largest_free_block);
10317 +
10318 +#ifdef CONFIG_OMAP2_VRAM
10319 +extern void omap_vram_set_sdram_vram(u32 size, u32 start);
10320 +extern void omap_vram_set_sram_vram(u32 size, u32 start);
10321 +
10322 +extern void omap_vram_reserve_sdram(void);
10323 +extern unsigned long omap_vram_reserve_sram(unsigned long sram_pstart,
10324 + unsigned long sram_vstart,
10325 + unsigned long sram_size,
10326 + unsigned long pstart_avail,
10327 + unsigned long size_avail);
10328 +#else
10329 +static inline void omap_vram_set_sdram_vram(u32 size, u32 start) { }
10330 +static inline void omap_vram_set_sram_vram(u32 size, u32 start) { }
10331 +
10332 +static inline void omap_vram_reserve_sdram(void) { }
10333 +static inline unsigned long omap_vram_reserve_sram(unsigned long sram_pstart,
10334 + unsigned long sram_vstart,
10335 + unsigned long sram_size,
10336 + unsigned long pstart_avail,
10337 + unsigned long size_avail)
10338 +{
10339 + return 0;
10340 +}
10341 +#endif
10342 +
10343 +#endif
10344 Index: linux-2.6.37-rc1/arch/arm/plat-omap/include/mach/vrfb.h
10345 ===================================================================
10346 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
10347 +++ linux-2.6.37-rc1/arch/arm/plat-omap/include/mach/vrfb.h 2010-11-05 17:36:26.179000001 +0100
10348 @@ -0,0 +1,50 @@
10349 +/*
10350 + * VRFB Rotation Engine
10351 + *
10352 + * Copyright (C) 2009 Nokia Corporation
10353 + * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
10354 + *
10355 + * This program is free software; you can redistribute it and/or modify
10356 + * it under the terms of the GNU General Public License version 2 as
10357 + * published by the Free Software Foundation.
10358 + *
10359 + * This program is distributed in the hope that it will be useful, but
10360 + * WITHOUT ANY WARRANTY; without even the implied warranty of
10361 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
10362 + * General Public License for more details.
10363 + *
10364 + * You should have received a copy of the GNU General Public License along
10365 + * with this program; if not, write to the Free Software Foundation, Inc.,
10366 + * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
10367 + */
10368 +
10369 +#ifndef __OMAP_VRFB_H__
10370 +#define __OMAP_VRFB_H__
10371 +
10372 +#define OMAP_VRFB_LINE_LEN 2048
10373 +
10374 +struct vrfb {
10375 + u8 context;
10376 + void __iomem *vaddr[4];
10377 + unsigned long paddr[4];
10378 + u16 xres;
10379 + u16 yres;
10380 + u16 xoffset;
10381 + u16 yoffset;
10382 + u8 bytespp;
10383 + bool yuv_mode;
10384 +};
10385 +
10386 +extern int omap_vrfb_request_ctx(struct vrfb *vrfb);
10387 +extern void omap_vrfb_release_ctx(struct vrfb *vrfb);
10388 +extern void omap_vrfb_adjust_size(u16 *width, u16 *height,
10389 + u8 bytespp);
10390 +extern u32 omap_vrfb_min_phys_size(u16 width, u16 height, u8 bytespp);
10391 +extern u16 omap_vrfb_max_height(u32 phys_size, u16 width, u8 bytespp);
10392 +extern void omap_vrfb_setup(struct vrfb *vrfb, unsigned long paddr,
10393 + u16 width, u16 height,
10394 + unsigned bytespp, bool yuv_mode);
10395 +extern int omap_vrfb_map_angle(struct vrfb *vrfb, u16 height, u8 rot);
10396 +extern void omap_vrfb_restore_context(void);
10397 +
10398 +#endif /* __VRFB_H */
10399 Index: linux-2.6.37-rc1/arch/arm/plat-omap/include/plat/cbus.h
10400 ===================================================================
10401 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
10402 +++ linux-2.6.37-rc1/arch/arm/plat-omap/include/plat/cbus.h 2010-11-05 17:36:26.179000001 +0100
10403 @@ -0,0 +1,31 @@
10404 +/*
10405 + * cbus.h - CBUS platform_data definition
10406 + *
10407 + * Copyright (C) 2004 - 2009 Nokia Corporation
10408 + *
10409 + * Written by Felipe Balbi <felipe.balbi@nokia.com>
10410 + *
10411 + * This file is subject to the terms and conditions of the GNU General
10412 + * Public License. See the file "COPYING" in the main directory of this
10413 + * archive for more details.
10414 + *
10415 + * This program is distributed in the hope that it will be useful,
10416 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
10417 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10418 + * GNU General Public License for more details.
10419 + *
10420 + * You should have received a copy of the GNU General Public License
10421 + * along with this program; if not, write to the Free Software
10422 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
10423 + */
10424 +
10425 +#ifndef __PLAT_CBUS_H
10426 +#define __PLAT_CBUS_H
10427 +
10428 +struct cbus_host_platform_data {
10429 + int dat_gpio;
10430 + int clk_gpio;
10431 + int sel_gpio;
10432 +};
10433 +
10434 +#endif /* __PLAT_CBUS_H */
10435 Index: linux-2.6.37-rc1/arch/arm/plat-omap/Kconfig
10436 ===================================================================
10437 --- linux-2.6.37-rc1.orig/arch/arm/plat-omap/Kconfig 2010-11-01 12:54:12.000000000 +0100
10438 +++ linux-2.6.37-rc1/arch/arm/plat-omap/Kconfig 2010-11-05 17:36:26.179000001 +0100
10439 @@ -47,6 +47,38 @@
10440 probably do not want this option enabled until your
10441 device drivers work properly.
10442
10443 +config OMAP_BOOT_TAG
10444 + bool "OMAP bootloader information passing"
10445 + depends on ARCH_OMAP
10446 + default n
10447 + help
10448 + Say Y, if you have a bootloader which passes information
10449 + about your board and its peripheral configuration.
10450 +
10451 +config OMAP_BOOT_REASON
10452 + bool "Support for boot reason"
10453 + depends on OMAP_BOOT_TAG
10454 + default n
10455 + help
10456 + Say Y, if you want to have a procfs entry for reading the boot
10457 + reason in user-space.
10458 +
10459 +config OMAP_COMPONENT_VERSION
10460 + bool "Support for component version display"
10461 + depends on OMAP_BOOT_TAG && PROC_FS
10462 + default n
10463 + help
10464 + Say Y, if you want to have a procfs entry for reading component
10465 + versions (supplied by the bootloader) in user-space.
10466 +
10467 +config OMAP_GPIO_SWITCH
10468 + bool "GPIO switch support"
10469 + help
10470 + Say Y, if you want to have support for reporting of GPIO
10471 + switches (e.g. cover switches) via sysfs. Your bootloader has
10472 + to provide information about the switches to the kernel via the
10473 + ATAG_BOARD mechanism if they're not defined by the board config.
10474 +
10475 config OMAP_MUX
10476 bool "OMAP multiplexing support"
10477 depends on ARCH_OMAP
10478 Index: linux-2.6.37-rc1/arch/arm/plat-omap/Makefile
10479 ===================================================================
10480 --- linux-2.6.37-rc1.orig/arch/arm/plat-omap/Makefile 2010-11-01 12:54:12.000000000 +0100
10481 +++ linux-2.6.37-rc1/arch/arm/plat-omap/Makefile 2010-11-05 17:38:08.817998974 +0100
10482 @@ -23,6 +23,9 @@
10483
10484 obj-$(CONFIG_CPU_FREQ) += cpu-omap.o
10485 obj-$(CONFIG_OMAP_DM_TIMER) += dmtimer.o
10486 +obj-$(CONFIG_OMAP_BOOT_REASON) += bootreason.o
10487 +obj-$(CONFIG_OMAP_COMPONENT_VERSION) += component-version.o
10488 +obj-$(CONFIG_OMAP_GPIO_SWITCH) += gpio-switch.o
10489 obj-$(CONFIG_OMAP_DEBUG_DEVICES) += debug-devices.o
10490 obj-$(CONFIG_OMAP_DEBUG_LEDS) += debug-leds.o
10491 i2c-omap-$(CONFIG_I2C_OMAP) := i2c.o
10492 Index: linux-2.6.37-rc1/arch/arm/include/asm/setup.h
10493 ===================================================================
10494 --- linux-2.6.37-rc1.orig/arch/arm/include/asm/setup.h 2010-11-01 12:54:12.000000000 +0100
10495 +++ linux-2.6.37-rc1/arch/arm/include/asm/setup.h 2010-11-05 17:36:26.179000001 +0100
10496 @@ -136,6 +136,13 @@
10497 __u8 adfsdrives;
10498 };
10499
10500 +/* TI OMAP specific information */
10501 +#define ATAG_BOARD 0x414f4d50
10502 +
10503 +struct tag_omap {
10504 + u8 data[0];
10505 +};
10506 +
10507 /* footbridge memory clock, see arch/arm/mach-footbridge/arch.c */
10508 #define ATAG_MEMCLK 0x41000402
10509
10510 @@ -162,6 +169,11 @@
10511 struct tag_acorn acorn;
10512
10513 /*
10514 + * OMAP specific
10515 + */
10516 + struct tag_omap omap;
10517 +
10518 + /*
10519 * DC21285 specific
10520 */
10521 struct tag_memclk memclk;
10522 Index: linux-2.6.37-rc1/arch/arm/plat-omap/gpio-switch.c
10523 ===================================================================
10524 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
10525 +++ linux-2.6.37-rc1/arch/arm/plat-omap/gpio-switch.c 2010-11-05 17:36:26.180000001 +0100
10526 @@ -0,0 +1,554 @@
10527 +/*
10528 + * linux/arch/arm/plat-omap/gpio-switch.c
10529 + *
10530 + * Copyright (C) 2004-2006 Nokia Corporation
10531 + * Written by Juha Yrjölä <juha.yrjola@nokia.com>
10532 + * and Paul Mundt <paul.mundt@nokia.com>
10533 + *
10534 + * This program is free software; you can redistribute it and/or modify
10535 + * it under the terms of the GNU General Public License version 2 as
10536 + * published by the Free Software Foundation.
10537 + */
10538 +
10539 +#include <linux/sched.h>
10540 +#include <linux/init.h>
10541 +#include <linux/list.h>
10542 +#include <linux/irq.h>
10543 +#include <linux/interrupt.h>
10544 +#include <linux/module.h>
10545 +#include <linux/platform_device.h>
10546 +#include <linux/timer.h>
10547 +#include <linux/err.h>
10548 +#include <linux/slab.h>
10549 +#include <linux/gpio.h>
10550 +#include <plat/hardware.h>
10551 +#include <plat/irqs.h>
10552 +#include <plat/mux.h>
10553 +#include <plat/board.h>
10554 +#include <plat/gpio-switch.h>
10555 +
10556 +struct gpio_switch {
10557 + char name[14];
10558 + u16 gpio;
10559 + unsigned flags:4;
10560 + unsigned type:4;
10561 + unsigned state:1;
10562 + unsigned both_edges:1;
10563 +
10564 + u16 debounce_rising;
10565 + u16 debounce_falling;
10566 +
10567 + void (* notify)(void *data, int state);
10568 + void *notify_data;
10569 +
10570 + struct work_struct work;
10571 + struct timer_list timer;
10572 + struct platform_device pdev;
10573 +
10574 + struct list_head node;
10575 +};
10576 +
10577 +static LIST_HEAD(gpio_switches);
10578 +static struct platform_device *gpio_sw_platform_dev;
10579 +static struct platform_driver gpio_sw_driver;
10580 +
10581 +static const struct omap_gpio_switch *board_gpio_sw_table;
10582 +static int board_gpio_sw_count;
10583 +
10584 +static const char *cover_str[2] = { "open", "closed" };
10585 +static const char *connection_str[2] = { "disconnected", "connected" };
10586 +static const char *activity_str[2] = { "inactive", "active" };
10587 +
10588 +/*
10589 + * GPIO switch state default debounce delay in ms
10590 + */
10591 +#define OMAP_GPIO_SW_DEFAULT_DEBOUNCE 10
10592 +
10593 +static const char **get_sw_str(struct gpio_switch *sw)
10594 +{
10595 + switch (sw->type) {
10596 + case OMAP_GPIO_SWITCH_TYPE_COVER:
10597 + return cover_str;
10598 + case OMAP_GPIO_SWITCH_TYPE_CONNECTION:
10599 + return connection_str;
10600 + case OMAP_GPIO_SWITCH_TYPE_ACTIVITY:
10601 + return activity_str;
10602 + default:
10603 + BUG();
10604 + return NULL;
10605 + }
10606 +}
10607 +
10608 +static const char *get_sw_type(struct gpio_switch *sw)
10609 +{
10610 + switch (sw->type) {
10611 + case OMAP_GPIO_SWITCH_TYPE_COVER:
10612 + return "cover";
10613 + case OMAP_GPIO_SWITCH_TYPE_CONNECTION:
10614 + return "connection";
10615 + case OMAP_GPIO_SWITCH_TYPE_ACTIVITY:
10616 + return "activity";
10617 + default:
10618 + BUG();
10619 + return NULL;
10620 + }
10621 +}
10622 +
10623 +static void print_sw_state(struct gpio_switch *sw, int state)
10624 +{
10625 + const char **str;
10626 +
10627 + str = get_sw_str(sw);
10628 + if (str != NULL)
10629 + printk(KERN_INFO "%s (GPIO %d) is now %s\n", sw->name, sw->gpio, str[state]);
10630 +}
10631 +
10632 +static int gpio_sw_get_state(struct gpio_switch *sw)
10633 +{
10634 + int state;
10635 +
10636 + state = gpio_get_value(sw->gpio);
10637 + if (sw->flags & OMAP_GPIO_SWITCH_FLAG_INVERTED)
10638 + state = !state;
10639 +
10640 + return state;
10641 +}
10642 +
10643 +static ssize_t gpio_sw_state_store(struct device *dev,
10644 + struct device_attribute *attr,
10645 + const char *buf,
10646 + size_t count)
10647 +{
10648 + struct gpio_switch *sw = dev_get_drvdata(dev);
10649 + const char **str;
10650 + char state[16];
10651 + int enable;
10652 +
10653 + if (!(sw->flags & OMAP_GPIO_SWITCH_FLAG_OUTPUT))
10654 + return -EPERM;
10655 +
10656 + if (sscanf(buf, "%15s", state) != 1)
10657 + return -EINVAL;
10658 +
10659 + str = get_sw_str(sw);
10660 + if (strcmp(state, str[0]) == 0)
10661 + sw->state = enable = 0;
10662 + else if (strcmp(state, str[1]) == 0)
10663 + sw->state = enable = 1;
10664 + else
10665 + return -EINVAL;
10666 +
10667 + if (sw->flags & OMAP_GPIO_SWITCH_FLAG_INVERTED)
10668 + enable = !enable;
10669 + gpio_set_value(sw->gpio, enable);
10670 +
10671 + return count;
10672 +}
10673 +
10674 +static ssize_t gpio_sw_state_show(struct device *dev,
10675 + struct device_attribute *attr,
10676 + char *buf)
10677 +{
10678 + struct gpio_switch *sw = dev_get_drvdata(dev);
10679 + const char **str;
10680 +
10681 + str = get_sw_str(sw);
10682 + return sprintf(buf, "%s\n", str[sw->state]);
10683 +}
10684 +
10685 +static DEVICE_ATTR(state, S_IRUGO | S_IWUSR, gpio_sw_state_show,
10686 + gpio_sw_state_store);
10687 +
10688 +static ssize_t gpio_sw_type_show(struct device *dev,
10689 + struct device_attribute *attr,
10690 + char *buf)
10691 +{
10692 + struct gpio_switch *sw = dev_get_drvdata(dev);
10693 +
10694 + return sprintf(buf, "%s\n", get_sw_type(sw));
10695 +}
10696 +
10697 +static DEVICE_ATTR(type, S_IRUGO, gpio_sw_type_show, NULL);
10698 +
10699 +static ssize_t gpio_sw_direction_show(struct device *dev,
10700 + struct device_attribute *attr,
10701 + char *buf)
10702 +{
10703 + struct gpio_switch *sw = dev_get_drvdata(dev);
10704 + int is_output;
10705 +
10706 + is_output = sw->flags & OMAP_GPIO_SWITCH_FLAG_OUTPUT;
10707 + return sprintf(buf, "%s\n", is_output ? "output" : "input");
10708 +}
10709 +
10710 +static DEVICE_ATTR(direction, S_IRUGO, gpio_sw_direction_show, NULL);
10711 +
10712 +
10713 +static irqreturn_t gpio_sw_irq_handler(int irq, void *arg)
10714 +{
10715 + struct gpio_switch *sw = arg;
10716 + unsigned long timeout;
10717 + int state;
10718 +
10719 + if (!sw->both_edges) {
10720 + if (gpio_get_value(sw->gpio))
10721 + set_irq_type(OMAP_GPIO_IRQ(sw->gpio), IRQ_TYPE_EDGE_FALLING);
10722 + else
10723 + set_irq_type(OMAP_GPIO_IRQ(sw->gpio), IRQ_TYPE_EDGE_RISING);
10724 + }
10725 +
10726 + state = gpio_sw_get_state(sw);
10727 + if (sw->state == state)
10728 + return IRQ_HANDLED;
10729 +
10730 + if (state)
10731 + timeout = sw->debounce_rising;
10732 + else
10733 + timeout = sw->debounce_falling;
10734 + if (!timeout)
10735 + schedule_work(&sw->work);
10736 + else
10737 + mod_timer(&sw->timer, jiffies + msecs_to_jiffies(timeout));
10738 +
10739 + return IRQ_HANDLED;
10740 +}
10741 +
10742 +static void gpio_sw_timer(unsigned long arg)
10743 +{
10744 + struct gpio_switch *sw = (struct gpio_switch *) arg;
10745 +
10746 + schedule_work(&sw->work);
10747 +}
10748 +
10749 +static void gpio_sw_handler(struct work_struct *work)
10750 +{
10751 + struct gpio_switch *sw = container_of(work, struct gpio_switch, work);
10752 + int state;
10753 +
10754 + state = gpio_sw_get_state(sw);
10755 + if (sw->state == state)
10756 + return;
10757 +
10758 + sw->state = state;
10759 + if (sw->notify != NULL)
10760 + sw->notify(sw->notify_data, state);
10761 + sysfs_notify(&sw->pdev.dev.kobj, NULL, "state");
10762 + print_sw_state(sw, state);
10763 +}
10764 +
10765 +static int __init can_do_both_edges(struct gpio_switch *sw)
10766 +{
10767 + if (!cpu_class_is_omap1())
10768 + return 1;
10769 + if (OMAP_GPIO_IS_MPUIO(sw->gpio))
10770 + return 0;
10771 + else
10772 + return 1;
10773 +}
10774 +
10775 +static void gpio_sw_release(struct device *dev)
10776 +{
10777 +}
10778 +
10779 +static int __init new_switch(struct gpio_switch *sw)
10780 +{
10781 + int r, direction, trigger;
10782 +
10783 + switch (sw->type) {
10784 + case OMAP_GPIO_SWITCH_TYPE_COVER:
10785 + case OMAP_GPIO_SWITCH_TYPE_CONNECTION:
10786 + case OMAP_GPIO_SWITCH_TYPE_ACTIVITY:
10787 + break;
10788 + default:
10789 + printk(KERN_ERR "invalid GPIO switch type: %d\n", sw->type);
10790 + return -EINVAL;
10791 + }
10792 +
10793 + sw->pdev.name = sw->name;
10794 + sw->pdev.id = -1;
10795 +
10796 + sw->pdev.dev.parent = &gpio_sw_platform_dev->dev;
10797 + sw->pdev.dev.driver = &gpio_sw_driver.driver;
10798 + sw->pdev.dev.release = gpio_sw_release;
10799 +
10800 + r = platform_device_register(&sw->pdev);
10801 + if (r) {
10802 + printk(KERN_ERR "gpio-switch: platform device registration "
10803 + "failed for %s", sw->name);
10804 + return r;
10805 + }
10806 + dev_set_drvdata(&sw->pdev.dev, sw);
10807 +
10808 + r = gpio_request(sw->gpio, "gpio-switch");
10809 + if (r < 0) {
10810 + platform_device_unregister(&sw->pdev);
10811 + return r;
10812 + }
10813 +
10814 + /* input: 1, output: 0 */
10815 + direction = !(sw->flags & OMAP_GPIO_SWITCH_FLAG_OUTPUT);
10816 + if (direction)
10817 + gpio_direction_input(sw->gpio);
10818 + else
10819 + gpio_direction_output(sw->gpio, 0);
10820 +
10821 + sw->state = gpio_sw_get_state(sw);
10822 +
10823 + r = 0;
10824 + r |= device_create_file(&sw->pdev.dev, &dev_attr_state);
10825 + r |= device_create_file(&sw->pdev.dev, &dev_attr_type);
10826 + r |= device_create_file(&sw->pdev.dev, &dev_attr_direction);
10827 + if (r)
10828 + printk(KERN_ERR "gpio-switch: attribute file creation "
10829 + "failed for %s\n", sw->name);
10830 +
10831 + if (!direction)
10832 + return 0;
10833 +
10834 + if (can_do_both_edges(sw)) {
10835 + trigger = IRQF_TRIGGER_FALLING | IRQF_TRIGGER_RISING;
10836 + sw->both_edges = 1;
10837 + } else {
10838 + if (gpio_get_value(sw->gpio))
10839 + trigger = IRQF_TRIGGER_FALLING;
10840 + else
10841 + trigger = IRQF_TRIGGER_RISING;
10842 + }
10843 + r = request_irq(OMAP_GPIO_IRQ(sw->gpio), gpio_sw_irq_handler,
10844 + IRQF_SHARED | trigger, sw->name, sw);
10845 + if (r < 0) {
10846 + printk(KERN_ERR "gpio-switch: request_irq() failed "
10847 + "for GPIO %d\n", sw->gpio);
10848 + platform_device_unregister(&sw->pdev);
10849 + gpio_free(sw->gpio);
10850 + return r;
10851 + }
10852 +
10853 + INIT_WORK(&sw->work, gpio_sw_handler);
10854 + init_timer(&sw->timer);
10855 +
10856 + sw->timer.function = gpio_sw_timer;
10857 + sw->timer.data = (unsigned long)sw;
10858 +
10859 + list_add(&sw->node, &gpio_switches);
10860 +
10861 + return 0;
10862 +}
10863 +
10864 +static int __init add_atag_switches(void)
10865 +{
10866 + const struct omap_gpio_switch_config *cfg;
10867 + struct gpio_switch *sw;
10868 + int i, r;
10869 +
10870 + for (i = 0; ; i++) {
10871 + cfg = omap_get_nr_config(OMAP_TAG_GPIO_SWITCH,
10872 + struct omap_gpio_switch_config, i);
10873 + if (cfg == NULL)
10874 + break;
10875 + sw = kzalloc(sizeof(*sw), GFP_KERNEL);
10876 + if (sw == NULL) {
10877 + printk(KERN_ERR "gpio-switch: kmalloc failed\n");
10878 + return -ENOMEM;
10879 + }
10880 + strncpy(sw->name, cfg->name, sizeof(cfg->name));
10881 + sw->gpio = cfg->gpio;
10882 + sw->flags = cfg->flags;
10883 + sw->type = cfg->type;
10884 + sw->debounce_rising = OMAP_GPIO_SW_DEFAULT_DEBOUNCE;
10885 + sw->debounce_falling = OMAP_GPIO_SW_DEFAULT_DEBOUNCE;
10886 + if ((r = new_switch(sw)) < 0) {
10887 + kfree(sw);
10888 + return r;
10889 + }
10890 + }
10891 + return 0;
10892 +}
10893 +
10894 +static struct gpio_switch * __init find_switch(int gpio, const char *name)
10895 +{
10896 + struct gpio_switch *sw;
10897 +
10898 + list_for_each_entry(sw, &gpio_switches, node) {
10899 + if ((gpio < 0 || sw->gpio != gpio) &&
10900 + (name == NULL || strcmp(sw->name, name) != 0))
10901 + continue;
10902 +
10903 + if (gpio < 0 || name == NULL)
10904 + goto no_check;
10905 +
10906 + if (strcmp(sw->name, name) != 0)
10907 + printk("gpio-switch: name mismatch for %d (%s, %s)\n",
10908 + gpio, name, sw->name);
10909 + else if (sw->gpio != gpio)
10910 + printk("gpio-switch: GPIO mismatch for %s (%d, %d)\n",
10911 + name, gpio, sw->gpio);
10912 +no_check:
10913 + return sw;
10914 + }
10915 + return NULL;
10916 +}
10917 +
10918 +static int __init add_board_switches(void)
10919 +{
10920 + int i;
10921 +
10922 + for (i = 0; i < board_gpio_sw_count; i++) {
10923 + const struct omap_gpio_switch *cfg;
10924 + struct gpio_switch *sw;
10925 + int r;
10926 +
10927 + cfg = board_gpio_sw_table + i;
10928 + if (strlen(cfg->name) > sizeof(sw->name) - 1)
10929 + return -EINVAL;
10930 + /* Check whether we only update an existing switch
10931 + * or add a new switch. */
10932 + sw = find_switch(cfg->gpio, cfg->name);
10933 + if (sw != NULL) {
10934 + sw->debounce_rising = cfg->debounce_rising;
10935 + sw->debounce_falling = cfg->debounce_falling;
10936 + sw->notify = cfg->notify;
10937 + sw->notify_data = cfg->notify_data;
10938 + continue;
10939 + } else {
10940 + if (cfg->gpio < 0 || cfg->name == NULL) {
10941 + printk("gpio-switch: required switch not "
10942 + "found (%d, %s)\n", cfg->gpio,
10943 + cfg->name);
10944 + continue;
10945 + }
10946 + }
10947 + sw = kzalloc(sizeof(*sw), GFP_KERNEL);
10948 + if (sw == NULL) {
10949 + printk(KERN_ERR "gpio-switch: kmalloc failed\n");
10950 + return -ENOMEM;
10951 + }
10952 + strlcpy(sw->name, cfg->name, sizeof(sw->name));
10953 + sw->gpio = cfg->gpio;
10954 + sw->flags = cfg->flags;
10955 + sw->type = cfg->type;
10956 + sw->debounce_rising = cfg->debounce_rising;
10957 + sw->debounce_falling = cfg->debounce_falling;
10958 + sw->notify = cfg->notify;
10959 + sw->notify_data = cfg->notify_data;
10960 + if ((r = new_switch(sw)) < 0) {
10961 + kfree(sw);
10962 + return r;
10963 + }
10964 + }
10965 + return 0;
10966 +}
10967 +
10968 +static void gpio_sw_cleanup(void)
10969 +{
10970 + struct gpio_switch *sw = NULL, *old = NULL;
10971 +
10972 + list_for_each_entry(sw, &gpio_switches, node) {
10973 + if (old != NULL)
10974 + kfree(old);
10975 + flush_scheduled_work();
10976 + del_timer_sync(&sw->timer);
10977 +
10978 + free_irq(OMAP_GPIO_IRQ(sw->gpio), sw);
10979 +
10980 + device_remove_file(&sw->pdev.dev, &dev_attr_state);
10981 + device_remove_file(&sw->pdev.dev, &dev_attr_type);
10982 + device_remove_file(&sw->pdev.dev, &dev_attr_direction);
10983 +
10984 + platform_device_unregister(&sw->pdev);
10985 + gpio_free(sw->gpio);
10986 + old = sw;
10987 + }
10988 + kfree(old);
10989 +}
10990 +
10991 +static void __init report_initial_state(void)
10992 +{
10993 + struct gpio_switch *sw;
10994 +
10995 + list_for_each_entry(sw, &gpio_switches, node) {
10996 + int state;
10997 +
10998 + state = gpio_get_value(sw->gpio);
10999 + if (sw->flags & OMAP_GPIO_SWITCH_FLAG_INVERTED)
11000 + state = !state;
11001 + if (sw->notify != NULL)
11002 + sw->notify(sw->notify_data, state);
11003 + print_sw_state(sw, state);
11004 + }
11005 +}
11006 +
11007 +static int gpio_sw_remove(struct platform_device *dev)
11008 +{
11009 + return 0;
11010 +}
11011 +
11012 +static struct platform_driver gpio_sw_driver = {
11013 + .remove = gpio_sw_remove,
11014 + .driver = {
11015 + .name = "gpio-switch",
11016 + },
11017 +};
11018 +
11019 +void __init omap_register_gpio_switches(const struct omap_gpio_switch *tbl,
11020 + int count)
11021 +{
11022 + BUG_ON(board_gpio_sw_table != NULL);
11023 +
11024 + board_gpio_sw_table = tbl;
11025 + board_gpio_sw_count = count;
11026 +}
11027 +
11028 +static int __init gpio_sw_init(void)
11029 +{
11030 + int r;
11031 +
11032 + printk(KERN_INFO "OMAP GPIO switch handler initializing\n");
11033 +
11034 + r = platform_driver_register(&gpio_sw_driver);
11035 + if (r)
11036 + return r;
11037 +
11038 + gpio_sw_platform_dev = platform_device_register_simple("gpio-switch",
11039 + -1, NULL, 0);
11040 + if (IS_ERR(gpio_sw_platform_dev)) {
11041 + r = PTR_ERR(gpio_sw_platform_dev);
11042 + goto err1;
11043 + }
11044 +
11045 + r = add_atag_switches();
11046 + if (r < 0)
11047 + goto err2;
11048 +
11049 + r = add_board_switches();
11050 + if (r < 0)
11051 + goto err2;
11052 +
11053 + report_initial_state();
11054 +
11055 + return 0;
11056 +err2:
11057 + gpio_sw_cleanup();
11058 + platform_device_unregister(gpio_sw_platform_dev);
11059 +err1:
11060 + platform_driver_unregister(&gpio_sw_driver);
11061 + return r;
11062 +}
11063 +
11064 +static void __exit gpio_sw_exit(void)
11065 +{
11066 + gpio_sw_cleanup();
11067 + platform_device_unregister(gpio_sw_platform_dev);
11068 + platform_driver_unregister(&gpio_sw_driver);
11069 +}
11070 +
11071 +#ifndef MODULE
11072 +late_initcall(gpio_sw_init);
11073 +#else
11074 +module_init(gpio_sw_init);
11075 +#endif
11076 +module_exit(gpio_sw_exit);
11077 +
11078 +MODULE_AUTHOR("Juha Yrjölä <juha.yrjola@nokia.com>, Paul Mundt <paul.mundt@nokia.com");
11079 +MODULE_DESCRIPTION("GPIO switch driver");
11080 +MODULE_LICENSE("GPL");
11081 Index: linux-2.6.37-rc1/arch/arm/plat-omap/include/plat/board.h
11082 ===================================================================
11083 --- linux-2.6.37-rc1.orig/arch/arm/plat-omap/include/plat/board.h 2010-11-01 12:54:12.000000000 +0100
11084 +++ linux-2.6.37-rc1/arch/arm/plat-omap/include/plat/board.h 2010-11-05 17:36:26.180000001 +0100
11085 @@ -151,6 +151,14 @@
11086 const void *data;
11087 };
11088
11089 +struct omap_gpio_switch_config {
11090 + char name[12];
11091 + u16 gpio;
11092 + int flags:4;
11093 + int type:4;
11094 + int key_code:24; /* Linux key code */
11095 +};
11096 +
11097 extern const void *__omap_get_config(u16 tag, size_t len, int nr);
11098
11099 #define omap_get_config(tag, type) \
Personal OpenWRT clone
This page took 0.562459 seconds and 5 git commands to generate.