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kernel: update bcma and ssb to version master-2011-12-16 from wireless-testing
[openwrt.git] / target / linux / generic / patches-2.6.31 / 025-bcma_backport.patch
1 --- /dev/null
2 +++ b/Documentation/ABI/testing/sysfs-bus-bcma
3 @@ -0,0 +1,31 @@
4 +What: /sys/bus/bcma/devices/.../manuf
5 +Date: May 2011
6 +KernelVersion: 2.6.40
7 +Contact: Rafał Miłecki <zajec5@gmail.com>
8 +Description:
9 + Each BCMA core has it's manufacturer id. See
10 + include/linux/bcma/bcma.h for possible values.
11 +
12 +What: /sys/bus/bcma/devices/.../id
13 +Date: May 2011
14 +KernelVersion: 2.6.40
15 +Contact: Rafał Miłecki <zajec5@gmail.com>
16 +Description:
17 + There are a few types of BCMA cores, they can be identified by
18 + id field.
19 +
20 +What: /sys/bus/bcma/devices/.../rev
21 +Date: May 2011
22 +KernelVersion: 2.6.40
23 +Contact: Rafał Miłecki <zajec5@gmail.com>
24 +Description:
25 + BCMA cores of the same type can still slightly differ depending
26 + on their revision. Use it for detailed programming.
27 +
28 +What: /sys/bus/bcma/devices/.../class
29 +Date: May 2011
30 +KernelVersion: 2.6.40
31 +Contact: Rafał Miłecki <zajec5@gmail.com>
32 +Description:
33 + Each BCMA core is identified by few fields, including class it
34 + belongs to. See include/linux/bcma/bcma.h for possible values.
35 --- a/MAINTAINERS
36 +++ b/MAINTAINERS
37 @@ -4716,6 +4716,13 @@ S: Maintained
38 F: drivers/ssb/
39 F: include/linux/ssb/
40
41 +BROADCOM SPECIFIC AMBA DRIVER (BCMA)
42 +M: Rafał Miłecki <zajec5@gmail.com>
43 +L: linux-wireless@vger.kernel.org
44 +S: Maintained
45 +F: drivers/bcma/
46 +F: include/linux/bcma/
47 +
48 SONY VAIO CONTROL DEVICE DRIVER
49 M: Mattia Dongili <malattia@linux.it>
50 L: linux-acpi@vger.kernel.org
51 --- a/drivers/Kconfig
52 +++ b/drivers/Kconfig
53 @@ -68,6 +68,8 @@ source "drivers/watchdog/Kconfig"
54
55 source "drivers/ssb/Kconfig"
56
57 +source "drivers/bcma/Kconfig"
58 +
59 source "drivers/mfd/Kconfig"
60
61 source "drivers/regulator/Kconfig"
62 --- a/drivers/Makefile
63 +++ b/drivers/Makefile
64 @@ -105,6 +105,7 @@ obj-$(CONFIG_HID) += hid/
65 obj-$(CONFIG_PPC_PS3) += ps3/
66 obj-$(CONFIG_OF) += of/
67 obj-$(CONFIG_SSB) += ssb/
68 +obj-$(CONFIG_BCMA) += bcma/
69 obj-$(CONFIG_VIRTIO) += virtio/
70 obj-$(CONFIG_VLYNQ) += vlynq/
71 obj-$(CONFIG_STAGING) += staging/
72 --- /dev/null
73 +++ b/drivers/bcma/Kconfig
74 @@ -0,0 +1,57 @@
75 +config BCMA_POSSIBLE
76 + bool
77 + depends on HAS_IOMEM && HAS_DMA
78 + default y
79 +
80 +menu "Broadcom specific AMBA"
81 + depends on BCMA_POSSIBLE
82 +
83 +config BCMA
84 + tristate "BCMA support"
85 + depends on BCMA_POSSIBLE
86 + help
87 + Bus driver for Broadcom specific Advanced Microcontroller Bus
88 + Architecture.
89 +
90 +# Support for Block-I/O. SELECT this from the driver that needs it.
91 +config BCMA_BLOCKIO
92 + bool
93 + depends on BCMA
94 +
95 +config BCMA_HOST_PCI_POSSIBLE
96 + bool
97 + depends on BCMA && PCI = y
98 + default y
99 +
100 +config BCMA_HOST_PCI
101 + bool "Support for BCMA on PCI-host bus"
102 + depends on BCMA_HOST_PCI_POSSIBLE
103 +
104 +config BCMA_DRIVER_PCI_HOSTMODE
105 + bool "Driver for PCI core working in hostmode"
106 + depends on BCMA && MIPS
107 + help
108 + PCI core hostmode operation (external PCI bus).
109 +
110 +config BCMA_HOST_SOC
111 + bool
112 + depends on BCMA_DRIVER_MIPS
113 +
114 +config BCMA_DRIVER_MIPS
115 + bool "BCMA Broadcom MIPS core driver"
116 + depends on BCMA && MIPS
117 + help
118 + Driver for the Broadcom MIPS core attached to Broadcom specific
119 + Advanced Microcontroller Bus.
120 +
121 + If unsure, say N
122 +
123 +config BCMA_DEBUG
124 + bool "BCMA debugging"
125 + depends on BCMA
126 + help
127 + This turns on additional debugging messages.
128 +
129 + If unsure, say N
130 +
131 +endmenu
132 --- /dev/null
133 +++ b/drivers/bcma/Makefile
134 @@ -0,0 +1,10 @@
135 +bcma-y += main.o scan.o core.o sprom.o
136 +bcma-y += driver_chipcommon.o driver_chipcommon_pmu.o
137 +bcma-y += driver_pci.o
138 +bcma-$(CONFIG_BCMA_DRIVER_PCI_HOSTMODE) += driver_pci_host.o
139 +bcma-$(CONFIG_BCMA_DRIVER_MIPS) += driver_mips.o
140 +bcma-$(CONFIG_BCMA_HOST_PCI) += host_pci.o
141 +bcma-$(CONFIG_BCMA_HOST_SOC) += host_soc.o
142 +obj-$(CONFIG_BCMA) += bcma.o
143 +
144 +ccflags-$(CONFIG_BCMA_DEBUG) := -DDEBUG
145 --- /dev/null
146 +++ b/drivers/bcma/README
147 @@ -0,0 +1,19 @@
148 +Broadcom introduced new bus as replacement for older SSB. It is based on AMBA,
149 +however from programming point of view there is nothing AMBA specific we use.
150 +
151 +Standard AMBA drivers are platform specific, have hardcoded addresses and use
152 +AMBA standard fields like CID and PID.
153 +
154 +In case of Broadcom's cards every device consists of:
155 +1) Broadcom specific AMBA device. It is put on AMBA bus, but can not be treated
156 + as standard AMBA device. Reading it's CID or PID can cause machine lockup.
157 +2) AMBA standard devices called ports or wrappers. They have CIDs (AMBA_CID)
158 + and PIDs (0x103BB369), but we do not use that info for anything. One of that
159 + devices is used for managing Broadcom specific core.
160 +
161 +Addresses of AMBA devices are not hardcoded in driver and have to be read from
162 +EPROM.
163 +
164 +In this situation we decided to introduce separated bus. It can contain up to
165 +16 devices identified by Broadcom specific fields: manufacturer, id, revision
166 +and class.
167 --- /dev/null
168 +++ b/drivers/bcma/TODO
169 @@ -0,0 +1,3 @@
170 +- Interrupts
171 +- Defines for PCI core driver
172 +- Create kernel Documentation (use info from README)
173 --- /dev/null
174 +++ b/drivers/bcma/bcma_private.h
175 @@ -0,0 +1,54 @@
176 +#ifndef LINUX_BCMA_PRIVATE_H_
177 +#define LINUX_BCMA_PRIVATE_H_
178 +
179 +#ifndef pr_fmt
180 +#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
181 +#endif
182 +
183 +#include <linux/bcma/bcma.h>
184 +#include <linux/delay.h>
185 +
186 +#define BCMA_CORE_SIZE 0x1000
187 +
188 +struct bcma_bus;
189 +
190 +/* main.c */
191 +int bcma_bus_register(struct bcma_bus *bus);
192 +void bcma_bus_unregister(struct bcma_bus *bus);
193 +int __init bcma_bus_early_register(struct bcma_bus *bus,
194 + struct bcma_device *core_cc,
195 + struct bcma_device *core_mips);
196 +#ifdef CONFIG_PM
197 +int bcma_bus_resume(struct bcma_bus *bus);
198 +#endif
199 +
200 +/* scan.c */
201 +int bcma_bus_scan(struct bcma_bus *bus);
202 +int __init bcma_bus_scan_early(struct bcma_bus *bus,
203 + struct bcma_device_id *match,
204 + struct bcma_device *core);
205 +void bcma_init_bus(struct bcma_bus *bus);
206 +
207 +/* sprom.c */
208 +int bcma_sprom_get(struct bcma_bus *bus);
209 +
210 +/* driver_chipcommon.c */
211 +#ifdef CONFIG_BCMA_DRIVER_MIPS
212 +void bcma_chipco_serial_init(struct bcma_drv_cc *cc);
213 +#endif /* CONFIG_BCMA_DRIVER_MIPS */
214 +
215 +/* driver_chipcommon_pmu.c */
216 +u32 bcma_pmu_alp_clock(struct bcma_drv_cc *cc);
217 +u32 bcma_pmu_get_clockcpu(struct bcma_drv_cc *cc);
218 +
219 +#ifdef CONFIG_BCMA_HOST_PCI
220 +/* host_pci.c */
221 +extern int __init bcma_host_pci_init(void);
222 +extern void __exit bcma_host_pci_exit(void);
223 +#endif /* CONFIG_BCMA_HOST_PCI */
224 +
225 +#ifdef CONFIG_BCMA_DRIVER_PCI_HOSTMODE
226 +void bcma_core_pci_hostmode_init(struct bcma_drv_pci *pc);
227 +#endif /* CONFIG_BCMA_DRIVER_PCI_HOSTMODE */
228 +
229 +#endif
230 --- /dev/null
231 +++ b/drivers/bcma/core.c
232 @@ -0,0 +1,126 @@
233 +/*
234 + * Broadcom specific AMBA
235 + * Core ops
236 + *
237 + * Licensed under the GNU/GPL. See COPYING for details.
238 + */
239 +
240 +#include "bcma_private.h"
241 +#include <linux/bcma/bcma.h>
242 +
243 +bool bcma_core_is_enabled(struct bcma_device *core)
244 +{
245 + if ((bcma_aread32(core, BCMA_IOCTL) & (BCMA_IOCTL_CLK | BCMA_IOCTL_FGC))
246 + != BCMA_IOCTL_CLK)
247 + return false;
248 + if (bcma_aread32(core, BCMA_RESET_CTL) & BCMA_RESET_CTL_RESET)
249 + return false;
250 + return true;
251 +}
252 +EXPORT_SYMBOL_GPL(bcma_core_is_enabled);
253 +
254 +void bcma_core_disable(struct bcma_device *core, u32 flags)
255 +{
256 + if (bcma_aread32(core, BCMA_RESET_CTL) & BCMA_RESET_CTL_RESET)
257 + return;
258 +
259 + bcma_awrite32(core, BCMA_IOCTL, flags);
260 + bcma_aread32(core, BCMA_IOCTL);
261 + udelay(10);
262 +
263 + bcma_awrite32(core, BCMA_RESET_CTL, BCMA_RESET_CTL_RESET);
264 + udelay(1);
265 +}
266 +EXPORT_SYMBOL_GPL(bcma_core_disable);
267 +
268 +int bcma_core_enable(struct bcma_device *core, u32 flags)
269 +{
270 + bcma_core_disable(core, flags);
271 +
272 + bcma_awrite32(core, BCMA_IOCTL, (BCMA_IOCTL_CLK | BCMA_IOCTL_FGC | flags));
273 + bcma_aread32(core, BCMA_IOCTL);
274 +
275 + bcma_awrite32(core, BCMA_RESET_CTL, 0);
276 + udelay(1);
277 +
278 + bcma_awrite32(core, BCMA_IOCTL, (BCMA_IOCTL_CLK | flags));
279 + bcma_aread32(core, BCMA_IOCTL);
280 + udelay(1);
281 +
282 + return 0;
283 +}
284 +EXPORT_SYMBOL_GPL(bcma_core_enable);
285 +
286 +void bcma_core_set_clockmode(struct bcma_device *core,
287 + enum bcma_clkmode clkmode)
288 +{
289 + u16 i;
290 +
291 + WARN_ON(core->id.id != BCMA_CORE_CHIPCOMMON &&
292 + core->id.id != BCMA_CORE_PCIE &&
293 + core->id.id != BCMA_CORE_80211);
294 +
295 + switch (clkmode) {
296 + case BCMA_CLKMODE_FAST:
297 + bcma_set32(core, BCMA_CLKCTLST, BCMA_CLKCTLST_FORCEHT);
298 + udelay(64);
299 + for (i = 0; i < 1500; i++) {
300 + if (bcma_read32(core, BCMA_CLKCTLST) &
301 + BCMA_CLKCTLST_HAVEHT) {
302 + i = 0;
303 + break;
304 + }
305 + udelay(10);
306 + }
307 + if (i)
308 + pr_err("HT force timeout\n");
309 + break;
310 + case BCMA_CLKMODE_DYNAMIC:
311 + pr_warning("Dynamic clockmode not supported yet!\n");
312 + break;
313 + }
314 +}
315 +EXPORT_SYMBOL_GPL(bcma_core_set_clockmode);
316 +
317 +void bcma_core_pll_ctl(struct bcma_device *core, u32 req, u32 status, bool on)
318 +{
319 + u16 i;
320 +
321 + WARN_ON(req & ~BCMA_CLKCTLST_EXTRESREQ);
322 + WARN_ON(status & ~BCMA_CLKCTLST_EXTRESST);
323 +
324 + if (on) {
325 + bcma_set32(core, BCMA_CLKCTLST, req);
326 + for (i = 0; i < 10000; i++) {
327 + if ((bcma_read32(core, BCMA_CLKCTLST) & status) ==
328 + status) {
329 + i = 0;
330 + break;
331 + }
332 + udelay(10);
333 + }
334 + if (i)
335 + pr_err("PLL enable timeout\n");
336 + } else {
337 + pr_warning("Disabling PLL not supported yet!\n");
338 + }
339 +}
340 +EXPORT_SYMBOL_GPL(bcma_core_pll_ctl);
341 +
342 +u32 bcma_core_dma_translation(struct bcma_device *core)
343 +{
344 + switch (core->bus->hosttype) {
345 + case BCMA_HOSTTYPE_SOC:
346 + return 0;
347 + case BCMA_HOSTTYPE_PCI:
348 + if (bcma_aread32(core, BCMA_IOST) & BCMA_IOST_DMA64)
349 + return BCMA_DMA_TRANSLATION_DMA64_CMT;
350 + else
351 + return BCMA_DMA_TRANSLATION_DMA32_CMT;
352 + default:
353 + pr_err("DMA translation unknown for host %d\n",
354 + core->bus->hosttype);
355 + }
356 + return BCMA_DMA_TRANSLATION_NONE;
357 +}
358 +EXPORT_SYMBOL(bcma_core_dma_translation);
359 --- /dev/null
360 +++ b/drivers/bcma/driver_chipcommon.c
361 @@ -0,0 +1,156 @@
362 +/*
363 + * Broadcom specific AMBA
364 + * ChipCommon core driver
365 + *
366 + * Copyright 2005, Broadcom Corporation
367 + * Copyright 2006, 2007, Michael Buesch <m@bues.ch>
368 + *
369 + * Licensed under the GNU/GPL. See COPYING for details.
370 + */
371 +
372 +#include "bcma_private.h"
373 +#include <linux/bcma/bcma.h>
374 +
375 +static inline u32 bcma_cc_write32_masked(struct bcma_drv_cc *cc, u16 offset,
376 + u32 mask, u32 value)
377 +{
378 + value &= mask;
379 + value |= bcma_cc_read32(cc, offset) & ~mask;
380 + bcma_cc_write32(cc, offset, value);
381 +
382 + return value;
383 +}
384 +
385 +void bcma_core_chipcommon_init(struct bcma_drv_cc *cc)
386 +{
387 + u32 leddc_on = 10;
388 + u32 leddc_off = 90;
389 +
390 + if (cc->setup_done)
391 + return;
392 +
393 + if (cc->core->id.rev >= 11)
394 + cc->status = bcma_cc_read32(cc, BCMA_CC_CHIPSTAT);
395 + cc->capabilities = bcma_cc_read32(cc, BCMA_CC_CAP);
396 + if (cc->core->id.rev >= 35)
397 + cc->capabilities_ext = bcma_cc_read32(cc, BCMA_CC_CAP_EXT);
398 +
399 + if (cc->core->id.rev >= 20) {
400 + bcma_cc_write32(cc, BCMA_CC_GPIOPULLUP, 0);
401 + bcma_cc_write32(cc, BCMA_CC_GPIOPULLDOWN, 0);
402 + }
403 +
404 + if (cc->capabilities & BCMA_CC_CAP_PMU)
405 + bcma_pmu_init(cc);
406 + if (cc->capabilities & BCMA_CC_CAP_PCTL)
407 + pr_err("Power control not implemented!\n");
408 +
409 + if (cc->core->id.rev >= 16) {
410 + if (cc->core->bus->sprom.leddc_on_time &&
411 + cc->core->bus->sprom.leddc_off_time) {
412 + leddc_on = cc->core->bus->sprom.leddc_on_time;
413 + leddc_off = cc->core->bus->sprom.leddc_off_time;
414 + }
415 + bcma_cc_write32(cc, BCMA_CC_GPIOTIMER,
416 + ((leddc_on << BCMA_CC_GPIOTIMER_ONTIME_SHIFT) |
417 + (leddc_off << BCMA_CC_GPIOTIMER_OFFTIME_SHIFT)));
418 + }
419 +
420 + cc->setup_done = true;
421 +}
422 +
423 +/* Set chip watchdog reset timer to fire in 'ticks' backplane cycles */
424 +void bcma_chipco_watchdog_timer_set(struct bcma_drv_cc *cc, u32 ticks)
425 +{
426 + /* instant NMI */
427 + bcma_cc_write32(cc, BCMA_CC_WATCHDOG, ticks);
428 +}
429 +
430 +void bcma_chipco_irq_mask(struct bcma_drv_cc *cc, u32 mask, u32 value)
431 +{
432 + bcma_cc_write32_masked(cc, BCMA_CC_IRQMASK, mask, value);
433 +}
434 +
435 +u32 bcma_chipco_irq_status(struct bcma_drv_cc *cc, u32 mask)
436 +{
437 + return bcma_cc_read32(cc, BCMA_CC_IRQSTAT) & mask;
438 +}
439 +
440 +u32 bcma_chipco_gpio_in(struct bcma_drv_cc *cc, u32 mask)
441 +{
442 + return bcma_cc_read32(cc, BCMA_CC_GPIOIN) & mask;
443 +}
444 +
445 +u32 bcma_chipco_gpio_out(struct bcma_drv_cc *cc, u32 mask, u32 value)
446 +{
447 + return bcma_cc_write32_masked(cc, BCMA_CC_GPIOOUT, mask, value);
448 +}
449 +
450 +u32 bcma_chipco_gpio_outen(struct bcma_drv_cc *cc, u32 mask, u32 value)
451 +{
452 + return bcma_cc_write32_masked(cc, BCMA_CC_GPIOOUTEN, mask, value);
453 +}
454 +
455 +u32 bcma_chipco_gpio_control(struct bcma_drv_cc *cc, u32 mask, u32 value)
456 +{
457 + return bcma_cc_write32_masked(cc, BCMA_CC_GPIOCTL, mask, value);
458 +}
459 +EXPORT_SYMBOL_GPL(bcma_chipco_gpio_control);
460 +
461 +u32 bcma_chipco_gpio_intmask(struct bcma_drv_cc *cc, u32 mask, u32 value)
462 +{
463 + return bcma_cc_write32_masked(cc, BCMA_CC_GPIOIRQ, mask, value);
464 +}
465 +
466 +u32 bcma_chipco_gpio_polarity(struct bcma_drv_cc *cc, u32 mask, u32 value)
467 +{
468 + return bcma_cc_write32_masked(cc, BCMA_CC_GPIOPOL, mask, value);
469 +}
470 +
471 +#ifdef CONFIG_BCMA_DRIVER_MIPS
472 +void bcma_chipco_serial_init(struct bcma_drv_cc *cc)
473 +{
474 + unsigned int irq;
475 + u32 baud_base;
476 + u32 i;
477 + unsigned int ccrev = cc->core->id.rev;
478 + struct bcma_serial_port *ports = cc->serial_ports;
479 +
480 + if (ccrev >= 11 && ccrev != 15) {
481 + /* Fixed ALP clock */
482 + baud_base = bcma_pmu_alp_clock(cc);
483 + if (ccrev >= 21) {
484 + /* Turn off UART clock before switching clocksource. */
485 + bcma_cc_write32(cc, BCMA_CC_CORECTL,
486 + bcma_cc_read32(cc, BCMA_CC_CORECTL)
487 + & ~BCMA_CC_CORECTL_UARTCLKEN);
488 + }
489 + /* Set the override bit so we don't divide it */
490 + bcma_cc_write32(cc, BCMA_CC_CORECTL,
491 + bcma_cc_read32(cc, BCMA_CC_CORECTL)
492 + | BCMA_CC_CORECTL_UARTCLK0);
493 + if (ccrev >= 21) {
494 + /* Re-enable the UART clock. */
495 + bcma_cc_write32(cc, BCMA_CC_CORECTL,
496 + bcma_cc_read32(cc, BCMA_CC_CORECTL)
497 + | BCMA_CC_CORECTL_UARTCLKEN);
498 + }
499 + } else {
500 + pr_err("serial not supported on this device ccrev: 0x%x\n",
501 + ccrev);
502 + return;
503 + }
504 +
505 + irq = bcma_core_mips_irq(cc->core);
506 +
507 + /* Determine the registers of the UARTs */
508 + cc->nr_serial_ports = (cc->capabilities & BCMA_CC_CAP_NRUART);
509 + for (i = 0; i < cc->nr_serial_ports; i++) {
510 + ports[i].regs = cc->core->io_addr + BCMA_CC_UART0_DATA +
511 + (i * 256);
512 + ports[i].irq = irq;
513 + ports[i].baud_base = baud_base;
514 + ports[i].reg_shift = 0;
515 + }
516 +}
517 +#endif /* CONFIG_BCMA_DRIVER_MIPS */
518 --- /dev/null
519 +++ b/drivers/bcma/driver_chipcommon_pmu.c
520 @@ -0,0 +1,309 @@
521 +/*
522 + * Broadcom specific AMBA
523 + * ChipCommon Power Management Unit driver
524 + *
525 + * Copyright 2009, Michael Buesch <m@bues.ch>
526 + * Copyright 2007, Broadcom Corporation
527 + *
528 + * Licensed under the GNU/GPL. See COPYING for details.
529 + */
530 +
531 +#include "bcma_private.h"
532 +#include <linux/bcma/bcma.h>
533 +
534 +static u32 bcma_chipco_pll_read(struct bcma_drv_cc *cc, u32 offset)
535 +{
536 + bcma_cc_write32(cc, BCMA_CC_PLLCTL_ADDR, offset);
537 + bcma_cc_read32(cc, BCMA_CC_PLLCTL_ADDR);
538 + return bcma_cc_read32(cc, BCMA_CC_PLLCTL_DATA);
539 +}
540 +
541 +void bcma_chipco_pll_write(struct bcma_drv_cc *cc, u32 offset, u32 value)
542 +{
543 + bcma_cc_write32(cc, BCMA_CC_PLLCTL_ADDR, offset);
544 + bcma_cc_read32(cc, BCMA_CC_PLLCTL_ADDR);
545 + bcma_cc_write32(cc, BCMA_CC_PLLCTL_DATA, value);
546 +}
547 +EXPORT_SYMBOL_GPL(bcma_chipco_pll_write);
548 +
549 +void bcma_chipco_pll_maskset(struct bcma_drv_cc *cc, u32 offset, u32 mask,
550 + u32 set)
551 +{
552 + bcma_cc_write32(cc, BCMA_CC_PLLCTL_ADDR, offset);
553 + bcma_cc_read32(cc, BCMA_CC_PLLCTL_ADDR);
554 + bcma_cc_maskset32(cc, BCMA_CC_PLLCTL_DATA, mask, set);
555 +}
556 +EXPORT_SYMBOL_GPL(bcma_chipco_pll_maskset);
557 +
558 +void bcma_chipco_chipctl_maskset(struct bcma_drv_cc *cc,
559 + u32 offset, u32 mask, u32 set)
560 +{
561 + bcma_cc_write32(cc, BCMA_CC_CHIPCTL_ADDR, offset);
562 + bcma_cc_read32(cc, BCMA_CC_CHIPCTL_ADDR);
563 + bcma_cc_maskset32(cc, BCMA_CC_CHIPCTL_DATA, mask, set);
564 +}
565 +EXPORT_SYMBOL_GPL(bcma_chipco_chipctl_maskset);
566 +
567 +void bcma_chipco_regctl_maskset(struct bcma_drv_cc *cc, u32 offset, u32 mask,
568 + u32 set)
569 +{
570 + bcma_cc_write32(cc, BCMA_CC_REGCTL_ADDR, offset);
571 + bcma_cc_read32(cc, BCMA_CC_REGCTL_ADDR);
572 + bcma_cc_maskset32(cc, BCMA_CC_REGCTL_DATA, mask, set);
573 +}
574 +EXPORT_SYMBOL_GPL(bcma_chipco_regctl_maskset);
575 +
576 +static void bcma_pmu_pll_init(struct bcma_drv_cc *cc)
577 +{
578 + struct bcma_bus *bus = cc->core->bus;
579 +
580 + switch (bus->chipinfo.id) {
581 + case 0x4313:
582 + case 0x4331:
583 + case 43224:
584 + case 43225:
585 + break;
586 + default:
587 + pr_err("PLL init unknown for device 0x%04X\n",
588 + bus->chipinfo.id);
589 + }
590 +}
591 +
592 +static void bcma_pmu_resources_init(struct bcma_drv_cc *cc)
593 +{
594 + struct bcma_bus *bus = cc->core->bus;
595 + u32 min_msk = 0, max_msk = 0;
596 +
597 + switch (bus->chipinfo.id) {
598 + case 0x4313:
599 + min_msk = 0x200D;
600 + max_msk = 0xFFFF;
601 + break;
602 + case 43224:
603 + case 43225:
604 + break;
605 + default:
606 + pr_err("PMU resource config unknown for device 0x%04X\n",
607 + bus->chipinfo.id);
608 + }
609 +
610 + /* Set the resource masks. */
611 + if (min_msk)
612 + bcma_cc_write32(cc, BCMA_CC_PMU_MINRES_MSK, min_msk);
613 + if (max_msk)
614 + bcma_cc_write32(cc, BCMA_CC_PMU_MAXRES_MSK, max_msk);
615 +}
616 +
617 +void bcma_pmu_swreg_init(struct bcma_drv_cc *cc)
618 +{
619 + struct bcma_bus *bus = cc->core->bus;
620 +
621 + switch (bus->chipinfo.id) {
622 + case 0x4313:
623 + case 0x4331:
624 + case 43224:
625 + case 43225:
626 + break;
627 + default:
628 + pr_err("PMU switch/regulators init unknown for device "
629 + "0x%04X\n", bus->chipinfo.id);
630 + }
631 +}
632 +
633 +/* Disable to allow reading SPROM. Don't know the adventages of enabling it. */
634 +void bcma_chipco_bcm4331_ext_pa_lines_ctl(struct bcma_drv_cc *cc, bool enable)
635 +{
636 + struct bcma_bus *bus = cc->core->bus;
637 + u32 val;
638 +
639 + val = bcma_cc_read32(cc, BCMA_CC_CHIPCTL);
640 + if (enable) {
641 + val |= BCMA_CHIPCTL_4331_EXTPA_EN;
642 + if (bus->chipinfo.pkg == 9 || bus->chipinfo.pkg == 11)
643 + val |= BCMA_CHIPCTL_4331_EXTPA_ON_GPIO2_5;
644 + } else {
645 + val &= ~BCMA_CHIPCTL_4331_EXTPA_EN;
646 + val &= ~BCMA_CHIPCTL_4331_EXTPA_ON_GPIO2_5;
647 + }
648 + bcma_cc_write32(cc, BCMA_CC_CHIPCTL, val);
649 +}
650 +
651 +void bcma_pmu_workarounds(struct bcma_drv_cc *cc)
652 +{
653 + struct bcma_bus *bus = cc->core->bus;
654 +
655 + switch (bus->chipinfo.id) {
656 + case 0x4313:
657 + bcma_chipco_chipctl_maskset(cc, 0, ~0, 0x7);
658 + break;
659 + case 0x4331:
660 + /* BCM4331 workaround is SPROM-related, we put it in sprom.c */
661 + break;
662 + case 43224:
663 + if (bus->chipinfo.rev == 0) {
664 + pr_err("Workarounds for 43224 rev 0 not fully "
665 + "implemented\n");
666 + bcma_chipco_chipctl_maskset(cc, 0, ~0, 0x00F000F0);
667 + } else {
668 + bcma_chipco_chipctl_maskset(cc, 0, ~0, 0xF0);
669 + }
670 + break;
671 + case 43225:
672 + break;
673 + default:
674 + pr_err("Workarounds unknown for device 0x%04X\n",
675 + bus->chipinfo.id);
676 + }
677 +}
678 +
679 +void bcma_pmu_init(struct bcma_drv_cc *cc)
680 +{
681 + u32 pmucap;
682 +
683 + pmucap = bcma_cc_read32(cc, BCMA_CC_PMU_CAP);
684 + cc->pmu.rev = (pmucap & BCMA_CC_PMU_CAP_REVISION);
685 +
686 + pr_debug("Found rev %u PMU (capabilities 0x%08X)\n", cc->pmu.rev,
687 + pmucap);
688 +
689 + if (cc->pmu.rev == 1)
690 + bcma_cc_mask32(cc, BCMA_CC_PMU_CTL,
691 + ~BCMA_CC_PMU_CTL_NOILPONW);
692 + else
693 + bcma_cc_set32(cc, BCMA_CC_PMU_CTL,
694 + BCMA_CC_PMU_CTL_NOILPONW);
695 +
696 + if (cc->core->id.id == 0x4329 && cc->core->id.rev == 2)
697 + pr_err("Fix for 4329b0 bad LPOM state not implemented!\n");
698 +
699 + bcma_pmu_pll_init(cc);
700 + bcma_pmu_resources_init(cc);
701 + bcma_pmu_swreg_init(cc);
702 + bcma_pmu_workarounds(cc);
703 +}
704 +
705 +u32 bcma_pmu_alp_clock(struct bcma_drv_cc *cc)
706 +{
707 + struct bcma_bus *bus = cc->core->bus;
708 +
709 + switch (bus->chipinfo.id) {
710 + case 0x4716:
711 + case 0x4748:
712 + case 47162:
713 + case 0x4313:
714 + case 0x5357:
715 + case 0x4749:
716 + case 53572:
717 + /* always 20Mhz */
718 + return 20000 * 1000;
719 + case 0x5356:
720 + case 0x5300:
721 + /* always 25Mhz */
722 + return 25000 * 1000;
723 + default:
724 + pr_warning("No ALP clock specified for %04X device, "
725 + "pmu rev. %d, using default %d Hz\n",
726 + bus->chipinfo.id, cc->pmu.rev, BCMA_CC_PMU_ALP_CLOCK);
727 + }
728 + return BCMA_CC_PMU_ALP_CLOCK;
729 +}
730 +
731 +/* Find the output of the "m" pll divider given pll controls that start with
732 + * pllreg "pll0" i.e. 12 for main 6 for phy, 0 for misc.
733 + */
734 +static u32 bcma_pmu_clock(struct bcma_drv_cc *cc, u32 pll0, u32 m)
735 +{
736 + u32 tmp, div, ndiv, p1, p2, fc;
737 + struct bcma_bus *bus = cc->core->bus;
738 +
739 + BUG_ON((pll0 & 3) || (pll0 > BCMA_CC_PMU4716_MAINPLL_PLL0));
740 +
741 + BUG_ON(!m || m > 4);
742 +
743 + if (bus->chipinfo.id == 0x5357 || bus->chipinfo.id == 0x4749) {
744 + /* Detect failure in clock setting */
745 + tmp = bcma_cc_read32(cc, BCMA_CC_CHIPSTAT);
746 + if (tmp & 0x40000)
747 + return 133 * 1000000;
748 + }
749 +
750 + tmp = bcma_chipco_pll_read(cc, pll0 + BCMA_CC_PPL_P1P2_OFF);
751 + p1 = (tmp & BCMA_CC_PPL_P1_MASK) >> BCMA_CC_PPL_P1_SHIFT;
752 + p2 = (tmp & BCMA_CC_PPL_P2_MASK) >> BCMA_CC_PPL_P2_SHIFT;
753 +
754 + tmp = bcma_chipco_pll_read(cc, pll0 + BCMA_CC_PPL_M14_OFF);
755 + div = (tmp >> ((m - 1) * BCMA_CC_PPL_MDIV_WIDTH)) &
756 + BCMA_CC_PPL_MDIV_MASK;
757 +
758 + tmp = bcma_chipco_pll_read(cc, pll0 + BCMA_CC_PPL_NM5_OFF);
759 + ndiv = (tmp & BCMA_CC_PPL_NDIV_MASK) >> BCMA_CC_PPL_NDIV_SHIFT;
760 +
761 + /* Do calculation in Mhz */
762 + fc = bcma_pmu_alp_clock(cc) / 1000000;
763 + fc = (p1 * ndiv * fc) / p2;
764 +
765 + /* Return clock in Hertz */
766 + return (fc / div) * 1000000;
767 +}
768 +
769 +/* query bus clock frequency for PMU-enabled chipcommon */
770 +u32 bcma_pmu_get_clockcontrol(struct bcma_drv_cc *cc)
771 +{
772 + struct bcma_bus *bus = cc->core->bus;
773 +
774 + switch (bus->chipinfo.id) {
775 + case 0x4716:
776 + case 0x4748:
777 + case 47162:
778 + return bcma_pmu_clock(cc, BCMA_CC_PMU4716_MAINPLL_PLL0,
779 + BCMA_CC_PMU5_MAINPLL_SSB);
780 + case 0x5356:
781 + return bcma_pmu_clock(cc, BCMA_CC_PMU5356_MAINPLL_PLL0,
782 + BCMA_CC_PMU5_MAINPLL_SSB);
783 + case 0x5357:
784 + case 0x4749:
785 + return bcma_pmu_clock(cc, BCMA_CC_PMU5357_MAINPLL_PLL0,
786 + BCMA_CC_PMU5_MAINPLL_SSB);
787 + case 0x5300:
788 + return bcma_pmu_clock(cc, BCMA_CC_PMU4706_MAINPLL_PLL0,
789 + BCMA_CC_PMU5_MAINPLL_SSB);
790 + case 53572:
791 + return 75000000;
792 + default:
793 + pr_warning("No backplane clock specified for %04X device, "
794 + "pmu rev. %d, using default %d Hz\n",
795 + bus->chipinfo.id, cc->pmu.rev, BCMA_CC_PMU_HT_CLOCK);
796 + }
797 + return BCMA_CC_PMU_HT_CLOCK;
798 +}
799 +
800 +/* query cpu clock frequency for PMU-enabled chipcommon */
801 +u32 bcma_pmu_get_clockcpu(struct bcma_drv_cc *cc)
802 +{
803 + struct bcma_bus *bus = cc->core->bus;
804 +
805 + if (bus->chipinfo.id == 53572)
806 + return 300000000;
807 +
808 + if (cc->pmu.rev >= 5) {
809 + u32 pll;
810 + switch (bus->chipinfo.id) {
811 + case 0x5356:
812 + pll = BCMA_CC_PMU5356_MAINPLL_PLL0;
813 + break;
814 + case 0x5357:
815 + case 0x4749:
816 + pll = BCMA_CC_PMU5357_MAINPLL_PLL0;
817 + break;
818 + default:
819 + pll = BCMA_CC_PMU4716_MAINPLL_PLL0;
820 + break;
821 + }
822 +
823 + /* TODO: if (bus->chipinfo.id == 0x5300)
824 + return si_4706_pmu_clock(sih, osh, cc, PMU4706_MAINPLL_PLL0, PMU5_MAINPLL_CPU); */
825 + return bcma_pmu_clock(cc, pll, BCMA_CC_PMU5_MAINPLL_CPU);
826 + }
827 +
828 + return bcma_pmu_get_clockcontrol(cc);
829 +}
830 --- /dev/null
831 +++ b/drivers/bcma/driver_pci.c
832 @@ -0,0 +1,237 @@
833 +/*
834 + * Broadcom specific AMBA
835 + * PCI Core
836 + *
837 + * Copyright 2005, Broadcom Corporation
838 + * Copyright 2006, 2007, Michael Buesch <m@bues.ch>
839 + *
840 + * Licensed under the GNU/GPL. See COPYING for details.
841 + */
842 +
843 +#include "bcma_private.h"
844 +#include <linux/bcma/bcma.h>
845 +
846 +/**************************************************
847 + * R/W ops.
848 + **************************************************/
849 +
850 +static u32 bcma_pcie_read(struct bcma_drv_pci *pc, u32 address)
851 +{
852 + pcicore_write32(pc, 0x130, address);
853 + pcicore_read32(pc, 0x130);
854 + return pcicore_read32(pc, 0x134);
855 +}
856 +
857 +#if 0
858 +static void bcma_pcie_write(struct bcma_drv_pci *pc, u32 address, u32 data)
859 +{
860 + pcicore_write32(pc, 0x130, address);
861 + pcicore_read32(pc, 0x130);
862 + pcicore_write32(pc, 0x134, data);
863 +}
864 +#endif
865 +
866 +static void bcma_pcie_mdio_set_phy(struct bcma_drv_pci *pc, u8 phy)
867 +{
868 + const u16 mdio_control = 0x128;
869 + const u16 mdio_data = 0x12C;
870 + u32 v;
871 + int i;
872 +
873 + v = (1 << 30); /* Start of Transaction */
874 + v |= (1 << 28); /* Write Transaction */
875 + v |= (1 << 17); /* Turnaround */
876 + v |= (0x1F << 18);
877 + v |= (phy << 4);
878 + pcicore_write32(pc, mdio_data, v);
879 +
880 + udelay(10);
881 + for (i = 0; i < 200; i++) {
882 + v = pcicore_read32(pc, mdio_control);
883 + if (v & 0x100 /* Trans complete */)
884 + break;
885 + msleep(1);
886 + }
887 +}
888 +
889 +static u16 bcma_pcie_mdio_read(struct bcma_drv_pci *pc, u8 device, u8 address)
890 +{
891 + const u16 mdio_control = 0x128;
892 + const u16 mdio_data = 0x12C;
893 + int max_retries = 10;
894 + u16 ret = 0;
895 + u32 v;
896 + int i;
897 +
898 + v = 0x80; /* Enable Preamble Sequence */
899 + v |= 0x2; /* MDIO Clock Divisor */
900 + pcicore_write32(pc, mdio_control, v);
901 +
902 + if (pc->core->id.rev >= 10) {
903 + max_retries = 200;
904 + bcma_pcie_mdio_set_phy(pc, device);
905 + }
906 +
907 + v = (1 << 30); /* Start of Transaction */
908 + v |= (1 << 29); /* Read Transaction */
909 + v |= (1 << 17); /* Turnaround */
910 + if (pc->core->id.rev < 10)
911 + v |= (u32)device << 22;
912 + v |= (u32)address << 18;
913 + pcicore_write32(pc, mdio_data, v);
914 + /* Wait for the device to complete the transaction */
915 + udelay(10);
916 + for (i = 0; i < max_retries; i++) {
917 + v = pcicore_read32(pc, mdio_control);
918 + if (v & 0x100 /* Trans complete */) {
919 + udelay(10);
920 + ret = pcicore_read32(pc, mdio_data);
921 + break;
922 + }
923 + msleep(1);
924 + }
925 + pcicore_write32(pc, mdio_control, 0);
926 + return ret;
927 +}
928 +
929 +static void bcma_pcie_mdio_write(struct bcma_drv_pci *pc, u8 device,
930 + u8 address, u16 data)
931 +{
932 + const u16 mdio_control = 0x128;
933 + const u16 mdio_data = 0x12C;
934 + int max_retries = 10;
935 + u32 v;
936 + int i;
937 +
938 + v = 0x80; /* Enable Preamble Sequence */
939 + v |= 0x2; /* MDIO Clock Divisor */
940 + pcicore_write32(pc, mdio_control, v);
941 +
942 + if (pc->core->id.rev >= 10) {
943 + max_retries = 200;
944 + bcma_pcie_mdio_set_phy(pc, device);
945 + }
946 +
947 + v = (1 << 30); /* Start of Transaction */
948 + v |= (1 << 28); /* Write Transaction */
949 + v |= (1 << 17); /* Turnaround */
950 + if (pc->core->id.rev < 10)
951 + v |= (u32)device << 22;
952 + v |= (u32)address << 18;
953 + v |= data;
954 + pcicore_write32(pc, mdio_data, v);
955 + /* Wait for the device to complete the transaction */
956 + udelay(10);
957 + for (i = 0; i < max_retries; i++) {
958 + v = pcicore_read32(pc, mdio_control);
959 + if (v & 0x100 /* Trans complete */)
960 + break;
961 + msleep(1);
962 + }
963 + pcicore_write32(pc, mdio_control, 0);
964 +}
965 +
966 +/**************************************************
967 + * Workarounds.
968 + **************************************************/
969 +
970 +static u8 bcma_pcicore_polarity_workaround(struct bcma_drv_pci *pc)
971 +{
972 + return (bcma_pcie_read(pc, 0x204) & 0x10) ? 0xC0 : 0x80;
973 +}
974 +
975 +static void bcma_pcicore_serdes_workaround(struct bcma_drv_pci *pc)
976 +{
977 + const u8 serdes_pll_device = 0x1D;
978 + const u8 serdes_rx_device = 0x1F;
979 + u16 tmp;
980 +
981 + bcma_pcie_mdio_write(pc, serdes_rx_device, 1 /* Control */,
982 + bcma_pcicore_polarity_workaround(pc));
983 + tmp = bcma_pcie_mdio_read(pc, serdes_pll_device, 1 /* Control */);
984 + if (tmp & 0x4000)
985 + bcma_pcie_mdio_write(pc, serdes_pll_device, 1, tmp & ~0x4000);
986 +}
987 +
988 +/**************************************************
989 + * Init.
990 + **************************************************/
991 +
992 +static void bcma_core_pci_clientmode_init(struct bcma_drv_pci *pc)
993 +{
994 + bcma_pcicore_serdes_workaround(pc);
995 +}
996 +
997 +static bool bcma_core_pci_is_in_hostmode(struct bcma_drv_pci *pc)
998 +{
999 + struct bcma_bus *bus = pc->core->bus;
1000 + u16 chipid_top;
1001 +
1002 + chipid_top = (bus->chipinfo.id & 0xFF00);
1003 + if (chipid_top != 0x4700 &&
1004 + chipid_top != 0x5300)
1005 + return false;
1006 +
1007 +#ifdef CONFIG_SSB_DRIVER_PCICORE
1008 + if (bus->sprom.boardflags_lo & SSB_BFL_NOPCI)
1009 + return false;
1010 +#endif /* CONFIG_SSB_DRIVER_PCICORE */
1011 +
1012 +#if 0
1013 + /* TODO: on BCMA we use address from EROM instead of magic formula */
1014 + u32 tmp;
1015 + return !mips_busprobe32(tmp, (bus->mmio +
1016 + (pc->core->core_index * BCMA_CORE_SIZE)));
1017 +#endif
1018 +
1019 + return true;
1020 +}
1021 +
1022 +void bcma_core_pci_init(struct bcma_drv_pci *pc)
1023 +{
1024 + if (pc->setup_done)
1025 + return;
1026 +
1027 + if (bcma_core_pci_is_in_hostmode(pc)) {
1028 +#ifdef CONFIG_BCMA_DRIVER_PCI_HOSTMODE
1029 + bcma_core_pci_hostmode_init(pc);
1030 +#else
1031 + pr_err("Driver compiled without support for hostmode PCI\n");
1032 +#endif /* CONFIG_BCMA_DRIVER_PCI_HOSTMODE */
1033 + } else {
1034 + bcma_core_pci_clientmode_init(pc);
1035 + }
1036 +
1037 + pc->setup_done = true;
1038 +}
1039 +
1040 +int bcma_core_pci_irq_ctl(struct bcma_drv_pci *pc, struct bcma_device *core,
1041 + bool enable)
1042 +{
1043 + struct pci_dev *pdev = pc->core->bus->host_pci;
1044 + u32 coremask, tmp;
1045 + int err = 0;
1046 +
1047 + if (core->bus->hosttype != BCMA_HOSTTYPE_PCI) {
1048 + /* This bcma device is not on a PCI host-bus. So the IRQs are
1049 + * not routed through the PCI core.
1050 + * So we must not enable routing through the PCI core. */
1051 + goto out;
1052 + }
1053 +
1054 + err = pci_read_config_dword(pdev, BCMA_PCI_IRQMASK, &tmp);
1055 + if (err)
1056 + goto out;
1057 +
1058 + coremask = BIT(core->core_index) << 8;
1059 + if (enable)
1060 + tmp |= coremask;
1061 + else
1062 + tmp &= ~coremask;
1063 +
1064 + err = pci_write_config_dword(pdev, BCMA_PCI_IRQMASK, tmp);
1065 +
1066 +out:
1067 + return err;
1068 +}
1069 +EXPORT_SYMBOL_GPL(bcma_core_pci_irq_ctl);
1070 --- /dev/null
1071 +++ b/drivers/bcma/host_pci.c
1072 @@ -0,0 +1,299 @@
1073 +/*
1074 + * Broadcom specific AMBA
1075 + * PCI Host
1076 + *
1077 + * Licensed under the GNU/GPL. See COPYING for details.
1078 + */
1079 +
1080 +#include "bcma_private.h"
1081 +#include <linux/slab.h>
1082 +#include <linux/bcma/bcma.h>
1083 +#include <linux/pci.h>
1084 +#include <linux/module.h>
1085 +
1086 +static void bcma_host_pci_switch_core(struct bcma_device *core)
1087 +{
1088 + pci_write_config_dword(core->bus->host_pci, BCMA_PCI_BAR0_WIN,
1089 + core->addr);
1090 + pci_write_config_dword(core->bus->host_pci, BCMA_PCI_BAR0_WIN2,
1091 + core->wrap);
1092 + core->bus->mapped_core = core;
1093 + pr_debug("Switched to core: 0x%X\n", core->id.id);
1094 +}
1095 +
1096 +/* Provides access to the requested core. Returns base offset that has to be
1097 + * used. It makes use of fixed windows when possible. */
1098 +static u16 bcma_host_pci_provide_access_to_core(struct bcma_device *core)
1099 +{
1100 + switch (core->id.id) {
1101 + case BCMA_CORE_CHIPCOMMON:
1102 + return 3 * BCMA_CORE_SIZE;
1103 + case BCMA_CORE_PCIE:
1104 + return 2 * BCMA_CORE_SIZE;
1105 + }
1106 +
1107 + if (core->bus->mapped_core != core)
1108 + bcma_host_pci_switch_core(core);
1109 + return 0;
1110 +}
1111 +
1112 +static u8 bcma_host_pci_read8(struct bcma_device *core, u16 offset)
1113 +{
1114 + offset += bcma_host_pci_provide_access_to_core(core);
1115 + return ioread8(core->bus->mmio + offset);
1116 +}
1117 +
1118 +static u16 bcma_host_pci_read16(struct bcma_device *core, u16 offset)
1119 +{
1120 + offset += bcma_host_pci_provide_access_to_core(core);
1121 + return ioread16(core->bus->mmio + offset);
1122 +}
1123 +
1124 +static u32 bcma_host_pci_read32(struct bcma_device *core, u16 offset)
1125 +{
1126 + offset += bcma_host_pci_provide_access_to_core(core);
1127 + return ioread32(core->bus->mmio + offset);
1128 +}
1129 +
1130 +static void bcma_host_pci_write8(struct bcma_device *core, u16 offset,
1131 + u8 value)
1132 +{
1133 + offset += bcma_host_pci_provide_access_to_core(core);
1134 + iowrite8(value, core->bus->mmio + offset);
1135 +}
1136 +
1137 +static void bcma_host_pci_write16(struct bcma_device *core, u16 offset,
1138 + u16 value)
1139 +{
1140 + offset += bcma_host_pci_provide_access_to_core(core);
1141 + iowrite16(value, core->bus->mmio + offset);
1142 +}
1143 +
1144 +static void bcma_host_pci_write32(struct bcma_device *core, u16 offset,
1145 + u32 value)
1146 +{
1147 + offset += bcma_host_pci_provide_access_to_core(core);
1148 + iowrite32(value, core->bus->mmio + offset);
1149 +}
1150 +
1151 +#ifdef CONFIG_BCMA_BLOCKIO
1152 +void bcma_host_pci_block_read(struct bcma_device *core, void *buffer,
1153 + size_t count, u16 offset, u8 reg_width)
1154 +{
1155 + void __iomem *addr = core->bus->mmio + offset;
1156 + if (core->bus->mapped_core != core)
1157 + bcma_host_pci_switch_core(core);
1158 + switch (reg_width) {
1159 + case sizeof(u8):
1160 + ioread8_rep(addr, buffer, count);
1161 + break;
1162 + case sizeof(u16):
1163 + WARN_ON(count & 1);
1164 + ioread16_rep(addr, buffer, count >> 1);
1165 + break;
1166 + case sizeof(u32):
1167 + WARN_ON(count & 3);
1168 + ioread32_rep(addr, buffer, count >> 2);
1169 + break;
1170 + default:
1171 + WARN_ON(1);
1172 + }
1173 +}
1174 +
1175 +void bcma_host_pci_block_write(struct bcma_device *core, const void *buffer,
1176 + size_t count, u16 offset, u8 reg_width)
1177 +{
1178 + void __iomem *addr = core->bus->mmio + offset;
1179 + if (core->bus->mapped_core != core)
1180 + bcma_host_pci_switch_core(core);
1181 + switch (reg_width) {
1182 + case sizeof(u8):
1183 + iowrite8_rep(addr, buffer, count);
1184 + break;
1185 + case sizeof(u16):
1186 + WARN_ON(count & 1);
1187 + iowrite16_rep(addr, buffer, count >> 1);
1188 + break;
1189 + case sizeof(u32):
1190 + WARN_ON(count & 3);
1191 + iowrite32_rep(addr, buffer, count >> 2);
1192 + break;
1193 + default:
1194 + WARN_ON(1);
1195 + }
1196 +}
1197 +#endif
1198 +
1199 +static u32 bcma_host_pci_aread32(struct bcma_device *core, u16 offset)
1200 +{
1201 + if (core->bus->mapped_core != core)
1202 + bcma_host_pci_switch_core(core);
1203 + return ioread32(core->bus->mmio + (1 * BCMA_CORE_SIZE) + offset);
1204 +}
1205 +
1206 +static void bcma_host_pci_awrite32(struct bcma_device *core, u16 offset,
1207 + u32 value)
1208 +{
1209 + if (core->bus->mapped_core != core)
1210 + bcma_host_pci_switch_core(core);
1211 + iowrite32(value, core->bus->mmio + (1 * BCMA_CORE_SIZE) + offset);
1212 +}
1213 +
1214 +const struct bcma_host_ops bcma_host_pci_ops = {
1215 + .read8 = bcma_host_pci_read8,
1216 + .read16 = bcma_host_pci_read16,
1217 + .read32 = bcma_host_pci_read32,
1218 + .write8 = bcma_host_pci_write8,
1219 + .write16 = bcma_host_pci_write16,
1220 + .write32 = bcma_host_pci_write32,
1221 +#ifdef CONFIG_BCMA_BLOCKIO
1222 + .block_read = bcma_host_pci_block_read,
1223 + .block_write = bcma_host_pci_block_write,
1224 +#endif
1225 + .aread32 = bcma_host_pci_aread32,
1226 + .awrite32 = bcma_host_pci_awrite32,
1227 +};
1228 +
1229 +static int bcma_host_pci_probe(struct pci_dev *dev,
1230 + const struct pci_device_id *id)
1231 +{
1232 + struct bcma_bus *bus;
1233 + int err = -ENOMEM;
1234 + const char *name;
1235 + u32 val;
1236 +
1237 + /* Alloc */
1238 + bus = kzalloc(sizeof(*bus), GFP_KERNEL);
1239 + if (!bus)
1240 + goto out;
1241 +
1242 + /* Basic PCI configuration */
1243 + err = pci_enable_device(dev);
1244 + if (err)
1245 + goto err_kfree_bus;
1246 +
1247 + name = dev_name(&dev->dev);
1248 + if (dev->driver && dev->driver->name)
1249 + name = dev->driver->name;
1250 + err = pci_request_regions(dev, name);
1251 + if (err)
1252 + goto err_pci_disable;
1253 + pci_set_master(dev);
1254 +
1255 + /* Disable the RETRY_TIMEOUT register (0x41) to keep
1256 + * PCI Tx retries from interfering with C3 CPU state */
1257 + pci_read_config_dword(dev, 0x40, &val);
1258 + if ((val & 0x0000ff00) != 0)
1259 + pci_write_config_dword(dev, 0x40, val & 0xffff00ff);
1260 +
1261 + /* SSB needed additional powering up, do we have any AMBA PCI cards? */
1262 + if (!dev->is_pcie)
1263 + pr_err("PCI card detected, report problems.\n");
1264 +
1265 + /* Map MMIO */
1266 + err = -ENOMEM;
1267 + bus->mmio = pci_iomap(dev, 0, ~0UL);
1268 + if (!bus->mmio)
1269 + goto err_pci_release_regions;
1270 +
1271 + /* Host specific */
1272 + bus->host_pci = dev;
1273 + bus->hosttype = BCMA_HOSTTYPE_PCI;
1274 + bus->ops = &bcma_host_pci_ops;
1275 +
1276 + /* Register */
1277 + err = bcma_bus_register(bus);
1278 + if (err)
1279 + goto err_pci_unmap_mmio;
1280 +
1281 + pci_set_drvdata(dev, bus);
1282 +
1283 +out:
1284 + return err;
1285 +
1286 +err_pci_unmap_mmio:
1287 + pci_iounmap(dev, bus->mmio);
1288 +err_pci_release_regions:
1289 + pci_release_regions(dev);
1290 +err_pci_disable:
1291 + pci_disable_device(dev);
1292 +err_kfree_bus:
1293 + kfree(bus);
1294 + return err;
1295 +}
1296 +
1297 +static void bcma_host_pci_remove(struct pci_dev *dev)
1298 +{
1299 + struct bcma_bus *bus = pci_get_drvdata(dev);
1300 +
1301 + bcma_bus_unregister(bus);
1302 + pci_iounmap(dev, bus->mmio);
1303 + pci_release_regions(dev);
1304 + pci_disable_device(dev);
1305 + kfree(bus);
1306 + pci_set_drvdata(dev, NULL);
1307 +}
1308 +
1309 +#ifdef CONFIG_PM
1310 +static int bcma_host_pci_suspend(struct pci_dev *dev, pm_message_t state)
1311 +{
1312 + /* Host specific */
1313 + pci_save_state(dev);
1314 + pci_disable_device(dev);
1315 + pci_set_power_state(dev, pci_choose_state(dev, state));
1316 +
1317 + return 0;
1318 +}
1319 +
1320 +static int bcma_host_pci_resume(struct pci_dev *dev)
1321 +{
1322 + struct bcma_bus *bus = pci_get_drvdata(dev);
1323 + int err;
1324 +
1325 + /* Host specific */
1326 + pci_set_power_state(dev, 0);
1327 + err = pci_enable_device(dev);
1328 + if (err)
1329 + return err;
1330 + pci_restore_state(dev);
1331 +
1332 + /* Bus specific */
1333 + err = bcma_bus_resume(bus);
1334 + if (err)
1335 + return err;
1336 +
1337 + return 0;
1338 +}
1339 +#else /* CONFIG_PM */
1340 +# define bcma_host_pci_suspend NULL
1341 +# define bcma_host_pci_resume NULL
1342 +#endif /* CONFIG_PM */
1343 +
1344 +static DEFINE_PCI_DEVICE_TABLE(bcma_pci_bridge_tbl) = {
1345 + { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x0576) },
1346 + { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4331) },
1347 + { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4353) },
1348 + { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4357) },
1349 + { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4727) },
1350 + { 0, },
1351 +};
1352 +MODULE_DEVICE_TABLE(pci, bcma_pci_bridge_tbl);
1353 +
1354 +static struct pci_driver bcma_pci_bridge_driver = {
1355 + .name = "bcma-pci-bridge",
1356 + .id_table = bcma_pci_bridge_tbl,
1357 + .probe = bcma_host_pci_probe,
1358 + .remove = bcma_host_pci_remove,
1359 + .suspend = bcma_host_pci_suspend,
1360 + .resume = bcma_host_pci_resume,
1361 +};
1362 +
1363 +int __init bcma_host_pci_init(void)
1364 +{
1365 + return pci_register_driver(&bcma_pci_bridge_driver);
1366 +}
1367 +
1368 +void __exit bcma_host_pci_exit(void)
1369 +{
1370 + pci_unregister_driver(&bcma_pci_bridge_driver);
1371 +}
1372 --- /dev/null
1373 +++ b/drivers/bcma/main.c
1374 @@ -0,0 +1,354 @@
1375 +/*
1376 + * Broadcom specific AMBA
1377 + * Bus subsystem
1378 + *
1379 + * Licensed under the GNU/GPL. See COPYING for details.
1380 + */
1381 +
1382 +#include "bcma_private.h"
1383 +#include <linux/module.h>
1384 +#include <linux/bcma/bcma.h>
1385 +#include <linux/slab.h>
1386 +
1387 +MODULE_DESCRIPTION("Broadcom's specific AMBA driver");
1388 +MODULE_LICENSE("GPL");
1389 +
1390 +static int bcma_bus_match(struct device *dev, struct device_driver *drv);
1391 +static int bcma_device_probe(struct device *dev);
1392 +static int bcma_device_remove(struct device *dev);
1393 +static int bcma_device_uevent(struct device *dev, struct kobj_uevent_env *env);
1394 +
1395 +static ssize_t manuf_show(struct device *dev, struct device_attribute *attr, char *buf)
1396 +{
1397 + struct bcma_device *core = container_of(dev, struct bcma_device, dev);
1398 + return sprintf(buf, "0x%03X\n", core->id.manuf);
1399 +}
1400 +static ssize_t id_show(struct device *dev, struct device_attribute *attr, char *buf)
1401 +{
1402 + struct bcma_device *core = container_of(dev, struct bcma_device, dev);
1403 + return sprintf(buf, "0x%03X\n", core->id.id);
1404 +}
1405 +static ssize_t rev_show(struct device *dev, struct device_attribute *attr, char *buf)
1406 +{
1407 + struct bcma_device *core = container_of(dev, struct bcma_device, dev);
1408 + return sprintf(buf, "0x%02X\n", core->id.rev);
1409 +}
1410 +static ssize_t class_show(struct device *dev, struct device_attribute *attr, char *buf)
1411 +{
1412 + struct bcma_device *core = container_of(dev, struct bcma_device, dev);
1413 + return sprintf(buf, "0x%X\n", core->id.class);
1414 +}
1415 +static struct device_attribute bcma_device_attrs[] = {
1416 + __ATTR_RO(manuf),
1417 + __ATTR_RO(id),
1418 + __ATTR_RO(rev),
1419 + __ATTR_RO(class),
1420 + __ATTR_NULL,
1421 +};
1422 +
1423 +static struct bus_type bcma_bus_type = {
1424 + .name = "bcma",
1425 + .match = bcma_bus_match,
1426 + .probe = bcma_device_probe,
1427 + .remove = bcma_device_remove,
1428 + .uevent = bcma_device_uevent,
1429 + .dev_attrs = bcma_device_attrs,
1430 +};
1431 +
1432 +static struct bcma_device *bcma_find_core(struct bcma_bus *bus, u16 coreid)
1433 +{
1434 + struct bcma_device *core;
1435 +
1436 + list_for_each_entry(core, &bus->cores, list) {
1437 + if (core->id.id == coreid)
1438 + return core;
1439 + }
1440 + return NULL;
1441 +}
1442 +
1443 +static void bcma_release_core_dev(struct device *dev)
1444 +{
1445 + struct bcma_device *core = container_of(dev, struct bcma_device, dev);
1446 + if (core->io_addr)
1447 + iounmap(core->io_addr);
1448 + if (core->io_wrap)
1449 + iounmap(core->io_wrap);
1450 + kfree(core);
1451 +}
1452 +
1453 +static int bcma_register_cores(struct bcma_bus *bus)
1454 +{
1455 + struct bcma_device *core;
1456 + int err, dev_id = 0;
1457 +
1458 + list_for_each_entry(core, &bus->cores, list) {
1459 + /* We support that cores ourself */
1460 + switch (core->id.id) {
1461 + case BCMA_CORE_CHIPCOMMON:
1462 + case BCMA_CORE_PCI:
1463 + case BCMA_CORE_PCIE:
1464 + case BCMA_CORE_MIPS_74K:
1465 + continue;
1466 + }
1467 +
1468 + core->dev.release = bcma_release_core_dev;
1469 + core->dev.bus = &bcma_bus_type;
1470 + dev_set_name(&core->dev, "bcma%d:%d", 0/*bus->num*/, dev_id);
1471 +
1472 + switch (bus->hosttype) {
1473 + case BCMA_HOSTTYPE_PCI:
1474 + core->dev.parent = &bus->host_pci->dev;
1475 + core->dma_dev = &bus->host_pci->dev;
1476 + core->irq = bus->host_pci->irq;
1477 + break;
1478 + case BCMA_HOSTTYPE_SOC:
1479 + core->dev.dma_mask = &core->dev.coherent_dma_mask;
1480 + core->dma_dev = &core->dev;
1481 + break;
1482 + case BCMA_HOSTTYPE_SDIO:
1483 + break;
1484 + }
1485 +
1486 + err = device_register(&core->dev);
1487 + if (err) {
1488 + pr_err("Could not register dev for core 0x%03X\n",
1489 + core->id.id);
1490 + continue;
1491 + }
1492 + core->dev_registered = true;
1493 + dev_id++;
1494 + }
1495 +
1496 + return 0;
1497 +}
1498 +
1499 +static void bcma_unregister_cores(struct bcma_bus *bus)
1500 +{
1501 + struct bcma_device *core;
1502 +
1503 + list_for_each_entry(core, &bus->cores, list) {
1504 + if (core->dev_registered)
1505 + device_unregister(&core->dev);
1506 + }
1507 +}
1508 +
1509 +int bcma_bus_register(struct bcma_bus *bus)
1510 +{
1511 + int err;
1512 + struct bcma_device *core;
1513 +
1514 + /* Scan for devices (cores) */
1515 + err = bcma_bus_scan(bus);
1516 + if (err) {
1517 + pr_err("Failed to scan: %d\n", err);
1518 + return -1;
1519 + }
1520 +
1521 + /* Init CC core */
1522 + core = bcma_find_core(bus, BCMA_CORE_CHIPCOMMON);
1523 + if (core) {
1524 + bus->drv_cc.core = core;
1525 + bcma_core_chipcommon_init(&bus->drv_cc);
1526 + }
1527 +
1528 + /* Init MIPS core */
1529 + core = bcma_find_core(bus, BCMA_CORE_MIPS_74K);
1530 + if (core) {
1531 + bus->drv_mips.core = core;
1532 + bcma_core_mips_init(&bus->drv_mips);
1533 + }
1534 +
1535 + /* Init PCIE core */
1536 + core = bcma_find_core(bus, BCMA_CORE_PCIE);
1537 + if (core) {
1538 + bus->drv_pci.core = core;
1539 + bcma_core_pci_init(&bus->drv_pci);
1540 + }
1541 +
1542 + /* Try to get SPROM */
1543 + err = bcma_sprom_get(bus);
1544 + if (err == -ENOENT) {
1545 + pr_err("No SPROM available\n");
1546 + } else if (err) {
1547 + pr_err("Failed to get SPROM: %d\n", err);
1548 + return -ENOENT;
1549 + }
1550 +
1551 + /* Register found cores */
1552 + bcma_register_cores(bus);
1553 +
1554 + pr_info("Bus registered\n");
1555 +
1556 + return 0;
1557 +}
1558 +
1559 +void bcma_bus_unregister(struct bcma_bus *bus)
1560 +{
1561 + bcma_unregister_cores(bus);
1562 +}
1563 +
1564 +int __init bcma_bus_early_register(struct bcma_bus *bus,
1565 + struct bcma_device *core_cc,
1566 + struct bcma_device *core_mips)
1567 +{
1568 + int err;
1569 + struct bcma_device *core;
1570 + struct bcma_device_id match;
1571 +
1572 + bcma_init_bus(bus);
1573 +
1574 + match.manuf = BCMA_MANUF_BCM;
1575 + match.id = BCMA_CORE_CHIPCOMMON;
1576 + match.class = BCMA_CL_SIM;
1577 + match.rev = BCMA_ANY_REV;
1578 +
1579 + /* Scan for chip common core */
1580 + err = bcma_bus_scan_early(bus, &match, core_cc);
1581 + if (err) {
1582 + pr_err("Failed to scan for common core: %d\n", err);
1583 + return -1;
1584 + }
1585 +
1586 + match.manuf = BCMA_MANUF_MIPS;
1587 + match.id = BCMA_CORE_MIPS_74K;
1588 + match.class = BCMA_CL_SIM;
1589 + match.rev = BCMA_ANY_REV;
1590 +
1591 + /* Scan for mips core */
1592 + err = bcma_bus_scan_early(bus, &match, core_mips);
1593 + if (err) {
1594 + pr_err("Failed to scan for mips core: %d\n", err);
1595 + return -1;
1596 + }
1597 +
1598 + /* Init CC core */
1599 + core = bcma_find_core(bus, BCMA_CORE_CHIPCOMMON);
1600 + if (core) {
1601 + bus->drv_cc.core = core;
1602 + bcma_core_chipcommon_init(&bus->drv_cc);
1603 + }
1604 +
1605 + /* Init MIPS core */
1606 + core = bcma_find_core(bus, BCMA_CORE_MIPS_74K);
1607 + if (core) {
1608 + bus->drv_mips.core = core;
1609 + bcma_core_mips_init(&bus->drv_mips);
1610 + }
1611 +
1612 + pr_info("Early bus registered\n");
1613 +
1614 + return 0;
1615 +}
1616 +
1617 +#ifdef CONFIG_PM
1618 +int bcma_bus_resume(struct bcma_bus *bus)
1619 +{
1620 + struct bcma_device *core;
1621 +
1622 + /* Init CC core */
1623 + core = bcma_find_core(bus, BCMA_CORE_CHIPCOMMON);
1624 + if (core) {
1625 + bus->drv_cc.setup_done = false;
1626 + bcma_core_chipcommon_init(&bus->drv_cc);
1627 + }
1628 +
1629 + return 0;
1630 +}
1631 +#endif
1632 +
1633 +int __bcma_driver_register(struct bcma_driver *drv, struct module *owner)
1634 +{
1635 + drv->drv.name = drv->name;
1636 + drv->drv.bus = &bcma_bus_type;
1637 + drv->drv.owner = owner;
1638 +
1639 + return driver_register(&drv->drv);
1640 +}
1641 +EXPORT_SYMBOL_GPL(__bcma_driver_register);
1642 +
1643 +void bcma_driver_unregister(struct bcma_driver *drv)
1644 +{
1645 + driver_unregister(&drv->drv);
1646 +}
1647 +EXPORT_SYMBOL_GPL(bcma_driver_unregister);
1648 +
1649 +static int bcma_bus_match(struct device *dev, struct device_driver *drv)
1650 +{
1651 + struct bcma_device *core = container_of(dev, struct bcma_device, dev);
1652 + struct bcma_driver *adrv = container_of(drv, struct bcma_driver, drv);
1653 + const struct bcma_device_id *cid = &core->id;
1654 + const struct bcma_device_id *did;
1655 +
1656 + for (did = adrv->id_table; did->manuf || did->id || did->rev; did++) {
1657 + if ((did->manuf == cid->manuf || did->manuf == BCMA_ANY_MANUF) &&
1658 + (did->id == cid->id || did->id == BCMA_ANY_ID) &&
1659 + (did->rev == cid->rev || did->rev == BCMA_ANY_REV) &&
1660 + (did->class == cid->class || did->class == BCMA_ANY_CLASS))
1661 + return 1;
1662 + }
1663 + return 0;
1664 +}
1665 +
1666 +static int bcma_device_probe(struct device *dev)
1667 +{
1668 + struct bcma_device *core = container_of(dev, struct bcma_device, dev);
1669 + struct bcma_driver *adrv = container_of(dev->driver, struct bcma_driver,
1670 + drv);
1671 + int err = 0;
1672 +
1673 + if (adrv->probe)
1674 + err = adrv->probe(core);
1675 +
1676 + return err;
1677 +}
1678 +
1679 +static int bcma_device_remove(struct device *dev)
1680 +{
1681 + struct bcma_device *core = container_of(dev, struct bcma_device, dev);
1682 + struct bcma_driver *adrv = container_of(dev->driver, struct bcma_driver,
1683 + drv);
1684 +
1685 + if (adrv->remove)
1686 + adrv->remove(core);
1687 +
1688 + return 0;
1689 +}
1690 +
1691 +static int bcma_device_uevent(struct device *dev, struct kobj_uevent_env *env)
1692 +{
1693 + struct bcma_device *core = container_of(dev, struct bcma_device, dev);
1694 +
1695 + return add_uevent_var(env,
1696 + "MODALIAS=bcma:m%04Xid%04Xrev%02Xcl%02X",
1697 + core->id.manuf, core->id.id,
1698 + core->id.rev, core->id.class);
1699 +}
1700 +
1701 +static int __init bcma_modinit(void)
1702 +{
1703 + int err;
1704 +
1705 + err = bus_register(&bcma_bus_type);
1706 + if (err)
1707 + return err;
1708 +
1709 +#ifdef CONFIG_BCMA_HOST_PCI
1710 + err = bcma_host_pci_init();
1711 + if (err) {
1712 + pr_err("PCI host initialization failed\n");
1713 + err = 0;
1714 + }
1715 +#endif
1716 +
1717 + return err;
1718 +}
1719 +fs_initcall(bcma_modinit);
1720 +
1721 +static void __exit bcma_modexit(void)
1722 +{
1723 +#ifdef CONFIG_BCMA_HOST_PCI
1724 + bcma_host_pci_exit();
1725 +#endif
1726 + bus_unregister(&bcma_bus_type);
1727 +}
1728 +module_exit(bcma_modexit)
1729 --- /dev/null
1730 +++ b/drivers/bcma/scan.c
1731 @@ -0,0 +1,486 @@
1732 +/*
1733 + * Broadcom specific AMBA
1734 + * Bus scanning
1735 + *
1736 + * Licensed under the GNU/GPL. See COPYING for details.
1737 + */
1738 +
1739 +#include "scan.h"
1740 +#include "bcma_private.h"
1741 +
1742 +#include <linux/bcma/bcma.h>
1743 +#include <linux/bcma/bcma_regs.h>
1744 +#include <linux/pci.h>
1745 +#include <linux/io.h>
1746 +#include <linux/dma-mapping.h>
1747 +#include <linux/slab.h>
1748 +
1749 +struct bcma_device_id_name {
1750 + u16 id;
1751 + const char *name;
1752 +};
1753 +struct bcma_device_id_name bcma_device_names[] = {
1754 + { BCMA_CORE_OOB_ROUTER, "OOB Router" },
1755 + { BCMA_CORE_INVALID, "Invalid" },
1756 + { BCMA_CORE_CHIPCOMMON, "ChipCommon" },
1757 + { BCMA_CORE_ILINE20, "ILine 20" },
1758 + { BCMA_CORE_SRAM, "SRAM" },
1759 + { BCMA_CORE_SDRAM, "SDRAM" },
1760 + { BCMA_CORE_PCI, "PCI" },
1761 + { BCMA_CORE_MIPS, "MIPS" },
1762 + { BCMA_CORE_ETHERNET, "Fast Ethernet" },
1763 + { BCMA_CORE_V90, "V90" },
1764 + { BCMA_CORE_USB11_HOSTDEV, "USB 1.1 Hostdev" },
1765 + { BCMA_CORE_ADSL, "ADSL" },
1766 + { BCMA_CORE_ILINE100, "ILine 100" },
1767 + { BCMA_CORE_IPSEC, "IPSEC" },
1768 + { BCMA_CORE_UTOPIA, "UTOPIA" },
1769 + { BCMA_CORE_PCMCIA, "PCMCIA" },
1770 + { BCMA_CORE_INTERNAL_MEM, "Internal Memory" },
1771 + { BCMA_CORE_MEMC_SDRAM, "MEMC SDRAM" },
1772 + { BCMA_CORE_OFDM, "OFDM" },
1773 + { BCMA_CORE_EXTIF, "EXTIF" },
1774 + { BCMA_CORE_80211, "IEEE 802.11" },
1775 + { BCMA_CORE_PHY_A, "PHY A" },
1776 + { BCMA_CORE_PHY_B, "PHY B" },
1777 + { BCMA_CORE_PHY_G, "PHY G" },
1778 + { BCMA_CORE_MIPS_3302, "MIPS 3302" },
1779 + { BCMA_CORE_USB11_HOST, "USB 1.1 Host" },
1780 + { BCMA_CORE_USB11_DEV, "USB 1.1 Device" },
1781 + { BCMA_CORE_USB20_HOST, "USB 2.0 Host" },
1782 + { BCMA_CORE_USB20_DEV, "USB 2.0 Device" },
1783 + { BCMA_CORE_SDIO_HOST, "SDIO Host" },
1784 + { BCMA_CORE_ROBOSWITCH, "Roboswitch" },
1785 + { BCMA_CORE_PARA_ATA, "PATA" },
1786 + { BCMA_CORE_SATA_XORDMA, "SATA XOR-DMA" },
1787 + { BCMA_CORE_ETHERNET_GBIT, "GBit Ethernet" },
1788 + { BCMA_CORE_PCIE, "PCIe" },
1789 + { BCMA_CORE_PHY_N, "PHY N" },
1790 + { BCMA_CORE_SRAM_CTL, "SRAM Controller" },
1791 + { BCMA_CORE_MINI_MACPHY, "Mini MACPHY" },
1792 + { BCMA_CORE_ARM_1176, "ARM 1176" },
1793 + { BCMA_CORE_ARM_7TDMI, "ARM 7TDMI" },
1794 + { BCMA_CORE_PHY_LP, "PHY LP" },
1795 + { BCMA_CORE_PMU, "PMU" },
1796 + { BCMA_CORE_PHY_SSN, "PHY SSN" },
1797 + { BCMA_CORE_SDIO_DEV, "SDIO Device" },
1798 + { BCMA_CORE_ARM_CM3, "ARM CM3" },
1799 + { BCMA_CORE_PHY_HT, "PHY HT" },
1800 + { BCMA_CORE_MIPS_74K, "MIPS 74K" },
1801 + { BCMA_CORE_MAC_GBIT, "GBit MAC" },
1802 + { BCMA_CORE_DDR12_MEM_CTL, "DDR1/DDR2 Memory Controller" },
1803 + { BCMA_CORE_PCIE_RC, "PCIe Root Complex" },
1804 + { BCMA_CORE_OCP_OCP_BRIDGE, "OCP to OCP Bridge" },
1805 + { BCMA_CORE_SHARED_COMMON, "Common Shared" },
1806 + { BCMA_CORE_OCP_AHB_BRIDGE, "OCP to AHB Bridge" },
1807 + { BCMA_CORE_SPI_HOST, "SPI Host" },
1808 + { BCMA_CORE_I2S, "I2S" },
1809 + { BCMA_CORE_SDR_DDR1_MEM_CTL, "SDR/DDR1 Memory Controller" },
1810 + { BCMA_CORE_SHIM, "SHIM" },
1811 + { BCMA_CORE_DEFAULT, "Default" },
1812 +};
1813 +const char *bcma_device_name(struct bcma_device_id *id)
1814 +{
1815 + int i;
1816 +
1817 + if (id->manuf == BCMA_MANUF_BCM) {
1818 + for (i = 0; i < ARRAY_SIZE(bcma_device_names); i++) {
1819 + if (bcma_device_names[i].id == id->id)
1820 + return bcma_device_names[i].name;
1821 + }
1822 + }
1823 + return "UNKNOWN";
1824 +}
1825 +
1826 +static u32 bcma_scan_read32(struct bcma_bus *bus, u8 current_coreidx,
1827 + u16 offset)
1828 +{
1829 + return readl(bus->mmio + offset);
1830 +}
1831 +
1832 +static void bcma_scan_switch_core(struct bcma_bus *bus, u32 addr)
1833 +{
1834 + if (bus->hosttype == BCMA_HOSTTYPE_PCI)
1835 + pci_write_config_dword(bus->host_pci, BCMA_PCI_BAR0_WIN,
1836 + addr);
1837 +}
1838 +
1839 +static u32 bcma_erom_get_ent(struct bcma_bus *bus, u32 **eromptr)
1840 +{
1841 + u32 ent = readl(*eromptr);
1842 + (*eromptr)++;
1843 + return ent;
1844 +}
1845 +
1846 +static void bcma_erom_push_ent(u32 **eromptr)
1847 +{
1848 + (*eromptr)--;
1849 +}
1850 +
1851 +static s32 bcma_erom_get_ci(struct bcma_bus *bus, u32 **eromptr)
1852 +{
1853 + u32 ent = bcma_erom_get_ent(bus, eromptr);
1854 + if (!(ent & SCAN_ER_VALID))
1855 + return -ENOENT;
1856 + if ((ent & SCAN_ER_TAG) != SCAN_ER_TAG_CI)
1857 + return -ENOENT;
1858 + return ent;
1859 +}
1860 +
1861 +static bool bcma_erom_is_end(struct bcma_bus *bus, u32 **eromptr)
1862 +{
1863 + u32 ent = bcma_erom_get_ent(bus, eromptr);
1864 + bcma_erom_push_ent(eromptr);
1865 + return (ent == (SCAN_ER_TAG_END | SCAN_ER_VALID));
1866 +}
1867 +
1868 +static bool bcma_erom_is_bridge(struct bcma_bus *bus, u32 **eromptr)
1869 +{
1870 + u32 ent = bcma_erom_get_ent(bus, eromptr);
1871 + bcma_erom_push_ent(eromptr);
1872 + return (((ent & SCAN_ER_VALID)) &&
1873 + ((ent & SCAN_ER_TAGX) == SCAN_ER_TAG_ADDR) &&
1874 + ((ent & SCAN_ADDR_TYPE) == SCAN_ADDR_TYPE_BRIDGE));
1875 +}
1876 +
1877 +static void bcma_erom_skip_component(struct bcma_bus *bus, u32 **eromptr)
1878 +{
1879 + u32 ent;
1880 + while (1) {
1881 + ent = bcma_erom_get_ent(bus, eromptr);
1882 + if ((ent & SCAN_ER_VALID) &&
1883 + ((ent & SCAN_ER_TAG) == SCAN_ER_TAG_CI))
1884 + break;
1885 + if (ent == (SCAN_ER_TAG_END | SCAN_ER_VALID))
1886 + break;
1887 + }
1888 + bcma_erom_push_ent(eromptr);
1889 +}
1890 +
1891 +static s32 bcma_erom_get_mst_port(struct bcma_bus *bus, u32 **eromptr)
1892 +{
1893 + u32 ent = bcma_erom_get_ent(bus, eromptr);
1894 + if (!(ent & SCAN_ER_VALID))
1895 + return -ENOENT;
1896 + if ((ent & SCAN_ER_TAG) != SCAN_ER_TAG_MP)
1897 + return -ENOENT;
1898 + return ent;
1899 +}
1900 +
1901 +static s32 bcma_erom_get_addr_desc(struct bcma_bus *bus, u32 **eromptr,
1902 + u32 type, u8 port)
1903 +{
1904 + u32 addrl, addrh, sizel, sizeh = 0;
1905 + u32 size;
1906 +
1907 + u32 ent = bcma_erom_get_ent(bus, eromptr);
1908 + if ((!(ent & SCAN_ER_VALID)) ||
1909 + ((ent & SCAN_ER_TAGX) != SCAN_ER_TAG_ADDR) ||
1910 + ((ent & SCAN_ADDR_TYPE) != type) ||
1911 + (((ent & SCAN_ADDR_PORT) >> SCAN_ADDR_PORT_SHIFT) != port)) {
1912 + bcma_erom_push_ent(eromptr);
1913 + return -EINVAL;
1914 + }
1915 +
1916 + addrl = ent & SCAN_ADDR_ADDR;
1917 + if (ent & SCAN_ADDR_AG32)
1918 + addrh = bcma_erom_get_ent(bus, eromptr);
1919 + else
1920 + addrh = 0;
1921 +
1922 + if ((ent & SCAN_ADDR_SZ) == SCAN_ADDR_SZ_SZD) {
1923 + size = bcma_erom_get_ent(bus, eromptr);
1924 + sizel = size & SCAN_SIZE_SZ;
1925 + if (size & SCAN_SIZE_SG32)
1926 + sizeh = bcma_erom_get_ent(bus, eromptr);
1927 + } else
1928 + sizel = SCAN_ADDR_SZ_BASE <<
1929 + ((ent & SCAN_ADDR_SZ) >> SCAN_ADDR_SZ_SHIFT);
1930 +
1931 + return addrl;
1932 +}
1933 +
1934 +static struct bcma_device *bcma_find_core_by_index(struct bcma_bus *bus,
1935 + u16 index)
1936 +{
1937 + struct bcma_device *core;
1938 +
1939 + list_for_each_entry(core, &bus->cores, list) {
1940 + if (core->core_index == index)
1941 + return core;
1942 + }
1943 + return NULL;
1944 +}
1945 +
1946 +static int bcma_get_next_core(struct bcma_bus *bus, u32 __iomem **eromptr,
1947 + struct bcma_device_id *match, int core_num,
1948 + struct bcma_device *core)
1949 +{
1950 + s32 tmp;
1951 + u8 i, j;
1952 + s32 cia, cib;
1953 + u8 ports[2], wrappers[2];
1954 +
1955 + /* get CIs */
1956 + cia = bcma_erom_get_ci(bus, eromptr);
1957 + if (cia < 0) {
1958 + bcma_erom_push_ent(eromptr);
1959 + if (bcma_erom_is_end(bus, eromptr))
1960 + return -ESPIPE;
1961 + return -EILSEQ;
1962 + }
1963 + cib = bcma_erom_get_ci(bus, eromptr);
1964 + if (cib < 0)
1965 + return -EILSEQ;
1966 +
1967 + /* parse CIs */
1968 + core->id.class = (cia & SCAN_CIA_CLASS) >> SCAN_CIA_CLASS_SHIFT;
1969 + core->id.id = (cia & SCAN_CIA_ID) >> SCAN_CIA_ID_SHIFT;
1970 + core->id.manuf = (cia & SCAN_CIA_MANUF) >> SCAN_CIA_MANUF_SHIFT;
1971 + ports[0] = (cib & SCAN_CIB_NMP) >> SCAN_CIB_NMP_SHIFT;
1972 + ports[1] = (cib & SCAN_CIB_NSP) >> SCAN_CIB_NSP_SHIFT;
1973 + wrappers[0] = (cib & SCAN_CIB_NMW) >> SCAN_CIB_NMW_SHIFT;
1974 + wrappers[1] = (cib & SCAN_CIB_NSW) >> SCAN_CIB_NSW_SHIFT;
1975 + core->id.rev = (cib & SCAN_CIB_REV) >> SCAN_CIB_REV_SHIFT;
1976 +
1977 + if (((core->id.manuf == BCMA_MANUF_ARM) &&
1978 + (core->id.id == 0xFFF)) ||
1979 + (ports[1] == 0)) {
1980 + bcma_erom_skip_component(bus, eromptr);
1981 + return -ENXIO;
1982 + }
1983 +
1984 + /* check if component is a core at all */
1985 + if (wrappers[0] + wrappers[1] == 0) {
1986 + /* we could save addrl of the router
1987 + if (cid == BCMA_CORE_OOB_ROUTER)
1988 + */
1989 + bcma_erom_skip_component(bus, eromptr);
1990 + return -ENXIO;
1991 + }
1992 +
1993 + if (bcma_erom_is_bridge(bus, eromptr)) {
1994 + bcma_erom_skip_component(bus, eromptr);
1995 + return -ENXIO;
1996 + }
1997 +
1998 + if (bcma_find_core_by_index(bus, core_num)) {
1999 + bcma_erom_skip_component(bus, eromptr);
2000 + return -ENODEV;
2001 + }
2002 +
2003 + if (match && ((match->manuf != BCMA_ANY_MANUF &&
2004 + match->manuf != core->id.manuf) ||
2005 + (match->id != BCMA_ANY_ID && match->id != core->id.id) ||
2006 + (match->rev != BCMA_ANY_REV && match->rev != core->id.rev) ||
2007 + (match->class != BCMA_ANY_CLASS && match->class != core->id.class)
2008 + )) {
2009 + bcma_erom_skip_component(bus, eromptr);
2010 + return -ENODEV;
2011 + }
2012 +
2013 + /* get & parse master ports */
2014 + for (i = 0; i < ports[0]; i++) {
2015 + s32 mst_port_d = bcma_erom_get_mst_port(bus, eromptr);
2016 + if (mst_port_d < 0)
2017 + return -EILSEQ;
2018 + }
2019 +
2020 + /* get & parse slave ports */
2021 + for (i = 0; i < ports[1]; i++) {
2022 + for (j = 0; ; j++) {
2023 + tmp = bcma_erom_get_addr_desc(bus, eromptr,
2024 + SCAN_ADDR_TYPE_SLAVE, i);
2025 + if (tmp < 0) {
2026 + /* no more entries for port _i_ */
2027 + /* pr_debug("erom: slave port %d "
2028 + * "has %d descriptors\n", i, j); */
2029 + break;
2030 + } else {
2031 + if (i == 0 && j == 0)
2032 + core->addr = tmp;
2033 + }
2034 + }
2035 + }
2036 +
2037 + /* get & parse master wrappers */
2038 + for (i = 0; i < wrappers[0]; i++) {
2039 + for (j = 0; ; j++) {
2040 + tmp = bcma_erom_get_addr_desc(bus, eromptr,
2041 + SCAN_ADDR_TYPE_MWRAP, i);
2042 + if (tmp < 0) {
2043 + /* no more entries for port _i_ */
2044 + /* pr_debug("erom: master wrapper %d "
2045 + * "has %d descriptors\n", i, j); */
2046 + break;
2047 + } else {
2048 + if (i == 0 && j == 0)
2049 + core->wrap = tmp;
2050 + }
2051 + }
2052 + }
2053 +
2054 + /* get & parse slave wrappers */
2055 + for (i = 0; i < wrappers[1]; i++) {
2056 + u8 hack = (ports[1] == 1) ? 0 : 1;
2057 + for (j = 0; ; j++) {
2058 + tmp = bcma_erom_get_addr_desc(bus, eromptr,
2059 + SCAN_ADDR_TYPE_SWRAP, i + hack);
2060 + if (tmp < 0) {
2061 + /* no more entries for port _i_ */
2062 + /* pr_debug("erom: master wrapper %d "
2063 + * has %d descriptors\n", i, j); */
2064 + break;
2065 + } else {
2066 + if (wrappers[0] == 0 && !i && !j)
2067 + core->wrap = tmp;
2068 + }
2069 + }
2070 + }
2071 + if (bus->hosttype == BCMA_HOSTTYPE_SOC) {
2072 + core->io_addr = ioremap_nocache(core->addr, BCMA_CORE_SIZE);
2073 + if (!core->io_addr)
2074 + return -ENOMEM;
2075 + core->io_wrap = ioremap_nocache(core->wrap, BCMA_CORE_SIZE);
2076 + if (!core->io_wrap) {
2077 + iounmap(core->io_addr);
2078 + return -ENOMEM;
2079 + }
2080 + }
2081 + return 0;
2082 +}
2083 +
2084 +void bcma_init_bus(struct bcma_bus *bus)
2085 +{
2086 + s32 tmp;
2087 +
2088 + if (bus->init_done)
2089 + return;
2090 +
2091 + INIT_LIST_HEAD(&bus->cores);
2092 + bus->nr_cores = 0;
2093 +
2094 + bcma_scan_switch_core(bus, BCMA_ADDR_BASE);
2095 +
2096 + tmp = bcma_scan_read32(bus, 0, BCMA_CC_ID);
2097 + bus->chipinfo.id = (tmp & BCMA_CC_ID_ID) >> BCMA_CC_ID_ID_SHIFT;
2098 + bus->chipinfo.rev = (tmp & BCMA_CC_ID_REV) >> BCMA_CC_ID_REV_SHIFT;
2099 + bus->chipinfo.pkg = (tmp & BCMA_CC_ID_PKG) >> BCMA_CC_ID_PKG_SHIFT;
2100 + bus->init_done = true;
2101 +}
2102 +
2103 +int bcma_bus_scan(struct bcma_bus *bus)
2104 +{
2105 + u32 erombase;
2106 + u32 __iomem *eromptr, *eromend;
2107 +
2108 + int err, core_num = 0;
2109 +
2110 + bcma_init_bus(bus);
2111 +
2112 + erombase = bcma_scan_read32(bus, 0, BCMA_CC_EROM);
2113 + if (bus->hosttype == BCMA_HOSTTYPE_SOC) {
2114 + eromptr = ioremap_nocache(erombase, BCMA_CORE_SIZE);
2115 + if (!eromptr)
2116 + return -ENOMEM;
2117 + } else {
2118 + eromptr = bus->mmio;
2119 + }
2120 +
2121 + eromend = eromptr + BCMA_CORE_SIZE / sizeof(u32);
2122 +
2123 + bcma_scan_switch_core(bus, erombase);
2124 +
2125 + while (eromptr < eromend) {
2126 + struct bcma_device *core = kzalloc(sizeof(*core), GFP_KERNEL);
2127 + if (!core)
2128 + return -ENOMEM;
2129 + INIT_LIST_HEAD(&core->list);
2130 + core->bus = bus;
2131 +
2132 + err = bcma_get_next_core(bus, &eromptr, NULL, core_num, core);
2133 + if (err == -ENODEV) {
2134 + core_num++;
2135 + continue;
2136 + } else if (err == -ENXIO)
2137 + continue;
2138 + else if (err == -ESPIPE)
2139 + break;
2140 + else if (err < 0)
2141 + return err;
2142 +
2143 + core->core_index = core_num++;
2144 + bus->nr_cores++;
2145 +
2146 + pr_info("Core %d found: %s "
2147 + "(manuf 0x%03X, id 0x%03X, rev 0x%02X, class 0x%X)\n",
2148 + core->core_index, bcma_device_name(&core->id),
2149 + core->id.manuf, core->id.id, core->id.rev,
2150 + core->id.class);
2151 +
2152 + list_add(&core->list, &bus->cores);
2153 + }
2154 +
2155 + if (bus->hosttype == BCMA_HOSTTYPE_SOC)
2156 + iounmap(eromptr);
2157 +
2158 + return 0;
2159 +}
2160 +
2161 +int __init bcma_bus_scan_early(struct bcma_bus *bus,
2162 + struct bcma_device_id *match,
2163 + struct bcma_device *core)
2164 +{
2165 + u32 erombase;
2166 + u32 __iomem *eromptr, *eromend;
2167 +
2168 + int err = -ENODEV;
2169 + int core_num = 0;
2170 +
2171 + erombase = bcma_scan_read32(bus, 0, BCMA_CC_EROM);
2172 + if (bus->hosttype == BCMA_HOSTTYPE_SOC) {
2173 + eromptr = ioremap_nocache(erombase, BCMA_CORE_SIZE);
2174 + if (!eromptr)
2175 + return -ENOMEM;
2176 + } else {
2177 + eromptr = bus->mmio;
2178 + }
2179 +
2180 + eromend = eromptr + BCMA_CORE_SIZE / sizeof(u32);
2181 +
2182 + bcma_scan_switch_core(bus, erombase);
2183 +
2184 + while (eromptr < eromend) {
2185 + memset(core, 0, sizeof(*core));
2186 + INIT_LIST_HEAD(&core->list);
2187 + core->bus = bus;
2188 +
2189 + err = bcma_get_next_core(bus, &eromptr, match, core_num, core);
2190 + if (err == -ENODEV) {
2191 + core_num++;
2192 + continue;
2193 + } else if (err == -ENXIO)
2194 + continue;
2195 + else if (err == -ESPIPE)
2196 + break;
2197 + else if (err < 0)
2198 + return err;
2199 +
2200 + core->core_index = core_num++;
2201 + bus->nr_cores++;
2202 + pr_info("Core %d found: %s "
2203 + "(manuf 0x%03X, id 0x%03X, rev 0x%02X, class 0x%X)\n",
2204 + core->core_index, bcma_device_name(&core->id),
2205 + core->id.manuf, core->id.id, core->id.rev,
2206 + core->id.class);
2207 +
2208 + list_add(&core->list, &bus->cores);
2209 + err = 0;
2210 + break;
2211 + }
2212 +
2213 + if (bus->hosttype == BCMA_HOSTTYPE_SOC)
2214 + iounmap(eromptr);
2215 +
2216 + return err;
2217 +}
2218 --- /dev/null
2219 +++ b/drivers/bcma/scan.h
2220 @@ -0,0 +1,56 @@
2221 +#ifndef BCMA_SCAN_H_
2222 +#define BCMA_SCAN_H_
2223 +
2224 +#define BCMA_ADDR_BASE 0x18000000
2225 +#define BCMA_WRAP_BASE 0x18100000
2226 +
2227 +#define SCAN_ER_VALID 0x00000001
2228 +#define SCAN_ER_TAGX 0x00000006 /* we have to ignore 0x8 bit when checking tag for SCAN_ER_TAG_ADDR */
2229 +#define SCAN_ER_TAG 0x0000000E
2230 +#define SCAN_ER_TAG_CI 0x00000000
2231 +#define SCAN_ER_TAG_MP 0x00000002
2232 +#define SCAN_ER_TAG_ADDR 0x00000004
2233 +#define SCAN_ER_TAG_END 0x0000000E
2234 +#define SCAN_ER_BAD 0xFFFFFFFF
2235 +
2236 +#define SCAN_CIA_CLASS 0x000000F0
2237 +#define SCAN_CIA_CLASS_SHIFT 4
2238 +#define SCAN_CIA_ID 0x000FFF00
2239 +#define SCAN_CIA_ID_SHIFT 8
2240 +#define SCAN_CIA_MANUF 0xFFF00000
2241 +#define SCAN_CIA_MANUF_SHIFT 20
2242 +
2243 +#define SCAN_CIB_NMP 0x000001F0
2244 +#define SCAN_CIB_NMP_SHIFT 4
2245 +#define SCAN_CIB_NSP 0x00003E00
2246 +#define SCAN_CIB_NSP_SHIFT 9
2247 +#define SCAN_CIB_NMW 0x0007C000
2248 +#define SCAN_CIB_NMW_SHIFT 14
2249 +#define SCAN_CIB_NSW 0x00F80000
2250 +#define SCAN_CIB_NSW_SHIFT 17
2251 +#define SCAN_CIB_REV 0xFF000000
2252 +#define SCAN_CIB_REV_SHIFT 24
2253 +
2254 +#define SCAN_ADDR_AG32 0x00000008
2255 +#define SCAN_ADDR_SZ 0x00000030
2256 +#define SCAN_ADDR_SZ_SHIFT 4
2257 +#define SCAN_ADDR_SZ_4K 0x00000000
2258 +#define SCAN_ADDR_SZ_8K 0x00000010
2259 +#define SCAN_ADDR_SZ_16K 0x00000020
2260 +#define SCAN_ADDR_SZ_SZD 0x00000030
2261 +#define SCAN_ADDR_TYPE 0x000000C0
2262 +#define SCAN_ADDR_TYPE_SLAVE 0x00000000
2263 +#define SCAN_ADDR_TYPE_BRIDGE 0x00000040
2264 +#define SCAN_ADDR_TYPE_SWRAP 0x00000080
2265 +#define SCAN_ADDR_TYPE_MWRAP 0x000000C0
2266 +#define SCAN_ADDR_PORT 0x00000F00
2267 +#define SCAN_ADDR_PORT_SHIFT 8
2268 +#define SCAN_ADDR_ADDR 0xFFFFF000
2269 +
2270 +#define SCAN_ADDR_SZ_BASE 0x00001000 /* 4KB */
2271 +
2272 +#define SCAN_SIZE_SZ_ALIGN 0x00000FFF
2273 +#define SCAN_SIZE_SZ 0xFFFFF000
2274 +#define SCAN_SIZE_SG32 0x00000008
2275 +
2276 +#endif /* BCMA_SCAN_H_ */
2277 --- /dev/null
2278 +++ b/include/linux/bcma/bcma.h
2279 @@ -0,0 +1,298 @@
2280 +#ifndef LINUX_BCMA_H_
2281 +#define LINUX_BCMA_H_
2282 +
2283 +#include <linux/pci.h>
2284 +#include <linux/mod_devicetable.h>
2285 +
2286 +#include <linux/bcma/bcma_driver_chipcommon.h>
2287 +#include <linux/bcma/bcma_driver_pci.h>
2288 +#include <linux/bcma/bcma_driver_mips.h>
2289 +#include <linux/ssb/ssb.h> /* SPROM sharing */
2290 +
2291 +#include "bcma_regs.h"
2292 +
2293 +struct bcma_device;
2294 +struct bcma_bus;
2295 +
2296 +enum bcma_hosttype {
2297 + BCMA_HOSTTYPE_PCI,
2298 + BCMA_HOSTTYPE_SDIO,
2299 + BCMA_HOSTTYPE_SOC,
2300 +};
2301 +
2302 +struct bcma_chipinfo {
2303 + u16 id;
2304 + u8 rev;
2305 + u8 pkg;
2306 +};
2307 +
2308 +enum bcma_clkmode {
2309 + BCMA_CLKMODE_FAST,
2310 + BCMA_CLKMODE_DYNAMIC,
2311 +};
2312 +
2313 +struct bcma_host_ops {
2314 + u8 (*read8)(struct bcma_device *core, u16 offset);
2315 + u16 (*read16)(struct bcma_device *core, u16 offset);
2316 + u32 (*read32)(struct bcma_device *core, u16 offset);
2317 + void (*write8)(struct bcma_device *core, u16 offset, u8 value);
2318 + void (*write16)(struct bcma_device *core, u16 offset, u16 value);
2319 + void (*write32)(struct bcma_device *core, u16 offset, u32 value);
2320 +#ifdef CONFIG_BCMA_BLOCKIO
2321 + void (*block_read)(struct bcma_device *core, void *buffer,
2322 + size_t count, u16 offset, u8 reg_width);
2323 + void (*block_write)(struct bcma_device *core, const void *buffer,
2324 + size_t count, u16 offset, u8 reg_width);
2325 +#endif
2326 + /* Agent ops */
2327 + u32 (*aread32)(struct bcma_device *core, u16 offset);
2328 + void (*awrite32)(struct bcma_device *core, u16 offset, u32 value);
2329 +};
2330 +
2331 +/* Core manufacturers */
2332 +#define BCMA_MANUF_ARM 0x43B
2333 +#define BCMA_MANUF_MIPS 0x4A7
2334 +#define BCMA_MANUF_BCM 0x4BF
2335 +
2336 +/* Core class values. */
2337 +#define BCMA_CL_SIM 0x0
2338 +#define BCMA_CL_EROM 0x1
2339 +#define BCMA_CL_CORESIGHT 0x9
2340 +#define BCMA_CL_VERIF 0xB
2341 +#define BCMA_CL_OPTIMO 0xD
2342 +#define BCMA_CL_GEN 0xE
2343 +#define BCMA_CL_PRIMECELL 0xF
2344 +
2345 +/* Core-ID values. */
2346 +#define BCMA_CORE_OOB_ROUTER 0x367 /* Out of band */
2347 +#define BCMA_CORE_INVALID 0x700
2348 +#define BCMA_CORE_CHIPCOMMON 0x800
2349 +#define BCMA_CORE_ILINE20 0x801
2350 +#define BCMA_CORE_SRAM 0x802
2351 +#define BCMA_CORE_SDRAM 0x803
2352 +#define BCMA_CORE_PCI 0x804
2353 +#define BCMA_CORE_MIPS 0x805
2354 +#define BCMA_CORE_ETHERNET 0x806
2355 +#define BCMA_CORE_V90 0x807
2356 +#define BCMA_CORE_USB11_HOSTDEV 0x808
2357 +#define BCMA_CORE_ADSL 0x809
2358 +#define BCMA_CORE_ILINE100 0x80A
2359 +#define BCMA_CORE_IPSEC 0x80B
2360 +#define BCMA_CORE_UTOPIA 0x80C
2361 +#define BCMA_CORE_PCMCIA 0x80D
2362 +#define BCMA_CORE_INTERNAL_MEM 0x80E
2363 +#define BCMA_CORE_MEMC_SDRAM 0x80F
2364 +#define BCMA_CORE_OFDM 0x810
2365 +#define BCMA_CORE_EXTIF 0x811
2366 +#define BCMA_CORE_80211 0x812
2367 +#define BCMA_CORE_PHY_A 0x813
2368 +#define BCMA_CORE_PHY_B 0x814
2369 +#define BCMA_CORE_PHY_G 0x815
2370 +#define BCMA_CORE_MIPS_3302 0x816
2371 +#define BCMA_CORE_USB11_HOST 0x817
2372 +#define BCMA_CORE_USB11_DEV 0x818
2373 +#define BCMA_CORE_USB20_HOST 0x819
2374 +#define BCMA_CORE_USB20_DEV 0x81A
2375 +#define BCMA_CORE_SDIO_HOST 0x81B
2376 +#define BCMA_CORE_ROBOSWITCH 0x81C
2377 +#define BCMA_CORE_PARA_ATA 0x81D
2378 +#define BCMA_CORE_SATA_XORDMA 0x81E
2379 +#define BCMA_CORE_ETHERNET_GBIT 0x81F
2380 +#define BCMA_CORE_PCIE 0x820
2381 +#define BCMA_CORE_PHY_N 0x821
2382 +#define BCMA_CORE_SRAM_CTL 0x822
2383 +#define BCMA_CORE_MINI_MACPHY 0x823
2384 +#define BCMA_CORE_ARM_1176 0x824
2385 +#define BCMA_CORE_ARM_7TDMI 0x825
2386 +#define BCMA_CORE_PHY_LP 0x826
2387 +#define BCMA_CORE_PMU 0x827
2388 +#define BCMA_CORE_PHY_SSN 0x828
2389 +#define BCMA_CORE_SDIO_DEV 0x829
2390 +#define BCMA_CORE_ARM_CM3 0x82A
2391 +#define BCMA_CORE_PHY_HT 0x82B
2392 +#define BCMA_CORE_MIPS_74K 0x82C
2393 +#define BCMA_CORE_MAC_GBIT 0x82D
2394 +#define BCMA_CORE_DDR12_MEM_CTL 0x82E
2395 +#define BCMA_CORE_PCIE_RC 0x82F /* PCIe Root Complex */
2396 +#define BCMA_CORE_OCP_OCP_BRIDGE 0x830
2397 +#define BCMA_CORE_SHARED_COMMON 0x831
2398 +#define BCMA_CORE_OCP_AHB_BRIDGE 0x832
2399 +#define BCMA_CORE_SPI_HOST 0x833
2400 +#define BCMA_CORE_I2S 0x834
2401 +#define BCMA_CORE_SDR_DDR1_MEM_CTL 0x835 /* SDR/DDR1 memory controller core */
2402 +#define BCMA_CORE_SHIM 0x837 /* SHIM component in ubus/6362 */
2403 +#define BCMA_CORE_DEFAULT 0xFFF
2404 +
2405 +#define BCMA_MAX_NR_CORES 16
2406 +
2407 +struct bcma_device {
2408 + struct bcma_bus *bus;
2409 + struct bcma_device_id id;
2410 +
2411 + struct device dev;
2412 + struct device *dma_dev;
2413 +
2414 + unsigned int irq;
2415 + bool dev_registered;
2416 +
2417 + u8 core_index;
2418 +
2419 + u32 addr;
2420 + u32 wrap;
2421 +
2422 + void __iomem *io_addr;
2423 + void __iomem *io_wrap;
2424 +
2425 + void *drvdata;
2426 + struct list_head list;
2427 +};
2428 +
2429 +static inline void *bcma_get_drvdata(struct bcma_device *core)
2430 +{
2431 + return core->drvdata;
2432 +}
2433 +static inline void bcma_set_drvdata(struct bcma_device *core, void *drvdata)
2434 +{
2435 + core->drvdata = drvdata;
2436 +}
2437 +
2438 +struct bcma_driver {
2439 + const char *name;
2440 + const struct bcma_device_id *id_table;
2441 +
2442 + int (*probe)(struct bcma_device *dev);
2443 + void (*remove)(struct bcma_device *dev);
2444 + int (*suspend)(struct bcma_device *dev, pm_message_t state);
2445 + int (*resume)(struct bcma_device *dev);
2446 + void (*shutdown)(struct bcma_device *dev);
2447 +
2448 + struct device_driver drv;
2449 +};
2450 +extern
2451 +int __bcma_driver_register(struct bcma_driver *drv, struct module *owner);
2452 +#define bcma_driver_register(drv) \
2453 + __bcma_driver_register(drv, THIS_MODULE)
2454 +
2455 +extern void bcma_driver_unregister(struct bcma_driver *drv);
2456 +
2457 +struct bcma_bus {
2458 + /* The MMIO area. */
2459 + void __iomem *mmio;
2460 +
2461 + const struct bcma_host_ops *ops;
2462 +
2463 + enum bcma_hosttype hosttype;
2464 + union {
2465 + /* Pointer to the PCI bus (only for BCMA_HOSTTYPE_PCI) */
2466 + struct pci_dev *host_pci;
2467 + /* Pointer to the SDIO device (only for BCMA_HOSTTYPE_SDIO) */
2468 + struct sdio_func *host_sdio;
2469 + };
2470 +
2471 + struct bcma_chipinfo chipinfo;
2472 +
2473 + struct bcma_device *mapped_core;
2474 + struct list_head cores;
2475 + u8 nr_cores;
2476 + u8 init_done:1;
2477 +
2478 + struct bcma_drv_cc drv_cc;
2479 + struct bcma_drv_pci drv_pci;
2480 + struct bcma_drv_mips drv_mips;
2481 +
2482 + /* We decided to share SPROM struct with SSB as long as we do not need
2483 + * any hacks for BCMA. This simplifies drivers code. */
2484 + struct ssb_sprom sprom;
2485 +};
2486 +
2487 +static inline u32 bcma_read8(struct bcma_device *core, u16 offset)
2488 +{
2489 + return core->bus->ops->read8(core, offset);
2490 +}
2491 +static inline u32 bcma_read16(struct bcma_device *core, u16 offset)
2492 +{
2493 + return core->bus->ops->read16(core, offset);
2494 +}
2495 +static inline u32 bcma_read32(struct bcma_device *core, u16 offset)
2496 +{
2497 + return core->bus->ops->read32(core, offset);
2498 +}
2499 +static inline
2500 +void bcma_write8(struct bcma_device *core, u16 offset, u32 value)
2501 +{
2502 + core->bus->ops->write8(core, offset, value);
2503 +}
2504 +static inline
2505 +void bcma_write16(struct bcma_device *core, u16 offset, u32 value)
2506 +{
2507 + core->bus->ops->write16(core, offset, value);
2508 +}
2509 +static inline
2510 +void bcma_write32(struct bcma_device *core, u16 offset, u32 value)
2511 +{
2512 + core->bus->ops->write32(core, offset, value);
2513 +}
2514 +#ifdef CONFIG_BCMA_BLOCKIO
2515 +static inline void bcma_block_read(struct bcma_device *core, void *buffer,
2516 + size_t count, u16 offset, u8 reg_width)
2517 +{
2518 + core->bus->ops->block_read(core, buffer, count, offset, reg_width);
2519 +}
2520 +static inline void bcma_block_write(struct bcma_device *core,
2521 + const void *buffer, size_t count,
2522 + u16 offset, u8 reg_width)
2523 +{
2524 + core->bus->ops->block_write(core, buffer, count, offset, reg_width);
2525 +}
2526 +#endif
2527 +static inline u32 bcma_aread32(struct bcma_device *core, u16 offset)
2528 +{
2529 + return core->bus->ops->aread32(core, offset);
2530 +}
2531 +static inline
2532 +void bcma_awrite32(struct bcma_device *core, u16 offset, u32 value)
2533 +{
2534 + core->bus->ops->awrite32(core, offset, value);
2535 +}
2536 +
2537 +static inline void bcma_mask32(struct bcma_device *cc, u16 offset, u32 mask)
2538 +{
2539 + bcma_write32(cc, offset, bcma_read32(cc, offset) & mask);
2540 +}
2541 +static inline void bcma_set32(struct bcma_device *cc, u16 offset, u32 set)
2542 +{
2543 + bcma_write32(cc, offset, bcma_read32(cc, offset) | set);
2544 +}
2545 +static inline void bcma_maskset32(struct bcma_device *cc,
2546 + u16 offset, u32 mask, u32 set)
2547 +{
2548 + bcma_write32(cc, offset, (bcma_read32(cc, offset) & mask) | set);
2549 +}
2550 +static inline void bcma_mask16(struct bcma_device *cc, u16 offset, u16 mask)
2551 +{
2552 + bcma_write16(cc, offset, bcma_read16(cc, offset) & mask);
2553 +}
2554 +static inline void bcma_set16(struct bcma_device *cc, u16 offset, u16 set)
2555 +{
2556 + bcma_write16(cc, offset, bcma_read16(cc, offset) | set);
2557 +}
2558 +static inline void bcma_maskset16(struct bcma_device *cc,
2559 + u16 offset, u16 mask, u16 set)
2560 +{
2561 + bcma_write16(cc, offset, (bcma_read16(cc, offset) & mask) | set);
2562 +}
2563 +
2564 +extern bool bcma_core_is_enabled(struct bcma_device *core);
2565 +extern void bcma_core_disable(struct bcma_device *core, u32 flags);
2566 +extern int bcma_core_enable(struct bcma_device *core, u32 flags);
2567 +extern void bcma_core_set_clockmode(struct bcma_device *core,
2568 + enum bcma_clkmode clkmode);
2569 +extern void bcma_core_pll_ctl(struct bcma_device *core, u32 req, u32 status,
2570 + bool on);
2571 +#define BCMA_DMA_TRANSLATION_MASK 0xC0000000
2572 +#define BCMA_DMA_TRANSLATION_NONE 0x00000000
2573 +#define BCMA_DMA_TRANSLATION_DMA32_CMT 0x40000000 /* Client Mode Translation for 32-bit DMA */
2574 +#define BCMA_DMA_TRANSLATION_DMA64_CMT 0x80000000 /* Client Mode Translation for 64-bit DMA */
2575 +extern u32 bcma_core_dma_translation(struct bcma_device *core);
2576 +
2577 +#endif /* LINUX_BCMA_H_ */
2578 --- /dev/null
2579 +++ b/include/linux/bcma/bcma_driver_chipcommon.h
2580 @@ -0,0 +1,391 @@
2581 +#ifndef LINUX_BCMA_DRIVER_CC_H_
2582 +#define LINUX_BCMA_DRIVER_CC_H_
2583 +
2584 +/** ChipCommon core registers. **/
2585 +#define BCMA_CC_ID 0x0000
2586 +#define BCMA_CC_ID_ID 0x0000FFFF
2587 +#define BCMA_CC_ID_ID_SHIFT 0
2588 +#define BCMA_CC_ID_REV 0x000F0000
2589 +#define BCMA_CC_ID_REV_SHIFT 16
2590 +#define BCMA_CC_ID_PKG 0x00F00000
2591 +#define BCMA_CC_ID_PKG_SHIFT 20
2592 +#define BCMA_CC_ID_NRCORES 0x0F000000
2593 +#define BCMA_CC_ID_NRCORES_SHIFT 24
2594 +#define BCMA_CC_ID_TYPE 0xF0000000
2595 +#define BCMA_CC_ID_TYPE_SHIFT 28
2596 +#define BCMA_CC_CAP 0x0004 /* Capabilities */
2597 +#define BCMA_CC_CAP_NRUART 0x00000003 /* # of UARTs */
2598 +#define BCMA_CC_CAP_MIPSEB 0x00000004 /* MIPS in BigEndian Mode */
2599 +#define BCMA_CC_CAP_UARTCLK 0x00000018 /* UART clock select */
2600 +#define BCMA_CC_CAP_UARTCLK_INT 0x00000008 /* UARTs are driven by internal divided clock */
2601 +#define BCMA_CC_CAP_UARTGPIO 0x00000020 /* UARTs on GPIO 15-12 */
2602 +#define BCMA_CC_CAP_EXTBUS 0x000000C0 /* External buses present */
2603 +#define BCMA_CC_CAP_FLASHT 0x00000700 /* Flash Type */
2604 +#define BCMA_CC_FLASHT_NONE 0x00000000 /* No flash */
2605 +#define BCMA_CC_FLASHT_STSER 0x00000100 /* ST serial flash */
2606 +#define BCMA_CC_FLASHT_ATSER 0x00000200 /* Atmel serial flash */
2607 +#define BCMA_CC_FLASHT_NFLASH 0x00000200
2608 +#define BCMA_CC_FLASHT_PARA 0x00000700 /* Parallel flash */
2609 +#define BCMA_CC_CAP_PLLT 0x00038000 /* PLL Type */
2610 +#define BCMA_PLLTYPE_NONE 0x00000000
2611 +#define BCMA_PLLTYPE_1 0x00010000 /* 48Mhz base, 3 dividers */
2612 +#define BCMA_PLLTYPE_2 0x00020000 /* 48Mhz, 4 dividers */
2613 +#define BCMA_PLLTYPE_3 0x00030000 /* 25Mhz, 2 dividers */
2614 +#define BCMA_PLLTYPE_4 0x00008000 /* 48Mhz, 4 dividers */
2615 +#define BCMA_PLLTYPE_5 0x00018000 /* 25Mhz, 4 dividers */
2616 +#define BCMA_PLLTYPE_6 0x00028000 /* 100/200 or 120/240 only */
2617 +#define BCMA_PLLTYPE_7 0x00038000 /* 25Mhz, 4 dividers */
2618 +#define BCMA_CC_CAP_PCTL 0x00040000 /* Power Control */
2619 +#define BCMA_CC_CAP_OTPS 0x00380000 /* OTP size */
2620 +#define BCMA_CC_CAP_OTPS_SHIFT 19
2621 +#define BCMA_CC_CAP_OTPS_BASE 5
2622 +#define BCMA_CC_CAP_JTAGM 0x00400000 /* JTAG master present */
2623 +#define BCMA_CC_CAP_BROM 0x00800000 /* Internal boot ROM active */
2624 +#define BCMA_CC_CAP_64BIT 0x08000000 /* 64-bit Backplane */
2625 +#define BCMA_CC_CAP_PMU 0x10000000 /* PMU available (rev >= 20) */
2626 +#define BCMA_CC_CAP_ECI 0x20000000 /* ECI available (rev >= 20) */
2627 +#define BCMA_CC_CAP_SPROM 0x40000000 /* SPROM present */
2628 +#define BCMA_CC_CORECTL 0x0008
2629 +#define BCMA_CC_CORECTL_UARTCLK0 0x00000001 /* Drive UART with internal clock */
2630 +#define BCMA_CC_CORECTL_SE 0x00000002 /* sync clk out enable (corerev >= 3) */
2631 +#define BCMA_CC_CORECTL_UARTCLKEN 0x00000008 /* UART clock enable (rev >= 21) */
2632 +#define BCMA_CC_BIST 0x000C
2633 +#define BCMA_CC_OTPS 0x0010 /* OTP status */
2634 +#define BCMA_CC_OTPS_PROGFAIL 0x80000000
2635 +#define BCMA_CC_OTPS_PROTECT 0x00000007
2636 +#define BCMA_CC_OTPS_HW_PROTECT 0x00000001
2637 +#define BCMA_CC_OTPS_SW_PROTECT 0x00000002
2638 +#define BCMA_CC_OTPS_CID_PROTECT 0x00000004
2639 +#define BCMA_CC_OTPC 0x0014 /* OTP control */
2640 +#define BCMA_CC_OTPC_RECWAIT 0xFF000000
2641 +#define BCMA_CC_OTPC_PROGWAIT 0x00FFFF00
2642 +#define BCMA_CC_OTPC_PRW_SHIFT 8
2643 +#define BCMA_CC_OTPC_MAXFAIL 0x00000038
2644 +#define BCMA_CC_OTPC_VSEL 0x00000006
2645 +#define BCMA_CC_OTPC_SELVL 0x00000001
2646 +#define BCMA_CC_OTPP 0x0018 /* OTP prog */
2647 +#define BCMA_CC_OTPP_COL 0x000000FF
2648 +#define BCMA_CC_OTPP_ROW 0x0000FF00
2649 +#define BCMA_CC_OTPP_ROW_SHIFT 8
2650 +#define BCMA_CC_OTPP_READERR 0x10000000
2651 +#define BCMA_CC_OTPP_VALUE 0x20000000
2652 +#define BCMA_CC_OTPP_READ 0x40000000
2653 +#define BCMA_CC_OTPP_START 0x80000000
2654 +#define BCMA_CC_OTPP_BUSY 0x80000000
2655 +#define BCMA_CC_IRQSTAT 0x0020
2656 +#define BCMA_CC_IRQMASK 0x0024
2657 +#define BCMA_CC_IRQ_GPIO 0x00000001 /* gpio intr */
2658 +#define BCMA_CC_IRQ_EXT 0x00000002 /* ro: ext intr pin (corerev >= 3) */
2659 +#define BCMA_CC_IRQ_WDRESET 0x80000000 /* watchdog reset occurred */
2660 +#define BCMA_CC_CHIPCTL 0x0028 /* Rev >= 11 only */
2661 +#define BCMA_CC_CHIPSTAT 0x002C /* Rev >= 11 only */
2662 +#define BCMA_CC_JCMD 0x0030 /* Rev >= 10 only */
2663 +#define BCMA_CC_JCMD_START 0x80000000
2664 +#define BCMA_CC_JCMD_BUSY 0x80000000
2665 +#define BCMA_CC_JCMD_PAUSE 0x40000000
2666 +#define BCMA_CC_JCMD0_ACC_MASK 0x0000F000
2667 +#define BCMA_CC_JCMD0_ACC_IRDR 0x00000000
2668 +#define BCMA_CC_JCMD0_ACC_DR 0x00001000
2669 +#define BCMA_CC_JCMD0_ACC_IR 0x00002000
2670 +#define BCMA_CC_JCMD0_ACC_RESET 0x00003000
2671 +#define BCMA_CC_JCMD0_ACC_IRPDR 0x00004000
2672 +#define BCMA_CC_JCMD0_ACC_PDR 0x00005000
2673 +#define BCMA_CC_JCMD0_IRW_MASK 0x00000F00
2674 +#define BCMA_CC_JCMD_ACC_MASK 0x000F0000 /* Changes for corerev 11 */
2675 +#define BCMA_CC_JCMD_ACC_IRDR 0x00000000
2676 +#define BCMA_CC_JCMD_ACC_DR 0x00010000
2677 +#define BCMA_CC_JCMD_ACC_IR 0x00020000
2678 +#define BCMA_CC_JCMD_ACC_RESET 0x00030000
2679 +#define BCMA_CC_JCMD_ACC_IRPDR 0x00040000
2680 +#define BCMA_CC_JCMD_ACC_PDR 0x00050000
2681 +#define BCMA_CC_JCMD_IRW_MASK 0x00001F00
2682 +#define BCMA_CC_JCMD_IRW_SHIFT 8
2683 +#define BCMA_CC_JCMD_DRW_MASK 0x0000003F
2684 +#define BCMA_CC_JIR 0x0034 /* Rev >= 10 only */
2685 +#define BCMA_CC_JDR 0x0038 /* Rev >= 10 only */
2686 +#define BCMA_CC_JCTL 0x003C /* Rev >= 10 only */
2687 +#define BCMA_CC_JCTL_FORCE_CLK 4 /* Force clock */
2688 +#define BCMA_CC_JCTL_EXT_EN 2 /* Enable external targets */
2689 +#define BCMA_CC_JCTL_EN 1 /* Enable Jtag master */
2690 +#define BCMA_CC_FLASHCTL 0x0040
2691 +#define BCMA_CC_FLASHCTL_START 0x80000000
2692 +#define BCMA_CC_FLASHCTL_BUSY BCMA_CC_FLASHCTL_START
2693 +#define BCMA_CC_FLASHADDR 0x0044
2694 +#define BCMA_CC_FLASHDATA 0x0048
2695 +#define BCMA_CC_BCAST_ADDR 0x0050
2696 +#define BCMA_CC_BCAST_DATA 0x0054
2697 +#define BCMA_CC_GPIOPULLUP 0x0058 /* Rev >= 20 only */
2698 +#define BCMA_CC_GPIOPULLDOWN 0x005C /* Rev >= 20 only */
2699 +#define BCMA_CC_GPIOIN 0x0060
2700 +#define BCMA_CC_GPIOOUT 0x0064
2701 +#define BCMA_CC_GPIOOUTEN 0x0068
2702 +#define BCMA_CC_GPIOCTL 0x006C
2703 +#define BCMA_CC_GPIOPOL 0x0070
2704 +#define BCMA_CC_GPIOIRQ 0x0074
2705 +#define BCMA_CC_WATCHDOG 0x0080
2706 +#define BCMA_CC_GPIOTIMER 0x0088 /* LED powersave (corerev >= 16) */
2707 +#define BCMA_CC_GPIOTIMER_OFFTIME 0x0000FFFF
2708 +#define BCMA_CC_GPIOTIMER_OFFTIME_SHIFT 0
2709 +#define BCMA_CC_GPIOTIMER_ONTIME 0xFFFF0000
2710 +#define BCMA_CC_GPIOTIMER_ONTIME_SHIFT 16
2711 +#define BCMA_CC_GPIOTOUTM 0x008C /* LED powersave (corerev >= 16) */
2712 +#define BCMA_CC_CLOCK_N 0x0090
2713 +#define BCMA_CC_CLOCK_SB 0x0094
2714 +#define BCMA_CC_CLOCK_PCI 0x0098
2715 +#define BCMA_CC_CLOCK_M2 0x009C
2716 +#define BCMA_CC_CLOCK_MIPS 0x00A0
2717 +#define BCMA_CC_CLKDIV 0x00A4 /* Rev >= 3 only */
2718 +#define BCMA_CC_CLKDIV_SFLASH 0x0F000000
2719 +#define BCMA_CC_CLKDIV_SFLASH_SHIFT 24
2720 +#define BCMA_CC_CLKDIV_OTP 0x000F0000
2721 +#define BCMA_CC_CLKDIV_OTP_SHIFT 16
2722 +#define BCMA_CC_CLKDIV_JTAG 0x00000F00
2723 +#define BCMA_CC_CLKDIV_JTAG_SHIFT 8
2724 +#define BCMA_CC_CLKDIV_UART 0x000000FF
2725 +#define BCMA_CC_CAP_EXT 0x00AC /* Capabilities */
2726 +#define BCMA_CC_PLLONDELAY 0x00B0 /* Rev >= 4 only */
2727 +#define BCMA_CC_FREFSELDELAY 0x00B4 /* Rev >= 4 only */
2728 +#define BCMA_CC_SLOWCLKCTL 0x00B8 /* 6 <= Rev <= 9 only */
2729 +#define BCMA_CC_SLOWCLKCTL_SRC 0x00000007 /* slow clock source mask */
2730 +#define BCMA_CC_SLOWCLKCTL_SRC_LPO 0x00000000 /* source of slow clock is LPO */
2731 +#define BCMA_CC_SLOWCLKCTL_SRC_XTAL 0x00000001 /* source of slow clock is crystal */
2732 +#define BCMA_CC_SLOECLKCTL_SRC_PCI 0x00000002 /* source of slow clock is PCI */
2733 +#define BCMA_CC_SLOWCLKCTL_LPOFREQ 0x00000200 /* LPOFreqSel, 1: 160Khz, 0: 32KHz */
2734 +#define BCMA_CC_SLOWCLKCTL_LPOPD 0x00000400 /* LPOPowerDown, 1: LPO is disabled, 0: LPO is enabled */
2735 +#define BCMA_CC_SLOWCLKCTL_FSLOW 0x00000800 /* ForceSlowClk, 1: sb/cores running on slow clock, 0: power logic control */
2736 +#define BCMA_CC_SLOWCLKCTL_IPLL 0x00001000 /* IgnorePllOffReq, 1/0: power logic ignores/honors PLL clock disable requests from core */
2737 +#define BCMA_CC_SLOWCLKCTL_ENXTAL 0x00002000 /* XtalControlEn, 1/0: power logic does/doesn't disable crystal when appropriate */
2738 +#define BCMA_CC_SLOWCLKCTL_XTALPU 0x00004000 /* XtalPU (RO), 1/0: crystal running/disabled */
2739 +#define BCMA_CC_SLOWCLKCTL_CLKDIV 0xFFFF0000 /* ClockDivider (SlowClk = 1/(4+divisor)) */
2740 +#define BCMA_CC_SLOWCLKCTL_CLKDIV_SHIFT 16
2741 +#define BCMA_CC_SYSCLKCTL 0x00C0 /* Rev >= 3 only */
2742 +#define BCMA_CC_SYSCLKCTL_IDLPEN 0x00000001 /* ILPen: Enable Idle Low Power */
2743 +#define BCMA_CC_SYSCLKCTL_ALPEN 0x00000002 /* ALPen: Enable Active Low Power */
2744 +#define BCMA_CC_SYSCLKCTL_PLLEN 0x00000004 /* ForcePLLOn */
2745 +#define BCMA_CC_SYSCLKCTL_FORCEALP 0x00000008 /* Force ALP (or HT if ALPen is not set */
2746 +#define BCMA_CC_SYSCLKCTL_FORCEHT 0x00000010 /* Force HT */
2747 +#define BCMA_CC_SYSCLKCTL_CLKDIV 0xFFFF0000 /* ClkDiv (ILP = 1/(4+divisor)) */
2748 +#define BCMA_CC_SYSCLKCTL_CLKDIV_SHIFT 16
2749 +#define BCMA_CC_CLKSTSTR 0x00C4 /* Rev >= 3 only */
2750 +#define BCMA_CC_EROM 0x00FC
2751 +#define BCMA_CC_PCMCIA_CFG 0x0100
2752 +#define BCMA_CC_PCMCIA_MEMWAIT 0x0104
2753 +#define BCMA_CC_PCMCIA_ATTRWAIT 0x0108
2754 +#define BCMA_CC_PCMCIA_IOWAIT 0x010C
2755 +#define BCMA_CC_IDE_CFG 0x0110
2756 +#define BCMA_CC_IDE_MEMWAIT 0x0114
2757 +#define BCMA_CC_IDE_ATTRWAIT 0x0118
2758 +#define BCMA_CC_IDE_IOWAIT 0x011C
2759 +#define BCMA_CC_PROG_CFG 0x0120
2760 +#define BCMA_CC_PROG_WAITCNT 0x0124
2761 +#define BCMA_CC_FLASH_CFG 0x0128
2762 +#define BCMA_CC_FLASH_CFG_DS 0x0010 /* Data size, 0=8bit, 1=16bit */
2763 +#define BCMA_CC_FLASH_WAITCNT 0x012C
2764 +/* 0x1E0 is defined as shared BCMA_CLKCTLST */
2765 +#define BCMA_CC_HW_WORKAROUND 0x01E4 /* Hardware workaround (rev >= 20) */
2766 +#define BCMA_CC_UART0_DATA 0x0300
2767 +#define BCMA_CC_UART0_IMR 0x0304
2768 +#define BCMA_CC_UART0_FCR 0x0308
2769 +#define BCMA_CC_UART0_LCR 0x030C
2770 +#define BCMA_CC_UART0_MCR 0x0310
2771 +#define BCMA_CC_UART0_LSR 0x0314
2772 +#define BCMA_CC_UART0_MSR 0x0318
2773 +#define BCMA_CC_UART0_SCRATCH 0x031C
2774 +#define BCMA_CC_UART1_DATA 0x0400
2775 +#define BCMA_CC_UART1_IMR 0x0404
2776 +#define BCMA_CC_UART1_FCR 0x0408
2777 +#define BCMA_CC_UART1_LCR 0x040C
2778 +#define BCMA_CC_UART1_MCR 0x0410
2779 +#define BCMA_CC_UART1_LSR 0x0414
2780 +#define BCMA_CC_UART1_MSR 0x0418
2781 +#define BCMA_CC_UART1_SCRATCH 0x041C
2782 +/* PMU registers (rev >= 20) */
2783 +#define BCMA_CC_PMU_CTL 0x0600 /* PMU control */
2784 +#define BCMA_CC_PMU_CTL_ILP_DIV 0xFFFF0000 /* ILP div mask */
2785 +#define BCMA_CC_PMU_CTL_ILP_DIV_SHIFT 16
2786 +#define BCMA_CC_PMU_CTL_PLL_UPD 0x00000400
2787 +#define BCMA_CC_PMU_CTL_NOILPONW 0x00000200 /* No ILP on wait */
2788 +#define BCMA_CC_PMU_CTL_HTREQEN 0x00000100 /* HT req enable */
2789 +#define BCMA_CC_PMU_CTL_ALPREQEN 0x00000080 /* ALP req enable */
2790 +#define BCMA_CC_PMU_CTL_XTALFREQ 0x0000007C /* Crystal freq */
2791 +#define BCMA_CC_PMU_CTL_XTALFREQ_SHIFT 2
2792 +#define BCMA_CC_PMU_CTL_ILPDIVEN 0x00000002 /* ILP div enable */
2793 +#define BCMA_CC_PMU_CTL_LPOSEL 0x00000001 /* LPO sel */
2794 +#define BCMA_CC_PMU_CAP 0x0604 /* PMU capabilities */
2795 +#define BCMA_CC_PMU_CAP_REVISION 0x000000FF /* Revision mask */
2796 +#define BCMA_CC_PMU_STAT 0x0608 /* PMU status */
2797 +#define BCMA_CC_PMU_STAT_INTPEND 0x00000040 /* Interrupt pending */
2798 +#define BCMA_CC_PMU_STAT_SBCLKST 0x00000030 /* Backplane clock status? */
2799 +#define BCMA_CC_PMU_STAT_HAVEALP 0x00000008 /* ALP available */
2800 +#define BCMA_CC_PMU_STAT_HAVEHT 0x00000004 /* HT available */
2801 +#define BCMA_CC_PMU_STAT_RESINIT 0x00000003 /* Res init */
2802 +#define BCMA_CC_PMU_RES_STAT 0x060C /* PMU res status */
2803 +#define BCMA_CC_PMU_RES_PEND 0x0610 /* PMU res pending */
2804 +#define BCMA_CC_PMU_TIMER 0x0614 /* PMU timer */
2805 +#define BCMA_CC_PMU_MINRES_MSK 0x0618 /* PMU min res mask */
2806 +#define BCMA_CC_PMU_MAXRES_MSK 0x061C /* PMU max res mask */
2807 +#define BCMA_CC_PMU_RES_TABSEL 0x0620 /* PMU res table sel */
2808 +#define BCMA_CC_PMU_RES_DEPMSK 0x0624 /* PMU res dep mask */
2809 +#define BCMA_CC_PMU_RES_UPDNTM 0x0628 /* PMU res updown timer */
2810 +#define BCMA_CC_PMU_RES_TIMER 0x062C /* PMU res timer */
2811 +#define BCMA_CC_PMU_CLKSTRETCH 0x0630 /* PMU clockstretch */
2812 +#define BCMA_CC_PMU_WATCHDOG 0x0634 /* PMU watchdog */
2813 +#define BCMA_CC_PMU_RES_REQTS 0x0640 /* PMU res req timer sel */
2814 +#define BCMA_CC_PMU_RES_REQT 0x0644 /* PMU res req timer */
2815 +#define BCMA_CC_PMU_RES_REQM 0x0648 /* PMU res req mask */
2816 +#define BCMA_CC_CHIPCTL_ADDR 0x0650
2817 +#define BCMA_CC_CHIPCTL_DATA 0x0654
2818 +#define BCMA_CC_REGCTL_ADDR 0x0658
2819 +#define BCMA_CC_REGCTL_DATA 0x065C
2820 +#define BCMA_CC_PLLCTL_ADDR 0x0660
2821 +#define BCMA_CC_PLLCTL_DATA 0x0664
2822 +#define BCMA_CC_SPROM 0x0800 /* SPROM beginning */
2823 +#define BCMA_CC_SPROM_PCIE6 0x0830 /* SPROM beginning on PCIe rev >= 6 */
2824 +
2825 +/* Divider allocation in 4716/47162/5356 */
2826 +#define BCMA_CC_PMU5_MAINPLL_CPU 1
2827 +#define BCMA_CC_PMU5_MAINPLL_MEM 2
2828 +#define BCMA_CC_PMU5_MAINPLL_SSB 3
2829 +
2830 +/* PLL usage in 4716/47162 */
2831 +#define BCMA_CC_PMU4716_MAINPLL_PLL0 12
2832 +
2833 +/* PLL usage in 5356/5357 */
2834 +#define BCMA_CC_PMU5356_MAINPLL_PLL0 0
2835 +#define BCMA_CC_PMU5357_MAINPLL_PLL0 0
2836 +
2837 +/* 4706 PMU */
2838 +#define BCMA_CC_PMU4706_MAINPLL_PLL0 0
2839 +
2840 +/* ALP clock on pre-PMU chips */
2841 +#define BCMA_CC_PMU_ALP_CLOCK 20000000
2842 +/* HT clock for systems with PMU-enabled chipcommon */
2843 +#define BCMA_CC_PMU_HT_CLOCK 80000000
2844 +
2845 +/* PMU rev 5 (& 6) */
2846 +#define BCMA_CC_PPL_P1P2_OFF 0
2847 +#define BCMA_CC_PPL_P1_MASK 0x0f000000
2848 +#define BCMA_CC_PPL_P1_SHIFT 24
2849 +#define BCMA_CC_PPL_P2_MASK 0x00f00000
2850 +#define BCMA_CC_PPL_P2_SHIFT 20
2851 +#define BCMA_CC_PPL_M14_OFF 1
2852 +#define BCMA_CC_PPL_MDIV_MASK 0x000000ff
2853 +#define BCMA_CC_PPL_MDIV_WIDTH 8
2854 +#define BCMA_CC_PPL_NM5_OFF 2
2855 +#define BCMA_CC_PPL_NDIV_MASK 0xfff00000
2856 +#define BCMA_CC_PPL_NDIV_SHIFT 20
2857 +#define BCMA_CC_PPL_FMAB_OFF 3
2858 +#define BCMA_CC_PPL_MRAT_MASK 0xf0000000
2859 +#define BCMA_CC_PPL_MRAT_SHIFT 28
2860 +#define BCMA_CC_PPL_ABRAT_MASK 0x08000000
2861 +#define BCMA_CC_PPL_ABRAT_SHIFT 27
2862 +#define BCMA_CC_PPL_FDIV_MASK 0x07ffffff
2863 +#define BCMA_CC_PPL_PLLCTL_OFF 4
2864 +#define BCMA_CC_PPL_PCHI_OFF 5
2865 +#define BCMA_CC_PPL_PCHI_MASK 0x0000003f
2866 +
2867 +/* BCM4331 ChipControl numbers. */
2868 +#define BCMA_CHIPCTL_4331_BT_COEXIST BIT(0) /* 0 disable */
2869 +#define BCMA_CHIPCTL_4331_SECI BIT(1) /* 0 SECI is disabled (JATG functional) */
2870 +#define BCMA_CHIPCTL_4331_EXT_LNA BIT(2) /* 0 disable */
2871 +#define BCMA_CHIPCTL_4331_SPROM_GPIO13_15 BIT(3) /* sprom/gpio13-15 mux */
2872 +#define BCMA_CHIPCTL_4331_EXTPA_EN BIT(4) /* 0 ext pa disable, 1 ext pa enabled */
2873 +#define BCMA_CHIPCTL_4331_GPIOCLK_ON_SPROMCS BIT(5) /* set drive out GPIO_CLK on sprom_cs pin */
2874 +#define BCMA_CHIPCTL_4331_PCIE_MDIO_ON_SPROMCS BIT(6) /* use sprom_cs pin as PCIE mdio interface */
2875 +#define BCMA_CHIPCTL_4331_EXTPA_ON_GPIO2_5 BIT(7) /* aband extpa will be at gpio2/5 and sprom_dout */
2876 +#define BCMA_CHIPCTL_4331_OVR_PIPEAUXCLKEN BIT(8) /* override core control on pipe_AuxClkEnable */
2877 +#define BCMA_CHIPCTL_4331_OVR_PIPEAUXPWRDOWN BIT(9) /* override core control on pipe_AuxPowerDown */
2878 +#define BCMA_CHIPCTL_4331_PCIE_AUXCLKEN BIT(10) /* pcie_auxclkenable */
2879 +#define BCMA_CHIPCTL_4331_PCIE_PIPE_PLLDOWN BIT(11) /* pcie_pipe_pllpowerdown */
2880 +#define BCMA_CHIPCTL_4331_BT_SHD0_ON_GPIO4 BIT(16) /* enable bt_shd0 at gpio4 */
2881 +#define BCMA_CHIPCTL_4331_BT_SHD1_ON_GPIO5 BIT(17) /* enable bt_shd1 at gpio5 */
2882 +
2883 +/* Data for the PMU, if available.
2884 + * Check availability with ((struct bcma_chipcommon)->capabilities & BCMA_CC_CAP_PMU)
2885 + */
2886 +struct bcma_chipcommon_pmu {
2887 + u8 rev; /* PMU revision */
2888 + u32 crystalfreq; /* The active crystal frequency (in kHz) */
2889 +};
2890 +
2891 +#ifdef CONFIG_BCMA_DRIVER_MIPS
2892 +struct bcma_pflash {
2893 + u8 buswidth;
2894 + u32 window;
2895 + u32 window_size;
2896 +};
2897 +
2898 +struct bcma_serial_port {
2899 + void *regs;
2900 + unsigned long clockspeed;
2901 + unsigned int irq;
2902 + unsigned int baud_base;
2903 + unsigned int reg_shift;
2904 +};
2905 +#endif /* CONFIG_BCMA_DRIVER_MIPS */
2906 +
2907 +struct bcma_drv_cc {
2908 + struct bcma_device *core;
2909 + u32 status;
2910 + u32 capabilities;
2911 + u32 capabilities_ext;
2912 + u8 setup_done:1;
2913 + /* Fast Powerup Delay constant */
2914 + u16 fast_pwrup_delay;
2915 + struct bcma_chipcommon_pmu pmu;
2916 +#ifdef CONFIG_BCMA_DRIVER_MIPS
2917 + struct bcma_pflash pflash;
2918 +
2919 + int nr_serial_ports;
2920 + struct bcma_serial_port serial_ports[4];
2921 +#endif /* CONFIG_BCMA_DRIVER_MIPS */
2922 +};
2923 +
2924 +/* Register access */
2925 +#define bcma_cc_read32(cc, offset) \
2926 + bcma_read32((cc)->core, offset)
2927 +#define bcma_cc_write32(cc, offset, val) \
2928 + bcma_write32((cc)->core, offset, val)
2929 +
2930 +#define bcma_cc_mask32(cc, offset, mask) \
2931 + bcma_cc_write32(cc, offset, bcma_cc_read32(cc, offset) & (mask))
2932 +#define bcma_cc_set32(cc, offset, set) \
2933 + bcma_cc_write32(cc, offset, bcma_cc_read32(cc, offset) | (set))
2934 +#define bcma_cc_maskset32(cc, offset, mask, set) \
2935 + bcma_cc_write32(cc, offset, (bcma_cc_read32(cc, offset) & (mask)) | (set))
2936 +
2937 +extern void bcma_core_chipcommon_init(struct bcma_drv_cc *cc);
2938 +
2939 +extern void bcma_chipco_suspend(struct bcma_drv_cc *cc);
2940 +extern void bcma_chipco_resume(struct bcma_drv_cc *cc);
2941 +
2942 +void bcma_chipco_bcm4331_ext_pa_lines_ctl(struct bcma_drv_cc *cc, bool enable);
2943 +
2944 +extern void bcma_chipco_watchdog_timer_set(struct bcma_drv_cc *cc,
2945 + u32 ticks);
2946 +
2947 +void bcma_chipco_irq_mask(struct bcma_drv_cc *cc, u32 mask, u32 value);
2948 +
2949 +u32 bcma_chipco_irq_status(struct bcma_drv_cc *cc, u32 mask);
2950 +
2951 +/* Chipcommon GPIO pin access. */
2952 +u32 bcma_chipco_gpio_in(struct bcma_drv_cc *cc, u32 mask);
2953 +u32 bcma_chipco_gpio_out(struct bcma_drv_cc *cc, u32 mask, u32 value);
2954 +u32 bcma_chipco_gpio_outen(struct bcma_drv_cc *cc, u32 mask, u32 value);
2955 +u32 bcma_chipco_gpio_control(struct bcma_drv_cc *cc, u32 mask, u32 value);
2956 +u32 bcma_chipco_gpio_intmask(struct bcma_drv_cc *cc, u32 mask, u32 value);
2957 +u32 bcma_chipco_gpio_polarity(struct bcma_drv_cc *cc, u32 mask, u32 value);
2958 +
2959 +/* PMU support */
2960 +extern void bcma_pmu_init(struct bcma_drv_cc *cc);
2961 +
2962 +extern void bcma_chipco_pll_write(struct bcma_drv_cc *cc, u32 offset,
2963 + u32 value);
2964 +extern void bcma_chipco_pll_maskset(struct bcma_drv_cc *cc, u32 offset,
2965 + u32 mask, u32 set);
2966 +extern void bcma_chipco_chipctl_maskset(struct bcma_drv_cc *cc,
2967 + u32 offset, u32 mask, u32 set);
2968 +extern void bcma_chipco_regctl_maskset(struct bcma_drv_cc *cc,
2969 + u32 offset, u32 mask, u32 set);
2970 +
2971 +#endif /* LINUX_BCMA_DRIVER_CC_H_ */
2972 --- /dev/null
2973 +++ b/include/linux/bcma/bcma_driver_pci.h
2974 @@ -0,0 +1,91 @@
2975 +#ifndef LINUX_BCMA_DRIVER_PCI_H_
2976 +#define LINUX_BCMA_DRIVER_PCI_H_
2977 +
2978 +#include <linux/types.h>
2979 +
2980 +struct pci_dev;
2981 +
2982 +/** PCI core registers. **/
2983 +#define BCMA_CORE_PCI_CTL 0x0000 /* PCI Control */
2984 +#define BCMA_CORE_PCI_CTL_RST_OE 0x00000001 /* PCI_RESET Output Enable */
2985 +#define BCMA_CORE_PCI_CTL_RST 0x00000002 /* PCI_RESET driven out to pin */
2986 +#define BCMA_CORE_PCI_CTL_CLK_OE 0x00000004 /* Clock gate Output Enable */
2987 +#define BCMA_CORE_PCI_CTL_CLK 0x00000008 /* Gate for clock driven out to pin */
2988 +#define BCMA_CORE_PCI_ARBCTL 0x0010 /* PCI Arbiter Control */
2989 +#define BCMA_CORE_PCI_ARBCTL_INTERN 0x00000001 /* Use internal arbiter */
2990 +#define BCMA_CORE_PCI_ARBCTL_EXTERN 0x00000002 /* Use external arbiter */
2991 +#define BCMA_CORE_PCI_ARBCTL_PARKID 0x00000006 /* Mask, selects which agent is parked on an idle bus */
2992 +#define BCMA_CORE_PCI_ARBCTL_PARKID_LAST 0x00000000 /* Last requestor */
2993 +#define BCMA_CORE_PCI_ARBCTL_PARKID_4710 0x00000002 /* 4710 */
2994 +#define BCMA_CORE_PCI_ARBCTL_PARKID_EXT0 0x00000004 /* External requestor 0 */
2995 +#define BCMA_CORE_PCI_ARBCTL_PARKID_EXT1 0x00000006 /* External requestor 1 */
2996 +#define BCMA_CORE_PCI_ISTAT 0x0020 /* Interrupt status */
2997 +#define BCMA_CORE_PCI_ISTAT_INTA 0x00000001 /* PCI INTA# */
2998 +#define BCMA_CORE_PCI_ISTAT_INTB 0x00000002 /* PCI INTB# */
2999 +#define BCMA_CORE_PCI_ISTAT_SERR 0x00000004 /* PCI SERR# (write to clear) */
3000 +#define BCMA_CORE_PCI_ISTAT_PERR 0x00000008 /* PCI PERR# (write to clear) */
3001 +#define BCMA_CORE_PCI_ISTAT_PME 0x00000010 /* PCI PME# */
3002 +#define BCMA_CORE_PCI_IMASK 0x0024 /* Interrupt mask */
3003 +#define BCMA_CORE_PCI_IMASK_INTA 0x00000001 /* PCI INTA# */
3004 +#define BCMA_CORE_PCI_IMASK_INTB 0x00000002 /* PCI INTB# */
3005 +#define BCMA_CORE_PCI_IMASK_SERR 0x00000004 /* PCI SERR# */
3006 +#define BCMA_CORE_PCI_IMASK_PERR 0x00000008 /* PCI PERR# */
3007 +#define BCMA_CORE_PCI_IMASK_PME 0x00000010 /* PCI PME# */
3008 +#define BCMA_CORE_PCI_MBOX 0x0028 /* Backplane to PCI Mailbox */
3009 +#define BCMA_CORE_PCI_MBOX_F0_0 0x00000100 /* PCI function 0, INT 0 */
3010 +#define BCMA_CORE_PCI_MBOX_F0_1 0x00000200 /* PCI function 0, INT 1 */
3011 +#define BCMA_CORE_PCI_MBOX_F1_0 0x00000400 /* PCI function 1, INT 0 */
3012 +#define BCMA_CORE_PCI_MBOX_F1_1 0x00000800 /* PCI function 1, INT 1 */
3013 +#define BCMA_CORE_PCI_MBOX_F2_0 0x00001000 /* PCI function 2, INT 0 */
3014 +#define BCMA_CORE_PCI_MBOX_F2_1 0x00002000 /* PCI function 2, INT 1 */
3015 +#define BCMA_CORE_PCI_MBOX_F3_0 0x00004000 /* PCI function 3, INT 0 */
3016 +#define BCMA_CORE_PCI_MBOX_F3_1 0x00008000 /* PCI function 3, INT 1 */
3017 +#define BCMA_CORE_PCI_BCAST_ADDR 0x0050 /* Backplane Broadcast Address */
3018 +#define BCMA_CORE_PCI_BCAST_ADDR_MASK 0x000000FF
3019 +#define BCMA_CORE_PCI_BCAST_DATA 0x0054 /* Backplane Broadcast Data */
3020 +#define BCMA_CORE_PCI_GPIO_IN 0x0060 /* rev >= 2 only */
3021 +#define BCMA_CORE_PCI_GPIO_OUT 0x0064 /* rev >= 2 only */
3022 +#define BCMA_CORE_PCI_GPIO_ENABLE 0x0068 /* rev >= 2 only */
3023 +#define BCMA_CORE_PCI_GPIO_CTL 0x006C /* rev >= 2 only */
3024 +#define BCMA_CORE_PCI_SBTOPCI0 0x0100 /* Backplane to PCI translation 0 (sbtopci0) */
3025 +#define BCMA_CORE_PCI_SBTOPCI0_MASK 0xFC000000
3026 +#define BCMA_CORE_PCI_SBTOPCI1 0x0104 /* Backplane to PCI translation 1 (sbtopci1) */
3027 +#define BCMA_CORE_PCI_SBTOPCI1_MASK 0xFC000000
3028 +#define BCMA_CORE_PCI_SBTOPCI2 0x0108 /* Backplane to PCI translation 2 (sbtopci2) */
3029 +#define BCMA_CORE_PCI_SBTOPCI2_MASK 0xC0000000
3030 +#define BCMA_CORE_PCI_PCICFG0 0x0400 /* PCI config space 0 (rev >= 8) */
3031 +#define BCMA_CORE_PCI_PCICFG1 0x0500 /* PCI config space 1 (rev >= 8) */
3032 +#define BCMA_CORE_PCI_PCICFG2 0x0600 /* PCI config space 2 (rev >= 8) */
3033 +#define BCMA_CORE_PCI_PCICFG3 0x0700 /* PCI config space 3 (rev >= 8) */
3034 +#define BCMA_CORE_PCI_SPROM(wordoffset) (0x0800 + ((wordoffset) * 2)) /* SPROM shadow area (72 bytes) */
3035 +
3036 +/* SBtoPCIx */
3037 +#define BCMA_CORE_PCI_SBTOPCI_MEM 0x00000000
3038 +#define BCMA_CORE_PCI_SBTOPCI_IO 0x00000001
3039 +#define BCMA_CORE_PCI_SBTOPCI_CFG0 0x00000002
3040 +#define BCMA_CORE_PCI_SBTOPCI_CFG1 0x00000003
3041 +#define BCMA_CORE_PCI_SBTOPCI_PREF 0x00000004 /* Prefetch enable */
3042 +#define BCMA_CORE_PCI_SBTOPCI_BURST 0x00000008 /* Burst enable */
3043 +#define BCMA_CORE_PCI_SBTOPCI_MRM 0x00000020 /* Memory Read Multiple */
3044 +#define BCMA_CORE_PCI_SBTOPCI_RC 0x00000030 /* Read Command mask (rev >= 11) */
3045 +#define BCMA_CORE_PCI_SBTOPCI_RC_READ 0x00000000 /* Memory read */
3046 +#define BCMA_CORE_PCI_SBTOPCI_RC_READL 0x00000010 /* Memory read line */
3047 +#define BCMA_CORE_PCI_SBTOPCI_RC_READM 0x00000020 /* Memory read multiple */
3048 +
3049 +/* PCIcore specific boardflags */
3050 +#define BCMA_CORE_PCI_BFL_NOPCI 0x00000400 /* Board leaves PCI floating */
3051 +
3052 +struct bcma_drv_pci {
3053 + struct bcma_device *core;
3054 + u8 setup_done:1;
3055 +};
3056 +
3057 +/* Register access */
3058 +#define pcicore_read32(pc, offset) bcma_read32((pc)->core, offset)
3059 +#define pcicore_write32(pc, offset, val) bcma_write32((pc)->core, offset, val)
3060 +
3061 +extern void bcma_core_pci_init(struct bcma_drv_pci *pc);
3062 +extern int bcma_core_pci_irq_ctl(struct bcma_drv_pci *pc,
3063 + struct bcma_device *core, bool enable);
3064 +
3065 +#endif /* LINUX_BCMA_DRIVER_PCI_H_ */
3066 --- /dev/null
3067 +++ b/include/linux/bcma/bcma_regs.h
3068 @@ -0,0 +1,59 @@
3069 +#ifndef LINUX_BCMA_REGS_H_
3070 +#define LINUX_BCMA_REGS_H_
3071 +
3072 +/* Some single registers are shared between many cores */
3073 +/* BCMA_CLKCTLST: ChipCommon (rev >= 20), PCIe, 80211 */
3074 +#define BCMA_CLKCTLST 0x01E0 /* Clock control and status */
3075 +#define BCMA_CLKCTLST_FORCEALP 0x00000001 /* Force ALP request */
3076 +#define BCMA_CLKCTLST_FORCEHT 0x00000002 /* Force HT request */
3077 +#define BCMA_CLKCTLST_FORCEILP 0x00000004 /* Force ILP request */
3078 +#define BCMA_CLKCTLST_HAVEALPREQ 0x00000008 /* ALP available request */
3079 +#define BCMA_CLKCTLST_HAVEHTREQ 0x00000010 /* HT available request */
3080 +#define BCMA_CLKCTLST_HWCROFF 0x00000020 /* Force HW clock request off */
3081 +#define BCMA_CLKCTLST_EXTRESREQ 0x00000700 /* Mask of external resource requests */
3082 +#define BCMA_CLKCTLST_HAVEALP 0x00010000 /* ALP available */
3083 +#define BCMA_CLKCTLST_HAVEHT 0x00020000 /* HT available */
3084 +#define BCMA_CLKCTLST_BP_ON_ALP 0x00040000 /* RO: running on ALP clock */
3085 +#define BCMA_CLKCTLST_BP_ON_HT 0x00080000 /* RO: running on HT clock */
3086 +#define BCMA_CLKCTLST_EXTRESST 0x07000000 /* Mask of external resource status */
3087 +/* Is there any BCM4328 on BCMA bus? */
3088 +#define BCMA_CLKCTLST_4328A0_HAVEHT 0x00010000 /* 4328a0 has reversed bits */
3089 +#define BCMA_CLKCTLST_4328A0_HAVEALP 0x00020000 /* 4328a0 has reversed bits */
3090 +
3091 +/* Agent registers (common for every core) */
3092 +#define BCMA_IOCTL 0x0408 /* IO control */
3093 +#define BCMA_IOCTL_CLK 0x0001
3094 +#define BCMA_IOCTL_FGC 0x0002
3095 +#define BCMA_IOCTL_CORE_BITS 0x3FFC
3096 +#define BCMA_IOCTL_PME_EN 0x4000
3097 +#define BCMA_IOCTL_BIST_EN 0x8000
3098 +#define BCMA_IOST 0x0500 /* IO status */
3099 +#define BCMA_IOST_CORE_BITS 0x0FFF
3100 +#define BCMA_IOST_DMA64 0x1000
3101 +#define BCMA_IOST_GATED_CLK 0x2000
3102 +#define BCMA_IOST_BIST_ERROR 0x4000
3103 +#define BCMA_IOST_BIST_DONE 0x8000
3104 +#define BCMA_RESET_CTL 0x0800
3105 +#define BCMA_RESET_CTL_RESET 0x0001
3106 +
3107 +/* BCMA PCI config space registers. */
3108 +#define BCMA_PCI_PMCSR 0x44
3109 +#define BCMA_PCI_PE 0x100
3110 +#define BCMA_PCI_BAR0_WIN 0x80 /* Backplane address space 0 */
3111 +#define BCMA_PCI_BAR1_WIN 0x84 /* Backplane address space 1 */
3112 +#define BCMA_PCI_SPROMCTL 0x88 /* SPROM control */
3113 +#define BCMA_PCI_SPROMCTL_WE 0x10 /* SPROM write enable */
3114 +#define BCMA_PCI_BAR1_CONTROL 0x8c /* Address space 1 burst control */
3115 +#define BCMA_PCI_IRQS 0x90 /* PCI interrupts */
3116 +#define BCMA_PCI_IRQMASK 0x94 /* PCI IRQ control and mask (pcirev >= 6 only) */
3117 +#define BCMA_PCI_BACKPLANE_IRQS 0x98 /* Backplane Interrupts */
3118 +#define BCMA_PCI_BAR0_WIN2 0xAC
3119 +#define BCMA_PCI_GPIO_IN 0xB0 /* GPIO Input (pcirev >= 3 only) */
3120 +#define BCMA_PCI_GPIO_OUT 0xB4 /* GPIO Output (pcirev >= 3 only) */
3121 +#define BCMA_PCI_GPIO_OUT_ENABLE 0xB8 /* GPIO Output Enable/Disable (pcirev >= 3 only) */
3122 +#define BCMA_PCI_GPIO_SCS 0x10 /* PCI config space bit 4 for 4306c0 slow clock source */
3123 +#define BCMA_PCI_GPIO_HWRAD 0x20 /* PCI config space GPIO 13 for hw radio disable */
3124 +#define BCMA_PCI_GPIO_XTAL 0x40 /* PCI config space GPIO 14 for Xtal powerup */
3125 +#define BCMA_PCI_GPIO_PLL 0x80 /* PCI config space GPIO 15 for PLL powerdown */
3126 +
3127 +#endif /* LINUX_BCMA_REGS_H_ */
3128 --- a/include/linux/mod_devicetable.h
3129 +++ b/include/linux/mod_devicetable.h
3130 @@ -382,6 +382,23 @@ struct ssb_device_id {
3131 #define SSB_ANY_ID 0xFFFF
3132 #define SSB_ANY_REV 0xFF
3133
3134 +/* Broadcom's specific AMBA core, see drivers/bcma/ */
3135 +struct bcma_device_id {
3136 + __u16 manuf;
3137 + __u16 id;
3138 + __u8 rev;
3139 + __u8 class;
3140 +};
3141 +#define BCMA_CORE(_manuf, _id, _rev, _class) \
3142 + { .manuf = _manuf, .id = _id, .rev = _rev, .class = _class, }
3143 +#define BCMA_CORETABLE_END \
3144 + { 0, },
3145 +
3146 +#define BCMA_ANY_MANUF 0xFFFF
3147 +#define BCMA_ANY_ID 0xFFFF
3148 +#define BCMA_ANY_REV 0xFF
3149 +#define BCMA_ANY_CLASS 0xFF
3150 +
3151 struct virtio_device_id {
3152 __u32 device;
3153 __u32 vendor;
3154 --- a/scripts/mod/file2alias.c
3155 +++ b/scripts/mod/file2alias.c
3156 @@ -633,6 +633,24 @@ static int do_ssb_entry(const char *file
3157 return 1;
3158 }
3159
3160 +/* Looks like: bcma:mNidNrevNclN. */
3161 +static int do_bcma_entry(const char *filename,
3162 + struct bcma_device_id *id, char *alias)
3163 +{
3164 + id->manuf = TO_NATIVE(id->manuf);
3165 + id->id = TO_NATIVE(id->id);
3166 + id->rev = TO_NATIVE(id->rev);
3167 + id->class = TO_NATIVE(id->class);
3168 +
3169 + strcpy(alias, "bcma:");
3170 + ADD(alias, "m", id->manuf != BCMA_ANY_MANUF, id->manuf);
3171 + ADD(alias, "id", id->id != BCMA_ANY_ID, id->id);
3172 + ADD(alias, "rev", id->rev != BCMA_ANY_REV, id->rev);
3173 + ADD(alias, "cl", id->class != BCMA_ANY_CLASS, id->class);
3174 + add_wildcard(alias);
3175 + return 1;
3176 +}
3177 +
3178 /* Looks like: virtio:dNvN */
3179 static int do_virtio_entry(const char *filename, struct virtio_device_id *id,
3180 char *alias)
3181 @@ -845,6 +863,10 @@ void handle_moddevtable(struct module *m
3182 do_table(symval, sym->st_size,
3183 sizeof(struct ssb_device_id), "ssb",
3184 do_ssb_entry, mod);
3185 + else if (sym_is(symname, "__mod_bcma_device_table"))
3186 + do_table(symval, sym->st_size,
3187 + sizeof(struct bcma_device_id), "bcma",
3188 + do_bcma_entry, mod);
3189 else if (sym_is(symname, "__mod_virtio_device_table"))
3190 do_table(symval, sym->st_size,
3191 sizeof(struct virtio_device_id), "virtio",
3192 --- /dev/null
3193 +++ b/drivers/bcma/sprom.c
3194 @@ -0,0 +1,247 @@
3195 +/*
3196 + * Broadcom specific AMBA
3197 + * SPROM reading
3198 + *
3199 + * Licensed under the GNU/GPL. See COPYING for details.
3200 + */
3201 +
3202 +#include "bcma_private.h"
3203 +
3204 +#include <linux/bcma/bcma.h>
3205 +#include <linux/bcma/bcma_regs.h>
3206 +#include <linux/pci.h>
3207 +#include <linux/io.h>
3208 +#include <linux/dma-mapping.h>
3209 +#include <linux/slab.h>
3210 +
3211 +#define SPOFF(offset) ((offset) / sizeof(u16))
3212 +
3213 +/**************************************************
3214 + * R/W ops.
3215 + **************************************************/
3216 +
3217 +static void bcma_sprom_read(struct bcma_bus *bus, u16 offset, u16 *sprom)
3218 +{
3219 + int i;
3220 + for (i = 0; i < SSB_SPROMSIZE_WORDS_R4; i++)
3221 + sprom[i] = bcma_read16(bus->drv_cc.core,
3222 + offset + (i * 2));
3223 +}
3224 +
3225 +/**************************************************
3226 + * Validation.
3227 + **************************************************/
3228 +
3229 +static inline u8 bcma_crc8(u8 crc, u8 data)
3230 +{
3231 + /* Polynomial: x^8 + x^7 + x^6 + x^4 + x^2 + 1 */
3232 + static const u8 t[] = {
3233 + 0x00, 0xF7, 0xB9, 0x4E, 0x25, 0xD2, 0x9C, 0x6B,
3234 + 0x4A, 0xBD, 0xF3, 0x04, 0x6F, 0x98, 0xD6, 0x21,
3235 + 0x94, 0x63, 0x2D, 0xDA, 0xB1, 0x46, 0x08, 0xFF,
3236 + 0xDE, 0x29, 0x67, 0x90, 0xFB, 0x0C, 0x42, 0xB5,
3237 + 0x7F, 0x88, 0xC6, 0x31, 0x5A, 0xAD, 0xE3, 0x14,
3238 + 0x35, 0xC2, 0x8C, 0x7B, 0x10, 0xE7, 0xA9, 0x5E,
3239 + 0xEB, 0x1C, 0x52, 0xA5, 0xCE, 0x39, 0x77, 0x80,
3240 + 0xA1, 0x56, 0x18, 0xEF, 0x84, 0x73, 0x3D, 0xCA,
3241 + 0xFE, 0x09, 0x47, 0xB0, 0xDB, 0x2C, 0x62, 0x95,
3242 + 0xB4, 0x43, 0x0D, 0xFA, 0x91, 0x66, 0x28, 0xDF,
3243 + 0x6A, 0x9D, 0xD3, 0x24, 0x4F, 0xB8, 0xF6, 0x01,
3244 + 0x20, 0xD7, 0x99, 0x6E, 0x05, 0xF2, 0xBC, 0x4B,
3245 + 0x81, 0x76, 0x38, 0xCF, 0xA4, 0x53, 0x1D, 0xEA,
3246 + 0xCB, 0x3C, 0x72, 0x85, 0xEE, 0x19, 0x57, 0xA0,
3247 + 0x15, 0xE2, 0xAC, 0x5B, 0x30, 0xC7, 0x89, 0x7E,
3248 + 0x5F, 0xA8, 0xE6, 0x11, 0x7A, 0x8D, 0xC3, 0x34,
3249 + 0xAB, 0x5C, 0x12, 0xE5, 0x8E, 0x79, 0x37, 0xC0,
3250 + 0xE1, 0x16, 0x58, 0xAF, 0xC4, 0x33, 0x7D, 0x8A,
3251 + 0x3F, 0xC8, 0x86, 0x71, 0x1A, 0xED, 0xA3, 0x54,
3252 + 0x75, 0x82, 0xCC, 0x3B, 0x50, 0xA7, 0xE9, 0x1E,
3253 + 0xD4, 0x23, 0x6D, 0x9A, 0xF1, 0x06, 0x48, 0xBF,
3254 + 0x9E, 0x69, 0x27, 0xD0, 0xBB, 0x4C, 0x02, 0xF5,
3255 + 0x40, 0xB7, 0xF9, 0x0E, 0x65, 0x92, 0xDC, 0x2B,
3256 + 0x0A, 0xFD, 0xB3, 0x44, 0x2F, 0xD8, 0x96, 0x61,
3257 + 0x55, 0xA2, 0xEC, 0x1B, 0x70, 0x87, 0xC9, 0x3E,
3258 + 0x1F, 0xE8, 0xA6, 0x51, 0x3A, 0xCD, 0x83, 0x74,
3259 + 0xC1, 0x36, 0x78, 0x8F, 0xE4, 0x13, 0x5D, 0xAA,
3260 + 0x8B, 0x7C, 0x32, 0xC5, 0xAE, 0x59, 0x17, 0xE0,
3261 + 0x2A, 0xDD, 0x93, 0x64, 0x0F, 0xF8, 0xB6, 0x41,
3262 + 0x60, 0x97, 0xD9, 0x2E, 0x45, 0xB2, 0xFC, 0x0B,
3263 + 0xBE, 0x49, 0x07, 0xF0, 0x9B, 0x6C, 0x22, 0xD5,
3264 + 0xF4, 0x03, 0x4D, 0xBA, 0xD1, 0x26, 0x68, 0x9F,
3265 + };
3266 + return t[crc ^ data];
3267 +}
3268 +
3269 +static u8 bcma_sprom_crc(const u16 *sprom)
3270 +{
3271 + int word;
3272 + u8 crc = 0xFF;
3273 +
3274 + for (word = 0; word < SSB_SPROMSIZE_WORDS_R4 - 1; word++) {
3275 + crc = bcma_crc8(crc, sprom[word] & 0x00FF);
3276 + crc = bcma_crc8(crc, (sprom[word] & 0xFF00) >> 8);
3277 + }
3278 + crc = bcma_crc8(crc, sprom[SSB_SPROMSIZE_WORDS_R4 - 1] & 0x00FF);
3279 + crc ^= 0xFF;
3280 +
3281 + return crc;
3282 +}
3283 +
3284 +static int bcma_sprom_check_crc(const u16 *sprom)
3285 +{
3286 + u8 crc;
3287 + u8 expected_crc;
3288 + u16 tmp;
3289 +
3290 + crc = bcma_sprom_crc(sprom);
3291 + tmp = sprom[SSB_SPROMSIZE_WORDS_R4 - 1] & SSB_SPROM_REVISION_CRC;
3292 + expected_crc = tmp >> SSB_SPROM_REVISION_CRC_SHIFT;
3293 + if (crc != expected_crc)
3294 + return -EPROTO;
3295 +
3296 + return 0;
3297 +}
3298 +
3299 +static int bcma_sprom_valid(const u16 *sprom)
3300 +{
3301 + u16 revision;
3302 + int err;
3303 +
3304 + err = bcma_sprom_check_crc(sprom);
3305 + if (err)
3306 + return err;
3307 +
3308 + revision = sprom[SSB_SPROMSIZE_WORDS_R4 - 1] & SSB_SPROM_REVISION_REV;
3309 + if (revision != 8 && revision != 9) {
3310 + pr_err("Unsupported SPROM revision: %d\n", revision);
3311 + return -ENOENT;
3312 + }
3313 +
3314 + return 0;
3315 +}
3316 +
3317 +/**************************************************
3318 + * SPROM extraction.
3319 + **************************************************/
3320 +
3321 +static void bcma_sprom_extract_r8(struct bcma_bus *bus, const u16 *sprom)
3322 +{
3323 + u16 v;
3324 + int i;
3325 +
3326 + bus->sprom.revision = sprom[SSB_SPROMSIZE_WORDS_R4 - 1] &
3327 + SSB_SPROM_REVISION_REV;
3328 +
3329 + for (i = 0; i < 3; i++) {
3330 + v = sprom[SPOFF(SSB_SPROM8_IL0MAC) + i];
3331 + *(((__be16 *)bus->sprom.il0mac) + i) = cpu_to_be16(v);
3332 + }
3333 +
3334 + bus->sprom.board_rev = sprom[SPOFF(SSB_SPROM8_BOARDREV)];
3335 +
3336 + bus->sprom.txpid2g[0] = (sprom[SPOFF(SSB_SPROM4_TXPID2G01)] &
3337 + SSB_SPROM4_TXPID2G0) >> SSB_SPROM4_TXPID2G0_SHIFT;
3338 + bus->sprom.txpid2g[1] = (sprom[SPOFF(SSB_SPROM4_TXPID2G01)] &
3339 + SSB_SPROM4_TXPID2G1) >> SSB_SPROM4_TXPID2G1_SHIFT;
3340 + bus->sprom.txpid2g[2] = (sprom[SPOFF(SSB_SPROM4_TXPID2G23)] &
3341 + SSB_SPROM4_TXPID2G2) >> SSB_SPROM4_TXPID2G2_SHIFT;
3342 + bus->sprom.txpid2g[3] = (sprom[SPOFF(SSB_SPROM4_TXPID2G23)] &
3343 + SSB_SPROM4_TXPID2G3) >> SSB_SPROM4_TXPID2G3_SHIFT;
3344 +
3345 + bus->sprom.txpid5gl[0] = (sprom[SPOFF(SSB_SPROM4_TXPID5GL01)] &
3346 + SSB_SPROM4_TXPID5GL0) >> SSB_SPROM4_TXPID5GL0_SHIFT;
3347 + bus->sprom.txpid5gl[1] = (sprom[SPOFF(SSB_SPROM4_TXPID5GL01)] &
3348 + SSB_SPROM4_TXPID5GL1) >> SSB_SPROM4_TXPID5GL1_SHIFT;
3349 + bus->sprom.txpid5gl[2] = (sprom[SPOFF(SSB_SPROM4_TXPID5GL23)] &
3350 + SSB_SPROM4_TXPID5GL2) >> SSB_SPROM4_TXPID5GL2_SHIFT;
3351 + bus->sprom.txpid5gl[3] = (sprom[SPOFF(SSB_SPROM4_TXPID5GL23)] &
3352 + SSB_SPROM4_TXPID5GL3) >> SSB_SPROM4_TXPID5GL3_SHIFT;
3353 +
3354 + bus->sprom.txpid5g[0] = (sprom[SPOFF(SSB_SPROM4_TXPID5G01)] &
3355 + SSB_SPROM4_TXPID5G0) >> SSB_SPROM4_TXPID5G0_SHIFT;
3356 + bus->sprom.txpid5g[1] = (sprom[SPOFF(SSB_SPROM4_TXPID5G01)] &
3357 + SSB_SPROM4_TXPID5G1) >> SSB_SPROM4_TXPID5G1_SHIFT;
3358 + bus->sprom.txpid5g[2] = (sprom[SPOFF(SSB_SPROM4_TXPID5G23)] &
3359 + SSB_SPROM4_TXPID5G2) >> SSB_SPROM4_TXPID5G2_SHIFT;
3360 + bus->sprom.txpid5g[3] = (sprom[SPOFF(SSB_SPROM4_TXPID5G23)] &
3361 + SSB_SPROM4_TXPID5G3) >> SSB_SPROM4_TXPID5G3_SHIFT;
3362 +
3363 + bus->sprom.txpid5gh[0] = (sprom[SPOFF(SSB_SPROM4_TXPID5GH01)] &
3364 + SSB_SPROM4_TXPID5GH0) >> SSB_SPROM4_TXPID5GH0_SHIFT;
3365 + bus->sprom.txpid5gh[1] = (sprom[SPOFF(SSB_SPROM4_TXPID5GH01)] &
3366 + SSB_SPROM4_TXPID5GH1) >> SSB_SPROM4_TXPID5GH1_SHIFT;
3367 + bus->sprom.txpid5gh[2] = (sprom[SPOFF(SSB_SPROM4_TXPID5GH23)] &
3368 + SSB_SPROM4_TXPID5GH2) >> SSB_SPROM4_TXPID5GH2_SHIFT;
3369 + bus->sprom.txpid5gh[3] = (sprom[SPOFF(SSB_SPROM4_TXPID5GH23)] &
3370 + SSB_SPROM4_TXPID5GH3) >> SSB_SPROM4_TXPID5GH3_SHIFT;
3371 +
3372 + bus->sprom.boardflags_lo = sprom[SPOFF(SSB_SPROM8_BFLLO)];
3373 + bus->sprom.boardflags_hi = sprom[SPOFF(SSB_SPROM8_BFLHI)];
3374 + bus->sprom.boardflags2_lo = sprom[SPOFF(SSB_SPROM8_BFL2LO)];
3375 + bus->sprom.boardflags2_hi = sprom[SPOFF(SSB_SPROM8_BFL2HI)];
3376 +
3377 + bus->sprom.country_code = sprom[SPOFF(SSB_SPROM8_CCODE)];
3378 +
3379 + bus->sprom.fem.ghz2.tssipos = (sprom[SPOFF(SSB_SPROM8_FEM2G)] &
3380 + SSB_SROM8_FEM_TSSIPOS) >> SSB_SROM8_FEM_TSSIPOS_SHIFT;
3381 + bus->sprom.fem.ghz2.extpa_gain = (sprom[SPOFF(SSB_SPROM8_FEM2G)] &
3382 + SSB_SROM8_FEM_EXTPA_GAIN) >> SSB_SROM8_FEM_EXTPA_GAIN_SHIFT;
3383 + bus->sprom.fem.ghz2.pdet_range = (sprom[SPOFF(SSB_SPROM8_FEM2G)] &
3384 + SSB_SROM8_FEM_PDET_RANGE) >> SSB_SROM8_FEM_PDET_RANGE_SHIFT;
3385 + bus->sprom.fem.ghz2.tr_iso = (sprom[SPOFF(SSB_SPROM8_FEM2G)] &
3386 + SSB_SROM8_FEM_TR_ISO) >> SSB_SROM8_FEM_TR_ISO_SHIFT;
3387 + bus->sprom.fem.ghz2.antswlut = (sprom[SPOFF(SSB_SPROM8_FEM2G)] &
3388 + SSB_SROM8_FEM_ANTSWLUT) >> SSB_SROM8_FEM_ANTSWLUT_SHIFT;
3389 +
3390 + bus->sprom.fem.ghz5.tssipos = (sprom[SPOFF(SSB_SPROM8_FEM5G)] &
3391 + SSB_SROM8_FEM_TSSIPOS) >> SSB_SROM8_FEM_TSSIPOS_SHIFT;
3392 + bus->sprom.fem.ghz5.extpa_gain = (sprom[SPOFF(SSB_SPROM8_FEM5G)] &
3393 + SSB_SROM8_FEM_EXTPA_GAIN) >> SSB_SROM8_FEM_EXTPA_GAIN_SHIFT;
3394 + bus->sprom.fem.ghz5.pdet_range = (sprom[SPOFF(SSB_SPROM8_FEM5G)] &
3395 + SSB_SROM8_FEM_PDET_RANGE) >> SSB_SROM8_FEM_PDET_RANGE_SHIFT;
3396 + bus->sprom.fem.ghz5.tr_iso = (sprom[SPOFF(SSB_SPROM8_FEM5G)] &
3397 + SSB_SROM8_FEM_TR_ISO) >> SSB_SROM8_FEM_TR_ISO_SHIFT;
3398 + bus->sprom.fem.ghz5.antswlut = (sprom[SPOFF(SSB_SPROM8_FEM5G)] &
3399 + SSB_SROM8_FEM_ANTSWLUT) >> SSB_SROM8_FEM_ANTSWLUT_SHIFT;
3400 +}
3401 +
3402 +int bcma_sprom_get(struct bcma_bus *bus)
3403 +{
3404 + u16 offset;
3405 + u16 *sprom;
3406 + int err = 0;
3407 +
3408 + if (!bus->drv_cc.core)
3409 + return -EOPNOTSUPP;
3410 +
3411 + if (!(bus->drv_cc.capabilities & BCMA_CC_CAP_SPROM))
3412 + return -ENOENT;
3413 +
3414 + sprom = kcalloc(SSB_SPROMSIZE_WORDS_R4, sizeof(u16),
3415 + GFP_KERNEL);
3416 + if (!sprom)
3417 + return -ENOMEM;
3418 +
3419 + if (bus->chipinfo.id == 0x4331)
3420 + bcma_chipco_bcm4331_ext_pa_lines_ctl(&bus->drv_cc, false);
3421 +
3422 + /* Most cards have SPROM moved by additional offset 0x30 (48 dwords).
3423 + * According to brcm80211 this applies to cards with PCIe rev >= 6
3424 + * TODO: understand this condition and use it */
3425 + offset = (bus->chipinfo.id == 0x4331) ? BCMA_CC_SPROM :
3426 + BCMA_CC_SPROM_PCIE6;
3427 + bcma_sprom_read(bus, offset, sprom);
3428 +
3429 + if (bus->chipinfo.id == 0x4331)
3430 + bcma_chipco_bcm4331_ext_pa_lines_ctl(&bus->drv_cc, true);
3431 +
3432 + err = bcma_sprom_valid(sprom);
3433 + if (err)
3434 + goto out;
3435 +
3436 + bcma_sprom_extract_r8(bus, sprom);
3437 +
3438 +out:
3439 + kfree(sprom);
3440 + return err;
3441 +}
3442 --- /dev/null
3443 +++ b/drivers/bcma/driver_pci_host.c
3444 @@ -0,0 +1,14 @@
3445 +/*
3446 + * Broadcom specific AMBA
3447 + * PCI Core in hostmode
3448 + *
3449 + * Licensed under the GNU/GPL. See COPYING for details.
3450 + */
3451 +
3452 +#include "bcma_private.h"
3453 +#include <linux/bcma/bcma.h>
3454 +
3455 +void bcma_core_pci_hostmode_init(struct bcma_drv_pci *pc)
3456 +{
3457 + pr_err("No support for PCI core in hostmode yet\n");
3458 +}
3459 --- /dev/null
3460 +++ b/drivers/bcma/driver_mips.c
3461 @@ -0,0 +1,256 @@
3462 +/*
3463 + * Broadcom specific AMBA
3464 + * Broadcom MIPS32 74K core driver
3465 + *
3466 + * Copyright 2009, Broadcom Corporation
3467 + * Copyright 2006, 2007, Michael Buesch <mb@bu3sch.de>
3468 + * Copyright 2010, Bernhard Loos <bernhardloos@googlemail.com>
3469 + * Copyright 2011, Hauke Mehrtens <hauke@hauke-m.de>
3470 + *
3471 + * Licensed under the GNU/GPL. See COPYING for details.
3472 + */
3473 +
3474 +#include "bcma_private.h"
3475 +
3476 +#include <linux/bcma/bcma.h>
3477 +
3478 +#include <linux/serial.h>
3479 +#include <linux/serial_core.h>
3480 +#include <linux/serial_reg.h>
3481 +#include <linux/time.h>
3482 +
3483 +/* The 47162a0 hangs when reading MIPS DMP registers registers */
3484 +static inline bool bcma_core_mips_bcm47162a0_quirk(struct bcma_device *dev)
3485 +{
3486 + return dev->bus->chipinfo.id == 47162 && dev->bus->chipinfo.rev == 0 &&
3487 + dev->id.id == BCMA_CORE_MIPS_74K;
3488 +}
3489 +
3490 +/* The 5357b0 hangs when reading USB20H DMP registers */
3491 +static inline bool bcma_core_mips_bcm5357b0_quirk(struct bcma_device *dev)
3492 +{
3493 + return (dev->bus->chipinfo.id == 0x5357 ||
3494 + dev->bus->chipinfo.id == 0x4749) &&
3495 + dev->bus->chipinfo.pkg == 11 &&
3496 + dev->id.id == BCMA_CORE_USB20_HOST;
3497 +}
3498 +
3499 +static inline u32 mips_read32(struct bcma_drv_mips *mcore,
3500 + u16 offset)
3501 +{
3502 + return bcma_read32(mcore->core, offset);
3503 +}
3504 +
3505 +static inline void mips_write32(struct bcma_drv_mips *mcore,
3506 + u16 offset,
3507 + u32 value)
3508 +{
3509 + bcma_write32(mcore->core, offset, value);
3510 +}
3511 +
3512 +static const u32 ipsflag_irq_mask[] = {
3513 + 0,
3514 + BCMA_MIPS_IPSFLAG_IRQ1,
3515 + BCMA_MIPS_IPSFLAG_IRQ2,
3516 + BCMA_MIPS_IPSFLAG_IRQ3,
3517 + BCMA_MIPS_IPSFLAG_IRQ4,
3518 +};
3519 +
3520 +static const u32 ipsflag_irq_shift[] = {
3521 + 0,
3522 + BCMA_MIPS_IPSFLAG_IRQ1_SHIFT,
3523 + BCMA_MIPS_IPSFLAG_IRQ2_SHIFT,
3524 + BCMA_MIPS_IPSFLAG_IRQ3_SHIFT,
3525 + BCMA_MIPS_IPSFLAG_IRQ4_SHIFT,
3526 +};
3527 +
3528 +static u32 bcma_core_mips_irqflag(struct bcma_device *dev)
3529 +{
3530 + u32 flag;
3531 +
3532 + if (bcma_core_mips_bcm47162a0_quirk(dev))
3533 + return dev->core_index;
3534 + if (bcma_core_mips_bcm5357b0_quirk(dev))
3535 + return dev->core_index;
3536 + flag = bcma_aread32(dev, BCMA_MIPS_OOBSELOUTA30);
3537 +
3538 + return flag & 0x1F;
3539 +}
3540 +
3541 +/* Get the MIPS IRQ assignment for a specified device.
3542 + * If unassigned, 0 is returned.
3543 + */
3544 +unsigned int bcma_core_mips_irq(struct bcma_device *dev)
3545 +{
3546 + struct bcma_device *mdev = dev->bus->drv_mips.core;
3547 + u32 irqflag;
3548 + unsigned int irq;
3549 +
3550 + irqflag = bcma_core_mips_irqflag(dev);
3551 +
3552 + for (irq = 1; irq <= 4; irq++)
3553 + if (bcma_read32(mdev, BCMA_MIPS_MIPS74K_INTMASK(irq)) &
3554 + (1 << irqflag))
3555 + return irq;
3556 +
3557 + return 0;
3558 +}
3559 +EXPORT_SYMBOL(bcma_core_mips_irq);
3560 +
3561 +static void bcma_core_mips_set_irq(struct bcma_device *dev, unsigned int irq)
3562 +{
3563 + unsigned int oldirq = bcma_core_mips_irq(dev);
3564 + struct bcma_bus *bus = dev->bus;
3565 + struct bcma_device *mdev = bus->drv_mips.core;
3566 + u32 irqflag;
3567 +
3568 + irqflag = bcma_core_mips_irqflag(dev);
3569 + BUG_ON(oldirq == 6);
3570 +
3571 + dev->irq = irq + 2;
3572 +
3573 + /* clear the old irq */
3574 + if (oldirq == 0)
3575 + bcma_write32(mdev, BCMA_MIPS_MIPS74K_INTMASK(0),
3576 + bcma_read32(mdev, BCMA_MIPS_MIPS74K_INTMASK(0)) &
3577 + ~(1 << irqflag));
3578 + else
3579 + bcma_write32(mdev, BCMA_MIPS_MIPS74K_INTMASK(irq), 0);
3580 +
3581 + /* assign the new one */
3582 + if (irq == 0) {
3583 + bcma_write32(mdev, BCMA_MIPS_MIPS74K_INTMASK(0),
3584 + bcma_read32(mdev, BCMA_MIPS_MIPS74K_INTMASK(0)) |
3585 + (1 << irqflag));
3586 + } else {
3587 + u32 oldirqflag = bcma_read32(mdev,
3588 + BCMA_MIPS_MIPS74K_INTMASK(irq));
3589 + if (oldirqflag) {
3590 + struct bcma_device *core;
3591 +
3592 + /* backplane irq line is in use, find out who uses
3593 + * it and set user to irq 0
3594 + */
3595 + list_for_each_entry_reverse(core, &bus->cores, list) {
3596 + if ((1 << bcma_core_mips_irqflag(core)) ==
3597 + oldirqflag) {
3598 + bcma_core_mips_set_irq(core, 0);
3599 + break;
3600 + }
3601 + }
3602 + }
3603 + bcma_write32(mdev, BCMA_MIPS_MIPS74K_INTMASK(irq),
3604 + 1 << irqflag);
3605 + }
3606 +
3607 + pr_info("set_irq: core 0x%04x, irq %d => %d\n",
3608 + dev->id.id, oldirq + 2, irq + 2);
3609 +}
3610 +
3611 +static void bcma_core_mips_print_irq(struct bcma_device *dev, unsigned int irq)
3612 +{
3613 + int i;
3614 + static const char *irq_name[] = {"2(S)", "3", "4", "5", "6", "D", "I"};
3615 + printk(KERN_INFO KBUILD_MODNAME ": core 0x%04x, irq :", dev->id.id);
3616 + for (i = 0; i <= 6; i++)
3617 + printk(" %s%s", irq_name[i], i == irq ? "*" : " ");
3618 + printk("\n");
3619 +}
3620 +
3621 +static void bcma_core_mips_dump_irq(struct bcma_bus *bus)
3622 +{
3623 + struct bcma_device *core;
3624 +
3625 + list_for_each_entry_reverse(core, &bus->cores, list) {
3626 + bcma_core_mips_print_irq(core, bcma_core_mips_irq(core));
3627 + }
3628 +}
3629 +
3630 +u32 bcma_cpu_clock(struct bcma_drv_mips *mcore)
3631 +{
3632 + struct bcma_bus *bus = mcore->core->bus;
3633 +
3634 + if (bus->drv_cc.capabilities & BCMA_CC_CAP_PMU)
3635 + return bcma_pmu_get_clockcpu(&bus->drv_cc);
3636 +
3637 + pr_err("No PMU available, need this to get the cpu clock\n");
3638 + return 0;
3639 +}
3640 +EXPORT_SYMBOL(bcma_cpu_clock);
3641 +
3642 +static void bcma_core_mips_flash_detect(struct bcma_drv_mips *mcore)
3643 +{
3644 + struct bcma_bus *bus = mcore->core->bus;
3645 +
3646 + switch (bus->drv_cc.capabilities & BCMA_CC_CAP_FLASHT) {
3647 + case BCMA_CC_FLASHT_STSER:
3648 + case BCMA_CC_FLASHT_ATSER:
3649 + pr_err("Serial flash not supported.\n");
3650 + break;
3651 + case BCMA_CC_FLASHT_PARA:
3652 + pr_info("found parallel flash.\n");
3653 + bus->drv_cc.pflash.window = 0x1c000000;
3654 + bus->drv_cc.pflash.window_size = 0x02000000;
3655 +
3656 + if ((bcma_read32(bus->drv_cc.core, BCMA_CC_FLASH_CFG) &
3657 + BCMA_CC_FLASH_CFG_DS) == 0)
3658 + bus->drv_cc.pflash.buswidth = 1;
3659 + else
3660 + bus->drv_cc.pflash.buswidth = 2;
3661 + break;
3662 + default:
3663 + pr_err("flash not supported.\n");
3664 + }
3665 +}
3666 +
3667 +void bcma_core_mips_init(struct bcma_drv_mips *mcore)
3668 +{
3669 + struct bcma_bus *bus;
3670 + struct bcma_device *core;
3671 + bus = mcore->core->bus;
3672 +
3673 + pr_info("Initializing MIPS core...\n");
3674 +
3675 + if (!mcore->setup_done)
3676 + mcore->assigned_irqs = 1;
3677 +
3678 + /* Assign IRQs to all cores on the bus */
3679 + list_for_each_entry_reverse(core, &bus->cores, list) {
3680 + int mips_irq;
3681 + if (core->irq)
3682 + continue;
3683 +
3684 + mips_irq = bcma_core_mips_irq(core);
3685 + if (mips_irq > 4)
3686 + core->irq = 0;
3687 + else
3688 + core->irq = mips_irq + 2;
3689 + if (core->irq > 5)
3690 + continue;
3691 + switch (core->id.id) {
3692 + case BCMA_CORE_PCI:
3693 + case BCMA_CORE_PCIE:
3694 + case BCMA_CORE_ETHERNET:
3695 + case BCMA_CORE_ETHERNET_GBIT:
3696 + case BCMA_CORE_MAC_GBIT:
3697 + case BCMA_CORE_80211:
3698 + case BCMA_CORE_USB20_HOST:
3699 + /* These devices get their own IRQ line if available,
3700 + * the rest goes on IRQ0
3701 + */
3702 + if (mcore->assigned_irqs <= 4)
3703 + bcma_core_mips_set_irq(core,
3704 + mcore->assigned_irqs++);
3705 + break;
3706 + }
3707 + }
3708 + pr_info("IRQ reconfiguration done\n");
3709 + bcma_core_mips_dump_irq(bus);
3710 +
3711 + if (mcore->setup_done)
3712 + return;
3713 +
3714 + bcma_chipco_serial_init(&bus->drv_cc);
3715 + bcma_core_mips_flash_detect(mcore);
3716 + mcore->setup_done = true;
3717 +}
3718 --- /dev/null
3719 +++ b/drivers/bcma/host_soc.c
3720 @@ -0,0 +1,183 @@
3721 +/*
3722 + * Broadcom specific AMBA
3723 + * System on Chip (SoC) Host
3724 + *
3725 + * Licensed under the GNU/GPL. See COPYING for details.
3726 + */
3727 +
3728 +#include "bcma_private.h"
3729 +#include "scan.h"
3730 +#include <linux/bcma/bcma.h>
3731 +#include <linux/bcma/bcma_soc.h>
3732 +
3733 +static u8 bcma_host_soc_read8(struct bcma_device *core, u16 offset)
3734 +{
3735 + return readb(core->io_addr + offset);
3736 +}
3737 +
3738 +static u16 bcma_host_soc_read16(struct bcma_device *core, u16 offset)
3739 +{
3740 + return readw(core->io_addr + offset);
3741 +}
3742 +
3743 +static u32 bcma_host_soc_read32(struct bcma_device *core, u16 offset)
3744 +{
3745 + return readl(core->io_addr + offset);
3746 +}
3747 +
3748 +static void bcma_host_soc_write8(struct bcma_device *core, u16 offset,
3749 + u8 value)
3750 +{
3751 + writeb(value, core->io_addr + offset);
3752 +}
3753 +
3754 +static void bcma_host_soc_write16(struct bcma_device *core, u16 offset,
3755 + u16 value)
3756 +{
3757 + writew(value, core->io_addr + offset);
3758 +}
3759 +
3760 +static void bcma_host_soc_write32(struct bcma_device *core, u16 offset,
3761 + u32 value)
3762 +{
3763 + writel(value, core->io_addr + offset);
3764 +}
3765 +
3766 +#ifdef CONFIG_BCMA_BLOCKIO
3767 +static void bcma_host_soc_block_read(struct bcma_device *core, void *buffer,
3768 + size_t count, u16 offset, u8 reg_width)
3769 +{
3770 + void __iomem *addr = core->io_addr + offset;
3771 +
3772 + switch (reg_width) {
3773 + case sizeof(u8): {
3774 + u8 *buf = buffer;
3775 +
3776 + while (count) {
3777 + *buf = __raw_readb(addr);
3778 + buf++;
3779 + count--;
3780 + }
3781 + break;
3782 + }
3783 + case sizeof(u16): {
3784 + __le16 *buf = buffer;
3785 +
3786 + WARN_ON(count & 1);
3787 + while (count) {
3788 + *buf = (__force __le16)__raw_readw(addr);
3789 + buf++;
3790 + count -= 2;
3791 + }
3792 + break;
3793 + }
3794 + case sizeof(u32): {
3795 + __le32 *buf = buffer;
3796 +
3797 + WARN_ON(count & 3);
3798 + while (count) {
3799 + *buf = (__force __le32)__raw_readl(addr);
3800 + buf++;
3801 + count -= 4;
3802 + }
3803 + break;
3804 + }
3805 + default:
3806 + WARN_ON(1);
3807 + }
3808 +}
3809 +
3810 +static void bcma_host_soc_block_write(struct bcma_device *core,
3811 + const void *buffer,
3812 + size_t count, u16 offset, u8 reg_width)
3813 +{
3814 + void __iomem *addr = core->io_addr + offset;
3815 +
3816 + switch (reg_width) {
3817 + case sizeof(u8): {
3818 + const u8 *buf = buffer;
3819 +
3820 + while (count) {
3821 + __raw_writeb(*buf, addr);
3822 + buf++;
3823 + count--;
3824 + }
3825 + break;
3826 + }
3827 + case sizeof(u16): {
3828 + const __le16 *buf = buffer;
3829 +
3830 + WARN_ON(count & 1);
3831 + while (count) {
3832 + __raw_writew((__force u16)(*buf), addr);
3833 + buf++;
3834 + count -= 2;
3835 + }
3836 + break;
3837 + }
3838 + case sizeof(u32): {
3839 + const __le32 *buf = buffer;
3840 +
3841 + WARN_ON(count & 3);
3842 + while (count) {
3843 + __raw_writel((__force u32)(*buf), addr);
3844 + buf++;
3845 + count -= 4;
3846 + }
3847 + break;
3848 + }
3849 + default:
3850 + WARN_ON(1);
3851 + }
3852 +}
3853 +#endif /* CONFIG_BCMA_BLOCKIO */
3854 +
3855 +static u32 bcma_host_soc_aread32(struct bcma_device *core, u16 offset)
3856 +{
3857 + return readl(core->io_wrap + offset);
3858 +}
3859 +
3860 +static void bcma_host_soc_awrite32(struct bcma_device *core, u16 offset,
3861 + u32 value)
3862 +{
3863 + writel(value, core->io_wrap + offset);
3864 +}
3865 +
3866 +const struct bcma_host_ops bcma_host_soc_ops = {
3867 + .read8 = bcma_host_soc_read8,
3868 + .read16 = bcma_host_soc_read16,
3869 + .read32 = bcma_host_soc_read32,
3870 + .write8 = bcma_host_soc_write8,
3871 + .write16 = bcma_host_soc_write16,
3872 + .write32 = bcma_host_soc_write32,
3873 +#ifdef CONFIG_BCMA_BLOCKIO
3874 + .block_read = bcma_host_soc_block_read,
3875 + .block_write = bcma_host_soc_block_write,
3876 +#endif
3877 + .aread32 = bcma_host_soc_aread32,
3878 + .awrite32 = bcma_host_soc_awrite32,
3879 +};
3880 +
3881 +int __init bcma_host_soc_register(struct bcma_soc *soc)
3882 +{
3883 + struct bcma_bus *bus = &soc->bus;
3884 + int err;
3885 +
3886 + /* iomap only first core. We have to read some register on this core
3887 + * to scan the bus.
3888 + */
3889 + bus->mmio = ioremap_nocache(BCMA_ADDR_BASE, BCMA_CORE_SIZE * 1);
3890 + if (!bus->mmio)
3891 + return -ENOMEM;
3892 +
3893 + /* Host specific */
3894 + bus->hosttype = BCMA_HOSTTYPE_SOC;
3895 + bus->ops = &bcma_host_soc_ops;
3896 +
3897 + /* Register */
3898 + err = bcma_bus_early_register(bus, &soc->core_cc, &soc->core_mips);
3899 + if (err)
3900 + iounmap(bus->mmio);
3901 +
3902 + return err;
3903 +}
3904 --- /dev/null
3905 +++ b/include/linux/bcma/bcma_driver_mips.h
3906 @@ -0,0 +1,51 @@
3907 +#ifndef LINUX_BCMA_DRIVER_MIPS_H_
3908 +#define LINUX_BCMA_DRIVER_MIPS_H_
3909 +
3910 +#define BCMA_MIPS_IPSFLAG 0x0F08
3911 +/* which sbflags get routed to mips interrupt 1 */
3912 +#define BCMA_MIPS_IPSFLAG_IRQ1 0x0000003F
3913 +#define BCMA_MIPS_IPSFLAG_IRQ1_SHIFT 0
3914 +/* which sbflags get routed to mips interrupt 2 */
3915 +#define BCMA_MIPS_IPSFLAG_IRQ2 0x00003F00
3916 +#define BCMA_MIPS_IPSFLAG_IRQ2_SHIFT 8
3917 +/* which sbflags get routed to mips interrupt 3 */
3918 +#define BCMA_MIPS_IPSFLAG_IRQ3 0x003F0000
3919 +#define BCMA_MIPS_IPSFLAG_IRQ3_SHIFT 16
3920 +/* which sbflags get routed to mips interrupt 4 */
3921 +#define BCMA_MIPS_IPSFLAG_IRQ4 0x3F000000
3922 +#define BCMA_MIPS_IPSFLAG_IRQ4_SHIFT 24
3923 +
3924 +/* MIPS 74K core registers */
3925 +#define BCMA_MIPS_MIPS74K_CORECTL 0x0000
3926 +#define BCMA_MIPS_MIPS74K_EXCEPTBASE 0x0004
3927 +#define BCMA_MIPS_MIPS74K_BIST 0x000C
3928 +#define BCMA_MIPS_MIPS74K_INTMASK_INT0 0x0014
3929 +#define BCMA_MIPS_MIPS74K_INTMASK(int) \
3930 + ((int) * 4 + BCMA_MIPS_MIPS74K_INTMASK_INT0)
3931 +#define BCMA_MIPS_MIPS74K_NMIMASK 0x002C
3932 +#define BCMA_MIPS_MIPS74K_GPIOSEL 0x0040
3933 +#define BCMA_MIPS_MIPS74K_GPIOOUT 0x0044
3934 +#define BCMA_MIPS_MIPS74K_GPIOEN 0x0048
3935 +#define BCMA_MIPS_MIPS74K_CLKCTLST 0x01E0
3936 +
3937 +#define BCMA_MIPS_OOBSELOUTA30 0x100
3938 +
3939 +struct bcma_device;
3940 +
3941 +struct bcma_drv_mips {
3942 + struct bcma_device *core;
3943 + u8 setup_done:1;
3944 + unsigned int assigned_irqs;
3945 +};
3946 +
3947 +#ifdef CONFIG_BCMA_DRIVER_MIPS
3948 +extern void bcma_core_mips_init(struct bcma_drv_mips *mcore);
3949 +#else
3950 +static inline void bcma_core_mips_init(struct bcma_drv_mips *mcore) { }
3951 +#endif
3952 +
3953 +extern u32 bcma_cpu_clock(struct bcma_drv_mips *mcore);
3954 +
3955 +extern unsigned int bcma_core_mips_irq(struct bcma_device *dev);
3956 +
3957 +#endif /* LINUX_BCMA_DRIVER_MIPS_H_ */
3958 --- /dev/null
3959 +++ b/include/linux/bcma/bcma_soc.h
3960 @@ -0,0 +1,16 @@
3961 +#ifndef LINUX_BCMA_SOC_H_
3962 +#define LINUX_BCMA_SOC_H_
3963 +
3964 +#include <linux/bcma/bcma.h>
3965 +
3966 +struct bcma_soc {
3967 + struct bcma_bus bus;
3968 + struct bcma_device core_cc;
3969 + struct bcma_device core_mips;
3970 +};
3971 +
3972 +int __init bcma_host_soc_register(struct bcma_soc *soc);
3973 +
3974 +int bcma_bus_register(struct bcma_bus *bus);
3975 +
3976 +#endif /* LINUX_BCMA_SOC_H_ */
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