ath9k: rework tx power handling - display the correct *current* tx power, and also...
[openwrt.git] / package / uboot-lantiq / arcadyan_psc166_64.conf
1 0xbf800060 0x7
2 0xbf800010 0x0
3 0xbf800020 0x0
4 0xbf800200 0x02
5 0xbf800210 0x0
6
7 ;REG32(MC_DC0) = 0x00001B1B;
8 0xbf801000 0x1b1b
9 ;REG32(MC_DC1) = 0x00000000;
10 0xbf801010 0x0
11 ;REG32(MC_DC2) = 0x00000000;
12 0xbf801020 0x0
13 ;REG32(MC_DC3) = 0x00000000;
14 0xbf801030 0x0
15 ;REG32(MC_DC4) = 0x00000000;
16 0xbf801040 0x0
17 ;REG32(MC_DC5) = 0x00000200;
18 0xbf801050 0x200
19 ;REG32(MC_DC6) = 0x00000306;
20 ; 0xbf801060 0x0306
21 0xbf801060 0x0605
22 ;REG32(MC_DC7) = 0x00000303;
23 ; 0xbf801070 0x302
24 ; 0xbf801070 0x0203
25 0xbf801070 0x0303
26 ;REG32(MC_DC8) = 0x00000102;
27 0xbf801080 0x102
28 ;REG32(MC_DC9) = 0x0000070A;
29 0xbf801090 0x70a
30 ; 0xbf801090 0x608
31 ;REG32(MC_DC10) = 0x00000203;
32 0xbf8010a0 0x203
33 ;REG32(MC_DC11) = 0x00000C02;
34 0xbf8010b0 0xc02
35 ; 0xbf8010b0 0x0a02
36 ;REG32(MC_DC12) = 0x000001C8;
37 0xbf8010c0 0x1c8
38 ;REG32(MC_DC13) = 0x00000001;
39 0xbf8010d0 0x1
40 ;REG32(MC_DC14) = 0x00000000;
41 0xbf8010e0 0x0
42 ;REG32(MC_DC15) = 0x00000F5F;
43 ; 0xbf8010f0 0xf5f
44 ; 0xbf8010f0 0xf3c
45 0xbf8010f0 0x130
46 ;REG32(MC_DC16) = 0x0000C800;
47 0xbf801100 0xc800
48 ;REG32(MC_DC17) = 0x0000000D;
49 ; 0xbf801110 0xd
50 0xbf801110 0xd
51 ;REG32(MC_DC18) = 0x00000300;
52 ; 0xbf801120 0x300
53 0xbf801120 0x301
54 ;REG32(MC_DC19) = 0x00000300;
55 ; 0xbf801130 0x300
56 0xbf801130 0x200
57 ;REG32(MC_DC20) = 0x00000A04;
58 ; 0xbf801140 0xa04
59 0xbf801140 0xa03
60 ;REG32(MC_DC21) = 0x00001c00;
61 ; 0xbf801150 0xd00
62 ; 0xbf801150 0x1f00
63 0xbf801150 0x1b00
64 ;REG32(MC_DC22) = 0x00001E1E;
65 ; 0xbf801160 0xd0d
66 ; 0xbf801160 0x1f1f
67 0xbf801160 0x1b1b
68 ;REG32(MC_DC23) = 0x00000000;
69 0xbf801170 0x0
70 ;//Disable ECC
71 ;REG32(MC_DC24) = 0x0000007F;
72 ; 0xbf801180 0x7f
73 ; 0xbf801180 0x062
74 ; 0xbf801180 0x37f
75 0xbf801180 0x59
76 ;REG32(MC_DC25) = 0x00000000;
77 0xbf801190 0x0
78 ;REG32(MC_DC26) = 0x00000000;
79 0xbf8011a0 0x0
80 ;REG32(MC_DC27) = 0x00000000;
81 0xbf8011b0 0x0
82 ;REG32(MC_DC28) = 0x00000A24;
83 ; 0xbf8011c0 0xa24
84 0xbf8011c0 0x510
85 ;REG32(MC_DC29) = 0x00002D89;
86 ; 0xbf8011d0 0x2d89
87 ; 0xbf8011d0 0x2d92
88 0xbf8011d0 0x4e20
89 ;REG32(MC_DC30) = 0x00000022;
90 ; 0xbf8011e0 0x8300
91 0xbf8011e0 0x8235
92 ;REG32(MC_DC31) = 0x00000000;
93 0xbf8011f0 0x0
94 ;REG32(MC_DC32) = 0x00000000;
95 0xbf801200 0x0
96 ;REG32(MC_DC33) = 0x00000000;
97 0xbf801210 0x0
98 ;REG32(MC_DC34) = 0x00000000;
99 0xbf801220 0x0
100 ;REG32(MC_DC35) = 0x00000000;
101 0xbf801230 0x0
102 ;REG32(MC_DC36) = 0x00000000;
103 0xbf801240 0x0
104 ;REG32(MC_DC37) = 0x00000000;
105 0xbf801250 0x0
106 ;REG32(MC_DC38) = 0x00000000;
107 0xbf801260 0x0
108 ;REG32(MC_DC39) = 0x00000000;
109 0xbf801270 0x0
110 ;REG32(MC_DC40) = 0x00000000;
111 0xbf801280 0x0
112 ;REG32(MC_DC41) = 0x00000000;
113 0xbf801290 0x0
114 ;REG32(MC_DC42) = 0x00000000;
115 0xbf8012a0 0x0
116 ;REG32(MC_DC43) = 0x00000000;
117 0xbf8012b0 0x0
118 ;REG32(MC_DC44) = 0x00000000;
119 0xbf8012c0 0x0
120 ;REG32(MC_DC45) = 0x00000600;
121 0xbf8012d0 0x500
122 ;REG32(MC_DC46) = 0x00000000;
123 0xbf8012e0 0x0
124
125 0xbf800060 0x05
126 0xbf801030 0x100
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
This page took 0.047982 seconds and 5 git commands to generate.