target/linux/ar7/patches-2.6.30/100-board_support.patch

   1 --- a/arch/mips/Kconfig
   2 +++ b/arch/mips/Kconfig
   3 @@ -19,6 +19,24 @@ choice
   4         prompt "System type"
   5         default SGI_IP22
   6
   7 +config AR7
   8 +       bool "Texas Instruments AR7"
   9 +       select BOOT_ELF32
  10 +       select DMA_NONCOHERENT
  11 +       select CEVT_R4K
  12 +       select CSRC_R4K
  13 +       select IRQ_CPU
  14 +       select NO_EXCEPT_FILL
  15 +       select SWAP_IO_SPACE
  16 +       select SYS_HAS_CPU_MIPS32_R1
  17 +       select SYS_HAS_EARLY_PRINTK
  18 +       select SYS_SUPPORTS_32BIT_KERNEL
  19 +       select SYS_SUPPORTS_KGDB
  20 +       select SYS_SUPPORTS_LITTLE_ENDIAN
  21 +       select SYS_SUPPORTS_BIG_ENDIAN
  22 +       select GENERIC_GPIO
  23 +       select GENERIC_HARDIRQS_NO__DO_IRQ
  24 +
  25  config MACH_ALCHEMY
  26         bool "Alchemy processor based machines"
  27
  28 --- a/arch/mips/kernel/traps.c
  29 +++ b/arch/mips/kernel/traps.c
  30 @@ -1256,9 +1256,22 @@ void *set_except_vector(int n, void *add
  31
  32         exception_handlers[n] = handler;
  33         if (n == 0 && cpu_has_divec) {
  34 -               *(u32 *)(ebase + 0x200) = 0x08000000 |
  35 -                                         (0x03ffffff & (handler >> 2));
  36 -               local_flush_icache_range(ebase + 0x200, ebase + 0x204);
  37 +               if ((handler ^ (ebase + 4)) & 0xfc000000) {
  38 +                       /* lui k0, 0x0000 */
  39 +                       *(u32 *)(ebase + 0x200) = 0x3c1a0000 | (handler >> 16);
  40 +                       /* ori k0, 0x0000 */
  41 +                       *(u32 *)(ebase + 0x204) =
  42 +                                       0x375a0000 | (handler & 0xffff);
  43 +                       /* jr k0 */
  44 +                       *(u32 *)(ebase + 0x208) = 0x03400008;
  45 +                       /* nop */
  46 +                       *(u32 *)(ebase + 0x20C) = 0x00000000;
  47 +                       flush_icache_range(ebase + 0x200, ebase + 0x210);
  48 +               } else {
  49 +                       *(u32 *)(ebase + 0x200) =
  50 +                               0x08000000 | (0x03ffffff & (handler >> 2));
  51 +                       flush_icache_range(ebase + 0x200, ebase + 0x204);
  52 +               }
  53         }
  54         return (void *)old_handler;
  55  }
  56 --- a/arch/mips/Makefile
  57 +++ b/arch/mips/Makefile
  58 @@ -174,6 +174,13 @@ libs-$(CONFIG_SIBYTE_CFE)  += arch/mips/s
  59  #
  60
  61  #
  62 +# Texas Instruments AR7
  63 +#
  64 +core-$(CONFIG_AR7)             += arch/mips/ar7/
  65 +cflags-$(CONFIG_AR7)           += -Iinclude/asm-mips/ar7
  66 +load-$(CONFIG_AR7)             += 0xffffffff94100000
  67 +
  68 +#
  69  # Acer PICA 61, Mips Magnum 4000 and Olivetti M700.
  70  #
  71  core-$(CONFIG_MACH_JAZZ)       += arch/mips/jazz/
  72 --- a/arch/mips/include/asm/page.h
  73 +++ b/arch/mips/include/asm/page.h
  74 @@ -185,8 +185,10 @@ typedef struct { unsigned long pgprot; }
  75  #define VM_DATA_DEFAULT_FLAGS  (VM_READ | VM_WRITE | VM_EXEC | \
  76                                  VM_MAYREAD | VM_MAYWRITE | VM_MAYEXEC)
  77
  78 -#define UNCAC_ADDR(addr)       ((addr) - PAGE_OFFSET + UNCAC_BASE)
  79 -#define CAC_ADDR(addr)         ((addr) - UNCAC_BASE + PAGE_OFFSET)
  80 +#define UNCAC_ADDR(addr)       ((addr) - PAGE_OFFSET + UNCAC_BASE +    \
  81 +                                PHYS_OFFSET)
  82 +#define CAC_ADDR(addr)         ((addr) - UNCAC_BASE + PAGE_OFFSET -    \
  83 +                                PHYS_OFFSET)
  84
  85  #include <asm-generic/memory_model.h>
  86  #include <asm-generic/page.h>