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generic: ar8216: allow to use more ports
[openwrt.git] / target / linux / lantiq / patches / 0006-MIPS-lantiq-add-basic-support-for-FALC-ON.patch
1 From ff57bc17a9964d24708759c6d78a51e337563d5f Mon Sep 17 00:00:00 2001
2 From: John Crispin <blogic@openwrt.org>
3 Date: Thu, 11 Aug 2011 14:33:04 +0200
4 Subject: [PATCH 06/24] MIPS: lantiq: add basic support for FALC-ON
5
6 Adds support for the FALC-ON SoC. This SoC is from the fiber to the home GPON
7 series.
8
9 Signed-off-by: John Crispin <blogic@openwrt.org>
10 Signed-off-by: Thomas Langer <thomas.langer@lantiq.com>
11 Cc: linux-mips@linux-mips.org
12 ---
13 .../include/asm/mach-lantiq/falcon/falcon_irq.h | 268 ++++++++++++++++++++
14 arch/mips/include/asm/mach-lantiq/falcon/irq.h | 18 ++
15 .../include/asm/mach-lantiq/falcon/lantiq_soc.h | 140 ++++++++++
16 arch/mips/include/asm/mach-lantiq/lantiq.h | 1 +
17 arch/mips/lantiq/Kconfig | 4 +
18 arch/mips/lantiq/Makefile | 1 +
19 arch/mips/lantiq/Platform | 1 +
20 arch/mips/lantiq/falcon/Makefile | 1 +
21 arch/mips/lantiq/falcon/clk.c | 44 ++++
22 arch/mips/lantiq/falcon/devices.c | 87 +++++++
23 arch/mips/lantiq/falcon/devices.h | 18 ++
24 arch/mips/lantiq/falcon/prom.c | 72 ++++++
25 arch/mips/lantiq/falcon/reset.c | 87 +++++++
26 arch/mips/lantiq/falcon/sysctrl.c | 181 +++++++++++++
27 14 files changed, 923 insertions(+), 0 deletions(-)
28 create mode 100644 arch/mips/include/asm/mach-lantiq/falcon/falcon_irq.h
29 create mode 100644 arch/mips/include/asm/mach-lantiq/falcon/irq.h
30 create mode 100644 arch/mips/include/asm/mach-lantiq/falcon/lantiq_soc.h
31 create mode 100644 arch/mips/lantiq/falcon/Makefile
32 create mode 100644 arch/mips/lantiq/falcon/clk.c
33 create mode 100644 arch/mips/lantiq/falcon/devices.c
34 create mode 100644 arch/mips/lantiq/falcon/devices.h
35 create mode 100644 arch/mips/lantiq/falcon/prom.c
36 create mode 100644 arch/mips/lantiq/falcon/reset.c
37 create mode 100644 arch/mips/lantiq/falcon/sysctrl.c
38
39 --- /dev/null
40 +++ b/arch/mips/include/asm/mach-lantiq/falcon/falcon_irq.h
41 @@ -0,0 +1,268 @@
42 +/*
43 + * This program is free software; you can redistribute it and/or modify it
44 + * under the terms of the GNU General Public License version 2 as published
45 + * by the Free Software Foundation.
46 + *
47 + * Copyright (C) 2010 Thomas Langer <thomas.langer@lantiq.com>
48 + */
49 +
50 +#ifndef _FALCON_IRQ__
51 +#define _FALCON_IRQ__
52 +
53 +#define INT_NUM_IRQ0 8
54 +#define INT_NUM_IM0_IRL0 (INT_NUM_IRQ0 + 0)
55 +#define INT_NUM_IM1_IRL0 (INT_NUM_IM0_IRL0 + 32)
56 +#define INT_NUM_IM2_IRL0 (INT_NUM_IM1_IRL0 + 32)
57 +#define INT_NUM_IM3_IRL0 (INT_NUM_IM2_IRL0 + 32)
58 +#define INT_NUM_IM4_IRL0 (INT_NUM_IM3_IRL0 + 32)
59 +#define INT_NUM_EXTRA_START (INT_NUM_IM4_IRL0 + 32)
60 +#define INT_NUM_IM_OFFSET (INT_NUM_IM1_IRL0 - INT_NUM_IM0_IRL0)
61 +
62 +#define MIPS_CPU_TIMER_IRQ 7
63 +
64 +/* HOST IF Event Interrupt */
65 +#define FALCON_IRQ_HOST (INT_NUM_IM0_IRL0 + 0)
66 +/* HOST IF Mailbox0 Receive Interrupt */
67 +#define FALCON_IRQ_HOST_MB0_RX (INT_NUM_IM0_IRL0 + 1)
68 +/* HOST IF Mailbox0 Transmit Interrupt */
69 +#define FALCON_IRQ_HOST_MB0_TX (INT_NUM_IM0_IRL0 + 2)
70 +/* HOST IF Mailbox1 Receive Interrupt */
71 +#define FALCON_IRQ_HOST_MB1_RX (INT_NUM_IM0_IRL0 + 3)
72 +/* HOST IF Mailbox1 Transmit Interrupt */
73 +#define FALCON_IRQ_HOST_MB1_TX (INT_NUM_IM0_IRL0 + 4)
74 +/* I2C Last Single Data Transfer Request */
75 +#define FALCON_IRQ_I2C_LSREQ (INT_NUM_IM0_IRL0 + 8)
76 +/* I2C Single Data Transfer Request */
77 +#define FALCON_IRQ_I2C_SREQ (INT_NUM_IM0_IRL0 + 9)
78 +/* I2C Last Burst Data Transfer Request */
79 +#define FALCON_IRQ_I2C_LBREQ (INT_NUM_IM0_IRL0 + 10)
80 +/* I2C Burst Data Transfer Request */
81 +#define FALCON_IRQ_I2C_BREQ (INT_NUM_IM0_IRL0 + 11)
82 +/* I2C Error Interrupt */
83 +#define FALCON_IRQ_I2C_I2C_ERR (INT_NUM_IM0_IRL0 + 12)
84 +/* I2C Protocol Interrupt */
85 +#define FALCON_IRQ_I2C_I2C_P (INT_NUM_IM0_IRL0 + 13)
86 +/* SSC Transmit Interrupt */
87 +#define FALCON_IRQ_SSC_T (INT_NUM_IM0_IRL0 + 14)
88 +/* SSC Receive Interrupt */
89 +#define FALCON_IRQ_SSC_R (INT_NUM_IM0_IRL0 + 15)
90 +/* SSC Error Interrupt */
91 +#define FALCON_IRQ_SSC_E (INT_NUM_IM0_IRL0 + 16)
92 +/* SSC Frame Interrupt */
93 +#define FALCON_IRQ_SSC_F (INT_NUM_IM0_IRL0 + 17)
94 +/* Advanced Encryption Standard Interrupt */
95 +#define FALCON_IRQ_AES_AES (INT_NUM_IM0_IRL0 + 27)
96 +/* Secure Hash Algorithm Interrupt */
97 +#define FALCON_IRQ_SHA_HASH (INT_NUM_IM0_IRL0 + 28)
98 +/* PCM Receive Interrupt */
99 +#define FALCON_IRQ_PCM_RX (INT_NUM_IM0_IRL0 + 29)
100 +/* PCM Transmit Interrupt */
101 +#define FALCON_IRQ_PCM_TX (INT_NUM_IM0_IRL0 + 30)
102 +/* PCM Transmit Crash Interrupt */
103 +#define FALCON_IRQ_PCM_HW2_CRASH (INT_NUM_IM0_IRL0 + 31)
104 +
105 +/* EBU Serial Flash Command Error */
106 +#define FALCON_IRQ_EBU_SF_CMDERR (INT_NUM_IM1_IRL0 + 0)
107 +/* EBU Serial Flash Command Overwrite Error */
108 +#define FALCON_IRQ_EBU_SF_COVERR (INT_NUM_IM1_IRL0 + 1)
109 +/* EBU Serial Flash Busy */
110 +#define FALCON_IRQ_EBU_SF_BUSY (INT_NUM_IM1_IRL0 + 2)
111 +/* External Interrupt from GPIO P0 */
112 +#define FALCON_IRQ_GPIO_P0 (INT_NUM_IM1_IRL0 + 4)
113 +/* External Interrupt from GPIO P1 */
114 +#define FALCON_IRQ_GPIO_P1 (INT_NUM_IM1_IRL0 + 5)
115 +/* External Interrupt from GPIO P2 */
116 +#define FALCON_IRQ_GPIO_P2 (INT_NUM_IM1_IRL0 + 6)
117 +/* External Interrupt from GPIO P3 */
118 +#define FALCON_IRQ_GPIO_P3 (INT_NUM_IM1_IRL0 + 7)
119 +/* External Interrupt from GPIO P4 */
120 +#define FALCON_IRQ_GPIO_P4 (INT_NUM_IM1_IRL0 + 8)
121 +/* 8kHz backup interrupt derived from core-PLL */
122 +#define FALCON_IRQ_FSC_BKP (INT_NUM_IM1_IRL0 + 10)
123 +/* FSC Timer Interrupt 0 */
124 +#define FALCON_IRQ_FSCT_CMP0 (INT_NUM_IM1_IRL0 + 11)
125 +/* FSC Timer Interrupt 1 */
126 +#define FALCON_IRQ_FSCT_CMP1 (INT_NUM_IM1_IRL0 + 12)
127 +/* 8kHz root interrupt derived from GPON interface */
128 +#define FALCON_IRQ_FSC_ROOT (INT_NUM_IM1_IRL0 + 13)
129 +/* Time of Day */
130 +#define FALCON_IRQ_TOD (INT_NUM_IM1_IRL0 + 14)
131 +/* PMA Interrupt from IntNode of the 200MHz Domain */
132 +#define FALCON_IRQ_PMA_200M (INT_NUM_IM1_IRL0 + 15)
133 +/* PMA Interrupt from IntNode of the TX Clk Domain */
134 +#define FALCON_IRQ_PMA_TX (INT_NUM_IM1_IRL0 + 16)
135 +/* PMA Interrupt from IntNode of the RX Clk Domain */
136 +#define FALCON_IRQ_PMA_RX (INT_NUM_IM1_IRL0 + 17)
137 +/* SYS1 Interrupt */
138 +#define FALCON_IRQ_SYS1 (INT_NUM_IM1_IRL0 + 20)
139 +/* SYS GPE Interrupt */
140 +#define FALCON_IRQ_SYS_GPE (INT_NUM_IM1_IRL0 + 21)
141 +/* Watchdog Access Error Interrupt */
142 +#define FALCON_IRQ_WDT_AEIR (INT_NUM_IM1_IRL0 + 24)
143 +/* Watchdog Prewarning Interrupt */
144 +#define FALCON_IRQ_WDT_PIR (INT_NUM_IM1_IRL0 + 25)
145 +/* SBIU interrupt */
146 +#define FALCON_IRQ_SBIU0 (INT_NUM_IM1_IRL0 + 27)
147 +/* FPI Bus Control Unit Interrupt */
148 +#define FALCON_IRQ_BCU0 (INT_NUM_IM1_IRL0 + 29)
149 +/* DDR Controller Interrupt */
150 +#define FALCON_IRQ_DDR (INT_NUM_IM1_IRL0 + 30)
151 +/* Crossbar Error Interrupt */
152 +#define FALCON_IRQ_XBAR_ERROR (INT_NUM_IM1_IRL0 + 31)
153 +
154 +/* ICTRLL 0 Interrupt */
155 +#define FALCON_IRQ_ICTRLL0 (INT_NUM_IM2_IRL0 + 0)
156 +/* ICTRLL 1 Interrupt */
157 +#define FALCON_IRQ_ICTRLL1 (INT_NUM_IM2_IRL0 + 1)
158 +/* ICTRLL 2 Interrupt */
159 +#define FALCON_IRQ_ICTRLL2 (INT_NUM_IM2_IRL0 + 2)
160 +/* ICTRLL 3 Interrupt */
161 +#define FALCON_IRQ_ICTRLL3 (INT_NUM_IM2_IRL0 + 3)
162 +/* OCTRLL 0 Interrupt */
163 +#define FALCON_IRQ_OCTRLL0 (INT_NUM_IM2_IRL0 + 4)
164 +/* OCTRLL 1 Interrupt */
165 +#define FALCON_IRQ_OCTRLL1 (INT_NUM_IM2_IRL0 + 5)
166 +/* OCTRLL 2 Interrupt */
167 +#define FALCON_IRQ_OCTRLL2 (INT_NUM_IM2_IRL0 + 6)
168 +/* OCTRLL 3 Interrupt */
169 +#define FALCON_IRQ_OCTRLL3 (INT_NUM_IM2_IRL0 + 7)
170 +/* OCTRLG Interrupt */
171 +#define FALCON_IRQ_OCTRLG (INT_NUM_IM2_IRL0 + 9)
172 +/* IQM Interrupt */
173 +#define FALCON_IRQ_IQM (INT_NUM_IM2_IRL0 + 10)
174 +/* FSQM Interrupt */
175 +#define FALCON_IRQ_FSQM (INT_NUM_IM2_IRL0 + 11)
176 +/* TMU Interrupt */
177 +#define FALCON_IRQ_TMU (INT_NUM_IM2_IRL0 + 12)
178 +/* LINK1 Interrupt */
179 +#define FALCON_IRQ_LINK1 (INT_NUM_IM2_IRL0 + 14)
180 +/* ICTRLC 0 Interrupt */
181 +#define FALCON_IRQ_ICTRLC0 (INT_NUM_IM2_IRL0 + 16)
182 +/* ICTRLC 1 Interrupt */
183 +#define FALCON_IRQ_ICTRLC1 (INT_NUM_IM2_IRL0 + 17)
184 +/* OCTRLC Interrupt */
185 +#define FALCON_IRQ_OCTRLC (INT_NUM_IM2_IRL0 + 18)
186 +/* CONFIG Break Interrupt */
187 +#define FALCON_IRQ_CONFIG_BREAK (INT_NUM_IM2_IRL0 + 19)
188 +/* CONFIG Interrupt */
189 +#define FALCON_IRQ_CONFIG (INT_NUM_IM2_IRL0 + 20)
190 +/* Dispatcher Interrupt */
191 +#define FALCON_IRQ_DISP (INT_NUM_IM2_IRL0 + 21)
192 +/* TBM Interrupt */
193 +#define FALCON_IRQ_TBM (INT_NUM_IM2_IRL0 + 22)
194 +/* GTC Downstream Interrupt */
195 +#define FALCON_IRQ_GTC_DS (INT_NUM_IM2_IRL0 + 29)
196 +/* GTC Upstream Interrupt */
197 +#define FALCON_IRQ_GTC_US (INT_NUM_IM2_IRL0 + 30)
198 +/* EIM Interrupt */
199 +#define FALCON_IRQ_EIM (INT_NUM_IM2_IRL0 + 31)
200 +
201 +/* ASC0 Transmit Interrupt */
202 +#define FALCON_IRQ_ASC0_T (INT_NUM_IM3_IRL0 + 0)
203 +/* ASC0 Receive Interrupt */
204 +#define FALCON_IRQ_ASC0_R (INT_NUM_IM3_IRL0 + 1)
205 +/* ASC0 Error Interrupt */
206 +#define FALCON_IRQ_ASC0_E (INT_NUM_IM3_IRL0 + 2)
207 +/* ASC0 Transmit Buffer Interrupt */
208 +#define FALCON_IRQ_ASC0_TB (INT_NUM_IM3_IRL0 + 3)
209 +/* ASC0 Autobaud Start Interrupt */
210 +#define FALCON_IRQ_ASC0_ABST (INT_NUM_IM3_IRL0 + 4)
211 +/* ASC0 Autobaud Detection Interrupt */
212 +#define FALCON_IRQ_ASC0_ABDET (INT_NUM_IM3_IRL0 + 5)
213 +/* ASC1 Modem Status Interrupt */
214 +#define FALCON_IRQ_ASC0_MS (INT_NUM_IM3_IRL0 + 6)
215 +/* ASC0 Soft Flow Control Interrupt */
216 +#define FALCON_IRQ_ASC0_SFC (INT_NUM_IM3_IRL0 + 7)
217 +/* ASC1 Transmit Interrupt */
218 +#define FALCON_IRQ_ASC1_T (INT_NUM_IM3_IRL0 + 8)
219 +/* ASC1 Receive Interrupt */
220 +#define FALCON_IRQ_ASC1_R (INT_NUM_IM3_IRL0 + 9)
221 +/* ASC1 Error Interrupt */
222 +#define FALCON_IRQ_ASC1_E (INT_NUM_IM3_IRL0 + 10)
223 +/* ASC1 Transmit Buffer Interrupt */
224 +#define FALCON_IRQ_ASC1_TB (INT_NUM_IM3_IRL0 + 11)
225 +/* ASC1 Autobaud Start Interrupt */
226 +#define FALCON_IRQ_ASC1_ABST (INT_NUM_IM3_IRL0 + 12)
227 +/* ASC1 Autobaud Detection Interrupt */
228 +#define FALCON_IRQ_ASC1_ABDET (INT_NUM_IM3_IRL0 + 13)
229 +/* ASC1 Modem Status Interrupt */
230 +#define FALCON_IRQ_ASC1_MS (INT_NUM_IM3_IRL0 + 14)
231 +/* ASC1 Soft Flow Control Interrupt */
232 +#define FALCON_IRQ_ASC1_SFC (INT_NUM_IM3_IRL0 + 15)
233 +/* GPTC Timer/Counter 1A Interrupt */
234 +#define FALCON_IRQ_GPTC_TC1A (INT_NUM_IM3_IRL0 + 16)
235 +/* GPTC Timer/Counter 1B Interrupt */
236 +#define FALCON_IRQ_GPTC_TC1B (INT_NUM_IM3_IRL0 + 17)
237 +/* GPTC Timer/Counter 2A Interrupt */
238 +#define FALCON_IRQ_GPTC_TC2A (INT_NUM_IM3_IRL0 + 18)
239 +/* GPTC Timer/Counter 2B Interrupt */
240 +#define FALCON_IRQ_GPTC_TC2B (INT_NUM_IM3_IRL0 + 19)
241 +/* GPTC Timer/Counter 3A Interrupt */
242 +#define FALCON_IRQ_GPTC_TC3A (INT_NUM_IM3_IRL0 + 20)
243 +/* GPTC Timer/Counter 3B Interrupt */
244 +#define FALCON_IRQ_GPTC_TC3B (INT_NUM_IM3_IRL0 + 21)
245 +/* DFEV0, Channel 1 Transmit Interrupt */
246 +#define FALCON_IRQ_DFEV0_2TX (INT_NUM_IM3_IRL0 + 26)
247 +/* DFEV0, Channel 1 Receive Interrupt */
248 +#define FALCON_IRQ_DFEV0_2RX (INT_NUM_IM3_IRL0 + 27)
249 +/* DFEV0, Channel 1 General Purpose Interrupt */
250 +#define FALCON_IRQ_DFEV0_2GP (INT_NUM_IM3_IRL0 + 28)
251 +/* DFEV0, Channel 0 Transmit Interrupt */
252 +#define FALCON_IRQ_DFEV0_1TX (INT_NUM_IM3_IRL0 + 29)
253 +/* DFEV0, Channel 0 Receive Interrupt */
254 +#define FALCON_IRQ_DFEV0_1RX (INT_NUM_IM3_IRL0 + 30)
255 +/* DFEV0, Channel 0 General Purpose Interrupt */
256 +#define FALCON_IRQ_DFEV0_1GP (INT_NUM_IM3_IRL0 + 31)
257 +
258 +/* ICTRLL 0 Error */
259 +#define FALCON_IRQ_ICTRLL0_ERR (INT_NUM_IM4_IRL0 + 0)
260 +/* ICTRLL 1 Error */
261 +#define FALCON_IRQ_ICTRLL1_ERR (INT_NUM_IM4_IRL0 + 1)
262 +/* ICTRLL 2 Error */
263 +#define FALCON_IRQ_ICTRLL2_ERR (INT_NUM_IM4_IRL0 + 2)
264 +/* ICTRLL 3 Error */
265 +#define FALCON_IRQ_ICTRLL3_ERR (INT_NUM_IM4_IRL0 + 3)
266 +/* OCTRLL 0 Error */
267 +#define FALCON_IRQ_OCTRLL0_ERR (INT_NUM_IM4_IRL0 + 4)
268 +/* OCTRLL 1 Error */
269 +#define FALCON_IRQ_OCTRLL1_ERR (INT_NUM_IM4_IRL0 + 5)
270 +/* OCTRLL 2 Error */
271 +#define FALCON_IRQ_OCTRLL2_ERR (INT_NUM_IM4_IRL0 + 6)
272 +/* OCTRLL 3 Error */
273 +#define FALCON_IRQ_OCTRLL3_ERR (INT_NUM_IM4_IRL0 + 7)
274 +/* ICTRLG Error */
275 +#define FALCON_IRQ_ICTRLG_ERR (INT_NUM_IM4_IRL0 + 8)
276 +/* OCTRLG Error */
277 +#define FALCON_IRQ_OCTRLG_ERR (INT_NUM_IM4_IRL0 + 9)
278 +/* IQM Error */
279 +#define FALCON_IRQ_IQM_ERR (INT_NUM_IM4_IRL0 + 10)
280 +/* FSQM Error */
281 +#define FALCON_IRQ_FSQM_ERR (INT_NUM_IM4_IRL0 + 11)
282 +/* TMU Error */
283 +#define FALCON_IRQ_TMU_ERR (INT_NUM_IM4_IRL0 + 12)
284 +/* MPS Status Interrupt #0 (VPE1 to VPE0) */
285 +#define FALCON_IRQ_MPS_IR0 (INT_NUM_IM4_IRL0 + 14)
286 +/* MPS Status Interrupt #1 (VPE1 to VPE0) */
287 +#define FALCON_IRQ_MPS_IR1 (INT_NUM_IM4_IRL0 + 15)
288 +/* MPS Status Interrupt #2 (VPE1 to VPE0) */
289 +#define FALCON_IRQ_MPS_IR2 (INT_NUM_IM4_IRL0 + 16)
290 +/* MPS Status Interrupt #3 (VPE1 to VPE0) */
291 +#define FALCON_IRQ_MPS_IR3 (INT_NUM_IM4_IRL0 + 17)
292 +/* MPS Status Interrupt #4 (VPE1 to VPE0) */
293 +#define FALCON_IRQ_MPS_IR4 (INT_NUM_IM4_IRL0 + 18)
294 +/* MPS Status Interrupt #5 (VPE1 to VPE0) */
295 +#define FALCON_IRQ_MPS_IR5 (INT_NUM_IM4_IRL0 + 19)
296 +/* MPS Status Interrupt #6 (VPE1 to VPE0) */
297 +#define FALCON_IRQ_MPS_IR6 (INT_NUM_IM4_IRL0 + 20)
298 +/* MPS Status Interrupt #7 (VPE1 to VPE0) */
299 +#define FALCON_IRQ_MPS_IR7 (INT_NUM_IM4_IRL0 + 21)
300 +/* MPS Status Interrupt #8 (VPE1 to VPE0) */
301 +#define FALCON_IRQ_MPS_IR8 (INT_NUM_IM4_IRL0 + 22)
302 +/* VPE0 Exception Level Flag Interrupt */
303 +#define FALCON_IRQ_VPE0_EXL (INT_NUM_IM4_IRL0 + 29)
304 +/* VPE0 Error Level Flag Interrupt */
305 +#define FALCON_IRQ_VPE0_ERL (INT_NUM_IM4_IRL0 + 30)
306 +/* VPE0 Performance Monitoring Counter Interrupt */
307 +#define FALCON_IRQ_VPE0_PMCIR (INT_NUM_IM4_IRL0 + 31)
308 +
309 +#endif /* _FALCON_IRQ__ */
310 --- /dev/null
311 +++ b/arch/mips/include/asm/mach-lantiq/falcon/irq.h
312 @@ -0,0 +1,18 @@
313 +/*
314 + * This program is free software; you can redistribute it and/or modify it
315 + * under the terms of the GNU General Public License version 2 as published
316 + * by the Free Software Foundation.
317 + *
318 + * Copyright (C) 2011 Thomas Langer <thomas.langer@lantiq.com>
319 + */
320 +
321 +#ifndef __FALCON_IRQ_H
322 +#define __FALCON_IRQ_H
323 +
324 +#include <falcon_irq.h>
325 +
326 +#define NR_IRQS 328
327 +
328 +#include_next <irq.h>
329 +
330 +#endif
331 --- /dev/null
332 +++ b/arch/mips/include/asm/mach-lantiq/falcon/lantiq_soc.h
333 @@ -0,0 +1,140 @@
334 +/*
335 + * This program is free software; you can redistribute it and/or modify it
336 + * under the terms of the GNU General Public License version 2 as published
337 + * by the Free Software Foundation.
338 + *
339 + * Copyright (C) 2010 John Crispin <blogic@openwrt.org>
340 + */
341 +
342 +#ifndef _LTQ_FALCON_H__
343 +#define _LTQ_FALCON_H__
344 +
345 +#ifdef CONFIG_SOC_FALCON
346 +
347 +#include <lantiq.h>
348 +
349 +/* Chip IDs */
350 +#define SOC_ID_FALCON 0x01B8
351 +
352 +/* SoC Types */
353 +#define SOC_TYPE_FALCON 0x01
354 +
355 +/* ASC0/1 - serial port */
356 +#define LTQ_ASC0_BASE_ADDR 0x1E100C00
357 +#define LTQ_ASC1_BASE_ADDR 0x1E100B00
358 +#define LTQ_ASC_SIZE 0x100
359 +
360 +#define LTQ_ASC_TIR(x) (INT_NUM_IM3_IRL0 + (x * 8))
361 +#define LTQ_ASC_RIR(x) (INT_NUM_IM3_IRL0 + (x * 8) + 1)
362 +#define LTQ_ASC_EIR(x) (INT_NUM_IM3_IRL0 + (x * 8) + 2)
363 +
364 +/* during early_printk no ioremap possible at this early stage
365 + lets use KSEG1 instead */
366 +#define LTQ_EARLY_ASC KSEG1ADDR(LTQ_ASC0_BASE_ADDR)
367 +
368 +/* ICU - interrupt control unit */
369 +#define LTQ_ICU_BASE_ADDR 0x1F880200
370 +#define LTQ_ICU_SIZE 0x100
371 +
372 +/* WDT */
373 +#define LTQ_WDT_BASE_ADDR 0x1F8803F0
374 +#define LTQ_WDT_SIZE 0x10
375 +
376 +#define LTQ_RST_CAUSE_WDTRST 0x0002
377 +
378 +/* EBU - external bus unit */
379 +#define LTQ_EBU_BASE_ADDR 0x18000000
380 +#define LTQ_EBU_SIZE 0x0100
381 +
382 +#define LTQ_EBU_MODCON 0x000C
383 +
384 +/* GPIO */
385 +#define LTQ_GPIO0_BASE_ADDR 0x1D810000
386 +#define LTQ_GPIO0_SIZE 0x0080
387 +#define LTQ_GPIO1_BASE_ADDR 0x1E800100
388 +#define LTQ_GPIO1_SIZE 0x0080
389 +#define LTQ_GPIO2_BASE_ADDR 0x1D810100
390 +#define LTQ_GPIO2_SIZE 0x0080
391 +#define LTQ_GPIO3_BASE_ADDR 0x1E800200
392 +#define LTQ_GPIO3_SIZE 0x0080
393 +#define LTQ_GPIO4_BASE_ADDR 0x1E800300
394 +#define LTQ_GPIO4_SIZE 0x0080
395 +#define LTQ_PADCTRL0_BASE_ADDR 0x1DB01000
396 +#define LTQ_PADCTRL0_SIZE 0x0100
397 +#define LTQ_PADCTRL1_BASE_ADDR 0x1E800400
398 +#define LTQ_PADCTRL1_SIZE 0x0100
399 +#define LTQ_PADCTRL2_BASE_ADDR 0x1DB02000
400 +#define LTQ_PADCTRL2_SIZE 0x0100
401 +#define LTQ_PADCTRL3_BASE_ADDR 0x1E800500
402 +#define LTQ_PADCTRL3_SIZE 0x0100
403 +#define LTQ_PADCTRL4_BASE_ADDR 0x1E800600
404 +#define LTQ_PADCTRL4_SIZE 0x0100
405 +
406 +/* CHIP ID */
407 +#define LTQ_STATUS_BASE_ADDR 0x1E802000
408 +
409 +#define LTQ_FALCON_CHIPID ((u32 *)(KSEG1 + LTQ_STATUS_BASE_ADDR + 0x0c))
410 +#define LTQ_FALCON_CHIPCONF ((u32 *)(KSEG1 + LTQ_STATUS_BASE_ADDR + 0x40))
411 +
412 +/* SYSCTL - start/stop/restart/configure/... different parts of the Soc */
413 +#define LTQ_SYS1_BASE_ADDR 0x1EF00000
414 +#define LTQ_SYS1_SIZE 0x0100
415 +#define LTQ_STATUS_BASE_ADDR 0x1E802000
416 +#define LTQ_STATUS_SIZE 0x0080
417 +#define LTQ_SYS_ETH_BASE_ADDR 0x1DB00000
418 +#define LTQ_SYS_ETH_SIZE 0x0100
419 +#define LTQ_SYS_GPE_BASE_ADDR 0x1D700000
420 +#define LTQ_SYS_GPE_SIZE 0x0100
421 +
422 +#define SYSCTL_SYS1 0
423 +#define SYSCTL_SYSETH 1
424 +#define SYSCTL_SYSGPE 2
425 +
426 +/* Activation Status Register */
427 +#define ACTS_ASC1_ACT 0x00000800
428 +#define ACTS_P0 0x00010000
429 +#define ACTS_P1 0x00010000
430 +#define ACTS_P2 0x00020000
431 +#define ACTS_P3 0x00020000
432 +#define ACTS_P4 0x00040000
433 +#define ACTS_PADCTRL0 0x00100000
434 +#define ACTS_PADCTRL1 0x00100000
435 +#define ACTS_PADCTRL2 0x00200000
436 +#define ACTS_PADCTRL3 0x00200000
437 +#define ACTS_PADCTRL4 0x00400000
438 +
439 +extern void ltq_sysctl_activate(int module, unsigned int mask);
440 +extern void ltq_sysctl_deactivate(int module, unsigned int mask);
441 +extern void ltq_sysctl_clken(int module, unsigned int mask);
442 +extern void ltq_sysctl_clkdis(int module, unsigned int mask);
443 +extern void ltq_sysctl_reboot(int module, unsigned int mask);
444 +extern int ltq_gpe_is_activated(unsigned int mask);
445 +
446 +/* global register ranges */
447 +extern __iomem void *ltq_ebu_membase;
448 +extern __iomem void *ltq_sys1_membase;
449 +#define ltq_ebu_w32(x, y) ltq_w32((x), ltq_ebu_membase + (y))
450 +#define ltq_ebu_r32(x) ltq_r32(ltq_ebu_membase + (x))
451 +#define ltq_ebu_w32_mask(clear, set, reg) \
452 + ltq_ebu_w32((ltq_ebu_r32(reg) & ~(clear)) | (set), reg)
453 +
454 +#define ltq_sys1_w32(x, y) ltq_w32((x), ltq_sys1_membase + (y))
455 +#define ltq_sys1_r32(x) ltq_r32(ltq_sys1_membase + (x))
456 +#define ltq_sys1_w32_mask(clear, set, reg) \
457 + ltq_sys1_w32((ltq_sys1_r32(reg) & ~(clear)) | (set), reg)
458 +
459 +/* gpio_request wrapper to help configure the pin */
460 +extern int ltq_gpio_request(unsigned int pin, unsigned int val,
461 + unsigned int dir, const char *name);
462 +extern int ltq_gpio_mux_set(unsigned int pin, unsigned int mux);
463 +
464 +/* to keep the irq code generic we need to define these to 0 as falcon
465 + has no EIU/EBU */
466 +#define LTQ_EIU_BASE_ADDR 0
467 +#define LTQ_EBU_PCC_ISTAT 0
468 +
469 +#define ltq_is_ar9() 0
470 +#define ltq_is_vr9() 0
471 +
472 +#endif /* CONFIG_SOC_FALCON */
473 +#endif /* _LTQ_XWAY_H__ */
474 --- a/arch/mips/include/asm/mach-lantiq/lantiq.h
475 +++ b/arch/mips/include/asm/mach-lantiq/lantiq.h
476 @@ -25,6 +25,7 @@ extern unsigned int ltq_get_soc_type(voi
477 /* clock speeds */
478 #define CLOCK_60M 60000000
479 #define CLOCK_83M 83333333
480 +#define CLOCK_100M 100000000
481 #define CLOCK_111M 111111111
482 #define CLOCK_133M 133333333
483 #define CLOCK_167M 166666667
484 --- a/arch/mips/lantiq/Kconfig
485 +++ b/arch/mips/lantiq/Kconfig
486 @@ -16,8 +16,12 @@ config SOC_XWAY
487 bool "XWAY"
488 select SOC_TYPE_XWAY
489 select HW_HAS_PCI
490 +
491 +config SOC_FALCON
492 + bool "FALCON"
493 endchoice
494
495 source "arch/mips/lantiq/xway/Kconfig"
496 +source "arch/mips/lantiq/falcon/Kconfig"
497
498 endif
499 --- a/arch/mips/lantiq/Makefile
500 +++ b/arch/mips/lantiq/Makefile
501 @@ -9,3 +9,4 @@ obj-y := irq.o setup.o clk.o prom.o devi
502 obj-$(CONFIG_EARLY_PRINTK) += early_printk.o
503
504 obj-$(CONFIG_SOC_TYPE_XWAY) += xway/
505 +obj-$(CONFIG_SOC_FALCON) += falcon/
506 --- a/arch/mips/lantiq/Platform
507 +++ b/arch/mips/lantiq/Platform
508 @@ -6,3 +6,4 @@ platform-$(CONFIG_LANTIQ) += lantiq/
509 cflags-$(CONFIG_LANTIQ) += -I$(srctree)/arch/mips/include/asm/mach-lantiq
510 load-$(CONFIG_LANTIQ) = 0xffffffff80002000
511 cflags-$(CONFIG_SOC_TYPE_XWAY) += -I$(srctree)/arch/mips/include/asm/mach-lantiq/xway
512 +cflags-$(CONFIG_SOC_FALCON) += -I$(srctree)/arch/mips/include/asm/mach-lantiq/falcon
513 --- /dev/null
514 +++ b/arch/mips/lantiq/falcon/Makefile
515 @@ -0,0 +1 @@
516 +obj-y := clk.o prom.o reset.o sysctrl.o devices.o
517 --- /dev/null
518 +++ b/arch/mips/lantiq/falcon/clk.c
519 @@ -0,0 +1,44 @@
520 +/*
521 + * This program is free software; you can redistribute it and/or modify it
522 + * under the terms of the GNU General Public License version 2 as published
523 + * by the Free Software Foundation.
524 + *
525 + * Copyright (C) 2011 Thomas Langer <thomas.langer@lantiq.com>
526 + * Copyright (C) 2011 John Crispin <blogic@openwrt.org>
527 + */
528 +
529 +#include <linux/ioport.h>
530 +#include <linux/module.h>
531 +
532 +#include <lantiq_soc.h>
533 +
534 +#include "devices.h"
535 +
536 +/* CPU0 Clock Control Register */
537 +#define LTQ_SYS1_CPU0CC 0x0040
538 +/* clock divider bit */
539 +#define LTQ_CPU0CC_CPUDIV 0x0001
540 +
541 +unsigned int
542 +ltq_get_io_region_clock(void)
543 +{
544 + return CLOCK_200M;
545 +}
546 +EXPORT_SYMBOL(ltq_get_io_region_clock);
547 +
548 +unsigned int
549 +ltq_get_cpu_hz(void)
550 +{
551 + if (ltq_sys1_r32(LTQ_SYS1_CPU0CC) & LTQ_CPU0CC_CPUDIV)
552 + return CLOCK_200M;
553 + else
554 + return CLOCK_400M;
555 +}
556 +EXPORT_SYMBOL(ltq_get_cpu_hz);
557 +
558 +unsigned int
559 +ltq_get_fpi_hz(void)
560 +{
561 + return CLOCK_100M;
562 +}
563 +EXPORT_SYMBOL(ltq_get_fpi_hz);
564 --- /dev/null
565 +++ b/arch/mips/lantiq/falcon/devices.c
566 @@ -0,0 +1,87 @@
567 +/*
568 + * This program is free software; you can redistribute it and/or modify it
569 + * under the terms of the GNU General Public License version 2 as published
570 + * by the Free Software Foundation.
571 + *
572 + * Copyright (C) 2011 Thomas Langer <thomas.langer@lantiq.com>
573 + * Copyright (C) 2011 John Crispin <blogic@openwrt.org>
574 + */
575 +
576 +#include <linux/platform_device.h>
577 +#include <linux/mtd/nand.h>
578 +
579 +#include <lantiq_soc.h>
580 +
581 +#include "devices.h"
582 +
583 +/* nand flash */
584 +/* address lines used for NAND control signals */
585 +#define NAND_ADDR_ALE 0x10000
586 +#define NAND_ADDR_CLE 0x20000
587 +/* Ready/Busy Status */
588 +#define MODCON_STS 0x0002
589 +/* Ready/Busy Status Edge */
590 +#define MODCON_STSEDGE 0x0004
591 +
592 +static const char *part_probes[] = { "cmdlinepart", NULL };
593 +
594 +static int
595 +falcon_nand_ready(struct mtd_info *mtd)
596 +{
597 + u32 modcon = ltq_ebu_r32(LTQ_EBU_MODCON);
598 +
599 + return (((modcon & (MODCON_STS | MODCON_STSEDGE)) ==
600 + (MODCON_STS | MODCON_STSEDGE)));
601 +}
602 +
603 +static void
604 +falcon_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int ctrl)
605 +{
606 + struct nand_chip *this = mtd->priv;
607 + unsigned long nandaddr = (unsigned long) this->IO_ADDR_W;
608 +
609 + if (ctrl & NAND_CTRL_CHANGE) {
610 + nandaddr &= ~(NAND_ADDR_ALE | NAND_ADDR_CLE);
611 +
612 + if (ctrl & NAND_CLE)
613 + nandaddr |= NAND_ADDR_CLE;
614 + if (ctrl & NAND_ALE)
615 + nandaddr |= NAND_ADDR_ALE;
616 +
617 + this->IO_ADDR_W = (void __iomem *) nandaddr;
618 + }
619 +
620 + if (cmd != NAND_CMD_NONE)
621 + writeb(cmd, this->IO_ADDR_W);
622 +}
623 +
624 +static struct platform_nand_data falcon_flash_nand_data = {
625 + .chip = {
626 + .nr_chips = 1,
627 + .chip_delay = 25,
628 + .part_probe_types = part_probes,
629 + },
630 + .ctrl = {
631 + .cmd_ctrl = falcon_hwcontrol,
632 + .dev_ready = falcon_nand_ready,
633 + }
634 +};
635 +
636 +static struct resource ltq_nand_res =
637 + MEM_RES("nand", LTQ_FLASH_START, LTQ_FLASH_MAX);
638 +
639 +static struct platform_device ltq_flash_nand = {
640 + .name = "gen_nand",
641 + .id = -1,
642 + .num_resources = 1,
643 + .resource = &ltq_nand_res,
644 + .dev = {
645 + .platform_data = &falcon_flash_nand_data,
646 + },
647 +};
648 +
649 +void __init
650 +falcon_register_nand(void)
651 +{
652 + platform_device_register(&ltq_flash_nand);
653 +}
654 --- /dev/null
655 +++ b/arch/mips/lantiq/falcon/devices.h
656 @@ -0,0 +1,18 @@
657 +/*
658 + * This program is free software; you can redistribute it and/or modify
659 + * it under the terms of the GNU General Public License as published by
660 + * the Free Software Foundation; either version 2 of the License, or
661 + * (at your option) any later version.
662 + *
663 + * Copyright (C) 2011 Thomas Langer <thomas.langer@lantiq.com>
664 + * Copyright (C) 2011 John Crispin <blogic@openwrt.org>
665 + */
666 +
667 +#ifndef _FALCON_DEVICES_H__
668 +#define _FALCON_DEVICES_H__
669 +
670 +#include "../devices.h"
671 +
672 +extern void falcon_register_nand(void);
673 +
674 +#endif
675 --- /dev/null
676 +++ b/arch/mips/lantiq/falcon/prom.c
677 @@ -0,0 +1,72 @@
678 +/*
679 + * This program is free software; you can redistribute it and/or modify it
680 + * under the terms of the GNU General Public License version 2 as published
681 + * by the Free Software Foundation.
682 + *
683 + * Copyright (C) 2011 Thomas Langer <thomas.langer@lantiq.com>
684 + * Copyright (C) 2011 John Crispin <blogic@openwrt.org>
685 + */
686 +
687 +#include <lantiq_soc.h>
688 +
689 +#include "devices.h"
690 +
691 +#include "../prom.h"
692 +
693 +#define SOC_FALCON "Falcon"
694 +
695 +#define PART_SHIFT 12
696 +#define PART_MASK 0x0FFFF000
697 +#define REV_SHIFT 28
698 +#define REV_MASK 0xF0000000
699 +#define SREV_SHIFT 22
700 +#define SREV_MASK 0x03C00000
701 +
702 +#define MUXC_SIF_RX_PIN 112
703 +#define MUXC_SIF_TX_PIN 113
704 +
705 +/* this parameter allows us enable/disable asc1 via commandline */
706 +static int register_asc1;
707 +static int __init
708 +ltq_parse_asc1(char *p)
709 +{
710 + register_asc1 = 1;
711 + return 0;
712 +}
713 +__setup("use_asc1", ltq_parse_asc1);
714 +
715 +void __init
716 +ltq_soc_setup(void)
717 +{
718 + ltq_register_asc(0);
719 + ltq_register_wdt();
720 + falcon_register_gpio();
721 + if (register_asc1) {
722 + ltq_register_asc(1);
723 + if (ltq_gpio_request(MUXC_SIF_RX_PIN, 3, 0, "asc1-rx"))
724 + pr_err("failed to request asc1-rx");
725 + if (ltq_gpio_request(MUXC_SIF_TX_PIN, 3, 1, "asc1-tx"))
726 + pr_err("failed to request asc1-tx");
727 + ltq_sysctl_activate(SYSCTL_SYS1, ACTS_ASC1_ACT);
728 + }
729 +}
730 +
731 +void __init
732 +ltq_soc_detect(struct ltq_soc_info *i)
733 +{
734 + i->partnum = (ltq_r32(LTQ_FALCON_CHIPID) & PART_MASK) >> PART_SHIFT;
735 + i->rev = (ltq_r32(LTQ_FALCON_CHIPID) & REV_MASK) >> REV_SHIFT;
736 + i->srev = (ltq_r32(LTQ_FALCON_CHIPCONF) & SREV_MASK) >> SREV_SHIFT;
737 + sprintf(i->rev_type, "%c%d%d", (i->srev & 0x4) ? ('B') : ('A'),
738 + i->rev & 0x7, i->srev & 0x3);
739 + switch (i->partnum) {
740 + case SOC_ID_FALCON:
741 + i->name = SOC_FALCON;
742 + i->type = SOC_TYPE_FALCON;
743 + break;
744 +
745 + default:
746 + unreachable();
747 + break;
748 + }
749 +}
750 --- /dev/null
751 +++ b/arch/mips/lantiq/falcon/reset.c
752 @@ -0,0 +1,87 @@
753 +/*
754 + * This program is free software; you can redistribute it and/or modify it
755 + * under the terms of the GNU General Public License version 2 as published
756 + * by the Free Software Foundation.
757 + *
758 + * Copyright (C) 2011 Thomas Langer <thomas.langer@lantiq.com>
759 + * Copyright (C) 2011 John Crispin <blogic@openwrt.org>
760 + */
761 +
762 +#include <linux/init.h>
763 +#include <linux/io.h>
764 +#include <linux/pm.h>
765 +#include <asm/reboot.h>
766 +#include <linux/module.h>
767 +
768 +#include <lantiq_soc.h>
769 +
770 +/* CPU0 Reset Source Register */
771 +#define LTQ_SYS1_CPU0RS 0x0040
772 +/* reset cause mask */
773 +#define LTQ_CPU0RS_MASK 0x0003
774 +
775 +int
776 +ltq_reset_cause(void)
777 +{
778 + return ltq_sys1_r32(LTQ_SYS1_CPU0RS) & LTQ_CPU0RS_MASK;
779 +}
780 +EXPORT_SYMBOL_GPL(ltq_reset_cause);
781 +
782 +#define BOOT_REG_BASE (KSEG1 | 0x1F200000)
783 +#define BOOT_PW1_REG (BOOT_REG_BASE | 0x20)
784 +#define BOOT_PW2_REG (BOOT_REG_BASE | 0x24)
785 +#define BOOT_PW1 0x4C545100
786 +#define BOOT_PW2 0x0051544C
787 +
788 +#define WDT_REG_BASE (KSEG1 | 0x1F8803F0)
789 +#define WDT_PW1 0x00BE0000
790 +#define WDT_PW2 0x00DC0000
791 +
792 +static void
793 +ltq_machine_restart(char *command)
794 +{
795 + pr_notice("System restart\n");
796 + local_irq_disable();
797 +
798 + /* reboot magic */
799 + ltq_w32(BOOT_PW1, (void *)BOOT_PW1_REG); /* 'LTQ\0' */
800 + ltq_w32(BOOT_PW2, (void *)BOOT_PW2_REG); /* '\0QTL' */
801 + ltq_w32(0, (void *)BOOT_REG_BASE); /* reset Bootreg RVEC */
802 +
803 + /* watchdog magic */
804 + ltq_w32(WDT_PW1, (void *)WDT_REG_BASE);
805 + ltq_w32(WDT_PW2 |
806 + (0x3 << 26) | /* PWL */
807 + (0x2 << 24) | /* CLKDIV */
808 + (0x1 << 31) | /* enable */
809 + (1), /* reload */
810 + (void *)WDT_REG_BASE);
811 + unreachable();
812 +}
813 +
814 +static void
815 +ltq_machine_halt(void)
816 +{
817 + pr_notice("System halted.\n");
818 + local_irq_disable();
819 + unreachable();
820 +}
821 +
822 +static void
823 +ltq_machine_power_off(void)
824 +{
825 + pr_notice("Please turn off the power now.\n");
826 + local_irq_disable();
827 + unreachable();
828 +}
829 +
830 +static int __init
831 +mips_reboot_setup(void)
832 +{
833 + _machine_restart = ltq_machine_restart;
834 + _machine_halt = ltq_machine_halt;
835 + pm_power_off = ltq_machine_power_off;
836 + return 0;
837 +}
838 +
839 +arch_initcall(mips_reboot_setup);
840 --- /dev/null
841 +++ b/arch/mips/lantiq/falcon/sysctrl.c
842 @@ -0,0 +1,181 @@
843 +/*
844 + * This program is free software; you can redistribute it and/or modify it
845 + * under the terms of the GNU General Public License version 2 as published
846 + * by the Free Software Foundation.
847 + *
848 + * Copyright (C) 2011 Thomas Langer <thomas.langer@lantiq.com>
849 + * Copyright (C) 2011 John Crispin <blogic@openwrt.org>
850 + */
851 +
852 +#include <linux/ioport.h>
853 +#include <asm/delay.h>
854 +
855 +#include <lantiq_soc.h>
856 +
857 +#include "devices.h"
858 +
859 +/* infrastructure control register */
860 +#define SYS1_INFRAC 0x00bc
861 +/* Configuration fuses for drivers and pll */
862 +#define STATUS_CONFIG 0x0040
863 +
864 +/* GPE frequency selection */
865 +#define GPPC_OFFSET 24
866 +#define GPEFREQ_MASK 0x00000C0
867 +#define GPEFREQ_OFFSET 10
868 +/* Clock status register */
869 +#define LTQ_SYSCTL_CLKS 0x0000
870 +/* Clock enable register */
871 +#define LTQ_SYSCTL_CLKEN 0x0004
872 +/* Clock clear register */
873 +#define LTQ_SYSCTL_CLKCLR 0x0008
874 +/* Activation Status Register */
875 +#define LTQ_SYSCTL_ACTS 0x0020
876 +/* Activation Register */
877 +#define LTQ_SYSCTL_ACT 0x0024
878 +/* Deactivation Register */
879 +#define LTQ_SYSCTL_DEACT 0x0028
880 +/* reboot Register */
881 +#define LTQ_SYSCTL_RBT 0x002c
882 +
883 +static struct resource ltq_sysctl_res[] = {
884 + MEM_RES("sys1", LTQ_SYS1_BASE_ADDR, LTQ_SYS1_SIZE),
885 + MEM_RES("syseth", LTQ_SYS_ETH_BASE_ADDR, LTQ_SYS_ETH_SIZE),
886 + MEM_RES("sysgpe", LTQ_SYS_GPE_BASE_ADDR, LTQ_SYS_GPE_SIZE),
887 +};
888 +
889 +static struct resource ltq_status_res =
890 + MEM_RES("status", LTQ_STATUS_BASE_ADDR, LTQ_STATUS_SIZE);
891 +static struct resource ltq_ebu_res =
892 + MEM_RES("ebu", LTQ_EBU_BASE_ADDR, LTQ_EBU_SIZE);
893 +
894 +static void __iomem *ltq_sysctl[3];
895 +static void __iomem *ltq_status_membase;
896 +void __iomem *ltq_sys1_membase;
897 +void __iomem *ltq_ebu_membase;
898 +
899 +#define ltq_reg_w32(m, x, y) ltq_w32((x), ltq_sysctl[m] + (y))
900 +#define ltq_reg_r32(m, x) ltq_r32(ltq_sysctl[m] + (x))
901 +#define ltq_reg_w32_mask(m, clear, set, reg) \
902 + ltq_reg_w32(m, (ltq_reg_r32(m, reg) & ~(clear)) | (set), reg)
903 +
904 +#define ltq_status_w32(x, y) ltq_w32((x), ltq_status_membase + (y))
905 +#define ltq_status_r32(x) ltq_r32(ltq_status_membase + (x))
906 +
907 +static inline void
908 +ltq_sysctl_wait(int module, unsigned int mask, unsigned int test)
909 +{
910 + int err = 1000000;
911 +
912 + do {} while (--err && ((ltq_reg_r32(module, LTQ_SYSCTL_ACTS)
913 + & mask) != test));
914 + if (!err)
915 + pr_err("module de/activation failed %d %08X %08X\n",
916 + module, mask, test);
917 +}
918 +
919 +void
920 +ltq_sysctl_activate(int module, unsigned int mask)
921 +{
922 + if (module > SYSCTL_SYSGPE)
923 + return;
924 +
925 + ltq_reg_w32(module, mask, LTQ_SYSCTL_CLKEN);
926 + ltq_reg_w32(module, mask, LTQ_SYSCTL_ACT);
927 + ltq_sysctl_wait(module, mask, mask);
928 +}
929 +EXPORT_SYMBOL(ltq_sysctl_activate);
930 +
931 +void
932 +ltq_sysctl_deactivate(int module, unsigned int mask)
933 +{
934 + if (module > SYSCTL_SYSGPE)
935 + return;
936 +
937 + ltq_reg_w32(module, mask, LTQ_SYSCTL_CLKCLR);
938 + ltq_reg_w32(module, mask, LTQ_SYSCTL_DEACT);
939 + ltq_sysctl_wait(module, mask, 0);
940 +}
941 +EXPORT_SYMBOL(ltq_sysctl_deactivate);
942 +
943 +void
944 +ltq_sysctl_clken(int module, unsigned int mask)
945 +{
946 + if (module > SYSCTL_SYSGPE)
947 + return;
948 +
949 + ltq_reg_w32(module, mask, LTQ_SYSCTL_CLKEN);
950 + ltq_sysctl_wait(module, mask, mask);
951 +}
952 +EXPORT_SYMBOL(ltq_sysctl_clken);
953 +
954 +void
955 +ltq_sysctl_clkdis(int module, unsigned int mask)
956 +{
957 + if (module > SYSCTL_SYSGPE)
958 + return;
959 +
960 + ltq_reg_w32(module, mask, LTQ_SYSCTL_CLKCLR);
961 + ltq_sysctl_wait(module, mask, 0);
962 +}
963 +EXPORT_SYMBOL(ltq_sysctl_clkdis);
964 +
965 +void
966 +ltq_sysctl_reboot(int module, unsigned int mask)
967 +{
968 + unsigned int act;
969 +
970 + if (module > SYSCTL_SYSGPE)
971 + return;
972 +
973 + act = ltq_reg_r32(module, LTQ_SYSCTL_ACT);
974 + if ((~act & mask) != 0)
975 + ltq_sysctl_activate(module, ~act & mask);
976 + ltq_reg_w32(module, act & mask, LTQ_SYSCTL_RBT);
977 + ltq_sysctl_wait(module, mask, mask);
978 +}
979 +EXPORT_SYMBOL(ltq_sysctl_reboot);
980 +
981 +/* enable the ONU core */
982 +static void
983 +ltq_gpe_enable(void)
984 +{
985 + unsigned int freq;
986 + unsigned int status;
987 +
988 + /* if if the clock is already enabled */
989 + status = ltq_reg_r32(SYSCTL_SYS1, SYS1_INFRAC);
990 + if (status & (1 << (GPPC_OFFSET + 1)))
991 + return;
992 +
993 + if (ltq_status_r32(STATUS_CONFIG) == 0)
994 + freq = 1; /* use 625MHz on unfused chip */
995 + else
996 + freq = (ltq_status_r32(STATUS_CONFIG) &
997 + GPEFREQ_MASK) >>
998 + GPEFREQ_OFFSET;
999 +
1000 + /* apply new frequency */
1001 + ltq_reg_w32_mask(SYSCTL_SYS1, 7 << (GPPC_OFFSET + 1),
1002 + freq << (GPPC_OFFSET + 2) , SYS1_INFRAC);
1003 + udelay(1);
1004 +
1005 + /* enable new frequency */
1006 + ltq_reg_w32_mask(SYSCTL_SYS1, 0, 1 << (GPPC_OFFSET + 1), SYS1_INFRAC);
1007 + udelay(1);
1008 +}
1009 +
1010 +void __init
1011 +ltq_soc_init(void)
1012 +{
1013 + int i;
1014 +
1015 + for (i = 0; i < 3; i++)
1016 + ltq_sysctl[i] = ltq_remap_resource(&ltq_sysctl_res[i]);
1017 +
1018 + ltq_sys1_membase = ltq_sysctl[0];
1019 + ltq_status_membase = ltq_remap_resource(&ltq_status_res);
1020 + ltq_ebu_membase = ltq_remap_resource(&ltq_ebu_res);
1021 +
1022 + ltq_gpe_enable();
1023 +}
Personal OpenWRT clone
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