target/linux/adm5120/files/include/asm-mips/mach-adm5120/adm5120_switch.h

   1 /*
   2  *  $Id$
   3  *
   4  *  ADM5120 ethernet switch definitions
   5  *
   6  *  This header file defines the hardware registers of the ADM5120 SoC
   7  *  built-in Ethernet switch.
   8  *
   9  *  Copyright (C) 2007 OpenWrt.org
  10  *  Copyright (C) 2007 Gabor Juhos <juhosg at openwrt.org>
  11  *
  12  *  This program is free software; you can redistribute it and/or
  13  *  modify it under the terms of the GNU General Public License
  14  *  as published by the Free Software Foundation; either version 2
  15  *  of the License, or (at your option) any later version.
  16  *
  17  *  This program is distributed in the hope that it will be useful,
  18  *  but WITHOUT ANY WARRANTY; without even the implied warranty of
  19  *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  20  *  GNU General Public License for more details.
  21  *
  22  *  You should have received a copy of the GNU General Public License
  23  *  along with this program; if not, write to the
  24  *  Free Software Foundation, Inc., 51 Franklin Street, Fifth Floor,
  25  *  Boston, MA  02110-1301, USA.
  26  */
  27
  28 #ifndef _ADM5120_SWITCH_H_
  29 #define _ADM5120_SWITCH_H_
  30
  31 #define BIT(at)         (1 << (at))
  32 #define BITMASK(len)    ((1 << (len))-1)
  33
  34 #define SW_READ_REG(r)          __raw_readl( \
  35         (void __iomem *)KSEG1ADDR(ADM5120_SWITCH_BASE) + SWITCH_REG_ ## r)
  36 #define SW_WRITE_REG(r, v)      __raw_writel((v), \
  37         (void __iomem *)KSEG1ADDR(ADM5120_SWITCH_BASE) + SWITCH_REG_ ## r)
  38
  39 /* Switch register offsets */
  40 #define SWITCH_REG_CODE         0x0000
  41 #define SWITCH_REG_SOFT_RESET   0x0004  /* Soft Reset */
  42 #define SWITCH_REG_BOOT_DONE    0x0008  /* Boot Done */
  43 #define SWITCH_REG_SW_RESET     0x000C  /* Switch Reset */
  44 #define SWITCH_REG_PHY_STATUS   0x0014  /* PHY Status */
  45 #define SWITCH_REG_MEMCTRL      0x001C  /* Memory Control */
  46 #define SWITCH_REG_CPUP_CONF    0x0024  /* CPU Port Configuration */
  47 #define SWITCH_REG_PORT_CONF0   0x0028  /* Port Configuration 0 */
  48 #define SWITCH_REG_PORT_CONF1   0x002C  /* Port Configuration 1 */
  49 #define SWITCH_REG_PORT_CONF2   0x0030  /* Port Configuration 2 */
  50 #define SWITCH_REG_VLAN_G1      0x0040  /* VLAN group 1 */
  51 #define SWITCH_REG_VLAN_G2      0x0044  /* VLAN group 2 */
  52 #define SWITCH_REG_SEND_TRIG    0x0048  /* Send Trigger */
  53 #define SWITCH_REG_MAC_WT0      0x0058  /* MAC Write Address 0 */
  54 #define SWITCH_REG_MAC_WT1      0x005C  /* MAC Write Address 1 */
  55 #define SWITCH_REG_BW_CNTL0     0x0060  /* Bandwidth Control 0 */
  56 #define SWITCH_REG_BW_CNTL1     0x0064  /* Bandwidth Control 1 */
  57 #define SWITCH_REG_PHY_CNTL0    0x0068  /* PHY Control 0 */
  58 #define SWITCH_REG_PHY_CNTL1    0x006C  /* PHY Control 1 */
  59 #define SWITCH_REG_PORT_TH      0x0078  /* Port Threshold */
  60 #define SWITCH_REG_PHY_CNTL2    0x007C  /* PHY Control 2 */
  61 #define SWITCH_REG_PHY_CNTL3    0x0080  /* PHY Control 3 */
  62 #define SWITCH_REG_PRI_CNTL     0x0084  /* Priority Control */
  63 #define SWITCH_REG_PHY_CNTL4    0x00A0  /* PHY Control 4 */
  64 #define SWITCH_REG_EMPTY_CNT    0x00A4  /* Empty Count */
  65 #define SWITCH_REG_PORT_CNTLS   0x00A8  /* Port Control Select */
  66 #define SWITCH_REG_PORT_CNTL    0x00AC  /* Port Control */
  67 #define SWITCH_REG_INT_STATUS   0x00B0  /* Interrupt Status */
  68 #define SWITCH_REG_INT_MASK     0x00B4  /* Interrupt Mask */
  69 #define SWITCH_REG_GPIO_CONF0   0x00B8  /* GPIO Configuration 0 */
  70 #define SWITCH_REG_GPIO_CONF2   0x00BC  /* GPIO Configuration 1 */
  71 #define SWITCH_REG_WDOG0        0x00C0  /* Watchdog 0 */
  72 #define SWITCH_REG_WDOG1        0x00C4  /* Watchdog 1 */
  73
  74 #define SWITCH_REG_SHDA         0x00D0  /* Send High Descriptors Address */
  75 #define SWITCH_REG_SLDA         0x00D4  /* Send Low Descriptors Address */
  76 #define SWITCH_REG_RHDA         0x00D8  /* Receive High Descriptor Address */
  77 #define SWITCH_REG_RLDA         0x00DC  /* Receive Low Descriptor Address */
  78 #define SWITCH_REG_SHWA         0x00E0  /* Send High Working Address */
  79 #define SWITCH_REG_SLWA         0x00E4  /* Send Low Working Address */
  80 #define SWITCH_REG_RHWA         0x00E8  /* Receive High Working Address */
  81 #define SWITCH_REG_RLWA         0x00EC  /* Receive Low Working Address */
  82
  83 #define SWITCH_REG_TIMER_INT    0x00F0  /* Timer */
  84 #define SWITCH_REG_TIMER        0x00F4  /* Timer Interrupt */
  85
  86 #define SWITCH_REG_PORT0_LED    0x0100
  87 #define SWITCH_REG_PORT1_LED    0x0104
  88 #define SWITCH_REG_PORT2_LED    0x0108
  89 #define SWITCH_REG_PORT3_LED    0x010C
  90 #define SWITCH_REG_PORT4_LED    0x0110
  91
  92 /* CODE register bits */
  93 #define CODE_PC_MASK            BITMASK(16)     /* Product Code */
  94 #define CODE_REV_SHIFT          16
  95 #define CODE_REV_MASK           BITMASK(4)      /* Product Revision */
  96 #define CODE_CLKS_SHIFT         20
  97 #define CODE_CLKS_MASK          BITMASK(2)      /* Clock Speed */
  98 #define CODE_CLKS_175           0               /* 175 MHz */
  99 #define CODE_CLKS_200           1               /* 200 MHz */
 100 #define CODE_CLKS_225           2               /* 225 MHz */
 101 #define CODE_CLKS_250           3               /* 250 MHz */
 102 #define CODE_NAB                BIT(24)         /* NAND boot */
 103 #define CODE_PK_MASK            BITMASK(1)      /* Package type */
 104 #define CODE_PK_SHIFT           29
 105 #define CODE_PK_BGA             0               /* BGA package */
 106 #define CODE_PK_PQFP            1               /* PQFP package */
 107
 108 /* MEMCTRL register bits */
 109 #define MEMCTRL_SDRS_MASK       BITMASK(3)      /* SDRAM bank size */
 110 #define MEMCTRL_SDRS_4M         0x01
 111 #define MEMCTRL_SDRS_8M         0x02
 112 #define MEMCTRL_SDRS_16M        0x03
 113 #define MEMCTRL_SDRS_64M        0x04
 114 #define MEMCTRL_SDRS_128M       0x05
 115 #define MEMCTRL_SDR1_ENABLE     BIT(5)          /* enable SDRAM bank 1 */
 116
 117 #define MEMCTRL_SRS0_SHIFT      8               /* shift for SRAM0 size */
 118 #define MEMCTRL_SRS1_SHIFT      16              /* shift for SRAM1 size */
 119 #define MEMCTRL_SRS_MASK        BITMASK(3)      /* SRAM size mask */
 120 #define MEMCTRL_SRS_DISABLED    0x00            /* Disabled */
 121 #define MEMCTRL_SRS_512K        0x01            /* 512KB*/
 122 #define MEMCTRL_SRS_1M          0x02            /* 1MB */
 123 #define MEMCTRL_SRS_2M          0x03            /* 2MB */
 124 #define MEMCTRL_SRS_4M          0x04            /* 4MB */
 125
 126 /* Port bits used in various registers */
 127 #define SWITCH_PORT_PHY0        BIT(0)
 128 #define SWITCH_PORT_PHY1        BIT(1)
 129 #define SWITCH_PORT_PHY2        BIT(2)
 130 #define SWITCH_PORT_PHY3        BIT(3)
 131 #define SWITCH_PORT_PHY4        BIT(4)
 132 #define SWITCH_PORT_MII         BIT(5)
 133 #define SWITCH_PORT_CPU         BIT(6)
 134
 135 /* Port bit shorthands */
 136 #define SWITCH_PORTS_PHY        0x1F    /* phy ports */
 137 #define SWITCH_PORTS_NOCPU      0x3F    /* physical ports */
 138 #define SWITCH_PORTS_ALL        0x7F    /* all ports */
 139
 140 /* CPUP_CONF register bits */
 141 #define CPUP_CONF_DCPUP         BIT(0)  /* Disable CPU port */
 142 #define CPUP_CONF_CRCP          BIT(1)  /* CRC padding from CPU */
 143 #define CPUP_CONF_BTM           BIT(2)  /* Bridge Testing Mode */
 144 #define CPUP_CONF_DUNP_SHIFT    9       /* Disable Unknown Packets for portX */
 145 #define CPUP_CONF_DMCP_SHIFT    16      /* Disable Mcast Packets form portX */
 146 #define CPUP_CONF_DBCP_SHIFT    24      /* Disable Bcast Packets form portX */
 147
 148 /* PORT_CONF0 register bits */
 149 #define PORT_CONF0_DP_SHIFT     0       /* Disable Port */
 150 #define PORT_CONF0_EMCP_SHIFT   8       /* Enable All MC Packets */
 151 #define PORT_CONF0_BP_SHIFT     16      /* Enable Back Pressure */
 152
 153 /* PORT_CONF1 register bits */
 154 #define PORT_CONF1_DISL_SHIFT   0       /* Disable Learning */
 155 #define PORT_CONF1_BS_SHIFT     6       /* Blocking State */
 156 #define PORT_CONF1_BM_SHIFT     12      /* Blocking Mode */
 157
 158 /* SEND_TRIG register bits */
 159 #define SEND_TRIG_STL           BIT(0)  /* Send Trigger Low */
 160 #define SEND_TRIG_STH           BIT(1)  /* Send Trigger High */
 161
 162 /* MAC_WT0 register bits */
 163 #define MAC_WT0_MAWC            BIT(0)  /* MAC address write command */
 164 #define MAC_WT0_MWD_SHIFT       1
 165 #define MAC_WT0_MWD             BIT(1)  /* MAC write done */
 166 #define MAC_WT0_WFB             BIT(2)  /* Write Filter Bit */
 167 #define MAC_WT0_WVN_SHIFT       3       /* Write Vlan Number shift */
 168 #define MAC_WT0_WVE             BIT(6)  /* Write VLAN enable */
 169 #define MAC_WT0_WPMN_SHIFT      7
 170 #define MAC_WT0_WAF_SHIFT       13      /* Write Age Field shift */
 171 #define MAC_WT0_WAF_EMPTY       0
 172 #define MAC_WT0_WAF_STATIC      7       /* age: static */
 173 #define MAC_WT0_MAC0_SHIFT      16
 174 #define MAC_WT0_MAC1_SHIFT      24
 175
 176 /* MAC_WT1 register bits */
 177 #define MAC_WT1_MAC2_SHIFT      0
 178 #define MAC_WT1_MAC3_SHIFT      8
 179 #define MAC_WT1_MAC4_SHIFT      16
 180 #define MAC_WT1_MAC5_SHIFT      24
 181
 182 /* BW_CNTL0/BW_CNTL1 register bits */
 183 #define BW_CNTL_DISABLE         0x00
 184 #define BW_CNTL_64K             0x01
 185 #define BW_CNTL_128K            0x02
 186 #define BW_CNTL_256K            0x03
 187 #define BW_CNTL_512K            0x04
 188 #define BW_CNTL_1M              0x05
 189 #define BW_CNTL_4M              0x06
 190 #define BW_CNTL_10M             0x07
 191
 192 #define P4TBC_SHIFT             0
 193 #define P4RBC_SHIFT             4
 194 #define P5TBC_SHIFT             8
 195 #define P5RBC_SHIFT             12
 196
 197 #define BW_CNTL1_NAND_ENABLE    0x100
 198
 199 /* PHY_CNTL0 register bits */
 200 #define PHY_CNTL0_PHYA_MASK     BITMASK(5)
 201 #define PHY_CNTL0_PHYR_MASK     BITMASK(5)
 202 #define PHY_CNTL0_PHYR_SHIFT    8
 203 #define PHY_CNTL0_WC            BIT(13)         /* Write Command */
 204 #define PHY_CNTL0_RC            BIT(14)         /* Read Command */
 205 #define PHY_CNTL0_WTD_MASK      BIT(16)         /* Read Command */
 206 #define PHY_CNTL0_WTD_SHIFT     16
 207
 208 /* PHY_CNTL1 register bits */
 209 #define PHY_CNTL1_WOD           BIT(0)          /* Write Operation Done */
 210 #define PHY_CNTL1_ROD           BIT(1)          /* Read Operation Done */
 211 #define PHY_CNTL1_RD_MASK       BITMASK(16)
 212 #define PHY_CNTL1_RD_SHIFT      16
 213
 214 /* PHY_CNTL2 register bits */
 215 #define PHY_CNTL2_ANE_SHIFT     0       /* Auto Negotiation Enable */
 216 #define PHY_CNTL2_SC_SHIFT      5       /* Speed Control */
 217 #define PHY_CNTL2_DC_SHIFT      10      /* Duplex Control */
 218 #define PHY_CNTL2_FNCV_SHIFT    15      /* Recommended FC Value */
 219 #define PHY_CNTL2_PHYR_SHIFT    20      /* PHY reset */
 220 #define PHY_CNTL2_AMDIX_SHIFT   25      /* Auto MDIX enable */
 221 /* PHY_CNTL2_RMAE is bad in datasheet */
 222 #define PHY_CNTL2_RMAE          BIT(31) /* Recommended MCC Average enable */
 223
 224 /* PHY_CNTL3 register bits */
 225 #define PHY_CNTL3_RNT           BIT(10) /* Recommend Normal Threshold */
 226
 227 /* PORT_TH register bits */
 228 #define PORT_TH_PPT_MASK        BITMASK(8)      /* Per Port Threshold */
 229 #define PORT_TH_CPUT_SHIFT      8               /* CPU Port Buffer Threshold */
 230 #define PORT_TH_CPUT_MASK       BITMASK(8)
 231 #define PORT_TH_CPUHT_SHIFT     16              /* CPU Hold Threshold */
 232 #define PORT_TH_CPUHT_MASK      BITMASK(8)
 233 #define PORT_TH_CPURT_SHIFT     24              /* CPU Release Threshold */
 234 #define PORT_TH_CPURT_MASK      BITMASK(8)
 235
 236 /* EMPTY_CNT register bits */
 237 #define EMPTY_CNT_EBGB_MASK     BITMASK(9) /* Empty Blocks in the Global Buffer */
 238
 239 /* GPIO_CONF0 register bits */
 240 #define GPIO_CONF0_MASK         BITMASK(8)
 241 #define GPIO_CONF0_IM_SHIFT     0
 242 #define GPIO_CONF0_IV_SHIFT     8
 243 #define GPIO_CONF0_OE_SHIFT     16
 244 #define GPIO_CONF0_OV_SHIFT     24
 245 #define GPIO_CONF0_IM_MASK      (0xFF << GPIO_CONF0_IM_SHIFT)
 246 #define GPIO_CONF0_IV_MASK      (0xFF << GPIO_CONF0_IV_SHIFT)
 247 #define GPIO_CONF0_OE_MASK      (0xFF << GPIO_CONF0_OE_SHIFT)
 248 #define GPIO_CONF0_OV_MASK      (0xFF << GPIO_CONF0_OV_SHIFT)
 249
 250 /* GPIO_CONF2 register bits */
 251 #define GPIO_CONF2_CSX0         BIT(4)  /* enable CSX0:INTX0 on GPIO 1:2 */
 252 #define GPIO_CONF2_CSX1         BIT(5)  /* enable CSX1:INTX1 on GPIO 3:4 */
 253 #define GPIO_CONF2_EW           BIT(6)  /* enable wait state pin for CSX0/1 */
 254
 255 /* INT_STATUS/INT_MASK register bits */
 256 #define SWITCH_INT_SHD          BIT(0)  /* Send High Done */
 257 #define SWITCH_INT_SLD          BIT(1)  /* Send Low Done */
 258 #define SWITCH_INT_RHD          BIT(2)  /* Receive High Done */
 259 #define SWITCH_INT_RLD          BIT(3)  /* Receive Low Done */
 260 #define SWITCH_INT_HDF          BIT(4)  /* High Descriptor Full */
 261 #define SWITCH_INT_LDF          BIT(5)  /* Low Descriptor Full */
 262 #define SWITCH_INT_P0QF         BIT(6)  /* Port0 Queue Full */
 263 #define SWITCH_INT_P1QF         BIT(7)  /* Port1 Queue Full */
 264 #define SWITCH_INT_P2QF         BIT(8)  /* Port2 Queue Full */
 265 #define SWITCH_INT_P3QF         BIT(9)  /* Port3 Queue Full */
 266 #define SWITCH_INT_P4QF         BIT(10) /* Port4 Queue Full */
 267 #define SWITCH_INT_P5QF         BIT(11) /* Port5 Queue Full */
 268 #define SWITCH_INT_CPQF         BIT(13) /* CPU Queue Full */
 269 #define SWITCH_INT_GQF          BIT(14) /* Global Queue Full */
 270 #define SWITCH_INT_MD           BIT(15) /* Must Drop */
 271 #define SWITCH_INT_BCS          BIT(16) /* BC Storm */
 272 #define SWITCH_INT_PSC          BIT(18) /* Port Status Change */
 273 #define SWITCH_INT_ID           BIT(19) /* Intruder Detected */
 274 #define SWITCH_INT_W0TE         BIT(20) /* Watchdog 0 Timer Expired */
 275 #define SWITCH_INT_W1TE         BIT(21) /* Watchdog 1 Timer Expired */
 276 #define SWITCH_INT_RDE          BIT(22) /* Receive Descriptor Error */
 277 #define SWITCH_INT_SDE          BIT(23) /* Send Descriptor Error */
 278 #define SWITCH_INT_CPUH         BIT(24) /* CPU Hold */
 279
 280 /* TIMER_INT register bits */
 281 #define TIMER_INT_TOS           BIT(0)  /* time-out status */
 282 #define TIMER_INT_TOM           BIT(16) /* mask time-out interrupt */
 283
 284 /* TIMER register bits */
 285 #define TIMER_PERIOD_MASK       BITMASK(16)     /* mask for timer period */
 286 #define TIMER_PERIOD_DEFAULT    0xFFFF          /* default timer period */
 287 #define TIMER_TE                BIT(16) /* timer enable bit */
 288
 289 /* PORTx_LED register bits */
 290 #define LED_MODE_MASK           BITMASK(4)
 291 #define LED_MODE_INPUT          0
 292 #define LED_MODE_FLASH          1
 293 #define LED_MODE_OUT_HIGH       2
 294 #define LED_MODE_OUT_LOW        3
 295 #define LED_MODE_LINK           4
 296 #define LED_MODE_SPEED          5
 297 #define LED_MODE_DUPLEX         6
 298 #define LED_MODE_ACT            7
 299 #define LED_MODE_COLL           8
 300 #define LED_MODE_LINK_ACT       9
 301 #define LED_MODE_DUPLEX_COLL    10
 302 #define LED_MODE_10M_ACT        11
 303 #define LED_MODE_100M_ACT       12
 304 #define LED0_MODE_SHIFT         0       /* LED0 mode shift */
 305 #define LED1_MODE_SHIFT         4       /* LED1 mode shift */
 306 #define LED2_MODE_SHIFT         8       /* LED2 mode shift */
 307 #define LED0_IV_SHIFT           12      /* LED0 input value shift */
 308 #define LED1_IV_SHIFT           13      /* LED1 input value shift */
 309 #define LED2_IV_SHIFT           14      /* LED2 input value shift */
 310
 311 #endif /* _ADM5120_SWITCH_H_ */