target/linux/rb532/files-2.6.24/include/asm-mips/rc32434/ddr.h

   1 #ifndef __IDT_DDR_H__
   2 #define __IDT_DDR_H__
   3
   4 /*******************************************************************************
   5  *
   6  * Copyright 2002 Integrated Device Technology, Inc.
   7  *              All rights reserved.
   8  *
   9  * DDR register definition.
  10  *
  11  *
  12  * Author : ryan.holmQVist@idt.com
  13  * Date   : 20011005
  14  * Update :
  15  *          $Log: ddr.h,v $
  16  *          Revision 1.2  2002/06/06 18:34:03  astichte
  17  *          Added XXX_PhysicalAddress and XXX_VirtualAddress
  18  *
  19  *          Revision 1.1  2002/05/29 17:33:21  sysarch
  20  *          jba File moved from vcode/include/idt/acacia
  21  *
  22  *
  23  ******************************************************************************/
  24
  25 enum
  26 {
  27         DDR0_PhysicalAddress    = 0x18018000,
  28         DDR_PhysicalAddress     = DDR0_PhysicalAddress,         // Default
  29
  30         DDR0_VirtualAddress     = 0xb8018000,
  31         DDR_VirtualAddress      = DDR0_VirtualAddress,          // Default
  32 } ;
  33
  34 typedef struct DDR_s
  35 {
  36         u32     ddrbase ;
  37         u32     ddrmask ;
  38         u32     res1;
  39         u32     res2;
  40         u32     ddrc ;
  41         u32     ddrabase ;
  42         u32     ddramask ;
  43         u32     ddramap ;
  44         u32     ddrcust;
  45         u32     ddrrdc;
  46         u32     ddrspare;
  47 } volatile *DDR_t ;
  48
  49 enum
  50 {
  51         DDR0BASE_baseaddr_b     = 16,
  52         DDR0BASE_baseaddr_m     = 0xffff0000,
  53
  54         DDR0MASK_mask_b         = 16,
  55         DDR0MASK_mask_m         = 0xffff0000,
  56
  57         DDR1BASE_baseaddr_b     = 16,
  58         DDR1BASE_baseaddr_m     = 0xffff0000,
  59
  60         DDR1MASK_mask_b         = 16,
  61         DDR1MASK_mask_m         = 0xffff0000,
  62
  63         DDRC_ata_b              = 5,
  64         DDRC_ata_m              = 0x000000E0,
  65         DDRC_dbw_b              = 8,
  66         DDRC_dbw_m              = 0x00000100,
  67         DDRC_wr_b               = 9,
  68         DDRC_wr_m               = 0x00000600,
  69         DDRC_ps_b               = 11,
  70         DDRC_ps_m               = 0x00001800,
  71         DDRC_dtype_b            = 13,
  72         DDRC_dtype_m            = 0x0000e000,
  73         DDRC_rfc_b              = 16,
  74         DDRC_rfc_m              = 0x000f0000,
  75         DDRC_rp_b               = 20,
  76         DDRC_rp_m               = 0x00300000,
  77         DDRC_ap_b               = 22,
  78         DDRC_ap_m               = 0x00400000,
  79         DDRC_rcd_b              = 23,
  80         DDRC_rcd_m              = 0x01800000,
  81         DDRC_cl_b               = 25,
  82         DDRC_cl_m               = 0x06000000,
  83         DDRC_dbm_b              = 27,
  84         DDRC_dbm_m              = 0x08000000,
  85         DDRC_sds_b              = 28,
  86         DDRC_sds_m              = 0x10000000,
  87         DDRC_atp_b              = 29,
  88         DDRC_atp_m              = 0x60000000,
  89         DDRC_re_b               = 31,
  90         DDRC_re_m               = 0x80000000,
  91
  92         DDRRDC_ces_b            = 0,
  93         DDRRDC_ces_m            = 0x00000001,
  94         DDRRDC_ace_b            = 1,
  95         DDRRDC_ace_m            = 0x00000002,
  96
  97         DDRABASE_baseaddr_b     = 16,
  98         DDRABASE_baseaddr_m     = 0xffff0000,
  99
 100         DDRAMASK_mask_b         = 16,
 101         DDRAMASK_mask_m         = 0xffff0000,
 102
 103         DDRAMAP_map_b           = 16,
 104         DDRAMAP_map_m           = 0xffff0000,
 105
 106         DDRCUST_cs_b            = 0,
 107         DDRCUST_cs_m            = 0x00000003,
 108         DDRCUST_we_b            = 2,
 109         DDRCUST_we_m            = 0x00000004,
 110         DDRCUST_ras_b           = 3,
 111         DDRCUST_ras_m           = 0x00000008,
 112         DDRCUST_cas_b           = 4,
 113         DDRCUST_cas_m           = 0x00000010,
 114         DDRCUST_cke_b           = 5,
 115         DDRCUST_cke_m           = 0x00000020,
 116         DDRCUST_ba_b            = 6,
 117         DDRCUST_ba_m            = 0x000000c0,
 118
 119         RCOUNT_rcount_b         = 0,
 120         RCOUNT_rcount_m         = 0x0000ffff,
 121
 122         RCOMPARE_rcompare_b     = 0,
 123         RCOMPARE_rcompare_m     = 0x0000ffff,
 124
 125         RTC_ce_b                = 0,
 126         RTC_ce_m                = 0x00000001,
 127         RTC_to_b                = 1,
 128         RTC_to_m                = 0x00000002,
 129         RTC_rqe_b               = 2,
 130         RTC_rqe_m               = 0x00000004,
 131
 132         DDRDQSC_dm_b            = 0,
 133         DDRDQSC_dm_m            = 0x00000003,
 134         DDRDQSC_dqsbs_b         = 2,
 135         DDRDQSC_dqsbs_m         = 0x000000fc,
 136         DDRDQSC_db_b            = 8,
 137         DDRDQSC_db_m            = 0x00000100,
 138         DDRDQSC_dbsp_b          = 9,
 139         DDRDQSC_dbsp_m          = 0x01fffe00,
 140         DDRDQSC_bdp_b           = 25,
 141         DDRDQSC_bdp_m           = 0x7e000000,
 142
 143         DDRDLLC_eao_b           = 0,
 144         DDRDLLC_eao_m           = 0x00000001,
 145         DDRDLLC_eo_b            = 1,
 146         DDRDLLC_eo_m            = 0x0000003e,
 147         DDRDLLC_fs_b            = 6,
 148         DDRDLLC_fs_m            = 0x000000c0,
 149         DDRDLLC_as_b            = 8,
 150         DDRDLLC_as_m            = 0x00000700,
 151         DDRDLLC_sp_b            = 11,
 152         DDRDLLC_sp_m            = 0x001ff800,
 153
 154         DDRDLLFC_men_b          = 0,
 155         DDRDLLFC_men_m          = 0x00000001,
 156         DDRDLLFC_aen_b          = 1,
 157         DDRDLLFC_aen_m          = 0x00000002,
 158         DDRDLLFC_ff_b           = 2,
 159         DDRDLLFC_ff_m           = 0x00000004,
 160
 161         DDRDLLTA_addr_b         = 2,
 162         DDRDLLTA_addr_m         = 0xfffffffc,
 163
 164         DDRDLLED_dbe_b          = 0,
 165         DDRDLLED_dbe_m          = 0x00000001,
 166         DDRDLLED_dte_b          = 1,
 167         DDRDLLED_dte_m          = 0x00000002,
 168
 169
 170 } ;
 171
 172 #endif  // __IDT_DDR_H__