openwrt/package/linux/kernel-source/arch/mips/brcm-boards/bcm947xx/time.c

   1 /*
   2  * Copyright 2004, Broadcom Corporation
   3  * All Rights Reserved.
   4  *
   5  * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
   6  * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
   7  * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
   8  * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
   9  *
  10  * $Id$
  11  */
  12 #include <linux/config.h>
  13 #include <linux/init.h>
  14 #include <linux/kernel.h>
  15 #include <linux/sched.h>
  16 #include <linux/serial_reg.h>
  17 #include <linux/interrupt.h>
  18 #include <asm/addrspace.h>
  19 #include <asm/io.h>
  20 #include <asm/time.h>
  21
  22 #include <typedefs.h>
  23 #include <bcmnvram.h>
  24 #include <sbconfig.h>
  25 #include <sbextif.h>
  26 #include <sbutils.h>
  27 #include <sbmips.h>
  28
  29 /* Global SB handle */
  30 extern void *bcm947xx_sbh;
  31 extern spinlock_t bcm947xx_sbh_lock;
  32
  33 /* Convenience */
  34 #define sbh bcm947xx_sbh
  35 #define sbh_lock bcm947xx_sbh_lock
  36
  37 extern int panic_timeout;
  38 static int watchdog = 0;
  39 static u8 *mcr = NULL;
  40
  41 void __init
  42 bcm947xx_time_init(void)
  43 {
  44         unsigned int hz;
  45         extifregs_t *eir;
  46
  47         /*
  48          * Use deterministic values for initial counter interrupt
  49          * so that calibrate delay avoids encountering a counter wrap.
  50          */
  51         write_c0_count(0);
  52         write_c0_compare(0xffff);
  53
  54         if (!(hz = sb_mips_clock(sbh)))
  55                 hz = 100000000;
  56
  57         printk("CPU: BCM%04x rev %d at %d MHz\n", sb_chip(sbh), sb_chiprev(sbh),
  58                (hz + 500000) / 1000000);
  59
  60         /* Set MIPS counter frequency for fixed_rate_gettimeoffset() */
  61         mips_hpt_frequency = hz / 2;
  62
  63         /* Set watchdog interval in ms */
  64         watchdog = simple_strtoul(nvram_safe_get("watchdog"), NULL, 0);
  65
  66         /* Please set the watchdog to 3 sec if it is less than 3 but not equal to 0 */
  67         if (watchdog > 0) {
  68                 if (watchdog < 3000)
  69                         watchdog = 3000;
  70         }
  71
  72
  73         /* Set panic timeout in seconds */
  74         panic_timeout = watchdog / 1000;
  75
  76         /* Setup blink */
  77         if ((eir = sb_setcore(sbh, SB_EXTIF, 0))) {
  78                 sbconfig_t *sb = (sbconfig_t *)((unsigned int) eir + SBCONFIGOFF);
  79                 unsigned long base = EXTIF_CFGIF_BASE(sb_base(readl(&sb->sbadmatch1)));
  80                 mcr = (u8 *) ioremap_nocache(base + UART_MCR, 1);
  81         }
  82 }
  83
  84 static void
  85 bcm947xx_timer_interrupt(int irq, void *dev_id, struct pt_regs *regs)
  86 {
  87         /* Generic MIPS timer code */
  88         timer_interrupt(irq, dev_id, regs);
  89
  90         /* Set the watchdog timer to reset after the specified number of ms */
  91         if (watchdog > 0)
  92                 sb_watchdog(sbh, WATCHDOG_CLOCK / 1000 * watchdog);
  93
  94 #ifdef  CONFIG_HWSIM
  95         (*((int *)0xa0000f1c))++;
  96 #else
  97         /* Blink one of the LEDs in the external UART */
  98         if (mcr && !(jiffies % (HZ/2)))
  99                 writeb(readb(mcr) ^ UART_MCR_OUT2, mcr);
 100 #endif
 101 }
 102
 103 static struct irqaction bcm947xx_timer_irqaction = {
 104         bcm947xx_timer_interrupt,
 105         SA_INTERRUPT,
 106         0,
 107         "timer",
 108         NULL,
 109         NULL
 110 };
 111
 112 void __init
 113 bcm947xx_timer_setup(struct irqaction *irq)
 114 {
 115         /* Enable the timer interrupt */
 116         setup_irq(7, &bcm947xx_timer_irqaction);
 117 }