target/linux/generic-2.6/patches-2.6.22/310-ssb_pcicore_fixes.patch

   1 Index: linux-2.6.22-rc5/drivers/ssb/driver_pcicore.c
   2 ===================================================================
   3 --- linux-2.6.22-rc5.orig/drivers/ssb/driver_pcicore.c  2007-06-10 16:44:31.000000000 +0100
   4 +++ linux-2.6.22-rc5/drivers/ssb/driver_pcicore.c       2007-06-24 20:07:15.000000000 +0100
   5 @@ -93,6 +93,9 @@
   6
   7         /* Enable PCI bridge BAR1 prefetch and burst */
   8         pci_write_config_dword(dev, SSB_BAR1_CONTROL, 3);
   9 +
  10 +       /* Make sure our latency is high enough to handle the devices behind us */
  11 +       pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0xa8);
  12  }
  13  DECLARE_PCI_FIXUP_EARLY(PCI_ANY_ID, PCI_ANY_ID, ssb_fixup_pcibridge);
  14
  15 @@ -110,7 +113,7 @@
  16
  17         if (unlikely(pc->cardbusmode && dev > 1))
  18                 goto out;
  19 -       if (bus == 0) {
  20 +       if (bus == 0) {//FIXME busnumber ok?
  21                 /* Type 0 transaction */
  22                 if (unlikely(dev >= SSB_PCI_SLOT_MAX))
  23                         goto out;
  24 @@ -224,7 +227,7 @@
  25                 val = *((const u32 *)buf);
  26                 break;
  27         }
  28 -       writel(*((const u32 *)buf), mmio);
  29 +       writel(val, mmio);
  30
  31         err = 0;
  32  unmap:
  33 @@ -307,6 +310,8 @@
  34         udelay(150);
  35         val |= SSB_PCICORE_CTL_RST; /* Deassert RST# */
  36         pcicore_write32(pc, SSB_PCICORE_CTL, val);
  37 +       val = SSB_PCICORE_ARBCTL_INTERN;
  38 +       pcicore_write32(pc, SSB_PCICORE_ARBCTL, val);
  39         udelay(1);
  40
  41         //TODO cardbus mode
  42 @@ -336,6 +341,7 @@
  43          * The following needs change, if we want to port hostmode
  44          * to non-MIPS platform. */
  45         set_io_port_base((unsigned long)ioremap_nocache(SSB_PCI_MEM, 0x04000000));
  46 +       mdelay(300);
  47         register_pci_controller(&ssb_pcicore_controller);
  48  }
  49