target/linux/brcm47xx/patches-3.0/700-ssb-gigabit-ethernet-driver.patch

   1 --- a/drivers/net/tg3.c
   2 +++ b/drivers/net/tg3.c
   3 @@ -43,6 +43,7 @@
   4  #include <linux/prefetch.h>
   5  #include <linux/dma-mapping.h>
   6  #include <linux/firmware.h>
   7 +#include <linux/ssb/ssb_driver_gige.h>
   8
   9  #include <net/checksum.h>
  10  #include <net/ip.h>
  11 @@ -515,7 +516,8 @@ static void _tw32_flush(struct tg3 *tp,
  12  static inline void tw32_mailbox_flush(struct tg3 *tp, u32 off, u32 val)
  13  {
  14         tp->write32_mbox(tp, off, val);
  15 -       if (!tg3_flag(tp, MBOX_WRITE_REORDER) && !tg3_flag(tp, ICH_WORKAROUND))
  16 +       if (tg3_flag(tp, FLUSH_POSTED_WRITES) ||
  17 +           (!tg3_flag(tp, MBOX_WRITE_REORDER) && !tg3_flag(tp, ICH_WORKAROUND)))
  18                 tp->read32_mbox(tp, off);
  19  }
  20
  21 @@ -525,7 +527,7 @@ static void tg3_write32_tx_mbox(struct t
  22         writel(val, mbox);
  23         if (tg3_flag(tp, TXD_MBOX_HWBUG))
  24                 writel(val, mbox);
  25 -       if (tg3_flag(tp, MBOX_WRITE_REORDER))
  26 +       if (tg3_flag(tp, MBOX_WRITE_REORDER) || tg3_flag(tp, FLUSH_POSTED_WRITES))
  27                 readl(mbox);
  28  }
  29
  30 @@ -804,7 +806,7 @@ static void tg3_switch_clocks(struct tg3
  31
  32  #define PHY_BUSY_LOOPS 5000
  33
  34 -static int tg3_readphy(struct tg3 *tp, int reg, u32 *val)
  35 +static int __tg3_readphy(struct tg3 *tp, unsigned int phy_addr, int reg, u32 *val)
  36  {
  37         u32 frame_val;
  38         unsigned int loops;
  39 @@ -818,7 +820,7 @@ static int tg3_readphy(struct tg3 *tp, i
  40
  41         *val = 0x0;
  42
  43 -       frame_val  = ((tp->phy_addr << MI_COM_PHY_ADDR_SHIFT) &
  44 +       frame_val  = ((phy_addr << MI_COM_PHY_ADDR_SHIFT) &
  45                       MI_COM_PHY_ADDR_MASK);
  46         frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
  47                       MI_COM_REG_ADDR_MASK);
  48 @@ -853,7 +855,12 @@ static int tg3_readphy(struct tg3 *tp, i
  49         return ret;
  50  }
  51
  52 -static int tg3_writephy(struct tg3 *tp, int reg, u32 val)
  53 +static int tg3_readphy(struct tg3 *tp, int reg, u32 *val)
  54 +{
  55 +       return __tg3_readphy(tp, tp->phy_addr, reg, val);
  56 +}
  57 +
  58 +static int __tg3_writephy(struct tg3 *tp, unsigned int phy_addr, int reg, u32 val)
  59  {
  60         u32 frame_val;
  61         unsigned int loops;
  62 @@ -869,7 +876,7 @@ static int tg3_writephy(struct tg3 *tp,
  63                 udelay(80);
  64         }
  65
  66 -       frame_val  = ((tp->phy_addr << MI_COM_PHY_ADDR_SHIFT) &
  67 +       frame_val  = ((phy_addr << MI_COM_PHY_ADDR_SHIFT) &
  68                       MI_COM_PHY_ADDR_MASK);
  69         frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
  70                       MI_COM_REG_ADDR_MASK);
  71 @@ -902,6 +909,11 @@ static int tg3_writephy(struct tg3 *tp,
  72         return ret;
  73  }
  74
  75 +static int tg3_writephy(struct tg3 *tp, int reg, u32 val)
  76 +{
  77 +       return __tg3_writephy(tp, tp->phy_addr, reg, val);
  78 +}
  79 +
  80  static int tg3_phy_cl45_write(struct tg3 *tp, u32 devad, u32 addr, u32 val)
  81  {
  82         int err;
  83 @@ -2532,6 +2544,9 @@ static int tg3_nvram_read(struct tg3 *tp
  84  {
  85         int ret;
  86
  87 +       if (tg3_flag(tp, IS_SSB_CORE))
  88 +               return -ENODEV;
  89 +
  90         if (!tg3_flag(tp, NVRAM))
  91                 return tg3_nvram_read_using_eeprom(tp, offset, val);
  92
  93 @@ -2855,8 +2870,10 @@ static int tg3_power_down_prepare(struct
  94         tg3_frob_aux_power(tp);
  95
  96         /* Workaround for unstable PLL clock */
  97 -       if ((GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX) ||
  98 -           (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX)) {
  99 +       if ((tp->phy_id & TG3_PHY_ID_MASK) != TG3_PHY_ID_BCM5750_2 &&
 100 +                               /* !!! FIXME !!! */
 101 +           ((GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX) ||
 102 +           (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX))) {
 103                 u32 val = tr32(0x7d00);
 104
 105                 val &= ~((1 << 16) | (1 << 4) | (1 << 2) | (1 << 1) | 1);
 106 @@ -3377,6 +3394,14 @@ relink:
 107         if (current_link_up == 0 || (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)) {
 108                 tg3_phy_copper_begin(tp);
 109
 110 +               if (tg3_flag(tp, ROBOSWITCH)) {
 111 +                       current_link_up = 1;
 112 +                       current_speed = SPEED_1000; /* FIXME */
 113 +                       current_duplex = DUPLEX_FULL;
 114 +                       tp->link_config.active_speed = current_speed;
 115 +                       tp->link_config.active_duplex = current_duplex;
 116 +               }
 117 +
 118                 tg3_readphy(tp, MII_BMSR, &bmsr);
 119                 if ((!tg3_readphy(tp, MII_BMSR, &bmsr) && (bmsr & BMSR_LSTATUS)) ||
 120                     (tp->mac_mode & MAC_MODE_PORT_INT_LPBACK))
 121 @@ -6962,6 +6987,11 @@ static int tg3_poll_fw(struct tg3 *tp)
 122         int i;
 123         u32 val;
 124
 125 +       if (tg3_flag(tp, IS_SSB_CORE)) {
 126 +               /* We don't use firmware. */
 127 +               return 0;
 128 +       }
 129 +
 130         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
 131                 /* Wait up to 20ms for init done. */
 132                 for (i = 0; i < 200; i++) {
 133 @@ -7251,6 +7281,14 @@ static int tg3_chip_reset(struct tg3 *tp
 134                 tw32(0x5000, 0x400);
 135         }
 136
 137 +       if (tg3_flag(tp, IS_SSB_CORE)) {
 138 +               /* BCM4785: In order to avoid repercussions from using potentially
 139 +                * defective internal ROM, stop the Rx RISC CPU, which is not
 140 +                * required. */
 141 +               tg3_stop_fw(tp);
 142 +               tg3_halt_cpu(tp, RX_CPU_BASE);
 143 +       }
 144 +
 145         tw32(GRC_MODE, tp->grc_mode);
 146
 147         if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0) {
 148 @@ -7408,9 +7446,12 @@ static int tg3_halt_cpu(struct tg3 *tp,
 149                 return -ENODEV;
 150         }
 151
 152 -       /* Clear firmware's nvram arbitration. */
 153 -       if (tg3_flag(tp, NVRAM))
 154 -               tw32(NVRAM_SWARB, SWARB_REQ_CLR0);
 155 +       if (!tg3_flag(tp, IS_SSB_CORE)) {
 156 +               /* Clear firmware's nvram arbitration. */
 157 +               if (tg3_flag(tp, NVRAM))
 158 +                       tw32(NVRAM_SWARB, SWARB_REQ_CLR0);
 159 +       }
 160 +
 161         return 0;
 162  }
 163
 164 @@ -7472,6 +7513,11 @@ static int tg3_load_5701_a0_firmware_fix
 165         const __be32 *fw_data;
 166         int err, i;
 167
 168 +       if (tg3_flag(tp, IS_SSB_CORE)) {
 169 +               /* We don't use firmware. */
 170 +               return 0;
 171 +       }
 172 +
 173         fw_data = (void *)tp->fw->data;
 174
 175         /* Firmware blob starts with version numbers, followed by
 176 @@ -7528,6 +7574,11 @@ static int tg3_load_tso_firmware(struct
 177         unsigned long cpu_base, cpu_scratch_base, cpu_scratch_size;
 178         int err, i;
 179
 180 +       if (tg3_flag(tp, IS_SSB_CORE)) {
 181 +               /* We don't use firmware. */
 182 +               return 0;
 183 +       }
 184 +
 185         if (tg3_flag(tp, HW_TSO_1) ||
 186             tg3_flag(tp, HW_TSO_2) ||
 187             tg3_flag(tp, HW_TSO_3))
 188 @@ -8825,6 +8876,11 @@ static void tg3_timer(unsigned long __op
 189
 190         spin_lock(&tp->lock);
 191
 192 +       if (tg3_flag(tp, FLUSH_POSTED_WRITES)) {
 193 +               /* BCM4785: Flush posted writes from GbE to host memory. */
 194 +               tr32(HOSTCC_MODE);
 195 +       }
 196 +
 197         if (!tg3_flag(tp, TAGGED_STATUS)) {
 198                 /* All of this garbage is because when using non-tagged
 199                  * IRQ status the mailbox/status_block protocol the chip
 200 @@ -10448,6 +10504,11 @@ static int tg3_test_nvram(struct tg3 *tp
 201         if (tg3_flag(tp, NO_NVRAM))
 202                 return 0;
 203
 204 +       if (tg3_flag(tp, IS_SSB_CORE)) {
 205 +               /* We don't have NVRAM. */
 206 +               return 0;
 207 +       }
 208 +
 209         if (tg3_nvram_read(tp, 0, &magic) != 0)
 210                 return -EIO;
 211
 212 @@ -11442,7 +11503,7 @@ static int tg3_ioctl(struct net_device *
 213                         return -EAGAIN;
 214
 215                 spin_lock_bh(&tp->lock);
 216 -               err = tg3_readphy(tp, data->reg_num & 0x1f, &mii_regval);
 217 +               err = __tg3_readphy(tp, data->phy_id & 0x1f, data->reg_num & 0x1f, &mii_regval);
 218                 spin_unlock_bh(&tp->lock);
 219
 220                 data->val_out = mii_regval;
 221 @@ -11458,7 +11519,7 @@ static int tg3_ioctl(struct net_device *
 222                         return -EAGAIN;
 223
 224                 spin_lock_bh(&tp->lock);
 225 -               err = tg3_writephy(tp, data->reg_num & 0x1f, data->val_in);
 226 +               err = __tg3_writephy(tp, data->phy_id & 0x1f, data->reg_num & 0x1f, data->val_in);
 227                 spin_unlock_bh(&tp->lock);
 228
 229                 return err;
 230 @@ -12188,6 +12249,13 @@ static void __devinit tg3_get_5720_nvram
 231  /* Chips other than 5700/5701 use the NVRAM for fetching info. */
 232  static void __devinit tg3_nvram_init(struct tg3 *tp)
 233  {
 234 +       if (tg3_flag(tp, IS_SSB_CORE)) {
 235 +               /* No NVRAM and EEPROM on the SSB Broadcom GigE core. */
 236 +               tg3_flag_clear(tp, NVRAM);
 237 +               tg3_flag_clear(tp, NVRAM_BUFFERED);
 238 +               return;
 239 +       }
 240 +
 241         tw32_f(GRC_EEPROM_ADDR,
 242              (EEPROM_ADDR_FSM_RESET |
 243               (EEPROM_DEFAULT_CLOCK_PERIOD <<
 244 @@ -12454,6 +12522,9 @@ static int tg3_nvram_write_block(struct
 245  {
 246         int ret;
 247
 248 +       if (tg3_flag(tp, IS_SSB_CORE))
 249 +               return -ENODEV;
 250 +
 251         if (tg3_flag(tp, EEPROM_WRITE_PROT)) {
 252                 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl &
 253                        ~GRC_LCLCTRL_GPIO_OUTPUT1);
 254 @@ -13863,6 +13934,11 @@ static int __devinit tg3_get_invariants(
 255               GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)))
 256                 tg3_flag_set(tp, SRAM_USE_CONFIG);
 257
 258 +       if (tg3_flag(tp, FLUSH_POSTED_WRITES)) {
 259 +               tp->write32_tx_mbox = tg3_write_flush_reg32;
 260 +               tp->write32_rx_mbox = tg3_write_flush_reg32;
 261 +       }
 262 +
 263         /* Get eeprom hw config before calling tg3_set_power_state().
 264          * In particular, the TG3_FLAG_IS_NIC flag must be
 265          * determined before calling tg3_set_power_state() so that
 266 @@ -14274,6 +14350,8 @@ static int __devinit tg3_get_device_addr
 267         }
 268
 269         if (!is_valid_ether_addr(&dev->dev_addr[0])) {
 270 +               if (tg3_flag(tp, IS_SSB_CORE))
 271 +                       ssb_gige_get_macaddr(tp->pdev, &dev->dev_addr[0]);
 272  #ifdef CONFIG_SPARC
 273                 if (!tg3_get_default_macaddr_sparc(tp))
 274                         return 0;
 275 @@ -14772,6 +14850,7 @@ static char * __devinit tg3_phy_string(s
 276         case TG3_PHY_ID_BCM5704:        return "5704";
 277         case TG3_PHY_ID_BCM5705:        return "5705";
 278         case TG3_PHY_ID_BCM5750:        return "5750";
 279 +       case TG3_PHY_ID_BCM5750_2:      return "5750-2";
 280         case TG3_PHY_ID_BCM5752:        return "5752";
 281         case TG3_PHY_ID_BCM5714:        return "5714";
 282         case TG3_PHY_ID_BCM5780:        return "5780";
 283 @@ -14961,6 +15040,13 @@ static int __devinit tg3_init_one(struct
 284                 tp->msg_enable = tg3_debug;
 285         else
 286                 tp->msg_enable = TG3_DEF_MSG_ENABLE;
 287 +       if (pdev_is_ssb_gige_core(pdev)) {
 288 +               tg3_flag_set(tp, IS_SSB_CORE);
 289 +               if (ssb_gige_must_flush_posted_writes(pdev))
 290 +                       tg3_flag_set(tp, FLUSH_POSTED_WRITES);
 291 +               if (ssb_gige_have_roboswitch(pdev))
 292 +                       tg3_flag_set(tp, ROBOSWITCH);
 293 +       }
 294
 295         /* The word/byte swap controls here control register access byte
 296          * swapping.  DMA data byte swapping is controlled in the GRC_MODE
 297 --- a/drivers/net/tg3.h
 298 +++ b/drivers/net/tg3.h
 299 @@ -2901,6 +2901,9 @@ enum TG3_FLAGS {
 300         TG3_FLAG_57765_PLUS,
 301         TG3_FLAG_APE_HAS_NCSI,
 302         TG3_FLAG_5717_PLUS,
 303 +       TG3_FLAG_IS_SSB_CORE,
 304 +       TG3_FLAG_FLUSH_POSTED_WRITES,
 305 +       TG3_FLAG_ROBOSWITCH,
 306
 307         /* Add new flags before this comment and TG3_FLAG_NUMBER_OF_FLAGS */
 308         TG3_FLAG_NUMBER_OF_FLAGS,       /* Last entry in enum TG3_FLAGS */
 309 @@ -3051,6 +3054,7 @@ struct tg3 {
 310  #define TG3_PHY_ID_BCM5704             0x60008190
 311  #define TG3_PHY_ID_BCM5705             0x600081a0
 312  #define TG3_PHY_ID_BCM5750             0x60008180
 313 +#define TG3_PHY_ID_BCM5750_2           0xbc050cd0
 314  #define TG3_PHY_ID_BCM5752             0x60008100
 315  #define TG3_PHY_ID_BCM5714             0x60008340
 316  #define TG3_PHY_ID_BCM5780             0x60008350
 317 @@ -3088,7 +3092,7 @@ struct tg3 {
 318          (X) == TG3_PHY_ID_BCM5906 || (X) == TG3_PHY_ID_BCM5761 || \
 319          (X) == TG3_PHY_ID_BCM5718C || (X) == TG3_PHY_ID_BCM5718S || \
 320          (X) == TG3_PHY_ID_BCM57765 || (X) == TG3_PHY_ID_BCM5719C || \
 321 -        (X) == TG3_PHY_ID_BCM8002)
 322 +        (X) == TG3_PHY_ID_BCM8002 || (X) == TG3_PHY_ID_BCM5750_2)
 323
 324         u32                             phy_flags;
 325  #define TG3_PHYFLG_IS_LOW_POWER                0x00000001