target/linux/lantiq/patches-3.2/0051-MIPS-adds-gptu-driver.patch

   1 From a7c55f5e927b69bb30912fe1c3e5bcd8751e8381 Mon Sep 17 00:00:00 2001
   2 From: John Crispin <blogic@openwrt.org>
   3 Date: Wed, 14 Mar 2012 15:37:19 +0100
   4 Subject: [PATCH 51/70] MIPS: adds gptu driver
   5
   6 ---
   7  arch/mips/lantiq/xway/gptu.c |  176 ++++++++++++++++++++++++++++++++++++++++++
   8  1 files changed, 176 insertions(+), 0 deletions(-)
   9  create mode 100644 arch/mips/lantiq/xway/gptu.c
  10
  11 --- /dev/null
  12 +++ b/arch/mips/lantiq/xway/gptu.c
  13 @@ -0,0 +1,176 @@
  14 +/*
  15 + *  This program is free software; you can redistribute it and/or modify it
  16 + *  under the terms of the GNU General Public License version 2 as published
  17 + *  by the Free Software Foundation.
  18 + *
  19 + *  Copyright (C) 2012 John Crispin <blogic@openwrt.org>
  20 + */
  21 +
  22 +#include <linux/init.h>
  23 +#include <linux/io.h>
  24 +#include <linux/ioport.h>
  25 +#include <linux/pm.h>
  26 +#include <linux/export.h>
  27 +#include <linux/delay.h>
  28 +#include <linux/interrupt.h>
  29 +#include <asm/reboot.h>
  30 +
  31 +#include <lantiq_soc.h>
  32 +#include "../clk.h"
  33 +
  34 +#include "../devices.h"
  35 +
  36 +#define ltq_gptu_w32(x, y)     ltq_w32((x), ltq_gptu_membase + (y))
  37 +#define ltq_gptu_r32(x)                ltq_r32(ltq_gptu_membase + (x))
  38 +
  39 +
  40 +/* the magic ID byte of the core */
  41 +#define GPTU_MAGIC     0x59
  42 +/* clock control register */
  43 +#define GPTU_CLC       0x00
  44 +/* id register */
  45 +#define GPTU_ID                0x08
  46 +/* interrupt node enable */
  47 +#define GPTU_IRNEN     0xf4
  48 +/* interrupt control register */
  49 +#define GPTU_IRCR      0xf8
  50 +/* interrupt capture register */
  51 +#define GPTU_IRNCR     0xfc
  52 +/* there are 3 identical blocks of 2 timers. calculate register offsets */
  53 +#define GPTU_SHIFT(x)  (x % 2 ? 4 : 0)
  54 +#define GPTU_BASE(x)   (((x >> 1) * 0x20) + 0x10)
  55 +/* timer control register */
  56 +#define GPTU_CON(x)    (GPTU_BASE(x) + GPTU_SHIFT(x) + 0x00)
  57 +/* timer auto reload register */
  58 +#define GPTU_RUN(x)    (GPTU_BASE(x) + GPTU_SHIFT(x) + 0x08)
  59 +/* timer manual reload register */
  60 +#define GPTU_RLD(x)    (GPTU_BASE(x) + GPTU_SHIFT(x) + 0x10)
  61 +/* timer count register */
  62 +#define GPTU_CNT(x)    (GPTU_BASE(x) + GPTU_SHIFT(x) + 0x18)
  63 +
  64 +/* GPTU_CON(x) */
  65 +#define CON_CNT                BIT(2)
  66 +#define CON_EDGE_FALL  BIT(7)
  67 +#define CON_SYNC       BIT(8)
  68 +#define CON_CLK_INT    BIT(10)
  69 +
  70 +/* GPTU_RUN(x) */
  71 +#define RUN_SEN                BIT(0)
  72 +#define RUN_RL         BIT(2)
  73 +
  74 +/* set clock to runmode */
  75 +#define CLC_RMC                BIT(8)
  76 +/* bring core out of suspend */
  77 +#define CLC_SUSPEND    BIT(4)
  78 +/* the disable bit */
  79 +#define CLC_DISABLE    BIT(0)
  80 +
  81 +#define TIMER_INTERRUPT        (INT_NUM_IM3_IRL0 + 22)
  82 +
  83 +enum gptu_timer {
  84 +       TIMER1A = 0,
  85 +       TIMER1B,
  86 +       TIMER2A,
  87 +       TIMER2B,
  88 +       TIMER3A,
  89 +       TIMER3B
  90 +};
  91 +
  92 +static struct resource ltq_gptu_resource =
  93 +       MEM_RES("GPTU", LTQ_GPTU_BASE_ADDR, LTQ_GPTU_SIZE);
  94 +
  95 +static void __iomem *ltq_gptu_membase;
  96 +
  97 +static irqreturn_t timer_irq_handler(int irq, void *priv)
  98 +{
  99 +       int timer = irq - TIMER_INTERRUPT;
 100 +       ltq_gptu_w32(1 << timer, GPTU_IRNCR);
 101 +       return IRQ_HANDLED;
 102 +}
 103 +
 104 +static void gptu_hwinit(void)
 105 +{
 106 +       struct clk *clk = clk_get_sys("ltq_gptu", NULL);
 107 +       clk_enable(clk);
 108 +       ltq_gptu_w32(0x00, GPTU_IRNEN);
 109 +       ltq_gptu_w32(0xff, GPTU_IRNCR);
 110 +       ltq_gptu_w32(CLC_RMC | CLC_SUSPEND, GPTU_CLC);
 111 +}
 112 +
 113 +static void gptu_hwexit(void)
 114 +{
 115 +       ltq_gptu_w32(0x00, GPTU_IRNEN);
 116 +       ltq_gptu_w32(0xff, GPTU_IRNCR);
 117 +       ltq_gptu_w32(CLC_DISABLE, GPTU_CLC);
 118 +}
 119 +
 120 +static int ltq_gptu_enable(struct clk *clk)
 121 +{
 122 +       int ret = request_irq(TIMER_INTERRUPT + clk->bits, timer_irq_handler,
 123 +               IRQF_TIMER, "timer", NULL);
 124 +       if (ret) {
 125 +               pr_err("gptu: failed to request irq\n");
 126 +               return ret;
 127 +       }
 128 +
 129 +        ltq_gptu_w32(CON_CNT | CON_EDGE_FALL | CON_SYNC | CON_CLK_INT,
 130 +               GPTU_CON(clk->bits));
 131 +       ltq_gptu_w32(1, GPTU_RLD(clk->bits));
 132 +       ltq_gptu_w32(ltq_gptu_r32(GPTU_IRNEN) | clk->bits, GPTU_IRNEN);
 133 +       ltq_gptu_w32(RUN_SEN | RUN_RL, GPTU_RUN(clk->bits));
 134 +       return 0;
 135 +}
 136 +
 137 +static void ltq_gptu_disable(struct clk *clk)
 138 +{
 139 +       ltq_gptu_w32(0, GPTU_RUN(clk->bits));
 140 +       ltq_gptu_w32(0, GPTU_CON(clk->bits));
 141 +       ltq_gptu_w32(0, GPTU_RLD(clk->bits));
 142 +       ltq_gptu_w32(ltq_gptu_r32(GPTU_IRNEN) & ~clk->bits, GPTU_IRNEN);
 143 +       free_irq(TIMER_INTERRUPT + clk->bits, NULL);
 144 +}
 145 +
 146 +static inline void clkdev_add_gptu(const char *con, unsigned int timer)
 147 +{
 148 +       struct clk *clk = kzalloc(sizeof(struct clk), GFP_KERNEL);
 149 +
 150 +       clk->cl.dev_id = "ltq_gptu";
 151 +       clk->cl.con_id = con;
 152 +       clk->cl.clk = clk;
 153 +       clk->enable = ltq_gptu_enable;
 154 +       clk->disable = ltq_gptu_disable;
 155 +       clk->bits = timer;
 156 +       clkdev_add(&clk->cl);
 157 +}
 158 +
 159 +static int __init gptu_setup(void)
 160 +{
 161 +       /* remap gptu register range */
 162 +       ltq_gptu_membase = ltq_remap_resource(&ltq_gptu_resource);
 163 +       if (!ltq_gptu_membase)
 164 +               panic("Failed to remap gptu memory");
 165 +
 166 +       /* power up the core */
 167 +       gptu_hwinit();
 168 +
 169 +       /* the gptu has a ID register */
 170 +       if (((ltq_gptu_r32(GPTU_ID) >> 8) & 0xff) != GPTU_MAGIC) {
 171 +               pr_err("gptu: failed to find magic\n");
 172 +               gptu_hwexit();
 173 +               return -ENAVAIL;
 174 +       }
 175 +
 176 +       /* register the clocks */
 177 +       clkdev_add_gptu("timer1a", TIMER1A);
 178 +       clkdev_add_gptu("timer1b", TIMER1B);
 179 +       clkdev_add_gptu("timer2a", TIMER2A);
 180 +       clkdev_add_gptu("timer2b", TIMER2B);
 181 +       clkdev_add_gptu("timer3a", TIMER3A);
 182 +       clkdev_add_gptu("timer3b", TIMER3B);
 183 +
 184 +       pr_info("gptu: 6 timers loaded\n");
 185 +
 186 +       return 0;
 187 +}
 188 +
 189 +arch_initcall(gptu_setup);