target/linux/xburst/patches-2.6.35/007-power-management.patch

   1 From 0c5476ab44aaffafcdce4885f09e86b300eb2241 Mon Sep 17 00:00:00 2001
   2 From: Lars-Peter Clausen <lars@metafoo.de>
   3 Date: Sat, 19 Jun 2010 04:08:11 +0000
   4 Subject: [PATCH] MIPS: JZ4740: Add power-management and system reset support
   5
   6 Add support for suspend/resume and poweroff/reboot on a JZ4740 SoC.
   7
   8 Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
   9 Cc: linux-mips@linux-mips.org
  10 Cc: linux-kernel@vger.kernel.org
  11 Patchwork: https://patchwork.linux-mips.org/patch/1398/
  12 Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
  13 ---
  14  arch/mips/jz4740/pm.c    |   56 ++++++++++++++++++++++++++++++++
  15  arch/mips/jz4740/reset.c |   79 ++++++++++++++++++++++++++++++++++++++++++++++
  16  arch/mips/jz4740/reset.h |    6 +++
  17  3 files changed, 141 insertions(+), 0 deletions(-)
  18  create mode 100644 arch/mips/jz4740/pm.c
  19  create mode 100644 arch/mips/jz4740/reset.c
  20  create mode 100644 arch/mips/jz4740/reset.h
  21
  22 --- /dev/null
  23 +++ b/arch/mips/jz4740/pm.c
  24 @@ -0,0 +1,56 @@
  25 +/*
  26 + *  Copyright (C) 2010, Lars-Peter Clausen <lars@metafoo.de>
  27 + *     JZ4740 SoC power management support
  28 + *
  29 + *  This program is free software; you can redistribute it and/or modify it
  30 + *  under  the terms of the GNU General  Public License as published by the
  31 + *  Free Software Foundation;  either version 2 of the License, or (at your
  32 + *  option) any later version.
  33 + *
  34 + *  You should have received a copy of the GNU General Public License along
  35 + *  with this program; if not, write to the Free Software Foundation, Inc.,
  36 + *  675 Mass Ave, Cambridge, MA 02139, USA.
  37 + *
  38 + */
  39 +
  40 +#include <linux/init.h>
  41 +#include <linux/pm.h>
  42 +#include <linux/delay.h>
  43 +#include <linux/suspend.h>
  44 +
  45 +#include <asm/mach-jz4740/clock.h>
  46 +
  47 +#include "clock.h"
  48 +#include "irq.h"
  49 +
  50 +static int jz4740_pm_enter(suspend_state_t state)
  51 +{
  52 +       jz4740_intc_suspend();
  53 +       jz4740_clock_suspend();
  54 +
  55 +       jz4740_clock_set_wait_mode(JZ4740_WAIT_MODE_SLEEP);
  56 +
  57 +       __asm__(".set\tmips3\n\t"
  58 +               "wait\n\t"
  59 +               ".set\tmips0");
  60 +
  61 +       jz4740_clock_set_wait_mode(JZ4740_WAIT_MODE_IDLE);
  62 +
  63 +       jz4740_clock_resume();
  64 +       jz4740_intc_resume();
  65 +
  66 +       return 0;
  67 +}
  68 +
  69 +static struct platform_suspend_ops jz4740_pm_ops = {
  70 +       .valid          = suspend_valid_only_mem,
  71 +       .enter          = jz4740_pm_enter,
  72 +};
  73 +
  74 +static int __init jz4740_pm_init(void)
  75 +{
  76 +       suspend_set_ops(&jz4740_pm_ops);
  77 +       return 0;
  78 +
  79 +}
  80 +late_initcall(jz4740_pm_init);
  81 --- /dev/null
  82 +++ b/arch/mips/jz4740/reset.c
  83 @@ -0,0 +1,79 @@
  84 +/*
  85 + *  Copyright (C) 2010, Lars-Peter Clausen <lars@metafoo.de>
  86 + *
  87 + *  This program is free software; you can redistribute it and/or modify it
  88 + *  under  the terms of the GNU General  Public License as published by the
  89 + *  Free Software Foundation;  either version 2 of the License, or (at your
  90 + *  option) any later version.
  91 + *
  92 + *  You should have received a copy of the GNU General Public License along
  93 + *  with this program; if not, write to the Free Software Foundation, Inc.,
  94 + *  675 Mass Ave, Cambridge, MA 02139, USA.
  95 + *
  96 + */
  97 +
  98 +#include <linux/io.h>
  99 +#include <linux/kernel.h>
 100 +#include <linux/pm.h>
 101 +
 102 +#include <asm/reboot.h>
 103 +
 104 +#include <asm/mach-jz4740/base.h>
 105 +#include <asm/mach-jz4740/timer.h>
 106 +
 107 +static void jz4740_halt(void)
 108 +{
 109 +       while (1) {
 110 +               __asm__(".set push;\n"
 111 +                       ".set mips3;\n"
 112 +                       "wait;\n"
 113 +                       ".set pop;\n"
 114 +               );
 115 +       }
 116 +}
 117 +
 118 +#define JZ_REG_WDT_DATA 0x00
 119 +#define JZ_REG_WDT_COUNTER_ENABLE 0x04
 120 +#define JZ_REG_WDT_COUNTER 0x08
 121 +#define JZ_REG_WDT_CTRL 0x0c
 122 +
 123 +static void jz4740_restart(char *command)
 124 +{
 125 +       void __iomem *wdt_base = ioremap(JZ4740_WDT_BASE_ADDR, 0x0f);
 126 +
 127 +       jz4740_timer_enable_watchdog();
 128 +
 129 +       writeb(0, wdt_base + JZ_REG_WDT_COUNTER_ENABLE);
 130 +
 131 +       writew(0, wdt_base + JZ_REG_WDT_COUNTER);
 132 +       writew(0, wdt_base + JZ_REG_WDT_DATA);
 133 +       writew(BIT(2), wdt_base + JZ_REG_WDT_CTRL);
 134 +
 135 +       writeb(1, wdt_base + JZ_REG_WDT_COUNTER_ENABLE);
 136 +       jz4740_halt();
 137 +}
 138 +
 139 +#define JZ_REG_RTC_CTRL                0x00
 140 +#define JZ_REG_RTC_HIBERNATE   0x20
 141 +
 142 +#define JZ_RTC_CTRL_WRDY       BIT(7)
 143 +
 144 +static void jz4740_power_off(void)
 145 +{
 146 +       void __iomem *rtc_base = ioremap(JZ4740_RTC_BASE_ADDR, 0x24);
 147 +       uint32_t ctrl;
 148 +
 149 +       do {
 150 +               ctrl = readl(rtc_base + JZ_REG_RTC_CTRL);
 151 +       } while (!(ctrl & JZ_RTC_CTRL_WRDY));
 152 +
 153 +       writel(1, rtc_base + JZ_REG_RTC_HIBERNATE);
 154 +       jz4740_halt();
 155 +}
 156 +
 157 +void jz4740_reset_init(void)
 158 +{
 159 +       _machine_restart = jz4740_restart;
 160 +       _machine_halt = jz4740_halt;
 161 +       pm_power_off = jz4740_power_off;
 162 +}
 163 --- /dev/null
 164 +++ b/arch/mips/jz4740/reset.h
 165 @@ -0,0 +1,6 @@
 166 +#ifndef __MIPS_JZ4740_RESET_H__
 167 +#define __MIPS_JZ4740_RESET_H__
 168 +
 169 +extern void jz4740_reset_init(void);
 170 +
 171 +#endif