target/linux/xburst/patches-2.6.35/052-rtc.patch

   1 From 21a0c050c7471b9d87e720a84f6733bbe8e19835 Mon Sep 17 00:00:00 2001
   2 From: Lars-Peter Clausen <lars@metafoo.de>
   3 Date: Sat, 19 Jun 2010 18:29:50 +0000
   4 Subject: [PATCH] RTC: Add JZ4740 RTC driver
   5
   6 Add support for the RTC unit on JZ4740 SoCs.
   7
   8 Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
   9 Cc: Alessandro Zummo <a.zummo@towertech.it>
  10 Cc: Paul Gortmaker <p_gortmaker@yahoo.com>
  11 Cc: rtc-linux@googlegroups.com
  12 Acked-by: Wan ZongShun <mcuos.com@gmail.com>
  13 Cc: linux-mips@linux-mips.org
  14 Cc: linux-kernel@vger.kernel.org
  15 Cc: Alessandro Zummo <a.zummo@towertech.it>,
  16 Patchwork: https://patchwork.linux-mips.org/patch/1424/
  17 Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
  18 ---
  19  drivers/rtc/Kconfig      |   11 ++
  20  drivers/rtc/Makefile     |    1 +
  21  drivers/rtc/rtc-jz4740.c |  345 ++++++++++++++++++++++++++++++++++++++++++++++
  22  3 files changed, 357 insertions(+), 0 deletions(-)
  23  create mode 100644 drivers/rtc/rtc-jz4740.c
  24
  25 --- a/drivers/rtc/Kconfig
  26 +++ b/drivers/rtc/Kconfig
  27 @@ -914,4 +914,15 @@ config RTC_DRV_MPC5121
  28           This driver can also be built as a module. If so, the module
  29           will be called rtc-mpc5121.
  30
  31 +config RTC_DRV_JZ4740
  32 +       tristate "Ingenic JZ4740 SoC"
  33 +       depends on RTC_CLASS
  34 +       depends on MACH_JZ4740
  35 +       help
  36 +         If you say yes here you get support for the Ingenic JZ4740 SoC RTC
  37 +         controller.
  38 +
  39 +         This driver can also be buillt as a module. If so, the module
  40 +         will be called rtc-jz4740.
  41 +
  42  endif # RTC_CLASS
  43 --- a/drivers/rtc/Makefile
  44 +++ b/drivers/rtc/Makefile
  45 @@ -47,6 +47,7 @@ obj-$(CONFIG_RTC_DRV_EP93XX)  += rtc-ep93
  46  obj-$(CONFIG_RTC_DRV_FM3130)   += rtc-fm3130.o
  47  obj-$(CONFIG_RTC_DRV_GENERIC)  += rtc-generic.o
  48  obj-$(CONFIG_RTC_DRV_ISL1208)  += rtc-isl1208.o
  49 +obj-$(CONFIG_RTC_DRV_JZ4740)   += rtc-jz4740.o
  50  obj-$(CONFIG_RTC_DRV_M41T80)   += rtc-m41t80.o
  51  obj-$(CONFIG_RTC_DRV_M41T94)   += rtc-m41t94.o
  52  obj-$(CONFIG_RTC_DRV_M48T35)   += rtc-m48t35.o
  53 --- /dev/null
  54 +++ b/drivers/rtc/rtc-jz4740.c
  55 @@ -0,0 +1,345 @@
  56 +/*
  57 + *  Copyright (C) 2009-2010, Lars-Peter Clausen <lars@metafoo.de>
  58 + *      JZ4740 SoC RTC driver
  59 + *
  60 + *  This program is free software; you can redistribute it and/or modify it
  61 + *  under  the terms of  the GNU General Public License as published by the
  62 + *  Free Software Foundation;  either version 2 of the License, or (at your
  63 + *  option) any later version.
  64 + *
  65 + *  You should have received a copy of the GNU General Public License along
  66 + *  with this program; if not, write to the Free Software Foundation, Inc.,
  67 + *  675 Mass Ave, Cambridge, MA 02139, USA.
  68 + *
  69 + */
  70 +
  71 +#include <linux/kernel.h>
  72 +#include <linux/module.h>
  73 +#include <linux/platform_device.h>
  74 +#include <linux/rtc.h>
  75 +#include <linux/slab.h>
  76 +#include <linux/spinlock.h>
  77 +
  78 +#define JZ_REG_RTC_CTRL                0x00
  79 +#define JZ_REG_RTC_SEC         0x04
  80 +#define JZ_REG_RTC_SEC_ALARM   0x08
  81 +#define JZ_REG_RTC_REGULATOR   0x0C
  82 +#define JZ_REG_RTC_HIBERNATE   0x20
  83 +#define JZ_REG_RTC_SCRATCHPAD  0x34
  84 +
  85 +#define JZ_RTC_CTRL_WRDY       BIT(7)
  86 +#define JZ_RTC_CTRL_1HZ                BIT(6)
  87 +#define JZ_RTC_CTRL_1HZ_IRQ    BIT(5)
  88 +#define JZ_RTC_CTRL_AF         BIT(4)
  89 +#define JZ_RTC_CTRL_AF_IRQ     BIT(3)
  90 +#define JZ_RTC_CTRL_AE         BIT(2)
  91 +#define JZ_RTC_CTRL_ENABLE     BIT(0)
  92 +
  93 +struct jz4740_rtc {
  94 +       struct resource *mem;
  95 +       void __iomem *base;
  96 +
  97 +       struct rtc_device *rtc;
  98 +
  99 +       unsigned int irq;
 100 +
 101 +       spinlock_t lock;
 102 +};
 103 +
 104 +static inline uint32_t jz4740_rtc_reg_read(struct jz4740_rtc *rtc, size_t reg)
 105 +{
 106 +       return readl(rtc->base + reg);
 107 +}
 108 +
 109 +static int jz4740_rtc_wait_write_ready(struct jz4740_rtc *rtc)
 110 +{
 111 +       uint32_t ctrl;
 112 +       int timeout = 1000;
 113 +
 114 +       do {
 115 +               ctrl = jz4740_rtc_reg_read(rtc, JZ_REG_RTC_CTRL);
 116 +       } while (!(ctrl & JZ_RTC_CTRL_WRDY) && --timeout);
 117 +
 118 +       return timeout ? 0 : -EIO;
 119 +}
 120 +
 121 +static inline int jz4740_rtc_reg_write(struct jz4740_rtc *rtc, size_t reg,
 122 +       uint32_t val)
 123 +{
 124 +       int ret;
 125 +       ret = jz4740_rtc_wait_write_ready(rtc);
 126 +       if (ret == 0)
 127 +               writel(val, rtc->base + reg);
 128 +
 129 +       return ret;
 130 +}
 131 +
 132 +static int jz4740_rtc_ctrl_set_bits(struct jz4740_rtc *rtc, uint32_t mask,
 133 +       bool set)
 134 +{
 135 +       int ret;
 136 +       unsigned long flags;
 137 +       uint32_t ctrl;
 138 +
 139 +       spin_lock_irqsave(&rtc->lock, flags);
 140 +
 141 +       ctrl = jz4740_rtc_reg_read(rtc, JZ_REG_RTC_CTRL);
 142 +
 143 +       /* Don't clear interrupt flags by accident */
 144 +       ctrl |= JZ_RTC_CTRL_1HZ | JZ_RTC_CTRL_AF;
 145 +
 146 +       if (set)
 147 +               ctrl |= mask;
 148 +       else
 149 +               ctrl &= ~mask;
 150 +
 151 +       ret = jz4740_rtc_reg_write(rtc, JZ_REG_RTC_CTRL, ctrl);
 152 +
 153 +       spin_unlock_irqrestore(&rtc->lock, flags);
 154 +
 155 +       return ret;
 156 +}
 157 +
 158 +static int jz4740_rtc_read_time(struct device *dev, struct rtc_time *time)
 159 +{
 160 +       struct jz4740_rtc *rtc = dev_get_drvdata(dev);
 161 +       uint32_t secs, secs2;
 162 +       int timeout = 5;
 163 +
 164 +       /* If the seconds register is read while it is updated, it can contain a
 165 +        * bogus value. This can be avoided by making sure that two consecutive
 166 +        * reads have the same value.
 167 +        */
 168 +       secs = jz4740_rtc_reg_read(rtc, JZ_REG_RTC_SEC);
 169 +       secs2 = jz4740_rtc_reg_read(rtc, JZ_REG_RTC_SEC);
 170 +
 171 +       while (secs != secs2 && --timeout) {
 172 +               secs = secs2;
 173 +               secs2 = jz4740_rtc_reg_read(rtc, JZ_REG_RTC_SEC);
 174 +       }
 175 +
 176 +       if (timeout == 0)
 177 +               return -EIO;
 178 +
 179 +       rtc_time_to_tm(secs, time);
 180 +
 181 +       return rtc_valid_tm(time);
 182 +}
 183 +
 184 +static int jz4740_rtc_set_mmss(struct device *dev, unsigned long secs)
 185 +{
 186 +       struct jz4740_rtc *rtc = dev_get_drvdata(dev);
 187 +
 188 +       return jz4740_rtc_reg_write(rtc, JZ_REG_RTC_SEC, secs);
 189 +}
 190 +
 191 +static int jz4740_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alrm)
 192 +{
 193 +       struct jz4740_rtc *rtc = dev_get_drvdata(dev);
 194 +       uint32_t secs;
 195 +       uint32_t ctrl;
 196 +
 197 +       secs = jz4740_rtc_reg_read(rtc, JZ_REG_RTC_SEC_ALARM);
 198 +
 199 +       ctrl = jz4740_rtc_reg_read(rtc, JZ_REG_RTC_CTRL);
 200 +
 201 +       alrm->enabled = !!(ctrl & JZ_RTC_CTRL_AE);
 202 +       alrm->pending = !!(ctrl & JZ_RTC_CTRL_AF);
 203 +
 204 +       rtc_time_to_tm(secs, &alrm->time);
 205 +
 206 +       return rtc_valid_tm(&alrm->time);
 207 +}
 208 +
 209 +static int jz4740_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alrm)
 210 +{
 211 +       int ret;
 212 +       struct jz4740_rtc *rtc = dev_get_drvdata(dev);
 213 +       unsigned long secs;
 214 +
 215 +       rtc_tm_to_time(&alrm->time, &secs);
 216 +
 217 +       ret = jz4740_rtc_reg_write(rtc, JZ_REG_RTC_SEC_ALARM, secs);
 218 +       if (!ret)
 219 +               ret = jz4740_rtc_ctrl_set_bits(rtc, JZ_RTC_CTRL_AE, alrm->enabled);
 220 +
 221 +       return ret;
 222 +}
 223 +
 224 +static int jz4740_rtc_update_irq_enable(struct device *dev, unsigned int enable)
 225 +{
 226 +       struct jz4740_rtc *rtc = dev_get_drvdata(dev);
 227 +       return jz4740_rtc_ctrl_set_bits(rtc, JZ_RTC_CTRL_1HZ_IRQ, enable);
 228 +}
 229 +
 230 +static int jz4740_rtc_alarm_irq_enable(struct device *dev, unsigned int enable)
 231 +{
 232 +       struct jz4740_rtc *rtc = dev_get_drvdata(dev);
 233 +       return jz4740_rtc_ctrl_set_bits(rtc, JZ_RTC_CTRL_AF_IRQ, enable);
 234 +}
 235 +
 236 +static struct rtc_class_ops jz4740_rtc_ops = {
 237 +       .read_time      = jz4740_rtc_read_time,
 238 +       .set_mmss       = jz4740_rtc_set_mmss,
 239 +       .read_alarm     = jz4740_rtc_read_alarm,
 240 +       .set_alarm      = jz4740_rtc_set_alarm,
 241 +       .update_irq_enable = jz4740_rtc_update_irq_enable,
 242 +       .alarm_irq_enable = jz4740_rtc_alarm_irq_enable,
 243 +};
 244 +
 245 +static irqreturn_t jz4740_rtc_irq(int irq, void *data)
 246 +{
 247 +       struct jz4740_rtc *rtc = data;
 248 +       uint32_t ctrl;
 249 +       unsigned long events = 0;
 250 +
 251 +       ctrl = jz4740_rtc_reg_read(rtc, JZ_REG_RTC_CTRL);
 252 +
 253 +       if (ctrl & JZ_RTC_CTRL_1HZ)
 254 +               events |= (RTC_UF | RTC_IRQF);
 255 +
 256 +       if (ctrl & JZ_RTC_CTRL_AF)
 257 +               events |= (RTC_AF | RTC_IRQF);
 258 +
 259 +       rtc_update_irq(rtc->rtc, 1, events);
 260 +
 261 +       jz4740_rtc_ctrl_set_bits(rtc, JZ_RTC_CTRL_1HZ | JZ_RTC_CTRL_AF, false);
 262 +
 263 +       return IRQ_HANDLED;
 264 +}
 265 +
 266 +void jz4740_rtc_poweroff(struct device *dev)
 267 +{
 268 +       struct jz4740_rtc *rtc = dev_get_drvdata(dev);
 269 +       jz4740_rtc_reg_write(rtc, JZ_REG_RTC_HIBERNATE, 1);
 270 +}
 271 +EXPORT_SYMBOL_GPL(jz4740_rtc_poweroff);
 272 +
 273 +static int __devinit jz4740_rtc_probe(struct platform_device *pdev)
 274 +{
 275 +       int ret;
 276 +       struct jz4740_rtc *rtc;
 277 +       uint32_t scratchpad;
 278 +
 279 +       rtc = kzalloc(sizeof(*rtc), GFP_KERNEL);
 280 +       if (!rtc)
 281 +               return -ENOMEM;
 282 +
 283 +       rtc->irq = platform_get_irq(pdev, 0);
 284 +       if (rtc->irq < 0) {
 285 +               ret = -ENOENT;
 286 +               dev_err(&pdev->dev, "Failed to get platform irq\n");
 287 +               goto err_free;
 288 +       }
 289 +
 290 +       rtc->mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 291 +       if (!rtc->mem) {
 292 +               ret = -ENOENT;
 293 +               dev_err(&pdev->dev, "Failed to get platform mmio memory\n");
 294 +               goto err_free;
 295 +       }
 296 +
 297 +       rtc->mem = request_mem_region(rtc->mem->start, resource_size(rtc->mem),
 298 +                                       pdev->name);
 299 +       if (!rtc->mem) {
 300 +               ret = -EBUSY;
 301 +               dev_err(&pdev->dev, "Failed to request mmio memory region\n");
 302 +               goto err_free;
 303 +       }
 304 +
 305 +       rtc->base = ioremap_nocache(rtc->mem->start, resource_size(rtc->mem));
 306 +       if (!rtc->base) {
 307 +               ret = -EBUSY;
 308 +               dev_err(&pdev->dev, "Failed to ioremap mmio memory\n");
 309 +               goto err_release_mem_region;
 310 +       }
 311 +
 312 +       spin_lock_init(&rtc->lock);
 313 +
 314 +       platform_set_drvdata(pdev, rtc);
 315 +
 316 +       rtc->rtc = rtc_device_register(pdev->name, &pdev->dev, &jz4740_rtc_ops,
 317 +                                       THIS_MODULE);
 318 +       if (IS_ERR(rtc->rtc)) {
 319 +               ret = PTR_ERR(rtc->rtc);
 320 +               dev_err(&pdev->dev, "Failed to register rtc device: %d\n", ret);
 321 +               goto err_iounmap;
 322 +       }
 323 +
 324 +       ret = request_irq(rtc->irq, jz4740_rtc_irq, 0,
 325 +                               pdev->name, rtc);
 326 +       if (ret) {
 327 +               dev_err(&pdev->dev, "Failed to request rtc irq: %d\n", ret);
 328 +               goto err_unregister_rtc;
 329 +       }
 330 +
 331 +       scratchpad = jz4740_rtc_reg_read(rtc, JZ_REG_RTC_SCRATCHPAD);
 332 +       if (scratchpad != 0x12345678) {
 333 +               ret = jz4740_rtc_reg_write(rtc, JZ_REG_RTC_SCRATCHPAD, 0x12345678);
 334 +               ret = jz4740_rtc_reg_write(rtc, JZ_REG_RTC_SEC, 0);
 335 +               if (ret) {
 336 +                       dev_err(&pdev->dev, "Could not write write to RTC registers\n");
 337 +                       goto err_free_irq;
 338 +               }
 339 +       }
 340 +
 341 +       return 0;
 342 +
 343 +err_free_irq:
 344 +       free_irq(rtc->irq, rtc);
 345 +err_unregister_rtc:
 346 +       rtc_device_unregister(rtc->rtc);
 347 +err_iounmap:
 348 +       platform_set_drvdata(pdev, NULL);
 349 +       iounmap(rtc->base);
 350 +err_release_mem_region:
 351 +       release_mem_region(rtc->mem->start, resource_size(rtc->mem));
 352 +err_free:
 353 +       kfree(rtc);
 354 +
 355 +       return ret;
 356 +}
 357 +
 358 +static int __devexit jz4740_rtc_remove(struct platform_device *pdev)
 359 +{
 360 +       struct jz4740_rtc *rtc = platform_get_drvdata(pdev);
 361 +
 362 +       free_irq(rtc->irq, rtc);
 363 +
 364 +       rtc_device_unregister(rtc->rtc);
 365 +
 366 +       iounmap(rtc->base);
 367 +       release_mem_region(rtc->mem->start, resource_size(rtc->mem));
 368 +
 369 +       kfree(rtc);
 370 +
 371 +       platform_set_drvdata(pdev, NULL);
 372 +
 373 +       return 0;
 374 +}
 375 +
 376 +struct platform_driver jz4740_rtc_driver = {
 377 +       .probe = jz4740_rtc_probe,
 378 +       .remove = __devexit_p(jz4740_rtc_remove),
 379 +       .driver = {
 380 +               .name = "jz4740-rtc",
 381 +               .owner = THIS_MODULE,
 382 +       },
 383 +};
 384 +
 385 +static int __init jz4740_rtc_init(void)
 386 +{
 387 +       return platform_driver_register(&jz4740_rtc_driver);
 388 +}
 389 +module_init(jz4740_rtc_init);
 390 +
 391 +static void __exit jz4740_rtc_exit(void)
 392 +{
 393 +       platform_driver_unregister(&jz4740_rtc_driver);
 394 +}
 395 +module_exit(jz4740_rtc_exit);
 396 +
 397 +MODULE_AUTHOR("Lars-Peter Clausen <lars@metafoo.de>");
 398 +MODULE_LICENSE("GPL");
 399 +MODULE_DESCRIPTION("RTC driver for the JZ4740 SoC\n");
 400 +MODULE_ALIAS("platform:jz4740-rtc");