openwrt/target/linux/aruba-2.6/patches/003-pci.patch

   1 diff -Nur linux-2.6.15/arch/mips/pci/fixup-aruba.c linux-2.6.15-openwrt/arch/mips/pci/fixup-aruba.c
   2 --- linux-2.6.15/arch/mips/pci/fixup-aruba.c    1970-01-01 01:00:00.000000000 +0100
   3 +++ linux-2.6.15-openwrt/arch/mips/pci/fixup-aruba.c    2006-01-10 00:34:41.000000000 +0100
   4 @@ -0,0 +1,115 @@
   5 +/**************************************************************************
   6 + *
   7 + *  BRIEF MODULE DESCRIPTION
   8 + *     PCI fixups for IDT EB434 board
   9 + *
  10 + *  Copyright 2004 IDT Inc. (rischelp@idt.com)
  11 + *
  12 + *  This program is free software; you can redistribute  it and/or modify it
  13 + *  under  the terms of  the GNU General  Public License as published by the
  14 + *  Free Software Foundation;  either version 2 of the  License, or (at your
  15 + *  option) any later version.
  16 + *
  17 + *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
  18 + *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
  19 + *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
  20 + *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
  21 + *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  22 + *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
  23 + *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
  24 + *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
  25 + *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  26 + *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27 + *
  28 + *  You should have received a copy of the  GNU General Public License along
  29 + *  with this program; if not, write  to the Free Software Foundation, Inc.,
  30 + *  675 Mass Ave, Cambridge, MA 02139, USA.
  31 + *
  32 + *
  33 + **************************************************************************
  34 + * May 2004 rkt, neb
  35 + *
  36 + * Initial Release
  37 + *
  38 + *
  39 + *
  40 + **************************************************************************
  41 + */
  42 +
  43 +#include <linux/config.h>
  44 +#include <linux/types.h>
  45 +#include <linux/pci.h>
  46 +#include <linux/kernel.h>
  47 +#include <linux/init.h>
  48 +#include <asm/idt-boards/rc32434/rc32434.h>
  49 +#include <asm/idt-boards/rc32434/rc32434_pci.h>
  50 +
  51 +int __init pcibios_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
  52 +{
  53 +
  54 +       if (dev->bus->number != 0) {
  55 +               return 0;
  56 +       }
  57 +
  58 +       slot = PCI_SLOT(dev->devfn);
  59 +       dev->irq = 0;
  60 +
  61 +       if (slot > 0 && slot <= 15) {
  62 +#if 1
  63 +               if(slot == 10) {
  64 +                       if(pin == 1) dev->irq = GROUP4_IRQ_BASE + 9; // intA
  65 +               } else if(slot == 11) {
  66 +                       if(pin == 1) dev->irq = GROUP4_IRQ_BASE + 10; // intA
  67 +                       if(pin == 2) dev->irq = GROUP4_IRQ_BASE + 10; // intA
  68 +                       if(pin == 3) dev->irq = GROUP4_IRQ_BASE + 10; // intA
  69 +               } else if(slot == 12) {
  70 +                       if(pin == 1) dev->irq = GROUP4_IRQ_BASE + 11; // intA
  71 +                       if(pin == 2) dev->irq = GROUP4_IRQ_BASE + 12; // intB
  72 +               } else if (slot == 13) {
  73 +                       if(pin == 1) dev->irq = GROUP4_IRQ_BASE + 12; // intA
  74 +                       if(pin == 2) dev->irq = GROUP4_IRQ_BASE + 11; // intB
  75 +               } else {
  76 +                       dev->irq = GROUP4_IRQ_BASE + 11;
  77 +               }
  78 +#else
  79 +                                switch (pin) {
  80 +                                case 1: /* INTA*/
  81 +                                        dev->irq = GROUP4_IRQ_BASE + 11;
  82 +                                        break;
  83 +                                case 2: /* INTB */
  84 +                                        dev->irq = GROUP4_IRQ_BASE + 11;
  85 +                                        break;
  86 +                                case 3: /* INTC */
  87 +                                        dev->irq = GROUP4_IRQ_BASE + 11;
  88 +                                        break;
  89 +                                case 4: /* INTD */
  90 +                                        dev->irq = GROUP4_IRQ_BASE + 11;
  91 +                                        break;
  92 +                                default:
  93 +                                        dev->irq = 0xff;
  94 +                                        break;
  95 +                                }
  96 +#endif
  97 +#ifdef DEBUG
  98 +               printk("irq fixup: slot %d, pin %d, irq %d\n",
  99 +                      slot, pin, dev->irq);
 100 +#endif
 101 +               pci_write_config_byte(dev, PCI_INTERRUPT_LINE,dev->irq);
 102 +       }
 103 +       return (dev->irq);
 104 +}
 105 +
 106 +struct pci_fixup pcibios_fixups[] = {
 107 +       {0}
 108 +};
 109 +
 110 +
 111 +
 112 +
 113 +
 114 +
 115 +
 116 +
 117 +
 118 +
 119 +
 120 diff -Nur linux-2.6.15/arch/mips/pci/Makefile linux-2.6.15-openwrt/arch/mips/pci/Makefile
 121 --- linux-2.6.15/arch/mips/pci/Makefile 2006-01-03 04:21:10.000000000 +0100
 122 +++ linux-2.6.15-openwrt/arch/mips/pci/Makefile 2006-01-10 00:32:32.000000000 +0100
 123 @@ -56,3 +56,4 @@
 124  obj-$(CONFIG_TOSHIBA_RBTX4938) += fixup-tx4938.o ops-tx4938.o
 125  obj-$(CONFIG_VICTOR_MPC30X)    += fixup-mpc30x.o
 126  obj-$(CONFIG_ZAO_CAPCELLA)     += fixup-capcella.o
 127 +obj-$(CONFIG_MACH_ARUBA)        += fixup-aruba.o ops-aruba.o pci-aruba.o
 128 diff -Nur linux-2.6.15/arch/mips/pci/ops-aruba.c linux-2.6.15-openwrt/arch/mips/pci/ops-aruba.c
 129 --- linux-2.6.15/arch/mips/pci/ops-aruba.c      1970-01-01 01:00:00.000000000 +0100
 130 +++ linux-2.6.15-openwrt/arch/mips/pci/ops-aruba.c      2006-01-10 00:32:32.000000000 +0100
 131 @@ -0,0 +1,204 @@
 132 +/**************************************************************************
 133 + *
 134 + *  BRIEF MODULE DESCRIPTION
 135 + *     pci_ops for IDT EB434 board
 136 + *
 137 + *  Copyright 2004 IDT Inc. (rischelp@idt.com)
 138 + *
 139 + *  This program is free software; you can redistribute  it and/or modify it
 140 + *  under  the terms of  the GNU General  Public License as published by the
 141 + *  Free Software Foundation;  either version 2 of the  License, or (at your
 142 + *  option) any later version.
 143 + *
 144 + *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
 145 + *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
 146 + *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
 147 + *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
 148 + *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
 149 + *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
 150 + *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
 151 + *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
 152 + *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
 153 + *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 154 + *
 155 + *  You should have received a copy of the  GNU General Public License along
 156 + *  with this program; if not, write  to the Free Software Foundation, Inc.,
 157 + *  675 Mass Ave, Cambridge, MA 02139, USA.
 158 + *
 159 + *
 160 + **************************************************************************
 161 + * May 2004 rkt, neb
 162 + *
 163 + * Initial Release
 164 + *
 165 + *
 166 + *
 167 + **************************************************************************
 168 + */
 169 +
 170 +#include <linux/config.h>
 171 +#include <linux/init.h>
 172 +#include <linux/pci.h>
 173 +#include <linux/types.h>
 174 +#include <linux/delay.h>
 175 +
 176 +#include <asm/cpu.h>
 177 +#include <asm/io.h>
 178 +
 179 +#include <asm/idt-boards/rc32434/rc32434.h>
 180 +#include <asm/idt-boards/rc32434/rc32434_pci.h>
 181 +
 182 +#define PCI_ACCESS_READ  0
 183 +#define PCI_ACCESS_WRITE 1
 184 +
 185 +
 186 +#define PCI_CFG_SET(slot,func,off) \
 187 +       (rc32434_pci->pcicfga = (0x80000000 | ((slot)<<11) | \
 188 +                           ((func)<<8) | (off)))
 189 +
 190 +static int config_access(unsigned char access_type, struct pci_bus *bus,
 191 +                         unsigned int devfn, unsigned char where,
 192 +                         u32 * data)
 193 +{
 194 +       /*
 195 +        * config cycles are on 4 byte boundary only
 196 +        */
 197 +       unsigned int slot = PCI_SLOT(devfn);
 198 +       u8 func = PCI_FUNC(devfn);
 199 +
 200 +       if (slot < 2 || slot > 15) {
 201 +               *data = 0xFFFFFFFF;
 202 +               return -1;
 203 +       }
 204 +       /* Setup address */
 205 +       PCI_CFG_SET(slot, func, where);
 206 +       rc32434_sync();
 207 +
 208 +       if (access_type == PCI_ACCESS_WRITE) {
 209 +               rc32434_sync();
 210 +               rc32434_pci->pcicfgd = *data;
 211 +       } else {
 212 +               rc32434_sync();
 213 +               *data = rc32434_pci->pcicfgd;
 214 +       }
 215 +
 216 +       rc32434_sync();
 217 +
 218 +       return 0;
 219 +}
 220 +
 221 +
 222 +/*
 223 + * We can't address 8 and 16 bit words directly.  Instead we have to
 224 + * read/write a 32bit word and mask/modify the data we actually want.
 225 + */
 226 +static int read_config_byte(struct pci_bus *bus, unsigned int devfn,
 227 +                            int where, u8 * val)
 228 +{
 229 +       u32 data;
 230 +       int ret;
 231 +
 232 +       ret = config_access(PCI_ACCESS_READ, bus, devfn, where, &data);
 233 +       *val = (data >> ((where & 3) << 3)) & 0xff;
 234 +       return ret;
 235 +}
 236 +
 237 +static int read_config_word(struct pci_bus *bus, unsigned int devfn,
 238 +                            int where, u16 * val)
 239 +{
 240 +       u32 data;
 241 +       int ret;
 242 +
 243 +       ret = config_access(PCI_ACCESS_READ, bus, devfn, where, &data);
 244 +       *val = (data >> ((where & 3) << 3)) & 0xffff;
 245 +       return ret;
 246 +}
 247 +
 248 +static int read_config_dword(struct pci_bus *bus, unsigned int devfn,
 249 +                             int where, u32 * val)
 250 +{
 251 +       int ret;
 252 +
 253 +       ret = config_access(PCI_ACCESS_READ, bus, devfn, where, val);
 254 +       return ret;
 255 +}
 256 +
 257 +static int
 258 +write_config_byte(struct pci_bus *bus, unsigned int devfn, int where,
 259 +                  u8 val)
 260 +{
 261 +       u32 data = 0;
 262 +
 263 +       if (config_access(PCI_ACCESS_READ, bus, devfn, where, &data))
 264 +               return -1;
 265 +
 266 +       data = (data & ~(0xff << ((where & 3) << 3))) |
 267 +               (val << ((where & 3) << 3));
 268 +
 269 +       if (config_access(PCI_ACCESS_WRITE, bus, devfn, where, &data))
 270 +               return -1;
 271 +
 272 +       return PCIBIOS_SUCCESSFUL;
 273 +}
 274 +
 275 +
 276 +static int
 277 +write_config_word(struct pci_bus *bus, unsigned int devfn, int where,
 278 +                  u16 val)
 279 +{
 280 +       u32 data = 0;
 281 +
 282 +       if (config_access(PCI_ACCESS_READ, bus, devfn, where, &data))
 283 +               return -1;
 284 +
 285 +       data = (data & ~(0xffff << ((where & 3) << 3))) |
 286 +               (val << ((where & 3) << 3));
 287 +
 288 +       if (config_access(PCI_ACCESS_WRITE, bus, devfn, where, &data))
 289 +               return -1;
 290 +
 291 +
 292 +       return PCIBIOS_SUCCESSFUL;
 293 +}
 294 +
 295 +
 296 +static int
 297 +write_config_dword(struct pci_bus *bus, unsigned int devfn, int where,
 298 +                   u32 val)
 299 +{
 300 +       if (config_access(PCI_ACCESS_WRITE, bus, devfn, where, &val))
 301 +               return -1;
 302 +
 303 +       return PCIBIOS_SUCCESSFUL;
 304 +}
 305 +
 306 +static int pci_config_read(struct pci_bus *bus, unsigned int devfn,
 307 +                          int where, int size, u32 * val)
 308 +{
 309 +       switch (size) {
 310 +       case 1:
 311 +               return read_config_byte(bus, devfn, where, (u8 *) val);
 312 +       case 2:
 313 +               return read_config_word(bus, devfn, where, (u16 *) val);
 314 +       default:
 315 +               return read_config_dword(bus, devfn, where, val);
 316 +       }
 317 +}
 318 +
 319 +static int pci_config_write(struct pci_bus *bus, unsigned int devfn,
 320 +                           int where, int size, u32 val)
 321 +{
 322 +       switch (size) {
 323 +       case 1:
 324 +               return write_config_byte(bus, devfn, where, (u8) val);
 325 +       case 2:
 326 +               return write_config_word(bus, devfn, where, (u16) val);
 327 +       default:
 328 +               return write_config_dword(bus, devfn, where, val);
 329 +       }
 330 +}
 331 +
 332 +struct pci_ops rc32434_pci_ops = {
 333 +       .read =  pci_config_read,
 334 +       .write = pci_config_write,
 335 +};
 336 diff -Nur linux-2.6.15/arch/mips/pci/pci-aruba.c linux-2.6.15-openwrt/arch/mips/pci/pci-aruba.c
 337 --- linux-2.6.15/arch/mips/pci/pci-aruba.c      1970-01-01 01:00:00.000000000 +0100
 338 +++ linux-2.6.15-openwrt/arch/mips/pci/pci-aruba.c      2006-01-10 00:32:32.000000000 +0100
 339 @@ -0,0 +1,235 @@
 340 +/**************************************************************************
 341 + *
 342 + *  BRIEF MODULE DESCRIPTION
 343 + *     PCI initialization for IDT EB434 board
 344 + *
 345 + *  Copyright 2004 IDT Inc. (rischelp@idt.com)
 346 + *
 347 + *  This program is free software; you can redistribute  it and/or modify it
 348 + *  under  the terms of  the GNU General  Public License as published by the
 349 + *  Free Software Foundation;  either version 2 of the  License, or (at your
 350 + *  option) any later version.
 351 + *
 352 + *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
 353 + *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
 354 + *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
 355 + *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
 356 + *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
 357 + *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
 358 + *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
 359 + *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
 360 + *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
 361 + *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 362 + *
 363 + *  You should have received a copy of the  GNU General Public License along
 364 + *  with this program; if not, write  to the Free Software Foundation, Inc.,
 365 + *  675 Mass Ave, Cambridge, MA 02139, USA.
 366 + *
 367 + *
 368 + **************************************************************************
 369 + * May 2004 rkt, neb
 370 + *
 371 + * Initial Release
 372 + *
 373 + *
 374 + *
 375 + **************************************************************************
 376 + */
 377 +
 378 +#include <linux/config.h>
 379 +#include <linux/types.h>
 380 +#include <linux/pci.h>
 381 +#include <linux/kernel.h>
 382 +#include <linux/init.h>
 383 +#include <asm/idt-boards/rc32434/rc32434.h>
 384 +#include <asm/idt-boards/rc32434/rc32434_pci.h>
 385 +
 386 +#define PCI_ACCESS_READ  0
 387 +#define PCI_ACCESS_WRITE 1
 388 +
 389 +#undef DEBUG
 390 +#ifdef DEBUG
 391 +#define DBG(x...) printk(x)
 392 +#else
 393 +#define DBG(x...)
 394 +#endif
 395 +/* define an unsigned array for the PCI registers */
 396 +unsigned int korinaCnfgRegs[25] = {
 397 +       KORINA_CNFG1,    KORINA_CNFG2,  KORINA_CNFG3,  KORINA_CNFG4,
 398 +       KORINA_CNFG5,    KORINA_CNFG6,  KORINA_CNFG7,  KORINA_CNFG8,
 399 +       KORINA_CNFG9,    KORINA_CNFG10, KORINA_CNFG11, KORINA_CNFG12,
 400 +       KORINA_CNFG13, KORINA_CNFG14, KORINA_CNFG15, KORINA_CNFG16,
 401 +       KORINA_CNFG17, KORINA_CNFG18, KORINA_CNFG19, KORINA_CNFG20,
 402 +       KORINA_CNFG21, KORINA_CNFG22, KORINA_CNFG23, KORINA_CNFG24
 403 +};
 404 +
 405 +static struct resource rc32434_res_pci_mem2;
 406 +
 407 +static struct resource rc32434_res_pci_mem1 = {
 408 +       .name = "PCI MEM1",
 409 +       .start = 0x50000000,
 410 +       .end = 0x5FFFFFFF,
 411 +       .flags = IORESOURCE_MEM,
 412 +       .child = &rc32434_res_pci_mem2,
 413 +};
 414 +static struct resource rc32434_res_pci_mem2 = {
 415 +       .name = "PCI MEM2",
 416 +       .start = 0x60000000,
 417 +       .end = 0x6FFFFFFF,
 418 +       .flags = IORESOURCE_MEM,
 419 +       .parent = &rc32434_res_pci_mem1,
 420 +};
 421 +static struct resource rc32434_res_pci_io1 = {
 422 +       .name = "PCI I/O1",
 423 +       .start = 0x18800000,
 424 +       .end = 0x188FFFFF,
 425 +       .flags = IORESOURCE_IO,
 426 +};
 427 +
 428 +extern struct pci_ops rc32434_pci_ops;
 429 +
 430 +struct pci_controller rc32434_controller = {
 431 +       .pci_ops = &rc32434_pci_ops,
 432 +       .mem_resource = &rc32434_res_pci_mem1,
 433 +       .io_resource = &rc32434_res_pci_io1,
 434 +       .mem_offset     = 0x00000000UL,
 435 +       .io_offset      = 0x00000000UL,
 436 +};
 437 +
 438 +extern unsigned int arch_has_pci;
 439 +
 440 +static int __init rc32434_pcibridge_init(void)
 441 +{
 442 +
 443 +       unsigned int pciConfigAddr = 0;/*used for writing pci config values */
 444 +       int          loopCount=0    ;/*used for the loop */
 445 +
 446 +       unsigned int pcicValue, pcicData=0;
 447 +       unsigned int dummyRead, pciCntlVal = 0;
 448 +
 449 +       if (!arch_has_pci) return 0;
 450 +
 451 +       printk("PCI: Initializing PCI\n");
 452 +
 453 +       /* Disable the IP bus error for PCI scaning */
 454 +       pciCntlVal=rc32434_pci->pcic;
 455 +       pciCntlVal &= 0xFFFFFF7;
 456 +       rc32434_pci->pcic = pciCntlVal;
 457 +
 458 +       ioport_resource.start = rc32434_res_pci_io1.start;
 459 +       ioport_resource.end = rc32434_res_pci_io1.end;
 460 +/*
 461 +       iomem_resource.start = rc32434_res_pci_mem1.start;
 462 +       iomem_resource.end = rc32434_res_pci_mem1.end;
 463 +*/
 464 +
 465 +       pcicValue = rc32434_pci->pcic;
 466 +       pcicValue = (pcicValue >> PCIM_SHFT) & PCIM_BIT_LEN;
 467 +       if (!((pcicValue == PCIM_H_EA) ||
 468 +             (pcicValue == PCIM_H_IA_FIX) ||
 469 +             (pcicValue == PCIM_H_IA_RR))) {
 470 +               /* Not in Host Mode, return ERROR */
 471 +               return -1;
 472 +       }
 473 +
 474 +       /* Enables the Idle Grant mode, Arbiter Parking */
 475 +       pcicData |=(PCIC_igm_m|PCIC_eap_m|PCIC_en_m);
 476 +       rc32434_pci->pcic = pcicData; /* Enable the PCI bus Interface */
 477 +       /* Zero out the PCI status & PCI Status Mask */
 478 +       for(;;) {
 479 +               pcicData = rc32434_pci->pcis;
 480 +               if (!(pcicData & PCIS_rip_m))
 481 +                       break;
 482 +       }
 483 +
 484 +       rc32434_pci->pcis = 0;
 485 +       rc32434_pci->pcism = 0xFFFFFFFF;
 486 +       /* Zero out the PCI decoupled registers */
 487 +       rc32434_pci->pcidac=0; /* disable PCI decoupled accesses at initialization */
 488 +       rc32434_pci->pcidas=0; /* clear the status */
 489 +       rc32434_pci->pcidasm=0x0000007F; /* Mask all the interrupts */
 490 +       /* Mask PCI Messaging Interrupts */
 491 +       rc32434_pci_msg->pciiic = 0;
 492 +       rc32434_pci_msg->pciiim = 0xFFFFFFFF;
 493 +       rc32434_pci_msg->pciioic = 0;
 494 +       rc32434_pci_msg->pciioim = 0;
 495 +
 496 +       /* Setup PCILB0 as Memory Window */
 497 +       rc32434_pci->pcilba[0].a = (unsigned int) (PCI_ADDR_START);
 498 +
 499 +       /* setup the PCI map address as same as the local address */
 500 +
 501 +       rc32434_pci->pcilba[0].m = (unsigned int) (PCI_ADDR_START);
 502 +
 503 +       /* Setup PCILBA1 as MEM */
 504 +#ifdef __MIPSEB__
 505 +       rc32434_pci->pcilba[0].c = ( ((SIZE_16MB & 0x1f) << PCILBAC_size_b) | PCILBAC_sb_m);
 506 +#else
 507 +       rc32434_pci->pcilba[0].c = ( ((SIZE_16MB & 0x1f) << PCILBAC_size_b));
 508 +#endif
 509 +       dummyRead = rc32434_pci->pcilba[0].c; /* flush the CPU write Buffers */
 510 +
 511 +       rc32434_pci->pcilba[1].a = 0x60000000;
 512 +
 513 +       rc32434_pci->pcilba[1].m = 0x60000000;
 514 +       /* setup PCILBA2 as IO Window*/
 515 +#ifdef __MIPSEB__
 516 +       rc32434_pci->pcilba[1].c = ( ((SIZE_256MB & 0x1f) << PCILBAC_size_b) |  PCILBAC_sb_m);
 517 +#else
 518 +       rc32434_pci->pcilba[1].c = ((SIZE_256MB & 0x1f) << PCILBAC_size_b);
 519 +#endif
 520 +       dummyRead = rc32434_pci->pcilba[1].c; /* flush the CPU write Buffers */
 521 +       rc32434_pci->pcilba[2].a = 0x18C00000;
 522 +
 523 +       rc32434_pci->pcilba[2].m = 0x18FFFFFF;
 524 +       /* setup PCILBA2 as IO Window*/
 525 +#ifdef __MIPSEB__
 526 +       rc32434_pci->pcilba[2].c = ( ((SIZE_4MB & 0x1f) << PCILBAC_size_b)  |  PCILBAC_sb_m);
 527 +#else
 528 +       rc32434_pci->pcilba[2].c = ((SIZE_4MB & 0x1f) << PCILBAC_size_b);
 529 +#endif
 530 +
 531 +       dummyRead = rc32434_pci->pcilba[2].c; /* flush the CPU write Buffers */
 532 +
 533 +
 534 +       rc32434_pci->pcilba[3].a = 0x18800000;
 535 +
 536 +       rc32434_pci->pcilba[3].m = 0x18800000;
 537 +       /* Setup PCILBA3 as IO Window */
 538 +
 539 +#ifdef __MIPSEB__
 540 +       rc32434_pci->pcilba[3].c = ( (((SIZE_1MB & 0x1ff) << PCILBAC_size_b) | PCILBAC_msi_m)   |  PCILBAC_sb_m);
 541 +#else
 542 +       rc32434_pci->pcilba[3].c = (((SIZE_1MB & 0x1ff) << PCILBAC_size_b) | PCILBAC_msi_m);
 543 +#endif
 544 +       dummyRead = rc32434_pci->pcilba[2].c; /* flush the CPU write Buffers */
 545 +
 546 +       pciConfigAddr = (unsigned int)(0x80000004);
 547 +       for(loopCount = 0; loopCount < 24; loopCount++){
 548 +               rc32434_pci->pcicfga = pciConfigAddr;
 549 +               dummyRead = rc32434_pci->pcicfga;
 550 +               rc32434_pci->pcicfgd = korinaCnfgRegs[loopCount];
 551 +               dummyRead=rc32434_pci->pcicfgd;
 552 +               pciConfigAddr += 4;
 553 +       }
 554 +       rc32434_pci->pcitc=(unsigned int)((PCITC_RTIMER_VAL&0xff) << PCITC_rtimer_b) |
 555 +               ((PCITC_DTIMER_VAL&0xff)<<PCITC_dtimer_b);
 556 +
 557 +       pciCntlVal = rc32434_pci->pcic;
 558 +       pciCntlVal &= ~(PCIC_tnr_m);
 559 +       rc32434_pci->pcic = pciCntlVal;
 560 +       pciCntlVal = rc32434_pci->pcic;
 561 +
 562 +       register_pci_controller(&rc32434_controller);
 563 +
 564 +       rc32434_sync();
 565 +       return 0;
 566 +}
 567 +
 568 +arch_initcall(rc32434_pcibridge_init);
 569 +
 570 +/* Do platform specific device initialization at pci_enable_device() time */
 571 +int pcibios_plat_dev_init(struct pci_dev *dev)
 572 +{
 573 +        return 0;
 574 +}
 575 diff -Nur linux-2.6.15/drivers/pci/access.c linux-2.6.15-openwrt/drivers/pci/access.c
 576 --- linux-2.6.15/drivers/pci/access.c   2006-01-03 04:21:10.000000000 +0100
 577 +++ linux-2.6.15-openwrt/drivers/pci/access.c   2006-01-10 00:43:10.000000000 +0100
 578 @@ -21,6 +21,7 @@
 579  #define PCI_word_BAD (pos & 1)
 580  #define PCI_dword_BAD (pos & 3)
 581
 582 +#ifdef __MIPSEB__
 583  #define PCI_OP_READ(size,type,len) \
 584  int pci_bus_read_config_##size \
 585         (struct pci_bus *bus, unsigned int devfn, int pos, type *value) \
 586 @@ -31,11 +32,32 @@
 587         if (PCI_##size##_BAD) return PCIBIOS_BAD_REGISTER_NUMBER;       \
 588         spin_lock_irqsave(&pci_lock, flags);                            \
 589         res = bus->ops->read(bus, devfn, pos, len, &data);              \
 590 +       if (len == 1)                                                   \
 591 +        *value = (type)((data >> 24) & 0xff);                          \
 592 +        else if (len == 2)                                             \
 593 +        *value = (type)((data >> 16) & 0xffff);                        \
 594 +       else                                                            \
 595         *value = (type)data;                                            \
 596         spin_unlock_irqrestore(&pci_lock, flags);                       \
 597         return res;                                                     \
 598  }
 599 +#else
 600
 601 +#define PCI_OP_READ(size,type,len) \
 602 +int pci_bus_read_config_##size \
 603 +       (struct pci_bus *bus, unsigned int devfn, int pos, type *value) \
 604 +{                                                                      \
 605 +       int res;                                                        \
 606 +       unsigned long flags;                                            \
 607 +       u32 data = 0;                                                   \
 608 +       if (PCI_##size##_BAD) return PCIBIOS_BAD_REGISTER_NUMBER;       \
 609 +       spin_lock_irqsave(&pci_lock, flags);                            \
 610 +       res = bus->ops->read(bus, devfn, pos, len, &data);              \
 611 +       *value = (type)data;                                            \
 612 +       spin_unlock_irqrestore(&pci_lock, flags);                       \
 613 +       return res;                                                     \
 614 +}
 615 +#endif
 616  #define PCI_OP_WRITE(size,type,len) \
 617  int pci_bus_write_config_##size \
 618         (struct pci_bus *bus, unsigned int devfn, int pos, type value)  \