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ath9k: use the number of pending aggregates instead of the queue depth to determine...
[openwrt.git] / package / mac80211 / patches / 321-ath9k_pending_cleanups.patch
1 --- a/drivers/net/wireless/ath/ath9k/ar9002_hw.c
2 +++ b/drivers/net/wireless/ath/ath9k/ar9002_hw.c
3 @@ -26,24 +26,6 @@ MODULE_PARM_DESC(nohwcrypt, "Force new A
4
5 /* General hardware code for the A5008/AR9001/AR9002 hadware families */
6
7 -static bool ar9002_hw_macversion_supported(u32 macversion)
8 -{
9 - switch (macversion) {
10 - case AR_SREV_VERSION_5416_PCI:
11 - case AR_SREV_VERSION_5416_PCIE:
12 - case AR_SREV_VERSION_9160:
13 - case AR_SREV_VERSION_9100:
14 - case AR_SREV_VERSION_9280:
15 - case AR_SREV_VERSION_9285:
16 - case AR_SREV_VERSION_9287:
17 - case AR_SREV_VERSION_9271:
18 - return true;
19 - default:
20 - break;
21 - }
22 - return false;
23 -}
24 -
25 static void ar9002_hw_init_mode_regs(struct ath_hw *ah)
26 {
27 if (AR_SREV_9271(ah)) {
28 @@ -565,7 +547,6 @@ void ar9002_hw_attach_ops(struct ath_hw
29
30 priv_ops->init_mode_regs = ar9002_hw_init_mode_regs;
31 priv_ops->init_mode_gain_regs = ar9002_hw_init_mode_gain_regs;
32 - priv_ops->macversion_supported = ar9002_hw_macversion_supported;
33
34 ops->config_pci_powersave = ar9002_hw_configpcipowersave;
35
36 --- a/drivers/net/wireless/ath/ath9k/ar9002_mac.c
37 +++ b/drivers/net/wireless/ath/ath9k/ar9002_mac.c
38 @@ -283,7 +283,6 @@ static void ar9002_hw_set11n_txdesc(stru
39 {
40 struct ar5416_desc *ads = AR5416DESC(ds);
41
42 - txPower += ah->txpower_indexoffset;
43 if (txPower > 63)
44 txPower = 63;
45
46 --- a/drivers/net/wireless/ath/ath9k/ar9003_eeprom.c
47 +++ b/drivers/net/wireless/ath/ath9k/ar9003_eeprom.c
48 @@ -72,7 +72,7 @@ static const struct ar9300_eeprom ar9300
49 .regDmn = { LE16(0), LE16(0x1f) },
50 .txrxMask = 0x77, /* 4 bits tx and 4 bits rx */
51 .opCapFlags = {
52 - .opFlags = AR9300_OPFLAGS_11G | AR9300_OPFLAGS_11A,
53 + .opFlags = AR5416_OPFLAGS_11G | AR5416_OPFLAGS_11A,
54 .eepMisc = 0,
55 },
56 .rfSilent = 0,
57 @@ -649,7 +649,7 @@ static const struct ar9300_eeprom ar9300
58 .regDmn = { LE16(0), LE16(0x1f) },
59 .txrxMask = 0x77, /* 4 bits tx and 4 bits rx */
60 .opCapFlags = {
61 - .opFlags = AR9300_OPFLAGS_11G | AR9300_OPFLAGS_11A,
62 + .opFlags = AR5416_OPFLAGS_11G | AR5416_OPFLAGS_11A,
63 .eepMisc = 0,
64 },
65 .rfSilent = 0,
66 @@ -1227,7 +1227,7 @@ static const struct ar9300_eeprom ar9300
67 .regDmn = { LE16(0), LE16(0x1f) },
68 .txrxMask = 0x77, /* 4 bits tx and 4 bits rx */
69 .opCapFlags = {
70 - .opFlags = AR9300_OPFLAGS_11G | AR9300_OPFLAGS_11A,
71 + .opFlags = AR5416_OPFLAGS_11G | AR5416_OPFLAGS_11A,
72 .eepMisc = 0,
73 },
74 .rfSilent = 0,
75 @@ -1805,7 +1805,7 @@ static const struct ar9300_eeprom ar9300
76 .regDmn = { LE16(0), LE16(0x1f) },
77 .txrxMask = 0x77, /* 4 bits tx and 4 bits rx */
78 .opCapFlags = {
79 - .opFlags = AR9300_OPFLAGS_11G | AR9300_OPFLAGS_11A,
80 + .opFlags = AR5416_OPFLAGS_11G | AR5416_OPFLAGS_11A,
81 .eepMisc = 0,
82 },
83 .rfSilent = 0,
84 @@ -2382,7 +2382,7 @@ static const struct ar9300_eeprom ar9300
85 .regDmn = { LE16(0), LE16(0x1f) },
86 .txrxMask = 0x33, /* 4 bits tx and 4 bits rx */
87 .opCapFlags = {
88 - .opFlags = AR9300_OPFLAGS_11G | AR9300_OPFLAGS_11A,
89 + .opFlags = AR5416_OPFLAGS_11G | AR5416_OPFLAGS_11A,
90 .eepMisc = 0,
91 },
92 .rfSilent = 0,
93 @@ -2974,7 +2974,7 @@ static const struct ar9300_eeprom *ar900
94
95 static u16 ath9k_hw_fbin2freq(u8 fbin, bool is2GHz)
96 {
97 - if (fbin == AR9300_BCHAN_UNUSED)
98 + if (fbin == AR5416_BCHAN_UNUSED)
99 return fbin;
100
101 return (u16) ((is2GHz) ? (2300 + fbin) : (4800 + 5 * fbin));
102 @@ -3427,18 +3427,6 @@ static int ath9k_hw_ar9300_get_eeprom_re
103 return 0;
104 }
105
106 -static u8 ath9k_hw_ar9300_get_num_ant_config(struct ath_hw *ah,
107 - enum ath9k_hal_freq_band freq_band)
108 -{
109 - return 1;
110 -}
111 -
112 -static u32 ath9k_hw_ar9300_get_eeprom_antenna_cfg(struct ath_hw *ah,
113 - struct ath9k_channel *chan)
114 -{
115 - return -EINVAL;
116 -}
117 -
118 static s32 ar9003_hw_xpa_bias_level_get(struct ath_hw *ah, bool is2ghz)
119 {
120 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
121 @@ -4485,7 +4473,7 @@ static u16 ar9003_hw_get_indirect_edge_p
122 return CTL_EDGE_TPOWER(ctl_5g[idx].ctlEdges[edge - 1]);
123 }
124
125 - return AR9300_MAX_RATE_POWER;
126 + return MAX_RATE_POWER;
127 }
128
129 /*
130 @@ -4494,7 +4482,7 @@ static u16 ar9003_hw_get_indirect_edge_p
131 static u16 ar9003_hw_get_max_edge_power(struct ar9300_eeprom *eep,
132 u16 freq, int idx, bool is2GHz)
133 {
134 - u16 twiceMaxEdgePower = AR9300_MAX_RATE_POWER;
135 + u16 twiceMaxEdgePower = MAX_RATE_POWER;
136 u8 *ctl_freqbin = is2GHz ?
137 &eep->ctl_freqbin_2G[idx][0] :
138 &eep->ctl_freqbin_5G[idx][0];
139 @@ -4504,7 +4492,7 @@ static u16 ar9003_hw_get_max_edge_power(
140
141 /* Get the edge power */
142 for (edge = 0;
143 - (edge < num_edges) && (ctl_freqbin[edge] != AR9300_BCHAN_UNUSED);
144 + (edge < num_edges) && (ctl_freqbin[edge] != AR5416_BCHAN_UNUSED);
145 edge++) {
146 /*
147 * If there's an exact channel match or an inband flag set
148 @@ -4542,9 +4530,9 @@ static void ar9003_hw_set_power_per_rate
149 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
150 struct ath_common *common = ath9k_hw_common(ah);
151 struct ar9300_eeprom *pEepData = &ah->eeprom.ar9300_eep;
152 - u16 twiceMaxEdgePower = AR9300_MAX_RATE_POWER;
153 + u16 twiceMaxEdgePower = MAX_RATE_POWER;
154 static const u16 tpScaleReductionTable[5] = {
155 - 0, 3, 6, 9, AR9300_MAX_RATE_POWER
156 + 0, 3, 6, 9, MAX_RATE_POWER
157 };
158 int i;
159 int16_t twiceLargestAntenna;
160 @@ -4848,8 +4836,6 @@ const struct eeprom_ops eep_ar9300_ops =
161 .fill_eeprom = ath9k_hw_ar9300_fill_eeprom,
162 .get_eeprom_ver = ath9k_hw_ar9300_get_eeprom_ver,
163 .get_eeprom_rev = ath9k_hw_ar9300_get_eeprom_rev,
164 - .get_num_ant_config = ath9k_hw_ar9300_get_num_ant_config,
165 - .get_eeprom_antenna_cfg = ath9k_hw_ar9300_get_eeprom_antenna_cfg,
166 .set_board_values = ath9k_hw_ar9300_set_board_values,
167 .set_addac = ath9k_hw_ar9300_set_addac,
168 .set_txpower = ath9k_hw_ar9300_set_txpower,
169 --- a/drivers/net/wireless/ath/ath9k/ar9003_hw.c
170 +++ b/drivers/net/wireless/ath/ath9k/ar9003_hw.c
171 @@ -21,18 +21,6 @@
172
173 /* General hardware code for the AR9003 hadware family */
174
175 -static bool ar9003_hw_macversion_supported(u32 macversion)
176 -{
177 - switch (macversion) {
178 - case AR_SREV_VERSION_9300:
179 - case AR_SREV_VERSION_9485:
180 - return true;
181 - default:
182 - break;
183 - }
184 - return false;
185 -}
186 -
187 /*
188 * The AR9003 family uses a new INI format (pre, core, post
189 * arrays per subsystem). This provides support for the
190 @@ -322,7 +310,6 @@ void ar9003_hw_attach_ops(struct ath_hw
191
192 priv_ops->init_mode_regs = ar9003_hw_init_mode_regs;
193 priv_ops->init_mode_gain_regs = ar9003_hw_init_mode_gain_regs;
194 - priv_ops->macversion_supported = ar9003_hw_macversion_supported;
195
196 ops->config_pci_powersave = ar9003_hw_configpcipowersave;
197
198 --- a/drivers/net/wireless/ath/ath9k/ar9003_mac.c
199 +++ b/drivers/net/wireless/ath/ath9k/ar9003_mac.c
200 @@ -322,7 +322,6 @@ static void ar9003_hw_set11n_txdesc(stru
201 if (txpower > ah->txpower_limit)
202 txpower = ah->txpower_limit;
203
204 - txpower += ah->txpower_indexoffset;
205 if (txpower > 63)
206 txpower = 63;
207
208 --- a/drivers/net/wireless/ath/ath9k/eeprom.c
209 +++ b/drivers/net/wireless/ath/ath9k/eeprom.c
210 @@ -234,7 +234,7 @@ void ath9k_hw_get_target_powers(struct a
211 u16 ath9k_hw_get_max_edge_power(u16 freq, struct cal_ctl_edges *pRdEdgesPower,
212 bool is2GHz, int num_band_edges)
213 {
214 - u16 twiceMaxEdgePower = AR5416_MAX_RATE_POWER;
215 + u16 twiceMaxEdgePower = MAX_RATE_POWER;
216 int i;
217
218 for (i = 0; (i < num_band_edges) &&
219 @@ -279,6 +279,219 @@ void ath9k_hw_update_regulatory_maxpower
220 }
221 }
222
223 +void ath9k_hw_get_gain_boundaries_pdadcs(struct ath_hw *ah,
224 + struct ath9k_channel *chan,
225 + void *pRawDataSet,
226 + u8 *bChans, u16 availPiers,
227 + u16 tPdGainOverlap,
228 + u16 *pPdGainBoundaries, u8 *pPDADCValues,
229 + u16 numXpdGains)
230 +{
231 + int i, j, k;
232 + int16_t ss;
233 + u16 idxL = 0, idxR = 0, numPiers;
234 + static u8 vpdTableL[AR5416_NUM_PD_GAINS]
235 + [AR5416_MAX_PWR_RANGE_IN_HALF_DB];
236 + static u8 vpdTableR[AR5416_NUM_PD_GAINS]
237 + [AR5416_MAX_PWR_RANGE_IN_HALF_DB];
238 + static u8 vpdTableI[AR5416_NUM_PD_GAINS]
239 + [AR5416_MAX_PWR_RANGE_IN_HALF_DB];
240 +
241 + u8 *pVpdL, *pVpdR, *pPwrL, *pPwrR;
242 + u8 minPwrT4[AR5416_NUM_PD_GAINS];
243 + u8 maxPwrT4[AR5416_NUM_PD_GAINS];
244 + int16_t vpdStep;
245 + int16_t tmpVal;
246 + u16 sizeCurrVpdTable, maxIndex, tgtIndex;
247 + bool match;
248 + int16_t minDelta = 0;
249 + struct chan_centers centers;
250 + int pdgain_boundary_default;
251 + struct cal_data_per_freq *data_def = pRawDataSet;
252 + struct cal_data_per_freq_4k *data_4k = pRawDataSet;
253 + struct cal_data_per_freq_ar9287 *data_9287 = pRawDataSet;
254 + bool eeprom_4k = AR_SREV_9285(ah) || AR_SREV_9271(ah);
255 + int intercepts;
256 +
257 + if (AR_SREV_9287(ah))
258 + intercepts = AR9287_PD_GAIN_ICEPTS;
259 + else
260 + intercepts = AR5416_PD_GAIN_ICEPTS;
261 +
262 + memset(&minPwrT4, 0, AR5416_NUM_PD_GAINS);
263 + ath9k_hw_get_channel_centers(ah, chan, &centers);
264 +
265 + for (numPiers = 0; numPiers < availPiers; numPiers++) {
266 + if (bChans[numPiers] == AR5416_BCHAN_UNUSED)
267 + break;
268 + }
269 +
270 + match = ath9k_hw_get_lower_upper_index((u8)FREQ2FBIN(centers.synth_center,
271 + IS_CHAN_2GHZ(chan)),
272 + bChans, numPiers, &idxL, &idxR);
273 +
274 + if (match) {
275 + if (AR_SREV_9287(ah)) {
276 + /* FIXME: array overrun? */
277 + for (i = 0; i < numXpdGains; i++) {
278 + minPwrT4[i] = data_9287[idxL].pwrPdg[i][0];
279 + maxPwrT4[i] = data_9287[idxL].pwrPdg[i][4];
280 + ath9k_hw_fill_vpd_table(minPwrT4[i], maxPwrT4[i],
281 + data_9287[idxL].pwrPdg[i],
282 + data_9287[idxL].vpdPdg[i],
283 + intercepts,
284 + vpdTableI[i]);
285 + }
286 + } else if (eeprom_4k) {
287 + for (i = 0; i < numXpdGains; i++) {
288 + minPwrT4[i] = data_4k[idxL].pwrPdg[i][0];
289 + maxPwrT4[i] = data_4k[idxL].pwrPdg[i][4];
290 + ath9k_hw_fill_vpd_table(minPwrT4[i], maxPwrT4[i],
291 + data_4k[idxL].pwrPdg[i],
292 + data_4k[idxL].vpdPdg[i],
293 + intercepts,
294 + vpdTableI[i]);
295 + }
296 + } else {
297 + for (i = 0; i < numXpdGains; i++) {
298 + minPwrT4[i] = data_def[idxL].pwrPdg[i][0];
299 + maxPwrT4[i] = data_def[idxL].pwrPdg[i][4];
300 + ath9k_hw_fill_vpd_table(minPwrT4[i], maxPwrT4[i],
301 + data_def[idxL].pwrPdg[i],
302 + data_def[idxL].vpdPdg[i],
303 + intercepts,
304 + vpdTableI[i]);
305 + }
306 + }
307 + } else {
308 + for (i = 0; i < numXpdGains; i++) {
309 + if (AR_SREV_9287(ah)) {
310 + pVpdL = data_9287[idxL].vpdPdg[i];
311 + pPwrL = data_9287[idxL].pwrPdg[i];
312 + pVpdR = data_9287[idxR].vpdPdg[i];
313 + pPwrR = data_9287[idxR].pwrPdg[i];
314 + } else if (eeprom_4k) {
315 + pVpdL = data_4k[idxL].vpdPdg[i];
316 + pPwrL = data_4k[idxL].pwrPdg[i];
317 + pVpdR = data_4k[idxR].vpdPdg[i];
318 + pPwrR = data_4k[idxR].pwrPdg[i];
319 + } else {
320 + pVpdL = data_def[idxL].vpdPdg[i];
321 + pPwrL = data_def[idxL].pwrPdg[i];
322 + pVpdR = data_def[idxR].vpdPdg[i];
323 + pPwrR = data_def[idxR].pwrPdg[i];
324 + }
325 +
326 + minPwrT4[i] = max(pPwrL[0], pPwrR[0]);
327 +
328 + maxPwrT4[i] =
329 + min(pPwrL[intercepts - 1],
330 + pPwrR[intercepts - 1]);
331 +
332 +
333 + ath9k_hw_fill_vpd_table(minPwrT4[i], maxPwrT4[i],
334 + pPwrL, pVpdL,
335 + intercepts,
336 + vpdTableL[i]);
337 + ath9k_hw_fill_vpd_table(minPwrT4[i], maxPwrT4[i],
338 + pPwrR, pVpdR,
339 + intercepts,
340 + vpdTableR[i]);
341 +
342 + for (j = 0; j <= (maxPwrT4[i] - minPwrT4[i]) / 2; j++) {
343 + vpdTableI[i][j] =
344 + (u8)(ath9k_hw_interpolate((u16)
345 + FREQ2FBIN(centers.
346 + synth_center,
347 + IS_CHAN_2GHZ
348 + (chan)),
349 + bChans[idxL], bChans[idxR],
350 + vpdTableL[i][j], vpdTableR[i][j]));
351 + }
352 + }
353 + }
354 +
355 + k = 0;
356 +
357 + for (i = 0; i < numXpdGains; i++) {
358 + if (i == (numXpdGains - 1))
359 + pPdGainBoundaries[i] =
360 + (u16)(maxPwrT4[i] / 2);
361 + else
362 + pPdGainBoundaries[i] =
363 + (u16)((maxPwrT4[i] + minPwrT4[i + 1]) / 4);
364 +
365 + pPdGainBoundaries[i] =
366 + min((u16)MAX_RATE_POWER, pPdGainBoundaries[i]);
367 +
368 + if ((i == 0) && !AR_SREV_5416_20_OR_LATER(ah)) {
369 + minDelta = pPdGainBoundaries[0] - 23;
370 + pPdGainBoundaries[0] = 23;
371 + } else {
372 + minDelta = 0;
373 + }
374 +
375 + if (i == 0) {
376 + if (AR_SREV_9280_20_OR_LATER(ah))
377 + ss = (int16_t)(0 - (minPwrT4[i] / 2));
378 + else
379 + ss = 0;
380 + } else {
381 + ss = (int16_t)((pPdGainBoundaries[i - 1] -
382 + (minPwrT4[i] / 2)) -
383 + tPdGainOverlap + 1 + minDelta);
384 + }
385 + vpdStep = (int16_t)(vpdTableI[i][1] - vpdTableI[i][0]);
386 + vpdStep = (int16_t)((vpdStep < 1) ? 1 : vpdStep);
387 +
388 + while ((ss < 0) && (k < (AR5416_NUM_PDADC_VALUES - 1))) {
389 + tmpVal = (int16_t)(vpdTableI[i][0] + ss * vpdStep);
390 + pPDADCValues[k++] = (u8)((tmpVal < 0) ? 0 : tmpVal);
391 + ss++;
392 + }
393 +
394 + sizeCurrVpdTable = (u8) ((maxPwrT4[i] - minPwrT4[i]) / 2 + 1);
395 + tgtIndex = (u8)(pPdGainBoundaries[i] + tPdGainOverlap -
396 + (minPwrT4[i] / 2));
397 + maxIndex = (tgtIndex < sizeCurrVpdTable) ?
398 + tgtIndex : sizeCurrVpdTable;
399 +
400 + while ((ss < maxIndex) && (k < (AR5416_NUM_PDADC_VALUES - 1))) {
401 + pPDADCValues[k++] = vpdTableI[i][ss++];
402 + }
403 +
404 + vpdStep = (int16_t)(vpdTableI[i][sizeCurrVpdTable - 1] -
405 + vpdTableI[i][sizeCurrVpdTable - 2]);
406 + vpdStep = (int16_t)((vpdStep < 1) ? 1 : vpdStep);
407 +
408 + if (tgtIndex >= maxIndex) {
409 + while ((ss <= tgtIndex) &&
410 + (k < (AR5416_NUM_PDADC_VALUES - 1))) {
411 + tmpVal = (int16_t)((vpdTableI[i][sizeCurrVpdTable - 1] +
412 + (ss - maxIndex + 1) * vpdStep));
413 + pPDADCValues[k++] = (u8)((tmpVal > 255) ?
414 + 255 : tmpVal);
415 + ss++;
416 + }
417 + }
418 + }
419 +
420 + if (eeprom_4k)
421 + pdgain_boundary_default = 58;
422 + else
423 + pdgain_boundary_default = pPdGainBoundaries[i - 1];
424 +
425 + while (i < AR5416_PD_GAINS_IN_MASK) {
426 + pPdGainBoundaries[i] = pdgain_boundary_default;
427 + i++;
428 + }
429 +
430 + while (k < AR5416_NUM_PDADC_VALUES) {
431 + pPDADCValues[k] = pPDADCValues[k - 1];
432 + k++;
433 + }
434 +}
435 +
436 int ath9k_hw_eeprom_init(struct ath_hw *ah)
437 {
438 int status;
439 --- a/drivers/net/wireless/ath/ath9k/eeprom.h
440 +++ b/drivers/net/wireless/ath/ath9k/eeprom.h
441 @@ -17,6 +17,8 @@
442 #ifndef EEPROM_H
443 #define EEPROM_H
444
445 +#define AR_EEPROM_MODAL_SPURS 5
446 +
447 #include "../ath.h"
448 #include <net/cfg80211.h>
449 #include "ar9003_eeprom.h"
450 @@ -149,8 +151,6 @@
451 #define AR5416_NUM_PD_GAINS 4
452 #define AR5416_PD_GAINS_IN_MASK 4
453 #define AR5416_PD_GAIN_ICEPTS 5
454 -#define AR5416_EEPROM_MODAL_SPURS 5
455 -#define AR5416_MAX_RATE_POWER 63
456 #define AR5416_NUM_PDADC_VALUES 128
457 #define AR5416_BCHAN_UNUSED 0xFF
458 #define AR5416_MAX_PWR_RANGE_IN_HALF_DB 64
459 @@ -175,8 +175,6 @@
460 #define AR5416_EEP4K_NUM_CTLS 12
461 #define AR5416_EEP4K_NUM_BAND_EDGES 4
462 #define AR5416_EEP4K_NUM_PD_GAINS 2
463 -#define AR5416_EEP4K_PD_GAINS_IN_MASK 4
464 -#define AR5416_EEP4K_PD_GAIN_ICEPTS 5
465 #define AR5416_EEP4K_MAX_CHAINS 1
466
467 #define AR9280_TX_GAIN_TABLE_SIZE 22
468 @@ -198,35 +196,12 @@
469 #define AR9287_NUM_2G_40_TARGET_POWERS 3
470 #define AR9287_NUM_CTLS 12
471 #define AR9287_NUM_BAND_EDGES 4
472 -#define AR9287_NUM_PD_GAINS 4
473 -#define AR9287_PD_GAINS_IN_MASK 4
474 #define AR9287_PD_GAIN_ICEPTS 1
475 -#define AR9287_EEPROM_MODAL_SPURS 5
476 -#define AR9287_MAX_RATE_POWER 63
477 -#define AR9287_NUM_PDADC_VALUES 128
478 -#define AR9287_NUM_RATES 16
479 -#define AR9287_BCHAN_UNUSED 0xFF
480 -#define AR9287_MAX_PWR_RANGE_IN_HALF_DB 64
481 -#define AR9287_OPFLAGS_11A 0x01
482 -#define AR9287_OPFLAGS_11G 0x02
483 -#define AR9287_OPFLAGS_2G_HT40 0x08
484 -#define AR9287_OPFLAGS_2G_HT20 0x20
485 -#define AR9287_OPFLAGS_5G_HT40 0x04
486 -#define AR9287_OPFLAGS_5G_HT20 0x10
487 #define AR9287_EEPMISC_BIG_ENDIAN 0x01
488 #define AR9287_EEPMISC_WOW 0x02
489 #define AR9287_MAX_CHAINS 2
490 #define AR9287_ANT_16S 32
491 -#define AR9287_custdatasize 20
492
493 -#define AR9287_NUM_ANT_CHAIN_FIELDS 6
494 -#define AR9287_NUM_ANT_COMMON_FIELDS 4
495 -#define AR9287_SIZE_ANT_CHAIN_FIELD 2
496 -#define AR9287_SIZE_ANT_COMMON_FIELD 4
497 -#define AR9287_ANT_CHAIN_MASK 0x3
498 -#define AR9287_ANT_COMMON_MASK 0xf
499 -#define AR9287_CHAIN_0_IDX 0
500 -#define AR9287_CHAIN_1_IDX 1
501 #define AR9287_DATA_SZ 32
502
503 #define AR9287_PWR_TABLE_OFFSET_DB -5
504 @@ -396,7 +371,7 @@ struct modal_eep_header {
505 u16 xpaBiasLvlFreq[3];
506 u8 futureModal[6];
507
508 - struct spur_chan spurChans[AR5416_EEPROM_MODAL_SPURS];
509 + struct spur_chan spurChans[AR_EEPROM_MODAL_SPURS];
510 } __packed;
511
512 struct calDataPerFreqOpLoop {
513 @@ -464,7 +439,7 @@ struct modal_eep_4k_header {
514 u8 db2_4:4, reserved:4;
515 #endif
516 u8 futureModal[4];
517 - struct spur_chan spurChans[AR5416_EEPROM_MODAL_SPURS];
518 + struct spur_chan spurChans[AR_EEPROM_MODAL_SPURS];
519 } __packed;
520
521 struct base_eep_ar9287_header {
522 @@ -522,7 +497,7 @@ struct modal_eep_ar9287_header {
523 u8 ob_qam;
524 u8 ob_pal_off;
525 u8 futureModal[30];
526 - struct spur_chan spurChans[AR9287_EEPROM_MODAL_SPURS];
527 + struct spur_chan spurChans[AR_EEPROM_MODAL_SPURS];
528 } __packed;
529
530 struct cal_data_per_freq {
531 @@ -531,8 +506,8 @@ struct cal_data_per_freq {
532 } __packed;
533
534 struct cal_data_per_freq_4k {
535 - u8 pwrPdg[AR5416_EEP4K_NUM_PD_GAINS][AR5416_EEP4K_PD_GAIN_ICEPTS];
536 - u8 vpdPdg[AR5416_EEP4K_NUM_PD_GAINS][AR5416_EEP4K_PD_GAIN_ICEPTS];
537 + u8 pwrPdg[AR5416_EEP4K_NUM_PD_GAINS][AR5416_PD_GAIN_ICEPTS];
538 + u8 vpdPdg[AR5416_EEP4K_NUM_PD_GAINS][AR5416_PD_GAIN_ICEPTS];
539 } __packed;
540
541 struct cal_target_power_leg {
542 @@ -558,8 +533,8 @@ struct cal_data_op_loop_ar9287 {
543 } __packed;
544
545 struct cal_data_per_freq_ar9287 {
546 - u8 pwrPdg[AR9287_NUM_PD_GAINS][AR9287_PD_GAIN_ICEPTS];
547 - u8 vpdPdg[AR9287_NUM_PD_GAINS][AR9287_PD_GAIN_ICEPTS];
548 + u8 pwrPdg[AR5416_NUM_PD_GAINS][AR9287_PD_GAIN_ICEPTS];
549 + u8 vpdPdg[AR5416_NUM_PD_GAINS][AR9287_PD_GAIN_ICEPTS];
550 } __packed;
551
552 union cal_data_per_freq_ar9287_u {
553 @@ -674,10 +649,6 @@ struct eeprom_ops {
554 bool (*fill_eeprom)(struct ath_hw *hw);
555 int (*get_eeprom_ver)(struct ath_hw *hw);
556 int (*get_eeprom_rev)(struct ath_hw *hw);
557 - u8 (*get_num_ant_config)(struct ath_hw *hw,
558 - enum ath9k_hal_freq_band band);
559 - u32 (*get_eeprom_antenna_cfg)(struct ath_hw *hw,
560 - struct ath9k_channel *chan);
561 void (*set_board_values)(struct ath_hw *hw, struct ath9k_channel *chan);
562 void (*set_addac)(struct ath_hw *hw, struct ath9k_channel *chan);
563 void (*set_txpower)(struct ath_hw *hw, struct ath9k_channel *chan,
564 @@ -716,6 +687,14 @@ u16 ath9k_hw_get_max_edge_power(u16 freq
565 void ath9k_hw_update_regulatory_maxpower(struct ath_hw *ah);
566 int ath9k_hw_eeprom_init(struct ath_hw *ah);
567
568 +void ath9k_hw_get_gain_boundaries_pdadcs(struct ath_hw *ah,
569 + struct ath9k_channel *chan,
570 + void *pRawDataSet,
571 + u8 *bChans, u16 availPiers,
572 + u16 tPdGainOverlap,
573 + u16 *pPdGainBoundaries, u8 *pPDADCValues,
574 + u16 numXpdGains);
575 +
576 #define ar5416_get_ntxchains(_txchainmask) \
577 (((_txchainmask >> 2) & 1) + \
578 ((_txchainmask >> 1) & 1) + (_txchainmask & 1))
579 --- a/drivers/net/wireless/ath/ath9k/eeprom_4k.c
580 +++ b/drivers/net/wireless/ath/ath9k/eeprom_4k.c
581 @@ -153,7 +153,7 @@ static int ath9k_hw_4k_check_eeprom(stru
582 eep->modalHeader.antCtrlChain[i] = integer;
583 }
584
585 - for (i = 0; i < AR5416_EEPROM_MODAL_SPURS; i++) {
586 + for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
587 word = swab16(eep->modalHeader.spurChans[i].spurChan);
588 eep->modalHeader.spurChans[i].spurChan = word;
589 }
590 @@ -227,173 +227,6 @@ static u32 ath9k_hw_4k_get_eeprom(struct
591 }
592 }
593
594 -static void ath9k_hw_get_4k_gain_boundaries_pdadcs(struct ath_hw *ah,
595 - struct ath9k_channel *chan,
596 - struct cal_data_per_freq_4k *pRawDataSet,
597 - u8 *bChans, u16 availPiers,
598 - u16 tPdGainOverlap,
599 - u16 *pPdGainBoundaries, u8 *pPDADCValues,
600 - u16 numXpdGains)
601 -{
602 -#define TMP_VAL_VPD_TABLE \
603 - ((vpdTableI[i][sizeCurrVpdTable - 1] + (ss - maxIndex + 1) * vpdStep));
604 - int i, j, k;
605 - int16_t ss;
606 - u16 idxL = 0, idxR = 0, numPiers;
607 - static u8 vpdTableL[AR5416_EEP4K_NUM_PD_GAINS]
608 - [AR5416_MAX_PWR_RANGE_IN_HALF_DB];
609 - static u8 vpdTableR[AR5416_EEP4K_NUM_PD_GAINS]
610 - [AR5416_MAX_PWR_RANGE_IN_HALF_DB];
611 - static u8 vpdTableI[AR5416_EEP4K_NUM_PD_GAINS]
612 - [AR5416_MAX_PWR_RANGE_IN_HALF_DB];
613 -
614 - u8 *pVpdL, *pVpdR, *pPwrL, *pPwrR;
615 - u8 minPwrT4[AR5416_EEP4K_NUM_PD_GAINS];
616 - u8 maxPwrT4[AR5416_EEP4K_NUM_PD_GAINS];
617 - int16_t vpdStep;
618 - int16_t tmpVal;
619 - u16 sizeCurrVpdTable, maxIndex, tgtIndex;
620 - bool match;
621 - int16_t minDelta = 0;
622 - struct chan_centers centers;
623 -#define PD_GAIN_BOUNDARY_DEFAULT 58;
624 -
625 - memset(&minPwrT4, 0, AR9287_NUM_PD_GAINS);
626 - ath9k_hw_get_channel_centers(ah, chan, &centers);
627 -
628 - for (numPiers = 0; numPiers < availPiers; numPiers++) {
629 - if (bChans[numPiers] == AR5416_BCHAN_UNUSED)
630 - break;
631 - }
632 -
633 - match = ath9k_hw_get_lower_upper_index(
634 - (u8)FREQ2FBIN(centers.synth_center,
635 - IS_CHAN_2GHZ(chan)), bChans, numPiers,
636 - &idxL, &idxR);
637 -
638 - if (match) {
639 - for (i = 0; i < numXpdGains; i++) {
640 - minPwrT4[i] = pRawDataSet[idxL].pwrPdg[i][0];
641 - maxPwrT4[i] = pRawDataSet[idxL].pwrPdg[i][4];
642 - ath9k_hw_fill_vpd_table(minPwrT4[i], maxPwrT4[i],
643 - pRawDataSet[idxL].pwrPdg[i],
644 - pRawDataSet[idxL].vpdPdg[i],
645 - AR5416_EEP4K_PD_GAIN_ICEPTS,
646 - vpdTableI[i]);
647 - }
648 - } else {
649 - for (i = 0; i < numXpdGains; i++) {
650 - pVpdL = pRawDataSet[idxL].vpdPdg[i];
651 - pPwrL = pRawDataSet[idxL].pwrPdg[i];
652 - pVpdR = pRawDataSet[idxR].vpdPdg[i];
653 - pPwrR = pRawDataSet[idxR].pwrPdg[i];
654 -
655 - minPwrT4[i] = max(pPwrL[0], pPwrR[0]);
656 -
657 - maxPwrT4[i] =
658 - min(pPwrL[AR5416_EEP4K_PD_GAIN_ICEPTS - 1],
659 - pPwrR[AR5416_EEP4K_PD_GAIN_ICEPTS - 1]);
660 -
661 -
662 - ath9k_hw_fill_vpd_table(minPwrT4[i], maxPwrT4[i],
663 - pPwrL, pVpdL,
664 - AR5416_EEP4K_PD_GAIN_ICEPTS,
665 - vpdTableL[i]);
666 - ath9k_hw_fill_vpd_table(minPwrT4[i], maxPwrT4[i],
667 - pPwrR, pVpdR,
668 - AR5416_EEP4K_PD_GAIN_ICEPTS,
669 - vpdTableR[i]);
670 -
671 - for (j = 0; j <= (maxPwrT4[i] - minPwrT4[i]) / 2; j++) {
672 - vpdTableI[i][j] =
673 - (u8)(ath9k_hw_interpolate((u16)
674 - FREQ2FBIN(centers.
675 - synth_center,
676 - IS_CHAN_2GHZ
677 - (chan)),
678 - bChans[idxL], bChans[idxR],
679 - vpdTableL[i][j], vpdTableR[i][j]));
680 - }
681 - }
682 - }
683 -
684 - k = 0;
685 -
686 - for (i = 0; i < numXpdGains; i++) {
687 - if (i == (numXpdGains - 1))
688 - pPdGainBoundaries[i] =
689 - (u16)(maxPwrT4[i] / 2);
690 - else
691 - pPdGainBoundaries[i] =
692 - (u16)((maxPwrT4[i] + minPwrT4[i + 1]) / 4);
693 -
694 - pPdGainBoundaries[i] =
695 - min((u16)AR5416_MAX_RATE_POWER, pPdGainBoundaries[i]);
696 -
697 - if ((i == 0) && !AR_SREV_5416_20_OR_LATER(ah)) {
698 - minDelta = pPdGainBoundaries[0] - 23;
699 - pPdGainBoundaries[0] = 23;
700 - } else {
701 - minDelta = 0;
702 - }
703 -
704 - if (i == 0) {
705 - if (AR_SREV_9280_20_OR_LATER(ah))
706 - ss = (int16_t)(0 - (minPwrT4[i] / 2));
707 - else
708 - ss = 0;
709 - } else {
710 - ss = (int16_t)((pPdGainBoundaries[i - 1] -
711 - (minPwrT4[i] / 2)) -
712 - tPdGainOverlap + 1 + minDelta);
713 - }
714 - vpdStep = (int16_t)(vpdTableI[i][1] - vpdTableI[i][0]);
715 - vpdStep = (int16_t)((vpdStep < 1) ? 1 : vpdStep);
716 -
717 - while ((ss < 0) && (k < (AR5416_NUM_PDADC_VALUES - 1))) {
718 - tmpVal = (int16_t)(vpdTableI[i][0] + ss * vpdStep);
719 - pPDADCValues[k++] = (u8)((tmpVal < 0) ? 0 : tmpVal);
720 - ss++;
721 - }
722 -
723 - sizeCurrVpdTable = (u8) ((maxPwrT4[i] - minPwrT4[i]) / 2 + 1);
724 - tgtIndex = (u8)(pPdGainBoundaries[i] + tPdGainOverlap -
725 - (minPwrT4[i] / 2));
726 - maxIndex = (tgtIndex < sizeCurrVpdTable) ?
727 - tgtIndex : sizeCurrVpdTable;
728 -
729 - while ((ss < maxIndex) && (k < (AR5416_NUM_PDADC_VALUES - 1)))
730 - pPDADCValues[k++] = vpdTableI[i][ss++];
731 -
732 - vpdStep = (int16_t)(vpdTableI[i][sizeCurrVpdTable - 1] -
733 - vpdTableI[i][sizeCurrVpdTable - 2]);
734 - vpdStep = (int16_t)((vpdStep < 1) ? 1 : vpdStep);
735 -
736 - if (tgtIndex >= maxIndex) {
737 - while ((ss <= tgtIndex) &&
738 - (k < (AR5416_NUM_PDADC_VALUES - 1))) {
739 - tmpVal = (int16_t) TMP_VAL_VPD_TABLE;
740 - pPDADCValues[k++] = (u8)((tmpVal > 255) ?
741 - 255 : tmpVal);
742 - ss++;
743 - }
744 - }
745 - }
746 -
747 - while (i < AR5416_EEP4K_PD_GAINS_IN_MASK) {
748 - pPdGainBoundaries[i] = PD_GAIN_BOUNDARY_DEFAULT;
749 - i++;
750 - }
751 -
752 - while (k < AR5416_NUM_PDADC_VALUES) {
753 - pPDADCValues[k] = pPDADCValues[k - 1];
754 - k++;
755 - }
756 -
757 - return;
758 -#undef TMP_VAL_VPD_TABLE
759 -}
760 -
761 static void ath9k_hw_set_4k_power_cal_table(struct ath_hw *ah,
762 struct ath9k_channel *chan,
763 int16_t *pTxPowerIndexOffset)
764 @@ -404,7 +237,7 @@ static void ath9k_hw_set_4k_power_cal_ta
765 u8 *pCalBChans = NULL;
766 u16 pdGainOverlap_t2;
767 static u8 pdadcValues[AR5416_NUM_PDADC_VALUES];
768 - u16 gainBoundaries[AR5416_EEP4K_PD_GAINS_IN_MASK];
769 + u16 gainBoundaries[AR5416_PD_GAINS_IN_MASK];
770 u16 numPiers, i, j;
771 u16 numXpdGain, xpdMask;
772 u16 xpdGainValues[AR5416_EEP4K_NUM_PD_GAINS] = { 0, 0 };
773 @@ -426,12 +259,12 @@ static void ath9k_hw_set_4k_power_cal_ta
774
775 numXpdGain = 0;
776
777 - for (i = 1; i <= AR5416_EEP4K_PD_GAINS_IN_MASK; i++) {
778 - if ((xpdMask >> (AR5416_EEP4K_PD_GAINS_IN_MASK - i)) & 1) {
779 + for (i = 1; i <= AR5416_PD_GAINS_IN_MASK; i++) {
780 + if ((xpdMask >> (AR5416_PD_GAINS_IN_MASK - i)) & 1) {
781 if (numXpdGain >= AR5416_EEP4K_NUM_PD_GAINS)
782 break;
783 xpdGainValues[numXpdGain] =
784 - (u16)(AR5416_EEP4K_PD_GAINS_IN_MASK - i);
785 + (u16)(AR5416_PD_GAINS_IN_MASK - i);
786 numXpdGain++;
787 }
788 }
789 @@ -455,7 +288,7 @@ static void ath9k_hw_set_4k_power_cal_ta
790 if (pEepData->baseEepHeader.txMask & (1 << i)) {
791 pRawDataset = pEepData->calPierData2G[i];
792
793 - ath9k_hw_get_4k_gain_boundaries_pdadcs(ah, chan,
794 + ath9k_hw_get_gain_boundaries_pdadcs(ah, chan,
795 pRawDataset, pCalBChans,
796 numPiers, pdGainOverlap_t2,
797 gainBoundaries,
798 @@ -528,7 +361,7 @@ static void ath9k_hw_set_4k_power_per_ra
799 int i;
800 int16_t twiceLargestAntenna;
801 u16 twiceMinEdgePower;
802 - u16 twiceMaxEdgePower = AR5416_MAX_RATE_POWER;
803 + u16 twiceMaxEdgePower = MAX_RATE_POWER;
804 u16 scaledPower = 0, minCtlPower, maxRegAllowedPower;
805 u16 numCtlModes;
806 const u16 *pCtlMode;
807 @@ -537,7 +370,7 @@ static void ath9k_hw_set_4k_power_per_ra
808 struct cal_ctl_data_4k *rep;
809 struct ar5416_eeprom_4k *pEepData = &ah->eeprom.map4k;
810 static const u16 tpScaleReductionTable[5] =
811 - { 0, 3, 6, 9, AR5416_MAX_RATE_POWER };
812 + { 0, 3, 6, 9, MAX_RATE_POWER };
813 struct cal_target_power_leg targetPowerOfdm, targetPowerCck = {
814 0, { 0, 0, 0, 0}
815 };
816 @@ -613,7 +446,7 @@ static void ath9k_hw_set_4k_power_per_ra
817
818 if (ah->eep_ops->get_eeprom_ver(ah) == 14 &&
819 ah->eep_ops->get_eeprom_rev(ah) <= 2)
820 - twiceMaxEdgePower = AR5416_MAX_RATE_POWER;
821 + twiceMaxEdgePower = MAX_RATE_POWER;
822
823 for (i = 0; (i < AR5416_EEP4K_NUM_CTLS) &&
824 pEepData->ctlIndex[i]; i++) {
825 @@ -752,8 +585,8 @@ static void ath9k_hw_4k_set_txpower(stru
826 regulatory->max_power_level = 0;
827 for (i = 0; i < ARRAY_SIZE(ratesArray); i++) {
828 ratesArray[i] = (int16_t)(txPowerIndexOffset + ratesArray[i]);
829 - if (ratesArray[i] > AR5416_MAX_RATE_POWER)
830 - ratesArray[i] = AR5416_MAX_RATE_POWER;
831 + if (ratesArray[i] > MAX_RATE_POWER)
832 + ratesArray[i] = MAX_RATE_POWER;
833
834 if (ratesArray[i] > regulatory->max_power_level)
835 regulatory->max_power_level = ratesArray[i];
836 @@ -937,8 +770,7 @@ static void ath9k_hw_4k_set_board_values
837 pModal = &eep->modalHeader;
838 txRxAttenLocal = 23;
839
840 - REG_WRITE(ah, AR_PHY_SWITCH_COM,
841 - ah->eep_ops->get_eeprom_antenna_cfg(ah, chan));
842 + REG_WRITE(ah, AR_PHY_SWITCH_COM, pModal->antCtrlCommon);
843
844 /* Single chain for 4K EEPROM*/
845 ath9k_hw_4k_set_gain(ah, pModal, eep, txRxAttenLocal);
846 @@ -1154,21 +986,6 @@ static void ath9k_hw_4k_set_board_values
847 }
848 }
849
850 -static u32 ath9k_hw_4k_get_eeprom_antenna_cfg(struct ath_hw *ah,
851 - struct ath9k_channel *chan)
852 -{
853 - struct ar5416_eeprom_4k *eep = &ah->eeprom.map4k;
854 - struct modal_eep_4k_header *pModal = &eep->modalHeader;
855 -
856 - return pModal->antCtrlCommon;
857 -}
858 -
859 -static u8 ath9k_hw_4k_get_num_ant_config(struct ath_hw *ah,
860 - enum ath9k_hal_freq_band freq_band)
861 -{
862 - return 1;
863 -}
864 -
865 static u16 ath9k_hw_4k_get_spur_channel(struct ath_hw *ah, u16 i, bool is2GHz)
866 {
867 #define EEP_MAP4K_SPURCHAN \
868 @@ -1205,8 +1022,6 @@ const struct eeprom_ops eep_4k_ops = {
869 .fill_eeprom = ath9k_hw_4k_fill_eeprom,
870 .get_eeprom_ver = ath9k_hw_4k_get_eeprom_ver,
871 .get_eeprom_rev = ath9k_hw_4k_get_eeprom_rev,
872 - .get_num_ant_config = ath9k_hw_4k_get_num_ant_config,
873 - .get_eeprom_antenna_cfg = ath9k_hw_4k_get_eeprom_antenna_cfg,
874 .set_board_values = ath9k_hw_4k_set_board_values,
875 .set_addac = ath9k_hw_4k_set_addac,
876 .set_txpower = ath9k_hw_4k_set_txpower,
877 --- a/drivers/net/wireless/ath/ath9k/eeprom_9287.c
878 +++ b/drivers/net/wireless/ath/ath9k/eeprom_9287.c
879 @@ -150,7 +150,7 @@ static int ath9k_hw_ar9287_check_eeprom(
880 eep->modalHeader.antCtrlChain[i] = integer;
881 }
882
883 - for (i = 0; i < AR9287_EEPROM_MODAL_SPURS; i++) {
884 + for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
885 word = swab16(eep->modalHeader.spurChans[i].spurChan);
886 eep->modalHeader.spurChans[i].spurChan = word;
887 }
888 @@ -220,163 +220,6 @@ static u32 ath9k_hw_ar9287_get_eeprom(st
889 }
890 }
891
892 -static void ath9k_hw_get_ar9287_gain_boundaries_pdadcs(struct ath_hw *ah,
893 - struct ath9k_channel *chan,
894 - struct cal_data_per_freq_ar9287 *pRawDataSet,
895 - u8 *bChans, u16 availPiers,
896 - u16 tPdGainOverlap,
897 - u16 *pPdGainBoundaries,
898 - u8 *pPDADCValues,
899 - u16 numXpdGains)
900 -{
901 -#define TMP_VAL_VPD_TABLE \
902 - ((vpdTableI[i][sizeCurrVpdTable - 1] + (ss - maxIndex + 1) * vpdStep));
903 -
904 - int i, j, k;
905 - int16_t ss;
906 - u16 idxL = 0, idxR = 0, numPiers;
907 - u8 *pVpdL, *pVpdR, *pPwrL, *pPwrR;
908 - u8 minPwrT4[AR9287_NUM_PD_GAINS];
909 - u8 maxPwrT4[AR9287_NUM_PD_GAINS];
910 - int16_t vpdStep;
911 - int16_t tmpVal;
912 - u16 sizeCurrVpdTable, maxIndex, tgtIndex;
913 - bool match;
914 - int16_t minDelta = 0;
915 - struct chan_centers centers;
916 - static u8 vpdTableL[AR5416_EEP4K_NUM_PD_GAINS]
917 - [AR5416_MAX_PWR_RANGE_IN_HALF_DB];
918 - static u8 vpdTableR[AR5416_EEP4K_NUM_PD_GAINS]
919 - [AR5416_MAX_PWR_RANGE_IN_HALF_DB];
920 - static u8 vpdTableI[AR5416_EEP4K_NUM_PD_GAINS]
921 - [AR5416_MAX_PWR_RANGE_IN_HALF_DB];
922 -
923 - memset(&minPwrT4, 0, AR9287_NUM_PD_GAINS);
924 - ath9k_hw_get_channel_centers(ah, chan, &centers);
925 -
926 - for (numPiers = 0; numPiers < availPiers; numPiers++) {
927 - if (bChans[numPiers] == AR9287_BCHAN_UNUSED)
928 - break;
929 - }
930 -
931 - match = ath9k_hw_get_lower_upper_index(
932 - (u8)FREQ2FBIN(centers.synth_center, IS_CHAN_2GHZ(chan)),
933 - bChans, numPiers, &idxL, &idxR);
934 -
935 - if (match) {
936 - for (i = 0; i < numXpdGains; i++) {
937 - minPwrT4[i] = pRawDataSet[idxL].pwrPdg[i][0];
938 - maxPwrT4[i] = pRawDataSet[idxL].pwrPdg[i][4];
939 - ath9k_hw_fill_vpd_table(minPwrT4[i], maxPwrT4[i],
940 - pRawDataSet[idxL].pwrPdg[i],
941 - pRawDataSet[idxL].vpdPdg[i],
942 - AR9287_PD_GAIN_ICEPTS,
943 - vpdTableI[i]);
944 - }
945 - } else {
946 - for (i = 0; i < numXpdGains; i++) {
947 - pVpdL = pRawDataSet[idxL].vpdPdg[i];
948 - pPwrL = pRawDataSet[idxL].pwrPdg[i];
949 - pVpdR = pRawDataSet[idxR].vpdPdg[i];
950 - pPwrR = pRawDataSet[idxR].pwrPdg[i];
951 -
952 - minPwrT4[i] = max(pPwrL[0], pPwrR[0]);
953 -
954 - maxPwrT4[i] = min(pPwrL[AR9287_PD_GAIN_ICEPTS - 1],
955 - pPwrR[AR9287_PD_GAIN_ICEPTS - 1]);
956 -
957 - ath9k_hw_fill_vpd_table(minPwrT4[i], maxPwrT4[i],
958 - pPwrL, pVpdL,
959 - AR9287_PD_GAIN_ICEPTS,
960 - vpdTableL[i]);
961 - ath9k_hw_fill_vpd_table(minPwrT4[i], maxPwrT4[i],
962 - pPwrR, pVpdR,
963 - AR9287_PD_GAIN_ICEPTS,
964 - vpdTableR[i]);
965 -
966 - for (j = 0; j <= (maxPwrT4[i] - minPwrT4[i]) / 2; j++) {
967 - vpdTableI[i][j] = (u8)(ath9k_hw_interpolate(
968 - (u16)FREQ2FBIN(centers. synth_center,
969 - IS_CHAN_2GHZ(chan)),
970 - bChans[idxL], bChans[idxR],
971 - vpdTableL[i][j], vpdTableR[i][j]));
972 - }
973 - }
974 - }
975 -
976 - k = 0;
977 -
978 - for (i = 0; i < numXpdGains; i++) {
979 - if (i == (numXpdGains - 1))
980 - pPdGainBoundaries[i] =
981 - (u16)(maxPwrT4[i] / 2);
982 - else
983 - pPdGainBoundaries[i] =
984 - (u16)((maxPwrT4[i] + minPwrT4[i+1]) / 4);
985 -
986 - pPdGainBoundaries[i] = min((u16)AR5416_MAX_RATE_POWER,
987 - pPdGainBoundaries[i]);
988 -
989 -
990 - minDelta = 0;
991 -
992 - if (i == 0) {
993 - if (AR_SREV_9280_20_OR_LATER(ah))
994 - ss = (int16_t)(0 - (minPwrT4[i] / 2));
995 - else
996 - ss = 0;
997 - } else {
998 - ss = (int16_t)((pPdGainBoundaries[i-1] -
999 - (minPwrT4[i] / 2)) -
1000 - tPdGainOverlap + 1 + minDelta);
1001 - }
1002 -
1003 - vpdStep = (int16_t)(vpdTableI[i][1] - vpdTableI[i][0]);
1004 - vpdStep = (int16_t)((vpdStep < 1) ? 1 : vpdStep);
1005 -
1006 - while ((ss < 0) && (k < (AR9287_NUM_PDADC_VALUES - 1))) {
1007 - tmpVal = (int16_t)(vpdTableI[i][0] + ss * vpdStep);
1008 - pPDADCValues[k++] = (u8)((tmpVal < 0) ? 0 : tmpVal);
1009 - ss++;
1010 - }
1011 -
1012 - sizeCurrVpdTable = (u8)((maxPwrT4[i] - minPwrT4[i]) / 2 + 1);
1013 - tgtIndex = (u8)(pPdGainBoundaries[i] +
1014 - tPdGainOverlap - (minPwrT4[i] / 2));
1015 - maxIndex = (tgtIndex < sizeCurrVpdTable) ?
1016 - tgtIndex : sizeCurrVpdTable;
1017 -
1018 - while ((ss < maxIndex) && (k < (AR9287_NUM_PDADC_VALUES - 1)))
1019 - pPDADCValues[k++] = vpdTableI[i][ss++];
1020 -
1021 - vpdStep = (int16_t)(vpdTableI[i][sizeCurrVpdTable - 1] -
1022 - vpdTableI[i][sizeCurrVpdTable - 2]);
1023 - vpdStep = (int16_t)((vpdStep < 1) ? 1 : vpdStep);
1024 -
1025 - if (tgtIndex > maxIndex) {
1026 - while ((ss <= tgtIndex) &&
1027 - (k < (AR9287_NUM_PDADC_VALUES - 1))) {
1028 - tmpVal = (int16_t) TMP_VAL_VPD_TABLE;
1029 - pPDADCValues[k++] =
1030 - (u8)((tmpVal > 255) ? 255 : tmpVal);
1031 - ss++;
1032 - }
1033 - }
1034 - }
1035 -
1036 - while (i < AR9287_PD_GAINS_IN_MASK) {
1037 - pPdGainBoundaries[i] = pPdGainBoundaries[i-1];
1038 - i++;
1039 - }
1040 -
1041 - while (k < AR9287_NUM_PDADC_VALUES) {
1042 - pPDADCValues[k] = pPDADCValues[k-1];
1043 - k++;
1044 - }
1045 -
1046 -#undef TMP_VAL_VPD_TABLE
1047 -}
1048 -
1049 static void ar9287_eeprom_get_tx_gain_index(struct ath_hw *ah,
1050 struct ath9k_channel *chan,
1051 struct cal_data_op_loop_ar9287 *pRawDatasetOpLoop,
1052 @@ -389,7 +232,7 @@ static void ar9287_eeprom_get_tx_gain_in
1053 ath9k_hw_get_channel_centers(ah, chan, &centers);
1054
1055 for (numPiers = 0; numPiers < availPiers; numPiers++) {
1056 - if (pCalChans[numPiers] == AR9287_BCHAN_UNUSED)
1057 + if (pCalChans[numPiers] == AR5416_BCHAN_UNUSED)
1058 break;
1059 }
1060
1061 @@ -455,11 +298,11 @@ static void ath9k_hw_set_ar9287_power_ca
1062 struct cal_data_op_loop_ar9287 *pRawDatasetOpenLoop;
1063 u8 *pCalBChans = NULL;
1064 u16 pdGainOverlap_t2;
1065 - u8 pdadcValues[AR9287_NUM_PDADC_VALUES];
1066 - u16 gainBoundaries[AR9287_PD_GAINS_IN_MASK];
1067 + u8 pdadcValues[AR5416_NUM_PDADC_VALUES];
1068 + u16 gainBoundaries[AR5416_PD_GAINS_IN_MASK];
1069 u16 numPiers = 0, i, j;
1070 u16 numXpdGain, xpdMask;
1071 - u16 xpdGainValues[AR9287_NUM_PD_GAINS] = {0, 0, 0, 0};
1072 + u16 xpdGainValues[AR5416_NUM_PD_GAINS] = {0, 0, 0, 0};
1073 u32 reg32, regOffset, regChainOffset, regval;
1074 int16_t modalIdx, diff = 0;
1075 struct ar9287_eeprom *pEepData = &ah->eeprom.map9287;
1076 @@ -487,12 +330,12 @@ static void ath9k_hw_set_ar9287_power_ca
1077 numXpdGain = 0;
1078
1079 /* Calculate the value of xpdgains from the xpdGain Mask */
1080 - for (i = 1; i <= AR9287_PD_GAINS_IN_MASK; i++) {
1081 - if ((xpdMask >> (AR9287_PD_GAINS_IN_MASK - i)) & 1) {
1082 - if (numXpdGain >= AR9287_NUM_PD_GAINS)
1083 + for (i = 1; i <= AR5416_PD_GAINS_IN_MASK; i++) {
1084 + if ((xpdMask >> (AR5416_PD_GAINS_IN_MASK - i)) & 1) {
1085 + if (numXpdGain >= AR5416_NUM_PD_GAINS)
1086 break;
1087 xpdGainValues[numXpdGain] =
1088 - (u16)(AR9287_PD_GAINS_IN_MASK-i);
1089 + (u16)(AR5416_PD_GAINS_IN_MASK-i);
1090 numXpdGain++;
1091 }
1092 }
1093 @@ -525,7 +368,7 @@ static void ath9k_hw_set_ar9287_power_ca
1094 (struct cal_data_per_freq_ar9287 *)
1095 pEepData->calPierData2G[i];
1096
1097 - ath9k_hw_get_ar9287_gain_boundaries_pdadcs(ah, chan,
1098 + ath9k_hw_get_gain_boundaries_pdadcs(ah, chan,
1099 pRawDataset,
1100 pCalBChans, numPiers,
1101 pdGainOverlap_t2,
1102 @@ -561,13 +404,13 @@ static void ath9k_hw_set_ar9287_power_ca
1103 (int32_t)AR9287_PWR_TABLE_OFFSET_DB);
1104 diff *= 2;
1105
1106 - for (j = 0; j < ((u16)AR9287_NUM_PDADC_VALUES-diff); j++)
1107 + for (j = 0; j < ((u16)AR5416_NUM_PDADC_VALUES-diff); j++)
1108 pdadcValues[j] = pdadcValues[j+diff];
1109
1110 - for (j = (u16)(AR9287_NUM_PDADC_VALUES-diff);
1111 - j < AR9287_NUM_PDADC_VALUES; j++)
1112 + for (j = (u16)(AR5416_NUM_PDADC_VALUES-diff);
1113 + j < AR5416_NUM_PDADC_VALUES; j++)
1114 pdadcValues[j] =
1115 - pdadcValues[AR9287_NUM_PDADC_VALUES-diff];
1116 + pdadcValues[AR5416_NUM_PDADC_VALUES-diff];
1117 }
1118
1119 if (!ath9k_hw_ar9287_get_eeprom(ah, EEP_OL_PWRCTRL)) {
1120 @@ -610,9 +453,9 @@ static void ath9k_hw_set_ar9287_power_pe
1121 #define REDUCE_SCALED_POWER_BY_THREE_CHAIN 10
1122
1123 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
1124 - u16 twiceMaxEdgePower = AR5416_MAX_RATE_POWER;
1125 + u16 twiceMaxEdgePower = MAX_RATE_POWER;
1126 static const u16 tpScaleReductionTable[5] =
1127 - { 0, 3, 6, 9, AR5416_MAX_RATE_POWER };
1128 + { 0, 3, 6, 9, MAX_RATE_POWER };
1129 int i;
1130 int16_t twiceLargestAntenna;
1131 struct cal_ctl_data_ar9287 *rep;
1132 @@ -877,8 +720,8 @@ static void ath9k_hw_ar9287_set_txpower(
1133 regulatory->max_power_level = 0;
1134 for (i = 0; i < ARRAY_SIZE(ratesArray); i++) {
1135 ratesArray[i] = (int16_t)(txPowerIndexOffset + ratesArray[i]);
1136 - if (ratesArray[i] > AR9287_MAX_RATE_POWER)
1137 - ratesArray[i] = AR9287_MAX_RATE_POWER;
1138 + if (ratesArray[i] > MAX_RATE_POWER)
1139 + ratesArray[i] = MAX_RATE_POWER;
1140
1141 if (ratesArray[i] > regulatory->max_power_level)
1142 regulatory->max_power_level = ratesArray[i];
1143 @@ -1023,8 +866,7 @@ static void ath9k_hw_ar9287_set_board_va
1144 antWrites[j++] = (u16)(pModal->antCtrlChain[i] & 0x3);
1145 }
1146
1147 - REG_WRITE(ah, AR_PHY_SWITCH_COM,
1148 - ah->eep_ops->get_eeprom_antenna_cfg(ah, chan));
1149 + REG_WRITE(ah, AR_PHY_SWITCH_COM, pModal->antCtrlCommon);
1150
1151 for (i = 0; i < AR9287_MAX_CHAINS; i++) {
1152 regChainOffset = i * 0x1000;
1153 @@ -1125,21 +967,6 @@ static void ath9k_hw_ar9287_set_board_va
1154 pModal->xpaBiasLvl);
1155 }
1156
1157 -static u8 ath9k_hw_ar9287_get_num_ant_config(struct ath_hw *ah,
1158 - enum ath9k_hal_freq_band freq_band)
1159 -{
1160 - return 1;
1161 -}
1162 -
1163 -static u32 ath9k_hw_ar9287_get_eeprom_antenna_cfg(struct ath_hw *ah,
1164 - struct ath9k_channel *chan)
1165 -{
1166 - struct ar9287_eeprom *eep = &ah->eeprom.map9287;
1167 - struct modal_eep_ar9287_header *pModal = &eep->modalHeader;
1168 -
1169 - return pModal->antCtrlCommon;
1170 -}
1171 -
1172 static u16 ath9k_hw_ar9287_get_spur_channel(struct ath_hw *ah,
1173 u16 i, bool is2GHz)
1174 {
1175 @@ -1177,8 +1004,6 @@ const struct eeprom_ops eep_ar9287_ops =
1176 .fill_eeprom = ath9k_hw_ar9287_fill_eeprom,
1177 .get_eeprom_ver = ath9k_hw_ar9287_get_eeprom_ver,
1178 .get_eeprom_rev = ath9k_hw_ar9287_get_eeprom_rev,
1179 - .get_num_ant_config = ath9k_hw_ar9287_get_num_ant_config,
1180 - .get_eeprom_antenna_cfg = ath9k_hw_ar9287_get_eeprom_antenna_cfg,
1181 .set_board_values = ath9k_hw_ar9287_set_board_values,
1182 .set_addac = ath9k_hw_ar9287_set_addac,
1183 .set_txpower = ath9k_hw_ar9287_set_txpower,
1184 --- a/drivers/net/wireless/ath/ath9k/eeprom_def.c
1185 +++ b/drivers/net/wireless/ath/ath9k/eeprom_def.c
1186 @@ -206,7 +206,7 @@ static int ath9k_hw_def_check_eeprom(str
1187 pModal->antCtrlChain[i] = integer;
1188 }
1189
1190 - for (i = 0; i < AR5416_EEPROM_MODAL_SPURS; i++) {
1191 + for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
1192 word = swab16(pModal->spurChans[i].spurChan);
1193 pModal->spurChans[i].spurChan = word;
1194 }
1195 @@ -374,8 +374,7 @@ static void ath9k_hw_def_set_board_value
1196 pModal = &(eep->modalHeader[IS_CHAN_2GHZ(chan)]);
1197 txRxAttenLocal = IS_CHAN_2GHZ(chan) ? 23 : 44;
1198
1199 - REG_WRITE(ah, AR_PHY_SWITCH_COM,
1200 - ah->eep_ops->get_eeprom_antenna_cfg(ah, chan));
1201 + REG_WRITE(ah, AR_PHY_SWITCH_COM, pModal->antCtrlCommon & 0xffff);
1202
1203 for (i = 0; i < AR5416_MAX_CHAINS; i++) {
1204 if (AR_SREV_9280(ah)) {
1205 @@ -588,168 +587,6 @@ static void ath9k_hw_def_set_addac(struc
1206 #undef XPA_LVL_FREQ
1207 }
1208
1209 -static void ath9k_hw_get_def_gain_boundaries_pdadcs(struct ath_hw *ah,
1210 - struct ath9k_channel *chan,
1211 - struct cal_data_per_freq *pRawDataSet,
1212 - u8 *bChans, u16 availPiers,
1213 - u16 tPdGainOverlap,
1214 - u16 *pPdGainBoundaries, u8 *pPDADCValues,
1215 - u16 numXpdGains)
1216 -{
1217 - int i, j, k;
1218 - int16_t ss;
1219 - u16 idxL = 0, idxR = 0, numPiers;
1220 - static u8 vpdTableL[AR5416_NUM_PD_GAINS]
1221 - [AR5416_MAX_PWR_RANGE_IN_HALF_DB];
1222 - static u8 vpdTableR[AR5416_NUM_PD_GAINS]
1223 - [AR5416_MAX_PWR_RANGE_IN_HALF_DB];
1224 - static u8 vpdTableI[AR5416_NUM_PD_GAINS]
1225 - [AR5416_MAX_PWR_RANGE_IN_HALF_DB];
1226 -
1227 - u8 *pVpdL, *pVpdR, *pPwrL, *pPwrR;
1228 - u8 minPwrT4[AR5416_NUM_PD_GAINS];
1229 - u8 maxPwrT4[AR5416_NUM_PD_GAINS];
1230 - int16_t vpdStep;
1231 - int16_t tmpVal;
1232 - u16 sizeCurrVpdTable, maxIndex, tgtIndex;
1233 - bool match;
1234 - int16_t minDelta = 0;
1235 - struct chan_centers centers;
1236 -
1237 - memset(&minPwrT4, 0, AR9287_NUM_PD_GAINS);
1238 - ath9k_hw_get_channel_centers(ah, chan, &centers);
1239 -
1240 - for (numPiers = 0; numPiers < availPiers; numPiers++) {
1241 - if (bChans[numPiers] == AR5416_BCHAN_UNUSED)
1242 - break;
1243 - }
1244 -
1245 - match = ath9k_hw_get_lower_upper_index((u8)FREQ2FBIN(centers.synth_center,
1246 - IS_CHAN_2GHZ(chan)),
1247 - bChans, numPiers, &idxL, &idxR);
1248 -
1249 - if (match) {
1250 - for (i = 0; i < numXpdGains; i++) {
1251 - minPwrT4[i] = pRawDataSet[idxL].pwrPdg[i][0];
1252 - maxPwrT4[i] = pRawDataSet[idxL].pwrPdg[i][4];
1253 - ath9k_hw_fill_vpd_table(minPwrT4[i], maxPwrT4[i],
1254 - pRawDataSet[idxL].pwrPdg[i],
1255 - pRawDataSet[idxL].vpdPdg[i],
1256 - AR5416_PD_GAIN_ICEPTS,
1257 - vpdTableI[i]);
1258 - }
1259 - } else {
1260 - for (i = 0; i < numXpdGains; i++) {
1261 - pVpdL = pRawDataSet[idxL].vpdPdg[i];
1262 - pPwrL = pRawDataSet[idxL].pwrPdg[i];
1263 - pVpdR = pRawDataSet[idxR].vpdPdg[i];
1264 - pPwrR = pRawDataSet[idxR].pwrPdg[i];
1265 -
1266 - minPwrT4[i] = max(pPwrL[0], pPwrR[0]);
1267 -
1268 - maxPwrT4[i] =
1269 - min(pPwrL[AR5416_PD_GAIN_ICEPTS - 1],
1270 - pPwrR[AR5416_PD_GAIN_ICEPTS - 1]);
1271 -
1272 -
1273 - ath9k_hw_fill_vpd_table(minPwrT4[i], maxPwrT4[i],
1274 - pPwrL, pVpdL,
1275 - AR5416_PD_GAIN_ICEPTS,
1276 - vpdTableL[i]);
1277 - ath9k_hw_fill_vpd_table(minPwrT4[i], maxPwrT4[i],
1278 - pPwrR, pVpdR,
1279 - AR5416_PD_GAIN_ICEPTS,
1280 - vpdTableR[i]);
1281 -
1282 - for (j = 0; j <= (maxPwrT4[i] - minPwrT4[i]) / 2; j++) {
1283 - vpdTableI[i][j] =
1284 - (u8)(ath9k_hw_interpolate((u16)
1285 - FREQ2FBIN(centers.
1286 - synth_center,
1287 - IS_CHAN_2GHZ
1288 - (chan)),
1289 - bChans[idxL], bChans[idxR],
1290 - vpdTableL[i][j], vpdTableR[i][j]));
1291 - }
1292 - }
1293 - }
1294 -
1295 - k = 0;
1296 -
1297 - for (i = 0; i < numXpdGains; i++) {
1298 - if (i == (numXpdGains - 1))
1299 - pPdGainBoundaries[i] =
1300 - (u16)(maxPwrT4[i] / 2);
1301 - else
1302 - pPdGainBoundaries[i] =
1303 - (u16)((maxPwrT4[i] + minPwrT4[i + 1]) / 4);
1304 -
1305 - pPdGainBoundaries[i] =
1306 - min((u16)AR5416_MAX_RATE_POWER, pPdGainBoundaries[i]);
1307 -
1308 - if ((i == 0) && !AR_SREV_5416_20_OR_LATER(ah)) {
1309 - minDelta = pPdGainBoundaries[0] - 23;
1310 - pPdGainBoundaries[0] = 23;
1311 - } else {
1312 - minDelta = 0;
1313 - }
1314 -
1315 - if (i == 0) {
1316 - if (AR_SREV_9280_20_OR_LATER(ah))
1317 - ss = (int16_t)(0 - (minPwrT4[i] / 2));
1318 - else
1319 - ss = 0;
1320 - } else {
1321 - ss = (int16_t)((pPdGainBoundaries[i - 1] -
1322 - (minPwrT4[i] / 2)) -
1323 - tPdGainOverlap + 1 + minDelta);
1324 - }
1325 - vpdStep = (int16_t)(vpdTableI[i][1] - vpdTableI[i][0]);
1326 - vpdStep = (int16_t)((vpdStep < 1) ? 1 : vpdStep);
1327 -
1328 - while ((ss < 0) && (k < (AR5416_NUM_PDADC_VALUES - 1))) {
1329 - tmpVal = (int16_t)(vpdTableI[i][0] + ss * vpdStep);
1330 - pPDADCValues[k++] = (u8)((tmpVal < 0) ? 0 : tmpVal);
1331 - ss++;
1332 - }
1333 -
1334 - sizeCurrVpdTable = (u8) ((maxPwrT4[i] - minPwrT4[i]) / 2 + 1);
1335 - tgtIndex = (u8)(pPdGainBoundaries[i] + tPdGainOverlap -
1336 - (minPwrT4[i] / 2));
1337 - maxIndex = (tgtIndex < sizeCurrVpdTable) ?
1338 - tgtIndex : sizeCurrVpdTable;
1339 -
1340 - while ((ss < maxIndex) && (k < (AR5416_NUM_PDADC_VALUES - 1))) {
1341 - pPDADCValues[k++] = vpdTableI[i][ss++];
1342 - }
1343 -
1344 - vpdStep = (int16_t)(vpdTableI[i][sizeCurrVpdTable - 1] -
1345 - vpdTableI[i][sizeCurrVpdTable - 2]);
1346 - vpdStep = (int16_t)((vpdStep < 1) ? 1 : vpdStep);
1347 -
1348 - if (tgtIndex >= maxIndex) {
1349 - while ((ss <= tgtIndex) &&
1350 - (k < (AR5416_NUM_PDADC_VALUES - 1))) {
1351 - tmpVal = (int16_t)((vpdTableI[i][sizeCurrVpdTable - 1] +
1352 - (ss - maxIndex + 1) * vpdStep));
1353 - pPDADCValues[k++] = (u8)((tmpVal > 255) ?
1354 - 255 : tmpVal);
1355 - ss++;
1356 - }
1357 - }
1358 - }
1359 -
1360 - while (i < AR5416_PD_GAINS_IN_MASK) {
1361 - pPdGainBoundaries[i] = pPdGainBoundaries[i - 1];
1362 - i++;
1363 - }
1364 -
1365 - while (k < AR5416_NUM_PDADC_VALUES) {
1366 - pPDADCValues[k] = pPDADCValues[k - 1];
1367 - k++;
1368 - }
1369 -}
1370 -
1371 static int16_t ath9k_change_gain_boundary_setting(struct ath_hw *ah,
1372 u16 *gb,
1373 u16 numXpdGain,
1374 @@ -782,7 +619,7 @@ static int16_t ath9k_change_gain_boundar
1375 /* Because of a hardware limitation, ensure the gain boundary
1376 * is not larger than (63 - overlap)
1377 */
1378 - gb_limit = (u16)(AR5416_MAX_RATE_POWER - pdGainOverlap_t2);
1379 + gb_limit = (u16)(MAX_RATE_POWER - pdGainOverlap_t2);
1380
1381 for (k = 0; k < numXpdGain; k++)
1382 gb[k] = (u16)min(gb_limit, gb[k]);
1383 @@ -916,7 +753,7 @@ static void ath9k_hw_set_def_power_cal_t
1384 ath9k_olc_get_pdadcs(ah, pcdacIdx,
1385 txPower/2, pdadcValues);
1386 } else {
1387 - ath9k_hw_get_def_gain_boundaries_pdadcs(ah,
1388 + ath9k_hw_get_gain_boundaries_pdadcs(ah,
1389 chan, pRawDataset,
1390 pCalBChans, numPiers,
1391 pdGainOverlap_t2,
1392 @@ -1001,9 +838,9 @@ static void ath9k_hw_set_def_power_per_r
1393
1394 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
1395 struct ar5416_eeprom_def *pEepData = &ah->eeprom.def;
1396 - u16 twiceMaxEdgePower = AR5416_MAX_RATE_POWER;
1397 + u16 twiceMaxEdgePower = MAX_RATE_POWER;
1398 static const u16 tpScaleReductionTable[5] =
1399 - { 0, 3, 6, 9, AR5416_MAX_RATE_POWER };
1400 + { 0, 3, 6, 9, MAX_RATE_POWER };
1401
1402 int i;
1403 int16_t twiceLargestAntenna;
1404 @@ -1148,7 +985,7 @@ static void ath9k_hw_set_def_power_per_r
1405
1406 if (ah->eep_ops->get_eeprom_ver(ah) == 14 &&
1407 ah->eep_ops->get_eeprom_rev(ah) <= 2)
1408 - twiceMaxEdgePower = AR5416_MAX_RATE_POWER;
1409 + twiceMaxEdgePower = MAX_RATE_POWER;
1410
1411 for (i = 0; (i < AR5416_NUM_CTLS) && pEepData->ctlIndex[i]; i++) {
1412 if ((((cfgCtl & ~CTL_MODE_M) |
1413 @@ -1293,8 +1130,8 @@ static void ath9k_hw_def_set_txpower(str
1414 regulatory->max_power_level = 0;
1415 for (i = 0; i < ARRAY_SIZE(ratesArray); i++) {
1416 ratesArray[i] = (int16_t)(txPowerIndexOffset + ratesArray[i]);
1417 - if (ratesArray[i] > AR5416_MAX_RATE_POWER)
1418 - ratesArray[i] = AR5416_MAX_RATE_POWER;
1419 + if (ratesArray[i] > MAX_RATE_POWER)
1420 + ratesArray[i] = MAX_RATE_POWER;
1421 if (ratesArray[i] > regulatory->max_power_level)
1422 regulatory->max_power_level = ratesArray[i];
1423 }
1424 @@ -1426,34 +1263,6 @@ static void ath9k_hw_def_set_txpower(str
1425 | ATH9K_POW_SM(pModal->pwrDecreaseFor2Chain, 0));
1426 }
1427
1428 -static u8 ath9k_hw_def_get_num_ant_config(struct ath_hw *ah,
1429 - enum ath9k_hal_freq_band freq_band)
1430 -{
1431 - struct ar5416_eeprom_def *eep = &ah->eeprom.def;
1432 - struct modal_eep_header *pModal =
1433 - &(eep->modalHeader[freq_band]);
1434 - struct base_eep_header *pBase = &eep->baseEepHeader;
1435 - u8 num_ant_config;
1436 -
1437 - num_ant_config = 1;
1438 -
1439 - if (pBase->version >= 0x0E0D &&
1440 - (pModal->lna_ctl & LNA_CTL_USE_ANT1))
1441 - num_ant_config += 1;
1442 -
1443 - return num_ant_config;
1444 -}
1445 -
1446 -static u32 ath9k_hw_def_get_eeprom_antenna_cfg(struct ath_hw *ah,
1447 - struct ath9k_channel *chan)
1448 -{
1449 - struct ar5416_eeprom_def *eep = &ah->eeprom.def;
1450 - struct modal_eep_header *pModal =
1451 - &(eep->modalHeader[IS_CHAN_2GHZ(chan)]);
1452 -
1453 - return pModal->antCtrlCommon;
1454 -}
1455 -
1456 static u16 ath9k_hw_def_get_spur_channel(struct ath_hw *ah, u16 i, bool is2GHz)
1457 {
1458 #define EEP_DEF_SPURCHAN \
1459 @@ -1490,8 +1299,6 @@ const struct eeprom_ops eep_def_ops = {
1460 .fill_eeprom = ath9k_hw_def_fill_eeprom,
1461 .get_eeprom_ver = ath9k_hw_def_get_eeprom_ver,
1462 .get_eeprom_rev = ath9k_hw_def_get_eeprom_rev,
1463 - .get_num_ant_config = ath9k_hw_def_get_num_ant_config,
1464 - .get_eeprom_antenna_cfg = ath9k_hw_def_get_eeprom_antenna_cfg,
1465 .set_board_values = ath9k_hw_def_set_board_values,
1466 .set_addac = ath9k_hw_def_set_addac,
1467 .set_txpower = ath9k_hw_def_set_txpower,
1468 --- a/drivers/net/wireless/ath/ath9k/hw.c
1469 +++ b/drivers/net/wireless/ath/ath9k/hw.c
1470 @@ -54,13 +54,6 @@ static void ath9k_hw_init_mode_regs(stru
1471 ath9k_hw_private_ops(ah)->init_mode_regs(ah);
1472 }
1473
1474 -static bool ath9k_hw_macversion_supported(struct ath_hw *ah)
1475 -{
1476 - struct ath_hw_private_ops *priv_ops = ath9k_hw_private_ops(ah);
1477 -
1478 - return priv_ops->macversion_supported(ah->hw_version.macVersion);
1479 -}
1480 -
1481 static u32 ath9k_hw_compute_pll_control(struct ath_hw *ah,
1482 struct ath9k_channel *chan)
1483 {
1484 @@ -414,7 +407,6 @@ static void ath9k_hw_init_defaults(struc
1485 ah->sta_id1_defaults =
1486 AR_STA_ID1_CRPT_MIC_ENABLE |
1487 AR_STA_ID1_MCAST_KSRCH;
1488 - ah->beacon_interval = 100;
1489 ah->enable_32kHz_clock = DONT_USE_32KHZ;
1490 ah->slottime = (u32) -1;
1491 ah->globaltxtimeout = (u32) -1;
1492 @@ -534,10 +526,22 @@ static int __ath9k_hw_init(struct ath_hw
1493 else
1494 ah->config.max_txtrig_level = MAX_TX_FIFO_THRESHOLD;
1495
1496 - if (!ath9k_hw_macversion_supported(ah)) {
1497 - ath_err(common,
1498 - "Mac Chip Rev 0x%02x.%x is not supported by this driver\n",
1499 - ah->hw_version.macVersion, ah->hw_version.macRev);
1500 + switch (ah->hw_version.macVersion) {
1501 + case AR_SREV_VERSION_5416_PCI:
1502 + case AR_SREV_VERSION_5416_PCIE:
1503 + case AR_SREV_VERSION_9160:
1504 + case AR_SREV_VERSION_9100:
1505 + case AR_SREV_VERSION_9280:
1506 + case AR_SREV_VERSION_9285:
1507 + case AR_SREV_VERSION_9287:
1508 + case AR_SREV_VERSION_9271:
1509 + case AR_SREV_VERSION_9300:
1510 + case AR_SREV_VERSION_9485:
1511 + break;
1512 + default:
1513 + ath_err(common, "Mac Chip Rev 0x%02x.%x is not supported by "
1514 + "this driver\n", ah->hw_version.macVersion,
1515 + ah->hw_version.macRev);
1516 return -EOPNOTSUPP;
1517 }
1518
1519 @@ -1639,8 +1643,6 @@ void ath9k_hw_beaconinit(struct ath_hw *
1520 {
1521 int flags = 0;
1522
1523 - ah->beacon_interval = beacon_period;
1524 -
1525 ENABLE_REGWRITE_BUFFER(ah);
1526
1527 switch (ah->opmode) {
1528 @@ -1932,11 +1934,6 @@ int ath9k_hw_fill_cap_info(struct ath_hw
1529 AR_SREV_5416(ah))
1530 pCap->reg_cap |= AR_EEPROM_EEREGCAP_EN_FCC_MIDBAND;
1531
1532 - pCap->num_antcfg_5ghz =
1533 - ah->eep_ops->get_num_ant_config(ah, ATH9K_HAL_FREQ_BAND_5GHZ);
1534 - pCap->num_antcfg_2ghz =
1535 - ah->eep_ops->get_num_ant_config(ah, ATH9K_HAL_FREQ_BAND_2GHZ);
1536 -
1537 if (AR_SREV_9280_20_OR_LATER(ah) && common->btcoex_enabled) {
1538 btcoex_hw->btactive_gpio = ATH_BTACTIVE_GPIO;
1539 btcoex_hw->wlanactive_gpio = ATH_WLANACTIVE_GPIO;
1540 --- a/drivers/net/wireless/ath/ath9k/hw.h
1541 +++ b/drivers/net/wireless/ath/ath9k/hw.h
1542 @@ -204,8 +204,6 @@ struct ath9k_hw_capabilities {
1543 u16 tx_triglevel_max;
1544 u16 reg_cap;
1545 u8 num_gpio_pins;
1546 - u8 num_antcfg_2ghz;
1547 - u8 num_antcfg_5ghz;
1548 u8 rx_hp_qdepth;
1549 u8 rx_lp_qdepth;
1550 u8 rx_status_len;
1551 @@ -238,7 +236,6 @@ struct ath9k_ops_config {
1552 #define SPUR_DISABLE 0
1553 #define SPUR_ENABLE_IOCTL 1
1554 #define SPUR_ENABLE_EEPROM 2
1555 -#define AR_EEPROM_MODAL_SPURS 5
1556 #define AR_SPUR_5413_1 1640
1557 #define AR_SPUR_5413_2 1200
1558 #define AR_NO_SPUR 0x8000
1559 @@ -535,7 +532,6 @@ struct ath_hw_radar_conf {
1560 *
1561 * @init_mode_regs: Initializes mode registers
1562 * @init_mode_gain_regs: Initialize TX/RX gain registers
1563 - * @macversion_supported: If this specific mac revision is supported
1564 *
1565 * @rf_set_freq: change frequency
1566 * @spur_mitigate_freq: spur mitigation
1567 @@ -557,7 +553,6 @@ struct ath_hw_private_ops {
1568
1569 void (*init_mode_regs)(struct ath_hw *ah);
1570 void (*init_mode_gain_regs)(struct ath_hw *ah);
1571 - bool (*macversion_supported)(u32 macversion);
1572 void (*setup_calibration)(struct ath_hw *ah,
1573 struct ath9k_cal_list *currCal);
1574
1575 @@ -767,9 +762,7 @@ struct ath_hw {
1576 u32 *bank6Temp;
1577
1578 u8 txpower_limit;
1579 - int16_t txpower_indexoffset;
1580 int coverage_class;
1581 - u32 beacon_interval;
1582 u32 slottime;
1583 u32 globaltxtimeout;
1584
1585 --- a/drivers/net/wireless/ath/ath9k/ar9003_eeprom.h
1586 +++ b/drivers/net/wireless/ath/ath9k/ar9003_eeprom.h
1587 @@ -20,48 +20,17 @@
1588 /* #define AR9300_NUM_CTLS 21 */
1589 #define AR9300_NUM_CTLS_5G 9
1590 #define AR9300_NUM_CTLS_2G 12
1591 -#define AR9300_CTL_MODE_M 0xF
1592 #define AR9300_NUM_BAND_EDGES_5G 8
1593 #define AR9300_NUM_BAND_EDGES_2G 4
1594 -#define AR9300_NUM_PD_GAINS 4
1595 -#define AR9300_PD_GAINS_IN_MASK 4
1596 -#define AR9300_PD_GAIN_ICEPTS 5
1597 -#define AR9300_EEPROM_MODAL_SPURS 5
1598 -#define AR9300_MAX_RATE_POWER 63
1599 -#define AR9300_NUM_PDADC_VALUES 128
1600 -#define AR9300_NUM_RATES 16
1601 -#define AR9300_BCHAN_UNUSED 0xFF
1602 -#define AR9300_MAX_PWR_RANGE_IN_HALF_DB 64
1603 -#define AR9300_OPFLAGS_11A 0x01
1604 -#define AR9300_OPFLAGS_11G 0x02
1605 -#define AR9300_OPFLAGS_5G_HT40 0x04
1606 -#define AR9300_OPFLAGS_2G_HT40 0x08
1607 -#define AR9300_OPFLAGS_5G_HT20 0x10
1608 -#define AR9300_OPFLAGS_2G_HT20 0x20
1609 #define AR9300_EEPMISC_BIG_ENDIAN 0x01
1610 #define AR9300_EEPMISC_WOW 0x02
1611 #define AR9300_CUSTOMER_DATA_SIZE 20
1612
1613 -#define FREQ2FBIN(x, y) ((y) ? ((x) - 2300) : (((x) - 4800) / 5))
1614 #define FBIN2FREQ(x, y) ((y) ? (2300 + x) : (4800 + 5 * x))
1615 #define AR9300_MAX_CHAINS 3
1616 #define AR9300_ANT_16S 25
1617 #define AR9300_FUTURE_MODAL_SZ 6
1618
1619 -#define AR9300_NUM_ANT_CHAIN_FIELDS 7
1620 -#define AR9300_NUM_ANT_COMMON_FIELDS 4
1621 -#define AR9300_SIZE_ANT_CHAIN_FIELD 3
1622 -#define AR9300_SIZE_ANT_COMMON_FIELD 4
1623 -#define AR9300_ANT_CHAIN_MASK 0x7
1624 -#define AR9300_ANT_COMMON_MASK 0xf
1625 -#define AR9300_CHAIN_0_IDX 0
1626 -#define AR9300_CHAIN_1_IDX 1
1627 -#define AR9300_CHAIN_2_IDX 2
1628 -
1629 -#define AR928X_NUM_ANT_CHAIN_FIELDS 6
1630 -#define AR928X_SIZE_ANT_CHAIN_FIELD 2
1631 -#define AR928X_ANT_CHAIN_MASK 0x3
1632 -
1633 /* Delta from which to start power to pdadc table */
1634 /* This offset is used in both open loop and closed loop power control
1635 * schemes. In open loop power control, it is not really needed, but for
1636 @@ -71,12 +40,8 @@
1637 */
1638 #define AR9300_PWR_TABLE_OFFSET 0
1639
1640 -/* enable flags for voltage and temp compensation */
1641 -#define ENABLE_TEMP_COMPENSATION 0x01
1642 -#define ENABLE_VOLT_COMPENSATION 0x02
1643 /* byte addressable */
1644 #define AR9300_EEPROM_SIZE (16*1024)
1645 -#define FIXED_CCA_THRESHOLD 15
1646
1647 #define AR9300_BASE_ADDR_4K 0xfff
1648 #define AR9300_BASE_ADDR 0x3ff
1649 @@ -226,7 +191,7 @@ struct ar9300_modal_eep_header {
1650 int8_t tempSlope;
1651 int8_t voltSlope;
1652 /* spur channels in usual fbin coding format */
1653 - u8 spurChans[AR9300_EEPROM_MODAL_SPURS];
1654 + u8 spurChans[AR_EEPROM_MODAL_SPURS];
1655 /* 3 Check if the register is per chain */
1656 int8_t noiseFloorThreshCh[AR9300_MAX_CHAINS];
1657 u8 ob[AR9300_MAX_CHAINS];
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