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[kernel] kmod-usb-core is buildin on etrax target
[openwrt.git] / target / linux / generic / patches-2.6.34 / 975-ssb_update.patch
1 --- a/drivers/ssb/driver_chipcommon.c
2 +++ b/drivers/ssb/driver_chipcommon.c
3 @@ -233,6 +233,8 @@ void ssb_chipcommon_init(struct ssb_chip
4 {
5 if (!cc->dev)
6 return; /* We don't have a ChipCommon */
7 + if (cc->dev->id.revision >= 11)
8 + cc->status = chipco_read32(cc, SSB_CHIPCO_CHIPSTAT);
9 ssb_pmu_init(cc);
10 chipco_powercontrol_init(cc);
11 ssb_chipco_set_clockmode(cc, SSB_CLKMODE_FAST);
12 @@ -370,6 +372,7 @@ u32 ssb_chipco_gpio_control(struct ssb_c
13 {
14 return chipco_write32_masked(cc, SSB_CHIPCO_GPIOCTL, mask, value);
15 }
16 +EXPORT_SYMBOL(ssb_chipco_gpio_control);
17
18 u32 ssb_chipco_gpio_intmask(struct ssb_chipcommon *cc, u32 mask, u32 value)
19 {
20 --- a/drivers/ssb/main.c
21 +++ b/drivers/ssb/main.c
22 @@ -834,6 +834,9 @@ int ssb_bus_pcibus_register(struct ssb_b
23 if (!err) {
24 ssb_printk(KERN_INFO PFX "Sonics Silicon Backplane found on "
25 "PCI device %s\n", dev_name(&host_pci->dev));
26 + } else {
27 + ssb_printk(KERN_ERR PFX "Failed to register PCI version"
28 + " of SSB with error %d\n", err);
29 }
30
31 return err;
32 --- a/drivers/ssb/pci.c
33 +++ b/drivers/ssb/pci.c
34 @@ -168,7 +168,7 @@ err_pci:
35 }
36
37 /* Get the word-offset for a SSB_SPROM_XXX define. */
38 -#define SPOFF(offset) (((offset) - SSB_SPROM_BASE) / sizeof(u16))
39 +#define SPOFF(offset) ((offset) / sizeof(u16))
40 /* Helper to extract some _offset, which is one of the SSB_SPROM_XXX defines. */
41 #define SPEX16(_outvar, _offset, _mask, _shift) \
42 out->_outvar = ((in[SPOFF(_offset)] & (_mask)) >> (_shift))
43 @@ -254,7 +254,7 @@ static int sprom_do_read(struct ssb_bus
44 int i;
45
46 for (i = 0; i < bus->sprom_size; i++)
47 - sprom[i] = ioread16(bus->mmio + SSB_SPROM_BASE + (i * 2));
48 + sprom[i] = ioread16(bus->mmio + bus->sprom_offset + (i * 2));
49
50 return 0;
51 }
52 @@ -285,7 +285,7 @@ static int sprom_do_write(struct ssb_bus
53 ssb_printk("75%%");
54 else if (i % 2)
55 ssb_printk(".");
56 - writew(sprom[i], bus->mmio + SSB_SPROM_BASE + (i * 2));
57 + writew(sprom[i], bus->mmio + bus->sprom_offset + (i * 2));
58 mmiowb();
59 msleep(20);
60 }
61 @@ -621,6 +621,14 @@ static int ssb_pci_sprom_get(struct ssb_
62 int err = -ENOMEM;
63 u16 *buf;
64
65 + if (!ssb_is_sprom_available(bus)) {
66 + ssb_printk(KERN_ERR PFX "No SPROM available!\n");
67 + return -ENODEV;
68 + }
69 +
70 + bus->sprom_offset = (bus->chipco.dev->id.revision < 31) ?
71 + SSB_SPROM_BASE1 : SSB_SPROM_BASE31;
72 +
73 buf = kcalloc(SSB_SPROMSIZE_WORDS_R123, sizeof(u16), GFP_KERNEL);
74 if (!buf)
75 goto out;
76 --- a/drivers/ssb/sprom.c
77 +++ b/drivers/ssb/sprom.c
78 @@ -176,3 +176,17 @@ const struct ssb_sprom *ssb_get_fallback
79 {
80 return fallback_sprom;
81 }
82 +
83 +/* http://bcm-v4.sipsolutions.net/802.11/IsSpromAvailable */
84 +bool ssb_is_sprom_available(struct ssb_bus *bus)
85 +{
86 + /* status register only exists on chipcomon rev >= 11 and we need check
87 + for >= 31 only */
88 + /* this routine differs from specs as we do not access SPROM directly
89 + on PCMCIA */
90 + if (bus->bustype == SSB_BUSTYPE_PCI &&
91 + bus->chipco.dev->id.revision >= 31)
92 + return bus->chipco.capabilities & SSB_CHIPCO_CAP_SPROM;
93 +
94 + return true;
95 +}
96 --- a/include/linux/ssb/ssb.h
97 +++ b/include/linux/ssb/ssb.h
98 @@ -305,6 +305,7 @@ struct ssb_bus {
99 /* ID information about the Chip. */
100 u16 chip_id;
101 u16 chip_rev;
102 + u16 sprom_offset;
103 u16 sprom_size; /* number of words in sprom */
104 u8 chip_package;
105
106 @@ -394,6 +395,9 @@ extern int ssb_bus_sdiobus_register(stru
107
108 extern void ssb_bus_unregister(struct ssb_bus *bus);
109
110 +/* Does the device have an SPROM? */
111 +extern bool ssb_is_sprom_available(struct ssb_bus *bus);
112 +
113 /* Set a fallback SPROM.
114 * See kdoc at the function definition for complete documentation. */
115 extern int ssb_arch_set_fallback_sprom(const struct ssb_sprom *sprom);
116 --- a/include/linux/ssb/ssb_driver_chipcommon.h
117 +++ b/include/linux/ssb/ssb_driver_chipcommon.h
118 @@ -53,6 +53,7 @@
119 #define SSB_CHIPCO_CAP_64BIT 0x08000000 /* 64-bit Backplane */
120 #define SSB_CHIPCO_CAP_PMU 0x10000000 /* PMU available (rev >= 20) */
121 #define SSB_CHIPCO_CAP_ECI 0x20000000 /* ECI available (rev >= 20) */
122 +#define SSB_CHIPCO_CAP_SPROM 0x40000000 /* SPROM present */
123 #define SSB_CHIPCO_CORECTL 0x0008
124 #define SSB_CHIPCO_CORECTL_UARTCLK0 0x00000001 /* Drive UART with internal clock */
125 #define SSB_CHIPCO_CORECTL_SE 0x00000002 /* sync clk out enable (corerev >= 3) */
126 @@ -385,6 +386,7 @@
127
128
129 /** Chip specific Chip-Status register contents. */
130 +#define SSB_CHIPCO_CHST_4322_SPROM_EXISTS 0x00000040 /* SPROM present */
131 #define SSB_CHIPCO_CHST_4325_SPROM_OTP_SEL 0x00000003
132 #define SSB_CHIPCO_CHST_4325_DEFCIS_SEL 0 /* OTP is powered up, use def. CIS, no SPROM */
133 #define SSB_CHIPCO_CHST_4325_SPROM_SEL 1 /* OTP is powered up, SPROM is present */
134 @@ -398,6 +400,18 @@
135 #define SSB_CHIPCO_CHST_4325_RCAL_VALUE_SHIFT 4
136 #define SSB_CHIPCO_CHST_4325_PMUTOP_2B 0x00000200 /* 1 for 2b, 0 for to 2a */
137
138 +/** Macros to determine SPROM presence based on Chip-Status register. */
139 +#define SSB_CHIPCO_CHST_4312_SPROM_PRESENT(status) \
140 + ((status & SSB_CHIPCO_CHST_4325_SPROM_OTP_SEL) != \
141 + SSB_CHIPCO_CHST_4325_OTP_SEL)
142 +#define SSB_CHIPCO_CHST_4322_SPROM_PRESENT(status) \
143 + (status & SSB_CHIPCO_CHST_4322_SPROM_EXISTS)
144 +#define SSB_CHIPCO_CHST_4325_SPROM_PRESENT(status) \
145 + (((status & SSB_CHIPCO_CHST_4325_SPROM_OTP_SEL) != \
146 + SSB_CHIPCO_CHST_4325_DEFCIS_SEL) && \
147 + ((status & SSB_CHIPCO_CHST_4325_SPROM_OTP_SEL) != \
148 + SSB_CHIPCO_CHST_4325_OTP_SEL))
149 +
150
151
152 /** Clockcontrol masks and values **/
153 @@ -564,6 +578,7 @@ struct ssb_chipcommon_pmu {
154 struct ssb_chipcommon {
155 struct ssb_device *dev;
156 u32 capabilities;
157 + u32 status;
158 /* Fast Powerup Delay constant */
159 u16 fast_pwrup_delay;
160 struct ssb_chipcommon_pmu pmu;
161 --- a/include/linux/ssb/ssb_regs.h
162 +++ b/include/linux/ssb/ssb_regs.h
163 @@ -170,26 +170,27 @@
164 #define SSB_SPROMSIZE_WORDS_R4 220
165 #define SSB_SPROMSIZE_BYTES_R123 (SSB_SPROMSIZE_WORDS_R123 * sizeof(u16))
166 #define SSB_SPROMSIZE_BYTES_R4 (SSB_SPROMSIZE_WORDS_R4 * sizeof(u16))
167 -#define SSB_SPROM_BASE 0x1000
168 -#define SSB_SPROM_REVISION 0x107E
169 +#define SSB_SPROM_BASE1 0x1000
170 +#define SSB_SPROM_BASE31 0x0800
171 +#define SSB_SPROM_REVISION 0x007E
172 #define SSB_SPROM_REVISION_REV 0x00FF /* SPROM Revision number */
173 #define SSB_SPROM_REVISION_CRC 0xFF00 /* SPROM CRC8 value */
174 #define SSB_SPROM_REVISION_CRC_SHIFT 8
175
176 /* SPROM Revision 1 */
177 -#define SSB_SPROM1_SPID 0x1004 /* Subsystem Product ID for PCI */
178 -#define SSB_SPROM1_SVID 0x1006 /* Subsystem Vendor ID for PCI */
179 -#define SSB_SPROM1_PID 0x1008 /* Product ID for PCI */
180 -#define SSB_SPROM1_IL0MAC 0x1048 /* 6 bytes MAC address for 802.11b/g */
181 -#define SSB_SPROM1_ET0MAC 0x104E /* 6 bytes MAC address for Ethernet */
182 -#define SSB_SPROM1_ET1MAC 0x1054 /* 6 bytes MAC address for 802.11a */
183 -#define SSB_SPROM1_ETHPHY 0x105A /* Ethernet PHY settings */
184 +#define SSB_SPROM1_SPID 0x0004 /* Subsystem Product ID for PCI */
185 +#define SSB_SPROM1_SVID 0x0006 /* Subsystem Vendor ID for PCI */
186 +#define SSB_SPROM1_PID 0x0008 /* Product ID for PCI */
187 +#define SSB_SPROM1_IL0MAC 0x0048 /* 6 bytes MAC address for 802.11b/g */
188 +#define SSB_SPROM1_ET0MAC 0x004E /* 6 bytes MAC address for Ethernet */
189 +#define SSB_SPROM1_ET1MAC 0x0054 /* 6 bytes MAC address for 802.11a */
190 +#define SSB_SPROM1_ETHPHY 0x005A /* Ethernet PHY settings */
191 #define SSB_SPROM1_ETHPHY_ET0A 0x001F /* MII Address for enet0 */
192 #define SSB_SPROM1_ETHPHY_ET1A 0x03E0 /* MII Address for enet1 */
193 #define SSB_SPROM1_ETHPHY_ET1A_SHIFT 5
194 #define SSB_SPROM1_ETHPHY_ET0M (1<<14) /* MDIO for enet0 */
195 #define SSB_SPROM1_ETHPHY_ET1M (1<<15) /* MDIO for enet1 */
196 -#define SSB_SPROM1_BINF 0x105C /* Board info */
197 +#define SSB_SPROM1_BINF 0x005C /* Board info */
198 #define SSB_SPROM1_BINF_BREV 0x00FF /* Board Revision */
199 #define SSB_SPROM1_BINF_CCODE 0x0F00 /* Country Code */
200 #define SSB_SPROM1_BINF_CCODE_SHIFT 8
201 @@ -197,63 +198,63 @@
202 #define SSB_SPROM1_BINF_ANTBG_SHIFT 12
203 #define SSB_SPROM1_BINF_ANTA 0xC000 /* Available A-PHY antennas */
204 #define SSB_SPROM1_BINF_ANTA_SHIFT 14
205 -#define SSB_SPROM1_PA0B0 0x105E
206 -#define SSB_SPROM1_PA0B1 0x1060
207 -#define SSB_SPROM1_PA0B2 0x1062
208 -#define SSB_SPROM1_GPIOA 0x1064 /* General Purpose IO pins 0 and 1 */
209 +#define SSB_SPROM1_PA0B0 0x005E
210 +#define SSB_SPROM1_PA0B1 0x0060
211 +#define SSB_SPROM1_PA0B2 0x0062
212 +#define SSB_SPROM1_GPIOA 0x0064 /* General Purpose IO pins 0 and 1 */
213 #define SSB_SPROM1_GPIOA_P0 0x00FF /* Pin 0 */
214 #define SSB_SPROM1_GPIOA_P1 0xFF00 /* Pin 1 */
215 #define SSB_SPROM1_GPIOA_P1_SHIFT 8
216 -#define SSB_SPROM1_GPIOB 0x1066 /* General Purpuse IO pins 2 and 3 */
217 +#define SSB_SPROM1_GPIOB 0x0066 /* General Purpuse IO pins 2 and 3 */
218 #define SSB_SPROM1_GPIOB_P2 0x00FF /* Pin 2 */
219 #define SSB_SPROM1_GPIOB_P3 0xFF00 /* Pin 3 */
220 #define SSB_SPROM1_GPIOB_P3_SHIFT 8
221 -#define SSB_SPROM1_MAXPWR 0x1068 /* Power Amplifier Max Power */
222 +#define SSB_SPROM1_MAXPWR 0x0068 /* Power Amplifier Max Power */
223 #define SSB_SPROM1_MAXPWR_BG 0x00FF /* B-PHY and G-PHY (in dBm Q5.2) */
224 #define SSB_SPROM1_MAXPWR_A 0xFF00 /* A-PHY (in dBm Q5.2) */
225 #define SSB_SPROM1_MAXPWR_A_SHIFT 8
226 -#define SSB_SPROM1_PA1B0 0x106A
227 -#define SSB_SPROM1_PA1B1 0x106C
228 -#define SSB_SPROM1_PA1B2 0x106E
229 -#define SSB_SPROM1_ITSSI 0x1070 /* Idle TSSI Target */
230 +#define SSB_SPROM1_PA1B0 0x006A
231 +#define SSB_SPROM1_PA1B1 0x006C
232 +#define SSB_SPROM1_PA1B2 0x006E
233 +#define SSB_SPROM1_ITSSI 0x0070 /* Idle TSSI Target */
234 #define SSB_SPROM1_ITSSI_BG 0x00FF /* B-PHY and G-PHY*/
235 #define SSB_SPROM1_ITSSI_A 0xFF00 /* A-PHY */
236 #define SSB_SPROM1_ITSSI_A_SHIFT 8
237 -#define SSB_SPROM1_BFLLO 0x1072 /* Boardflags (low 16 bits) */
238 -#define SSB_SPROM1_AGAIN 0x1074 /* Antenna Gain (in dBm Q5.2) */
239 +#define SSB_SPROM1_BFLLO 0x0072 /* Boardflags (low 16 bits) */
240 +#define SSB_SPROM1_AGAIN 0x0074 /* Antenna Gain (in dBm Q5.2) */
241 #define SSB_SPROM1_AGAIN_BG 0x00FF /* B-PHY and G-PHY */
242 #define SSB_SPROM1_AGAIN_BG_SHIFT 0
243 #define SSB_SPROM1_AGAIN_A 0xFF00 /* A-PHY */
244 #define SSB_SPROM1_AGAIN_A_SHIFT 8
245
246 /* SPROM Revision 2 (inherits from rev 1) */
247 -#define SSB_SPROM2_BFLHI 0x1038 /* Boardflags (high 16 bits) */
248 -#define SSB_SPROM2_MAXP_A 0x103A /* A-PHY Max Power */
249 +#define SSB_SPROM2_BFLHI 0x0038 /* Boardflags (high 16 bits) */
250 +#define SSB_SPROM2_MAXP_A 0x003A /* A-PHY Max Power */
251 #define SSB_SPROM2_MAXP_A_HI 0x00FF /* Max Power High */
252 #define SSB_SPROM2_MAXP_A_LO 0xFF00 /* Max Power Low */
253 #define SSB_SPROM2_MAXP_A_LO_SHIFT 8
254 -#define SSB_SPROM2_PA1LOB0 0x103C /* A-PHY PowerAmplifier Low Settings */
255 -#define SSB_SPROM2_PA1LOB1 0x103E /* A-PHY PowerAmplifier Low Settings */
256 -#define SSB_SPROM2_PA1LOB2 0x1040 /* A-PHY PowerAmplifier Low Settings */
257 -#define SSB_SPROM2_PA1HIB0 0x1042 /* A-PHY PowerAmplifier High Settings */
258 -#define SSB_SPROM2_PA1HIB1 0x1044 /* A-PHY PowerAmplifier High Settings */
259 -#define SSB_SPROM2_PA1HIB2 0x1046 /* A-PHY PowerAmplifier High Settings */
260 -#define SSB_SPROM2_OPO 0x1078 /* OFDM Power Offset from CCK Level */
261 +#define SSB_SPROM2_PA1LOB0 0x003C /* A-PHY PowerAmplifier Low Settings */
262 +#define SSB_SPROM2_PA1LOB1 0x003E /* A-PHY PowerAmplifier Low Settings */
263 +#define SSB_SPROM2_PA1LOB2 0x0040 /* A-PHY PowerAmplifier Low Settings */
264 +#define SSB_SPROM2_PA1HIB0 0x0042 /* A-PHY PowerAmplifier High Settings */
265 +#define SSB_SPROM2_PA1HIB1 0x0044 /* A-PHY PowerAmplifier High Settings */
266 +#define SSB_SPROM2_PA1HIB2 0x0046 /* A-PHY PowerAmplifier High Settings */
267 +#define SSB_SPROM2_OPO 0x0078 /* OFDM Power Offset from CCK Level */
268 #define SSB_SPROM2_OPO_VALUE 0x00FF
269 #define SSB_SPROM2_OPO_UNUSED 0xFF00
270 -#define SSB_SPROM2_CCODE 0x107C /* Two char Country Code */
271 +#define SSB_SPROM2_CCODE 0x007C /* Two char Country Code */
272
273 /* SPROM Revision 3 (inherits most data from rev 2) */
274 -#define SSB_SPROM3_IL0MAC 0x104A /* 6 bytes MAC address for 802.11b/g */
275 -#define SSB_SPROM3_OFDMAPO 0x102C /* A-PHY OFDM Mid Power Offset (4 bytes, BigEndian) */
276 -#define SSB_SPROM3_OFDMALPO 0x1030 /* A-PHY OFDM Low Power Offset (4 bytes, BigEndian) */
277 -#define SSB_SPROM3_OFDMAHPO 0x1034 /* A-PHY OFDM High Power Offset (4 bytes, BigEndian) */
278 -#define SSB_SPROM3_GPIOLDC 0x1042 /* GPIO LED Powersave Duty Cycle (4 bytes, BigEndian) */
279 +#define SSB_SPROM3_OFDMAPO 0x002C /* A-PHY OFDM Mid Power Offset (4 bytes, BigEndian) */
280 +#define SSB_SPROM3_OFDMALPO 0x0030 /* A-PHY OFDM Low Power Offset (4 bytes, BigEndian) */
281 +#define SSB_SPROM3_OFDMAHPO 0x0034 /* A-PHY OFDM High Power Offset (4 bytes, BigEndian) */
282 +#define SSB_SPROM3_GPIOLDC 0x0042 /* GPIO LED Powersave Duty Cycle (4 bytes, BigEndian) */
283 #define SSB_SPROM3_GPIOLDC_OFF 0x0000FF00 /* Off Count */
284 #define SSB_SPROM3_GPIOLDC_OFF_SHIFT 8
285 #define SSB_SPROM3_GPIOLDC_ON 0x00FF0000 /* On Count */
286 #define SSB_SPROM3_GPIOLDC_ON_SHIFT 16
287 -#define SSB_SPROM3_CCKPO 0x1078 /* CCK Power Offset */
288 +#define SSB_SPROM3_IL0MAC 0x004A /* 6 bytes MAC address for 802.11b/g */
289 +#define SSB_SPROM3_CCKPO 0x0078 /* CCK Power Offset */
290 #define SSB_SPROM3_CCKPO_1M 0x000F /* 1M Rate PO */
291 #define SSB_SPROM3_CCKPO_2M 0x00F0 /* 2M Rate PO */
292 #define SSB_SPROM3_CCKPO_2M_SHIFT 4
293 @@ -264,100 +265,100 @@
294 #define SSB_SPROM3_OFDMGPO 0x107A /* G-PHY OFDM Power Offset (4 bytes, BigEndian) */
295
296 /* SPROM Revision 4 */
297 -#define SSB_SPROM4_IL0MAC 0x104C /* 6 byte MAC address for a/b/g/n */
298 -#define SSB_SPROM4_ETHPHY 0x105A /* Ethernet PHY settings ?? */
299 +#define SSB_SPROM4_BFLLO 0x0044 /* Boardflags (low 16 bits) */
300 +#define SSB_SPROM4_BFLHI 0x0046 /* Board Flags Hi */
301 +#define SSB_SPROM4_IL0MAC 0x004C /* 6 byte MAC address for a/b/g/n */
302 +#define SSB_SPROM4_CCODE 0x0052 /* Country Code (2 bytes) */
303 +#define SSB_SPROM4_GPIOA 0x0056 /* Gen. Purpose IO # 0 and 1 */
304 +#define SSB_SPROM4_GPIOA_P0 0x00FF /* Pin 0 */
305 +#define SSB_SPROM4_GPIOA_P1 0xFF00 /* Pin 1 */
306 +#define SSB_SPROM4_GPIOA_P1_SHIFT 8
307 +#define SSB_SPROM4_GPIOB 0x0058 /* Gen. Purpose IO # 2 and 3 */
308 +#define SSB_SPROM4_GPIOB_P2 0x00FF /* Pin 2 */
309 +#define SSB_SPROM4_GPIOB_P3 0xFF00 /* Pin 3 */
310 +#define SSB_SPROM4_GPIOB_P3_SHIFT 8
311 +#define SSB_SPROM4_ETHPHY 0x005A /* Ethernet PHY settings ?? */
312 #define SSB_SPROM4_ETHPHY_ET0A 0x001F /* MII Address for enet0 */
313 #define SSB_SPROM4_ETHPHY_ET1A 0x03E0 /* MII Address for enet1 */
314 #define SSB_SPROM4_ETHPHY_ET1A_SHIFT 5
315 #define SSB_SPROM4_ETHPHY_ET0M (1<<14) /* MDIO for enet0 */
316 #define SSB_SPROM4_ETHPHY_ET1M (1<<15) /* MDIO for enet1 */
317 -#define SSB_SPROM4_CCODE 0x1052 /* Country Code (2 bytes) */
318 -#define SSB_SPROM4_ANTAVAIL 0x105D /* Antenna available bitfields */
319 -#define SSB_SPROM4_ANTAVAIL_A 0x00FF /* A-PHY bitfield */
320 -#define SSB_SPROM4_ANTAVAIL_A_SHIFT 0
321 -#define SSB_SPROM4_ANTAVAIL_BG 0xFF00 /* B-PHY and G-PHY bitfield */
322 -#define SSB_SPROM4_ANTAVAIL_BG_SHIFT 8
323 -#define SSB_SPROM4_BFLLO 0x1044 /* Boardflags (low 16 bits) */
324 -#define SSB_SPROM4_AGAIN01 0x105E /* Antenna Gain (in dBm Q5.2) */
325 +#define SSB_SPROM4_ANTAVAIL 0x005D /* Antenna available bitfields */
326 +#define SSB_SPROM4_ANTAVAIL_A 0x00FF /* A-PHY bitfield */
327 +#define SSB_SPROM4_ANTAVAIL_A_SHIFT 0
328 +#define SSB_SPROM4_ANTAVAIL_BG 0xFF00 /* B-PHY and G-PHY bitfield */
329 +#define SSB_SPROM4_ANTAVAIL_BG_SHIFT 8
330 +#define SSB_SPROM4_AGAIN01 0x005E /* Antenna Gain (in dBm Q5.2) */
331 #define SSB_SPROM4_AGAIN0 0x00FF /* Antenna 0 */
332 #define SSB_SPROM4_AGAIN0_SHIFT 0
333 #define SSB_SPROM4_AGAIN1 0xFF00 /* Antenna 1 */
334 #define SSB_SPROM4_AGAIN1_SHIFT 8
335 -#define SSB_SPROM4_AGAIN23 0x1060
336 +#define SSB_SPROM4_AGAIN23 0x0060
337 #define SSB_SPROM4_AGAIN2 0x00FF /* Antenna 2 */
338 #define SSB_SPROM4_AGAIN2_SHIFT 0
339 #define SSB_SPROM4_AGAIN3 0xFF00 /* Antenna 3 */
340 #define SSB_SPROM4_AGAIN3_SHIFT 8
341 -#define SSB_SPROM4_BFLHI 0x1046 /* Board Flags Hi */
342 -#define SSB_SPROM4_MAXP_BG 0x1080 /* Max Power BG in path 1 */
343 +#define SSB_SPROM4_MAXP_BG 0x0080 /* Max Power BG in path 1 */
344 #define SSB_SPROM4_MAXP_BG_MASK 0x00FF /* Mask for Max Power BG */
345 #define SSB_SPROM4_ITSSI_BG 0xFF00 /* Mask for path 1 itssi_bg */
346 #define SSB_SPROM4_ITSSI_BG_SHIFT 8
347 -#define SSB_SPROM4_MAXP_A 0x108A /* Max Power A in path 1 */
348 +#define SSB_SPROM4_MAXP_A 0x008A /* Max Power A in path 1 */
349 #define SSB_SPROM4_MAXP_A_MASK 0x00FF /* Mask for Max Power A */
350 #define SSB_SPROM4_ITSSI_A 0xFF00 /* Mask for path 1 itssi_a */
351 #define SSB_SPROM4_ITSSI_A_SHIFT 8
352 -#define SSB_SPROM4_GPIOA 0x1056 /* Gen. Purpose IO # 0 and 1 */
353 -#define SSB_SPROM4_GPIOA_P0 0x00FF /* Pin 0 */
354 -#define SSB_SPROM4_GPIOA_P1 0xFF00 /* Pin 1 */
355 -#define SSB_SPROM4_GPIOA_P1_SHIFT 8
356 -#define SSB_SPROM4_GPIOB 0x1058 /* Gen. Purpose IO # 2 and 3 */
357 -#define SSB_SPROM4_GPIOB_P2 0x00FF /* Pin 2 */
358 -#define SSB_SPROM4_GPIOB_P3 0xFF00 /* Pin 3 */
359 -#define SSB_SPROM4_GPIOB_P3_SHIFT 8
360 -#define SSB_SPROM4_PA0B0 0x1082 /* The paXbY locations are */
361 -#define SSB_SPROM4_PA0B1 0x1084 /* only guesses */
362 -#define SSB_SPROM4_PA0B2 0x1086
363 -#define SSB_SPROM4_PA1B0 0x108E
364 -#define SSB_SPROM4_PA1B1 0x1090
365 -#define SSB_SPROM4_PA1B2 0x1092
366 +#define SSB_SPROM4_PA0B0 0x0082 /* The paXbY locations are */
367 +#define SSB_SPROM4_PA0B1 0x0084 /* only guesses */
368 +#define SSB_SPROM4_PA0B2 0x0086
369 +#define SSB_SPROM4_PA1B0 0x008E
370 +#define SSB_SPROM4_PA1B1 0x0090
371 +#define SSB_SPROM4_PA1B2 0x0092
372
373 /* SPROM Revision 5 (inherits most data from rev 4) */
374 -#define SSB_SPROM5_BFLLO 0x104A /* Boardflags (low 16 bits) */
375 -#define SSB_SPROM5_BFLHI 0x104C /* Board Flags Hi */
376 -#define SSB_SPROM5_IL0MAC 0x1052 /* 6 byte MAC address for a/b/g/n */
377 -#define SSB_SPROM5_CCODE 0x1044 /* Country Code (2 bytes) */
378 -#define SSB_SPROM5_GPIOA 0x1076 /* Gen. Purpose IO # 0 and 1 */
379 +#define SSB_SPROM5_CCODE 0x0044 /* Country Code (2 bytes) */
380 +#define SSB_SPROM5_BFLLO 0x004A /* Boardflags (low 16 bits) */
381 +#define SSB_SPROM5_BFLHI 0x004C /* Board Flags Hi */
382 +#define SSB_SPROM5_IL0MAC 0x0052 /* 6 byte MAC address for a/b/g/n */
383 +#define SSB_SPROM5_GPIOA 0x0076 /* Gen. Purpose IO # 0 and 1 */
384 #define SSB_SPROM5_GPIOA_P0 0x00FF /* Pin 0 */
385 #define SSB_SPROM5_GPIOA_P1 0xFF00 /* Pin 1 */
386 #define SSB_SPROM5_GPIOA_P1_SHIFT 8
387 -#define SSB_SPROM5_GPIOB 0x1078 /* Gen. Purpose IO # 2 and 3 */
388 +#define SSB_SPROM5_GPIOB 0x0078 /* Gen. Purpose IO # 2 and 3 */
389 #define SSB_SPROM5_GPIOB_P2 0x00FF /* Pin 2 */
390 #define SSB_SPROM5_GPIOB_P3 0xFF00 /* Pin 3 */
391 #define SSB_SPROM5_GPIOB_P3_SHIFT 8
392
393 /* SPROM Revision 8 */
394 -#define SSB_SPROM8_BOARDREV 0x1082 /* Board revision */
395 -#define SSB_SPROM8_BFLLO 0x1084 /* Board flags (bits 0-15) */
396 -#define SSB_SPROM8_BFLHI 0x1086 /* Board flags (bits 16-31) */
397 -#define SSB_SPROM8_BFL2LO 0x1088 /* Board flags (bits 32-47) */
398 -#define SSB_SPROM8_BFL2HI 0x108A /* Board flags (bits 48-63) */
399 -#define SSB_SPROM8_IL0MAC 0x108C /* 6 byte MAC address */
400 -#define SSB_SPROM8_CCODE 0x1092 /* 2 byte country code */
401 -#define SSB_SPROM8_ANTAVAIL 0x109C /* Antenna available bitfields*/
402 -#define SSB_SPROM8_ANTAVAIL_A 0xFF00 /* A-PHY bitfield */
403 -#define SSB_SPROM8_ANTAVAIL_A_SHIFT 8
404 -#define SSB_SPROM8_ANTAVAIL_BG 0x00FF /* B-PHY and G-PHY bitfield */
405 -#define SSB_SPROM8_ANTAVAIL_BG_SHIFT 0
406 -#define SSB_SPROM8_AGAIN01 0x109E /* Antenna Gain (in dBm Q5.2) */
407 +#define SSB_SPROM8_BOARDREV 0x0082 /* Board revision */
408 +#define SSB_SPROM8_BFLLO 0x0084 /* Board flags (bits 0-15) */
409 +#define SSB_SPROM8_BFLHI 0x0086 /* Board flags (bits 16-31) */
410 +#define SSB_SPROM8_BFL2LO 0x0088 /* Board flags (bits 32-47) */
411 +#define SSB_SPROM8_BFL2HI 0x008A /* Board flags (bits 48-63) */
412 +#define SSB_SPROM8_IL0MAC 0x008C /* 6 byte MAC address */
413 +#define SSB_SPROM8_CCODE 0x0092 /* 2 byte country code */
414 +#define SSB_SPROM8_GPIOA 0x0096 /*Gen. Purpose IO # 0 and 1 */
415 +#define SSB_SPROM8_GPIOA_P0 0x00FF /* Pin 0 */
416 +#define SSB_SPROM8_GPIOA_P1 0xFF00 /* Pin 1 */
417 +#define SSB_SPROM8_GPIOA_P1_SHIFT 8
418 +#define SSB_SPROM8_GPIOB 0x0098 /* Gen. Purpose IO # 2 and 3 */
419 +#define SSB_SPROM8_GPIOB_P2 0x00FF /* Pin 2 */
420 +#define SSB_SPROM8_GPIOB_P3 0xFF00 /* Pin 3 */
421 +#define SSB_SPROM8_GPIOB_P3_SHIFT 8
422 +#define SSB_SPROM8_ANTAVAIL 0x009C /* Antenna available bitfields*/
423 +#define SSB_SPROM8_ANTAVAIL_A 0xFF00 /* A-PHY bitfield */
424 +#define SSB_SPROM8_ANTAVAIL_A_SHIFT 8
425 +#define SSB_SPROM8_ANTAVAIL_BG 0x00FF /* B-PHY and G-PHY bitfield */
426 +#define SSB_SPROM8_ANTAVAIL_BG_SHIFT 0
427 +#define SSB_SPROM8_AGAIN01 0x009E /* Antenna Gain (in dBm Q5.2) */
428 #define SSB_SPROM8_AGAIN0 0x00FF /* Antenna 0 */
429 #define SSB_SPROM8_AGAIN0_SHIFT 0
430 #define SSB_SPROM8_AGAIN1 0xFF00 /* Antenna 1 */
431 #define SSB_SPROM8_AGAIN1_SHIFT 8
432 -#define SSB_SPROM8_AGAIN23 0x10A0
433 +#define SSB_SPROM8_AGAIN23 0x00A0
434 #define SSB_SPROM8_AGAIN2 0x00FF /* Antenna 2 */
435 #define SSB_SPROM8_AGAIN2_SHIFT 0
436 #define SSB_SPROM8_AGAIN3 0xFF00 /* Antenna 3 */
437 #define SSB_SPROM8_AGAIN3_SHIFT 8
438 -#define SSB_SPROM8_GPIOA 0x1096 /*Gen. Purpose IO # 0 and 1 */
439 -#define SSB_SPROM8_GPIOA_P0 0x00FF /* Pin 0 */
440 -#define SSB_SPROM8_GPIOA_P1 0xFF00 /* Pin 1 */
441 -#define SSB_SPROM8_GPIOA_P1_SHIFT 8
442 -#define SSB_SPROM8_GPIOB 0x1098 /* Gen. Purpose IO # 2 and 3 */
443 -#define SSB_SPROM8_GPIOB_P2 0x00FF /* Pin 2 */
444 -#define SSB_SPROM8_GPIOB_P3 0xFF00 /* Pin 3 */
445 -#define SSB_SPROM8_GPIOB_P3_SHIFT 8
446 -#define SSB_SPROM8_RSSIPARM2G 0x10A4 /* RSSI params for 2GHz */
447 +#define SSB_SPROM8_RSSIPARM2G 0x00A4 /* RSSI params for 2GHz */
448 #define SSB_SPROM8_RSSISMF2G 0x000F
449 #define SSB_SPROM8_RSSISMC2G 0x00F0
450 #define SSB_SPROM8_RSSISMC2G_SHIFT 4
451 @@ -365,7 +366,7 @@
452 #define SSB_SPROM8_RSSISAV2G_SHIFT 8
453 #define SSB_SPROM8_BXA2G 0x1800
454 #define SSB_SPROM8_BXA2G_SHIFT 11
455 -#define SSB_SPROM8_RSSIPARM5G 0x10A6 /* RSSI params for 5GHz */
456 +#define SSB_SPROM8_RSSIPARM5G 0x00A6 /* RSSI params for 5GHz */
457 #define SSB_SPROM8_RSSISMF5G 0x000F
458 #define SSB_SPROM8_RSSISMC5G 0x00F0
459 #define SSB_SPROM8_RSSISMC5G_SHIFT 4
460 @@ -373,47 +374,47 @@
461 #define SSB_SPROM8_RSSISAV5G_SHIFT 8
462 #define SSB_SPROM8_BXA5G 0x1800
463 #define SSB_SPROM8_BXA5G_SHIFT 11
464 -#define SSB_SPROM8_TRI25G 0x10A8 /* TX isolation 2.4&5.3GHz */
465 +#define SSB_SPROM8_TRI25G 0x00A8 /* TX isolation 2.4&5.3GHz */
466 #define SSB_SPROM8_TRI2G 0x00FF /* TX isolation 2.4GHz */
467 #define SSB_SPROM8_TRI5G 0xFF00 /* TX isolation 5.3GHz */
468 #define SSB_SPROM8_TRI5G_SHIFT 8
469 -#define SSB_SPROM8_TRI5GHL 0x10AA /* TX isolation 5.2/5.8GHz */
470 +#define SSB_SPROM8_TRI5GHL 0x00AA /* TX isolation 5.2/5.8GHz */
471 #define SSB_SPROM8_TRI5GL 0x00FF /* TX isolation 5.2GHz */
472 #define SSB_SPROM8_TRI5GH 0xFF00 /* TX isolation 5.8GHz */
473 #define SSB_SPROM8_TRI5GH_SHIFT 8
474 -#define SSB_SPROM8_RXPO 0x10AC /* RX power offsets */
475 +#define SSB_SPROM8_RXPO 0x00AC /* RX power offsets */
476 #define SSB_SPROM8_RXPO2G 0x00FF /* 2GHz RX power offset */
477 #define SSB_SPROM8_RXPO5G 0xFF00 /* 5GHz RX power offset */
478 #define SSB_SPROM8_RXPO5G_SHIFT 8
479 -#define SSB_SPROM8_MAXP_BG 0x10C0 /* Max Power 2GHz in path 1 */
480 +#define SSB_SPROM8_MAXP_BG 0x00C0 /* Max Power 2GHz in path 1 */
481 #define SSB_SPROM8_MAXP_BG_MASK 0x00FF /* Mask for Max Power 2GHz */
482 #define SSB_SPROM8_ITSSI_BG 0xFF00 /* Mask for path 1 itssi_bg */
483 #define SSB_SPROM8_ITSSI_BG_SHIFT 8
484 -#define SSB_SPROM8_PA0B0 0x10C2 /* 2GHz power amp settings */
485 -#define SSB_SPROM8_PA0B1 0x10C4
486 -#define SSB_SPROM8_PA0B2 0x10C6
487 -#define SSB_SPROM8_MAXP_A 0x10C8 /* Max Power 5.3GHz */
488 +#define SSB_SPROM8_PA0B0 0x00C2 /* 2GHz power amp settings */
489 +#define SSB_SPROM8_PA0B1 0x00C4
490 +#define SSB_SPROM8_PA0B2 0x00C6
491 +#define SSB_SPROM8_MAXP_A 0x00C8 /* Max Power 5.3GHz */
492 #define SSB_SPROM8_MAXP_A_MASK 0x00FF /* Mask for Max Power 5.3GHz */
493 #define SSB_SPROM8_ITSSI_A 0xFF00 /* Mask for path 1 itssi_a */
494 #define SSB_SPROM8_ITSSI_A_SHIFT 8
495 -#define SSB_SPROM8_MAXP_AHL 0x10CA /* Max Power 5.2/5.8GHz */
496 +#define SSB_SPROM8_MAXP_AHL 0x00CA /* Max Power 5.2/5.8GHz */
497 #define SSB_SPROM8_MAXP_AH_MASK 0x00FF /* Mask for Max Power 5.8GHz */
498 #define SSB_SPROM8_MAXP_AL_MASK 0xFF00 /* Mask for Max Power 5.2GHz */
499 #define SSB_SPROM8_MAXP_AL_SHIFT 8
500 -#define SSB_SPROM8_PA1B0 0x10CC /* 5.3GHz power amp settings */
501 -#define SSB_SPROM8_PA1B1 0x10CE
502 -#define SSB_SPROM8_PA1B2 0x10D0
503 -#define SSB_SPROM8_PA1LOB0 0x10D2 /* 5.2GHz power amp settings */
504 -#define SSB_SPROM8_PA1LOB1 0x10D4
505 -#define SSB_SPROM8_PA1LOB2 0x10D6
506 -#define SSB_SPROM8_PA1HIB0 0x10D8 /* 5.8GHz power amp settings */
507 -#define SSB_SPROM8_PA1HIB1 0x10DA
508 -#define SSB_SPROM8_PA1HIB2 0x10DC
509 -#define SSB_SPROM8_CCK2GPO 0x1140 /* CCK power offset */
510 -#define SSB_SPROM8_OFDM2GPO 0x1142 /* 2.4GHz OFDM power offset */
511 -#define SSB_SPROM8_OFDM5GPO 0x1146 /* 5.3GHz OFDM power offset */
512 -#define SSB_SPROM8_OFDM5GLPO 0x114A /* 5.2GHz OFDM power offset */
513 -#define SSB_SPROM8_OFDM5GHPO 0x114E /* 5.8GHz OFDM power offset */
514 +#define SSB_SPROM8_PA1B0 0x00CC /* 5.3GHz power amp settings */
515 +#define SSB_SPROM8_PA1B1 0x00CE
516 +#define SSB_SPROM8_PA1B2 0x00D0
517 +#define SSB_SPROM8_PA1LOB0 0x00D2 /* 5.2GHz power amp settings */
518 +#define SSB_SPROM8_PA1LOB1 0x00D4
519 +#define SSB_SPROM8_PA1LOB2 0x00D6
520 +#define SSB_SPROM8_PA1HIB0 0x00D8 /* 5.8GHz power amp settings */
521 +#define SSB_SPROM8_PA1HIB1 0x00DA
522 +#define SSB_SPROM8_PA1HIB2 0x00DC
523 +#define SSB_SPROM8_CCK2GPO 0x0140 /* CCK power offset */
524 +#define SSB_SPROM8_OFDM2GPO 0x0142 /* 2.4GHz OFDM power offset */
525 +#define SSB_SPROM8_OFDM5GPO 0x0146 /* 5.3GHz OFDM power offset */
526 +#define SSB_SPROM8_OFDM5GLPO 0x014A /* 5.2GHz OFDM power offset */
527 +#define SSB_SPROM8_OFDM5GHPO 0x014E /* 5.8GHz OFDM power offset */
528
529 /* Values for SSB_SPROM1_BINF_CCODE */
530 enum {
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