target/linux/ubicom32/files/drivers/mtd/devices/nand-spi-er.c

   1 /*
   2  * Micron SPI-ER NAND Flash Memory
   3  *
   4  * (C) Copyright 2009, Ubicom, Inc.
   5  *
   6  * This file is part of the Ubicom32 Linux Kernel Port.
   7  *
   8  * The Ubicom32 Linux Kernel Port is free software: you can redistribute
   9  * it and/or modify it under the terms of the GNU General Public License
  10  * as published by the Free Software Foundation, either version 2 of the
  11  * License, or (at your option) any later version.
  12  *
  13  * The Ubicom32 Linux Kernel Port is distributed in the hope that it
  14  * will be useful, but WITHOUT ANY WARRANTY; without even the implied
  15  * warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See
  16  * the GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with the Ubicom32 Linux Kernel Port.  If not,
  20  * see <http://www.gnu.org/licenses/>.
  21 */
  22 #include <linux/module.h>
  23 #include <linux/init.h>
  24 #include <linux/slab.h>
  25 #include <linux/delay.h>
  26 #include <linux/device.h>
  27 #include <linux/mutex.h>
  28 #include <linux/err.h>
  29
  30 #include <linux/spi/spi.h>
  31 #include <linux/spi/flash.h>
  32
  33 #include <linux/mtd/mtd.h>
  34 #include <linux/mtd/partitions.h>
  35
  36 #define NAND_SPI_ER_BLOCK_FROM_ROW(row)         (row >> 6)
  37
  38 #define NAND_SPI_ER_STATUS_P_FAIL               (1 << 3)
  39 #define NAND_SPI_ER_STATUS_E_FAIL               (1 << 2)
  40 #define NAND_SPI_ER_STATUS_OIP                  (1 << 0)
  41
  42 #define NAND_SPI_ER_LAST_ROW_INVALID            0xFFFFFFFF
  43 #define NAND_SPI_ER_BAD_BLOCK_MARK_OFFSET       0x08
  44
  45 struct nand_spi_er_device {
  46         const char              *name;
  47
  48         uint8_t                 id0;
  49         uint8_t                 id1;
  50
  51         unsigned int            blocks;
  52         unsigned int            pages_per_block;
  53         unsigned int            page_size;
  54         unsigned int            write_size;
  55         unsigned int            erase_size;
  56 };
  57
  58 struct nand_spi_er {
  59         char                            name[24];
  60
  61         const struct nand_spi_er_device *device;
  62
  63         struct mutex                    lock;
  64         struct spi_device               *spi;
  65
  66         struct mtd_info                 mtd;
  67
  68         unsigned int                    last_row;       /* the last row we fetched */
  69
  70         /*
  71          * Bad block table (MUST be last in strcuture)
  72          */
  73         unsigned long                   nbb;
  74         unsigned long                   bbt[0];
  75 };
  76
  77 const struct nand_spi_er_device nand_spi_er_devices[] = {
  78         {
  79                 name:                   "MT29F1G01ZDC",
  80                 id0:                    0x2C,
  81                 id1:                    0x12,
  82                 blocks:                 1024,
  83                 pages_per_block:        64,
  84                 page_size:              2048,
  85                 write_size:             512,
  86                 erase_size:             64 * 2048,
  87         },
  88         {
  89                 name:                   "MT29F1G01ZDC",
  90                 id0:                    0x2C,
  91                 id1:                    0x13,
  92                 blocks:                 1024,
  93                 pages_per_block:        64,
  94                 page_size:              2048,
  95                 write_size:             512,
  96                 erase_size:             64 * 2048,
  97         },
  98 };
  99
 100 static int read_only = 0;
 101 module_param(read_only, int, 0);
 102 MODULE_PARM_DESC(read_only, "Leave device locked");
 103
 104 /*
 105  * nand_spi_er_get_feature
 106  *      Get Feature register
 107  */
 108 static int nand_spi_er_get_feature(struct nand_spi_er *chip, int reg, uint8_t *data)
 109 {
 110         uint8_t txbuf[2];
 111         uint8_t rxbuf[1];
 112         int res;
 113
 114         txbuf[0] = 0x0F;
 115         txbuf[1] = reg;
 116         res = spi_write_then_read(chip->spi, txbuf, 2, rxbuf, 1);
 117         if (res) {
 118                 DEBUG(MTD_DEBUG_LEVEL1, "%s: failed get feature res=%d\n", chip->name, res);
 119                 return res;
 120         }
 121         *data = rxbuf[0];
 122         return 0;
 123 }
 124
 125 /*
 126  * nand_spi_er_busywait
 127  *      Wait until the chip is not busy
 128  */
 129 static int nand_spi_er_busywait(struct nand_spi_er *chip, uint8_t *data)
 130 {
 131         int i;
 132
 133         for (i = 0; i < 100; i++) {
 134                 int res = nand_spi_er_get_feature(chip, 0xC0, data);
 135                 if (res) {
 136                         return res;
 137                 }
 138                 if (!(*data & NAND_SPI_ER_STATUS_OIP)) {
 139                         break;
 140                 }
 141         }
 142
 143         return 0;
 144 }
 145
 146 /*
 147  * nand_spi_er_erase
 148  *      Erase a block, parameters must be block aligned
 149  */
 150 static int nand_spi_er_erase(struct mtd_info *mtd, struct erase_info *instr)
 151 {
 152         struct nand_spi_er *chip = mtd->priv;
 153         struct spi_device *spi = chip->spi;
 154         uint8_t txbuf[4];
 155         int res;
 156
 157         DEBUG(MTD_DEBUG_LEVEL3, "%s: erase addr:%x len:%x\n", chip->name, instr->addr, instr->len);
 158
 159         if ((instr->addr + instr->len) > mtd->size) {
 160                 return -EINVAL;
 161         }
 162
 163         if (instr->addr & (chip->device->erase_size - 1)) {
 164                 DEBUG(MTD_DEBUG_LEVEL1, "%s: erase address is not aligned %x\n", chip->name, instr->addr);
 165                 return -EINVAL;
 166         }
 167
 168         if (instr->len & (chip->device->erase_size - 1)) {
 169                 DEBUG(MTD_DEBUG_LEVEL1, "%s: erase len is not aligned %x\n", chip->name, instr->len);
 170                 return -EINVAL;
 171         }
 172
 173         mutex_lock(&chip->lock);
 174         chip->last_row = NAND_SPI_ER_LAST_ROW_INVALID;
 175
 176         while (instr->len) {
 177                 uint32_t block = instr->addr >> 17;
 178                 uint32_t row = block << 6;
 179                 uint8_t stat;
 180                 DEBUG(MTD_DEBUG_LEVEL3, "%s: block erase row:%x block:%x addr:%x rem:%x\n", chip->name, row, block, instr->addr, instr->len);
 181
 182                 /*
 183                  * Write enable
 184                  */
 185                 txbuf[0] = 0x06;
 186                 res = spi_write(spi, txbuf, 1);
 187                 if (res) {
 188                         DEBUG(MTD_DEBUG_LEVEL1, "%s: failed write enable res=%d\n", chip->name, res);
 189                         mutex_unlock(&chip->lock);
 190                         return res;
 191                 }
 192
 193                 /*
 194                  * Test for bad block
 195                  */
 196                 if (test_bit(block, chip->bbt)) {
 197                         instr->fail_addr = block << 17;
 198                         instr->state = MTD_ERASE_FAILED;
 199                         res = -EBADMSG;
 200                         goto done;
 201                 }
 202
 203                 /*
 204                  * Block erase
 205                  */
 206                 txbuf[0] = 0xD8;
 207                 txbuf[1] = 0x00;
 208                 txbuf[2] = row >> 8;
 209                 txbuf[3] = row & 0xFF;
 210                 res = spi_write(spi, txbuf, 4);
 211                 if (res) {
 212                         DEBUG(MTD_DEBUG_LEVEL1, "%s: failed block erase res=%d\n", chip->name, res);
 213                         instr->fail_addr = block << 17;
 214                         instr->state = MTD_ERASE_FAILED;
 215                         goto done;
 216                 }
 217
 218                 /*
 219                  * Wait
 220                  */
 221                 res = nand_spi_er_busywait(chip, &stat);
 222                 if (res || (stat & NAND_SPI_ER_STATUS_OIP)) {
 223                         instr->fail_addr = block << 17;
 224                         instr->state = MTD_ERASE_FAILED;
 225                         DEBUG(MTD_DEBUG_LEVEL1, "%s: chip is busy or nonresponsive res=%d stat=%02x\n", chip->name, res, stat);
 226                         if (res) {
 227                                 goto done;
 228                         }
 229
 230                         /*
 231                          * Chip is stuck?
 232                          */
 233                         res = -EIO;
 234                         goto done;
 235                 }
 236
 237                 /*
 238                  * Check the status register
 239                  */
 240                 if (stat & NAND_SPI_ER_STATUS_E_FAIL) {
 241                         DEBUG(MTD_DEBUG_LEVEL1, "%s: E_FAIL signalled (%02x)\n", chip->name, stat);
 242                         instr->fail_addr = block << 17;
 243                         instr->state = MTD_ERASE_FAILED;
 244                         goto done;
 245                 }
 246
 247                 /*
 248                  * Next
 249                  */
 250                 block++;
 251                 instr->len -= chip->device->erase_size;
 252                 instr->addr += chip->device->erase_size;
 253         }
 254
 255         instr->state = MTD_ERASE_DONE;
 256
 257         mutex_unlock(&chip->lock);
 258         return 0;
 259
 260 done:
 261         /*
 262          * Write disable
 263          */
 264         txbuf[0] = 0x04;
 265         res = spi_write(spi, txbuf, 1);
 266         if (res) {
 267                 DEBUG(MTD_DEBUG_LEVEL1, "%s: failed write disable res=%d\n", chip->name, res);
 268         }
 269
 270         mutex_unlock(&chip->lock);
 271
 272         mtd_erase_callback(instr);
 273         return 0;
 274 }
 275
 276 /*
 277  * nand_spi_er_read
 278  *
 279  * return -EUCLEAN: ecc error recovered
 280  * return -EBADMSG: ecc error not recovered
 281 */
 282 static int nand_spi_er_read(struct mtd_info *mtd, loff_t from, size_t len,
 283                                size_t *retlen, u_char *buf)
 284 {
 285         struct nand_spi_er *chip = mtd->priv;
 286         struct spi_device *spi = chip->spi;
 287
 288         uint32_t row;
 289         uint32_t column;
 290         int retval = 0;
 291
 292         *retlen = 0;
 293         DEBUG(MTD_DEBUG_LEVEL2, "%s: read block from %llx len %d into %p\n", chip->name, from, len, buf);
 294
 295         /*
 296          * Zero length reads, nothing to do
 297          */
 298         if (len == 0) {
 299                 return 0;
 300         }
 301
 302         /*
 303          * Reject reads which go over the end of the flash
 304          */
 305         if ((from + len) > mtd->size) {
 306                 return -EINVAL;
 307         }
 308
 309         /*
 310          * Get the row and column address to start at
 311          */
 312         row = from >> 11;
 313         column = from & 0x7FF;
 314         DEBUG(MTD_DEBUG_LEVEL3, "%s: row=%x %d column=%x %d last_row=%x %d\n", chip->name, row, row, column, column, chip->last_row, chip->last_row);
 315
 316         /*
 317          * Read the data from the chip
 318          */
 319         mutex_lock(&chip->lock);
 320         while (len) {
 321                 uint8_t stat;
 322                 uint8_t txbuf[4];
 323                 struct spi_message message;
 324                 struct spi_transfer x[2];
 325                 int res;
 326                 size_t toread;
 327
 328                 /*
 329                  * Figure out how much to read
 330                  *
 331                  * If we are reading from the middle of a page then the most we
 332                  * can read is to the end of the page
 333                  */
 334                 toread = len;
 335                 if (toread > (chip->device->page_size - column)) {
 336                         toread = chip->device->page_size - column;
 337                 }
 338
 339                 DEBUG(MTD_DEBUG_LEVEL3, "%s: buf=%p toread=%x row=%x column=%x last_row=%x\n", chip->name, buf, toread, row, column, chip->last_row);
 340
 341                 if (chip->last_row != row) {
 342                         /*
 343                          * Check if the block is bad
 344                          */
 345                         if (test_bit(NAND_SPI_ER_BLOCK_FROM_ROW(row), chip->bbt)) {
 346                                 mutex_unlock(&chip->lock);
 347                                 return -EBADMSG;
 348                         }
 349
 350                         /*
 351                          * Load the appropriate page
 352                          */
 353                         txbuf[0] = 0x13;
 354                         txbuf[1] = 0x00;
 355                         txbuf[2] = row >> 8;
 356                         txbuf[3] = row & 0xFF;
 357                         res = spi_write(spi, txbuf, 4);
 358                         if (res) {
 359                                 DEBUG(MTD_DEBUG_LEVEL1, "%s: failed page load res=%d\n", chip->name, res);
 360                                 mutex_unlock(&chip->lock);
 361                                 return res;
 362                         }
 363
 364                         /*
 365                          * Wait
 366                          */
 367                         res = nand_spi_er_busywait(chip, &stat);
 368                         if (res || (stat & NAND_SPI_ER_STATUS_OIP)) {
 369                                 DEBUG(MTD_DEBUG_LEVEL1, "%s: chip is busy or nonresponsive res=%d stat=%02x\n", chip->name, res, stat);
 370                                 if (res) {
 371                                         mutex_unlock(&chip->lock);
 372                                         return res;
 373                                 }
 374
 375                                 /*
 376                                  * Chip is stuck?
 377                                  */
 378                                 mutex_unlock(&chip->lock);
 379                                 return -EIO;
 380                         }
 381
 382                         /*
 383                          * Check the ECC bits
 384                          */
 385                         stat >>= 4;
 386                         if (stat == 1) {
 387                                 DEBUG(MTD_DEBUG_LEVEL1, "%s: ECC recovered, row=%x\n", chip->name, row);
 388                                 retval = -EUCLEAN;
 389                         }
 390                         if (stat == 2) {
 391                                 DEBUG(MTD_DEBUG_LEVEL0, "%s: failed ECC, row=%x\n", chip->name, row);
 392                                 chip->last_row = NAND_SPI_ER_LAST_ROW_INVALID;
 393                                 mutex_unlock(&chip->lock);
 394                                 return -EBADMSG;
 395                         }
 396
 397                 }
 398
 399                 chip->last_row = row;
 400
 401                 /*
 402                  * Read out the data
 403                  */
 404                 spi_message_init(&message);
 405                 memset(x, 0, sizeof(x));
 406
 407                 txbuf[0] = 0x03;
 408                 txbuf[1] = column >> 8;
 409                 txbuf[2] = column & 0xFF;
 410                 txbuf[3] = 0;
 411                 x[0].tx_buf = txbuf;
 412                 x[0].len = 4;
 413                 spi_message_add_tail(&x[0], &message);
 414
 415                 x[1].rx_buf = buf;
 416                 x[1].len = toread;
 417                 spi_message_add_tail(&x[1], &message);
 418
 419                 res = spi_sync(spi, &message);
 420                 if (res) {
 421                         DEBUG(MTD_DEBUG_LEVEL1, "%s: failed data read res=%d\n", chip->name, res);
 422                         mutex_unlock(&chip->lock);
 423                         return res;
 424                 }
 425                 buf += toread;
 426                 len -= toread;
 427                 *retlen += toread;
 428
 429                 /*
 430                  * For the next page, increment the row and always start at column 0
 431                  */
 432                 column = 0;
 433                 row++;
 434         }
 435
 436         mutex_unlock(&chip->lock);
 437         return retval;
 438 }
 439
 440 /*
 441  * nand_spi_er_write
 442  */
 443 #define NOT_ALIGNED(x) ((x & (device->write_size - 1)) != 0)
 444 static int nand_spi_er_write(struct mtd_info *mtd, loff_t to, size_t len,
 445                                 size_t *retlen, const u_char *buf)
 446 {
 447         struct nand_spi_er *chip = mtd->priv;
 448         struct spi_device *spi = chip->spi;
 449         const struct nand_spi_er_device *device = chip->device;
 450         uint32_t row;
 451         uint32_t col;
 452         uint8_t txbuf[4];
 453         int res;
 454         size_t towrite;
 455
 456         DEBUG(MTD_DEBUG_LEVEL2, "%s: write block to %llx len %d from %p\n", chip->name, to, len, buf);
 457
 458         *retlen = 0;
 459
 460         /*
 461          * nothing to write
 462          */
 463         if (!len) {
 464                 return 0;
 465         }
 466
 467         /*
 468          * Reject writes which go over the end of the flash
 469          */
 470         if ((to + len) > mtd->size) {
 471                 return -EINVAL;
 472         }
 473
 474         /*
 475          * Check to see if everything is page aligned
 476          */
 477         if (NOT_ALIGNED(to) || NOT_ALIGNED(len)) {
 478                 printk(KERN_NOTICE "nand_spi_er_write: Attempt to write non page aligned data\n");
 479                 return -EINVAL;
 480         }
 481
 482         mutex_lock(&chip->lock);
 483         chip->last_row = NAND_SPI_ER_LAST_ROW_INVALID;
 484
 485         /*
 486          * If the first write is a partial write then write at most the number of
 487          * bytes to get us page aligned and then the remainder will be
 488          * page aligned.  The last bit may be a partial page as well.
 489          */
 490         col = to & (device->page_size - 1);
 491         towrite = device->page_size - col;
 492         if (towrite > len) {
 493                 towrite = len;
 494         }
 495
 496         /*
 497          * Write the data
 498          */
 499         row = to >> 11;
 500         while (len) {
 501                 struct spi_message message;
 502                 struct spi_transfer x[2];
 503                 uint8_t stat;
 504
 505                 DEBUG(MTD_DEBUG_LEVEL3, "%s: write %p to row:%x col:%x len:%x rem:%x\n", chip->name, buf, row, col, towrite, len);
 506
 507                 /*
 508                  * Write enable
 509                  */
 510                 txbuf[0] = 0x06;
 511                 res = spi_write(spi, txbuf, 1);
 512                 if (res) {
 513                         DEBUG(MTD_DEBUG_LEVEL1, "%s: failed write enable res=%d\n", chip->name, res);
 514                         mutex_unlock(&chip->lock);
 515                         return res;
 516                 }
 517
 518                 /*
 519                  * Write the data into the cache
 520                  */
 521                 spi_message_init(&message);
 522                 memset(x, 0, sizeof(x));
 523                 txbuf[0] = 0x02;
 524                 txbuf[1] = col >> 8;
 525                 txbuf[2] = col & 0xFF;
 526                 x[0].tx_buf = txbuf;
 527                 x[0].len = 3;
 528                 spi_message_add_tail(&x[0], &message);
 529                 x[1].tx_buf = buf;
 530                 x[1].len = towrite;
 531                 spi_message_add_tail(&x[1], &message);
 532                 res = spi_sync(spi, &message);
 533                 if (res) {
 534                         DEBUG(MTD_DEBUG_LEVEL1, "%s: failed cache write res=%d\n", chip->name, res);
 535                         goto done;
 536                 }
 537
 538                 /*
 539                  * Program execute
 540                  */
 541                 txbuf[0] = 0x10;
 542                 txbuf[1] = 0x00;
 543                 txbuf[2] = row >> 8;
 544                 txbuf[3] = row & 0xFF;
 545                 res = spi_write(spi, txbuf, 4);
 546                 if (res) {
 547                         DEBUG(MTD_DEBUG_LEVEL1, "%s: failed prog execute res=%d\n", chip->name, res);
 548                         goto done;
 549                 }
 550
 551                 /*
 552                  * Wait
 553                  */
 554                 res = nand_spi_er_busywait(chip, &stat);
 555                 if (res || (stat & NAND_SPI_ER_STATUS_OIP)) {
 556                         DEBUG(MTD_DEBUG_LEVEL1, "%s: chip is busy or nonresponsive res=%d stat=%02x\n", chip->name, res, stat);
 557                         if (res) {
 558                                 goto done;
 559                         }
 560
 561                         /*
 562                          * Chip is stuck?
 563                          */
 564                         res = -EIO;
 565                         goto done;
 566                 }
 567
 568                 if (stat & (1 << 3)) {
 569                         res = -EBADMSG;
 570                         goto done;
 571                 }
 572
 573                 row++;
 574                 buf += towrite;
 575                 len -= towrite;
 576                 *retlen += towrite;
 577
 578                 /*
 579                  * At this point, we are always page aligned so start at column 0.
 580                  * Note we may not have a full page to write at the end, hence the
 581                  * check if towrite > len.
 582                  */
 583                 col = 0;
 584                 towrite = device->page_size;
 585                 if (towrite > len) {
 586                         towrite = len;
 587                 }
 588         }
 589
 590         mutex_unlock(&chip->lock);
 591         return res;
 592
 593 done:
 594         /*
 595          * Write disable
 596          */
 597         txbuf[0] = 0x04;
 598         res = spi_write(spi, txbuf, 1);
 599         if (res) {
 600                 DEBUG(MTD_DEBUG_LEVEL1, "%s: failed write disable res=%d\n", chip->name, res);
 601         }
 602
 603         mutex_unlock(&chip->lock);
 604
 605         return res;
 606 }
 607
 608 /*
 609  * nand_spi_er_isbad
 610  */
 611 static int nand_spi_er_isbad(struct mtd_info *mtd, loff_t ofs)
 612 {
 613         struct nand_spi_er *chip = mtd->priv;
 614         uint32_t block;
 615
 616         if (ofs & (chip->device->erase_size - 1)) {
 617                 DEBUG(MTD_DEBUG_LEVEL1, "%s: address not aligned %llx\n", chip->name, ofs);
 618                 return -EINVAL;
 619         }
 620
 621         block = ofs >> 17;
 622
 623         return test_bit(block, chip->bbt);
 624 }
 625
 626 /*
 627  * nand_spi_er_markbad
 628  */
 629 static int nand_spi_er_markbad(struct mtd_info *mtd, loff_t ofs)
 630 {
 631         struct nand_spi_er *chip = mtd->priv;
 632         struct spi_device *spi = chip->spi;
 633         uint32_t block;
 634         uint32_t row;
 635         uint8_t txbuf[7];
 636         int res;
 637         uint8_t stat;
 638
 639         if (ofs & (chip->device->erase_size - 1)) {
 640                 DEBUG(MTD_DEBUG_LEVEL1, "%s: address not aligned %llx\n", chip->name, ofs);
 641                 return -EINVAL;
 642         }
 643
 644         block = ofs >> 17;
 645
 646         /*
 647          * If it's already marked bad, no need to mark it
 648          */
 649         if (test_bit(block, chip->bbt)) {
 650                 return 0;
 651         }
 652
 653         /*
 654          * Mark it in our cache
 655          */
 656         __set_bit(block, chip->bbt);
 657
 658         /*
 659          * Write the user bad block mark.  If it fails, then we really
 660          * can't do anything about it.
 661          */
 662         mutex_lock(&chip->lock);
 663         chip->last_row = NAND_SPI_ER_LAST_ROW_INVALID;
 664
 665         /*
 666          * Write enable
 667          */
 668         txbuf[0] = 0x06;
 669         res = spi_write(spi, txbuf, 1);
 670         if (res) {
 671                 DEBUG(MTD_DEBUG_LEVEL1, "%s: failed write enable res=%d\n", chip->name, res);
 672                 mutex_unlock(&chip->lock);
 673                 return res;
 674         }
 675
 676         /*
 677          * Write the mark
 678          */
 679         txbuf[0] = 0x84;
 680         txbuf[1] = 0x08;
 681         txbuf[2] = NAND_SPI_ER_BAD_BLOCK_MARK_OFFSET;
 682         txbuf[3] = 0xde;
 683         txbuf[4] = 0xad;
 684         txbuf[5] = 0xbe;
 685         txbuf[6] = 0xef;
 686         res = spi_write(spi, txbuf, 7);
 687         if (res) {
 688                 DEBUG(MTD_DEBUG_LEVEL1, "%s: failed write mark res=%d\n", chip->name, res);
 689                 goto done;
 690         }
 691
 692         /*
 693          * Program execute
 694          */
 695         row = ofs >> 11;
 696         txbuf[0] = 0x10;
 697         txbuf[1] = 0x00;
 698         txbuf[2] = row >> 8;
 699         txbuf[3] = row & 0xFF;
 700         res = spi_write(spi, txbuf, 4);
 701         if (res) {
 702                 DEBUG(MTD_DEBUG_LEVEL1, "%s: failed program execute res=%d\n", chip->name, res);
 703                 goto done;
 704         }
 705
 706         /*
 707          * Wait
 708          */
 709         res = nand_spi_er_busywait(chip, &stat);
 710         if (res || (stat & NAND_SPI_ER_STATUS_OIP)) {
 711                 DEBUG(MTD_DEBUG_LEVEL1, "%s: chip is busy or nonresponsive res=%d stat=%02x\n", chip->name, res, stat);
 712                 if (res) {
 713                         goto done;
 714                 }
 715
 716                 /*
 717                  * Chip is stuck?
 718                  */
 719                 res = -EIO;
 720                 goto done;
 721         }
 722
 723         if (stat & (1 << 3)) {
 724                 res = -EBADMSG;
 725         }
 726
 727 done:
 728         /*
 729          * Write disable
 730          */
 731         txbuf[0] = 0x04;
 732         res = spi_write(spi, txbuf, 1);
 733         if (res) {
 734                 DEBUG(MTD_DEBUG_LEVEL1, "%s: failed write disable res=%d\n", chip->name, res);
 735         }
 736
 737         mutex_unlock(&chip->lock);
 738
 739         return res;
 740 }
 741
 742 /*
 743  * nand_spi_er_read_bbt
 744  */
 745 static int nand_spi_er_read_bbt(struct nand_spi_er *chip)
 746 {
 747         int j;
 748         for (j = 0; j < chip->device->blocks; j++) {
 749                 uint8_t txbuf[4];
 750                 uint8_t rxbuf[16];
 751                 uint32_t bbmark;
 752                 int res;
 753                 unsigned short row = j << 6;
 754                 uint8_t stat;
 755
 756                 /*
 757                  * Read Page
 758                  */
 759                 txbuf[0] = 0x13;
 760                 txbuf[1] = 0x00;
 761                 txbuf[2] = row >> 8;
 762                 txbuf[3] = row & 0xFF;
 763                 res = spi_write(chip->spi, txbuf, 4);
 764                 if (res) {
 765                         return res;
 766                 }
 767
 768                 /*
 769                  * Wait
 770                  */
 771                 res = nand_spi_er_busywait(chip, &stat);
 772                 if (res || (stat & NAND_SPI_ER_STATUS_OIP)) {
 773                         DEBUG(MTD_DEBUG_LEVEL1, "%s: chip is busy or nonresponsive res=%d stat=%02x\n", chip->name, res, stat);
 774                         if (res) {
 775                                 return res;
 776                         }
 777
 778                         /*
 779                          * Chip is stuck?
 780                          */
 781                         return -EIO;
 782                 }
 783
 784                 /*
 785                  * Check factory bad block mark
 786                  */
 787                 txbuf[0] = 0x03;
 788                 txbuf[1] = 0x08;
 789                 txbuf[2] = 0x00;
 790                 txbuf[3] = 0x00;
 791                 res = spi_write_then_read(chip->spi, txbuf, 4, rxbuf, 16);
 792                 if (res) {
 793                         return res;
 794                 }
 795                 if (rxbuf[0] != 0xFF) {
 796                         chip->nbb++;
 797                         __set_bit(j, chip->bbt);
 798                         continue;
 799                 }
 800
 801                 memcpy(&bbmark, &rxbuf[8], 4);
 802                 if (bbmark == 0xdeadbeef) {
 803                         chip->nbb++;
 804                         __set_bit(j, chip->bbt);
 805                 }
 806         }
 807
 808 #if defined(CONFIG_MTD_DEBUG) && (MTD_DEBUG_LEVEL3 <= CONFIG_MTD_DEBUG_VERBOSE)
 809         printk("%s: Bad Block Table:", chip->name);
 810         for (j = 0; j < chip->device->blocks; j++) {
 811                 if ((j % 64) == 0) {
 812                         printk("\n%s: block %03x: ", chip->name, j);
 813                 }
 814                 printk("%c", test_bit(j, chip->bbt) ? 'X' : '.');
 815         }
 816         printk("\n%s: Bad Block Numbers: ", chip->name);
 817         for (j = 0; j < chip->device->blocks; j++) {
 818                 if (test_bit(j, chip->bbt)) {
 819                         printk("%x ", j);
 820                 }
 821         }
 822         printk("\n");
 823 #endif
 824
 825         return 0;
 826 }
 827
 828 #ifndef MODULE
 829 /*
 830  * Called at boot time:
 831  *
 832  * nand_spi_er=read_only
 833  *      if read_only specified then do not unlock device
 834  */
 835 static int __init nand_spi_er_setup(char *str)
 836 {
 837         if (str && (strncasecmp(str, "read_only", 9) == 0)) {
 838                 read_only = 1;
 839         }
 840         return 0;
 841 }
 842
 843 __setup("nand_spi_er=", nand_spi_er_setup);
 844 #endif
 845
 846 /*
 847  * nand_spi_er_probe
 848  *      Detect and initialize nand_spi_er device.
 849  */
 850 static int __devinit nand_spi_er_probe(struct spi_device *spi)
 851 {
 852         uint8_t txbuf[3];
 853         uint8_t rxbuf[2];
 854         int i;
 855         int res;
 856         size_t bbt_bytes;
 857         struct nand_spi_er *chip;
 858         const struct nand_spi_er_device *device;
 859
 860         res = spi_setup(spi);
 861         if (res) {
 862                 return res;
 863         }
 864
 865         /*
 866          * Reset
 867          */
 868         for (i = 0; i < 2; i++) {
 869                 txbuf[0] = 0xFF;
 870                 res = spi_write(spi, txbuf, 1);
 871                 if (res) {
 872                         return res;
 873                 }
 874                 udelay(250);
 875         }
 876         udelay(1000);
 877
 878         /*
 879          * Read ID
 880          */
 881         txbuf[0] = 0x9F;
 882         txbuf[1] = 0x00;
 883         res = spi_write_then_read(spi, txbuf, 2, rxbuf, 2);
 884         if (res) {
 885                 return res;
 886         }
 887
 888         device = nand_spi_er_devices;
 889         for (i = 0; i < ARRAY_SIZE(nand_spi_er_devices); i++) {
 890                 if ((device->id0 == rxbuf[0]) && (device->id1 == rxbuf[1])) {
 891                         break;
 892                 }
 893                 device++;
 894         }
 895         if (i == ARRAY_SIZE(nand_spi_er_devices)) {
 896                 return -ENODEV;
 897         }
 898
 899         /*
 900          * Initialize our chip structure
 901          */
 902         bbt_bytes = DIV_ROUND_UP(device->blocks, BITS_PER_BYTE);
 903         chip = kzalloc(sizeof(struct nand_spi_er) + bbt_bytes, GFP_KERNEL);
 904         if (!chip) {
 905                 return -ENOMEM;
 906         }
 907         snprintf(chip->name, sizeof(chip->name), "%s.%d.%d", device->name, spi->master->bus_num, spi->chip_select);
 908
 909         chip->spi = spi;
 910         chip->device = device;
 911         chip->last_row = NAND_SPI_ER_LAST_ROW_INVALID;
 912
 913         mutex_init(&chip->lock);
 914
 915         chip->mtd.type = MTD_NANDFLASH;
 916         chip->mtd.flags = MTD_WRITEABLE;
 917
 918         /*
 919          * #blocks * block size * n blocks
 920          */
 921         chip->mtd.size = device->blocks * device->pages_per_block * device->page_size;
 922         chip->mtd.erasesize = device->erase_size;
 923
 924         /*
 925          * 1 page, optionally we can support partial write (512)
 926          */
 927         chip->mtd.writesize = device->write_size;
 928         chip->mtd.name = device->name;
 929         chip->mtd.erase = nand_spi_er_erase;
 930         chip->mtd.read = nand_spi_er_read;
 931         chip->mtd.write = nand_spi_er_write;
 932         chip->mtd.block_isbad = nand_spi_er_isbad;
 933         chip->mtd.block_markbad = nand_spi_er_markbad;
 934         chip->mtd.priv = chip;
 935
 936         /*
 937          * Cache the bad block table
 938          */
 939         res = nand_spi_er_read_bbt(chip);
 940         if (res) {
 941                 kfree(chip);
 942                 return res;
 943         }
 944
 945         /*
 946          * Un/lock the chip
 947          */
 948         txbuf[0] = 0x1F;
 949         txbuf[1] = 0xA0;
 950         if (read_only) {
 951                 txbuf[2] = 0x38;
 952         } else {
 953                 txbuf[2] = 0x00;
 954         }
 955         res = spi_write(spi, txbuf, 3);
 956         if (res) {
 957                 DEBUG(MTD_DEBUG_LEVEL1, "%s: failed lock operation res=%d\n", chip->name, res);
 958                 mutex_unlock(&chip->lock);
 959                 return res;
 960         }
 961
 962         spi_set_drvdata(spi, chip);
 963
 964         printk(KERN_INFO "%s: added device %s size: %u KBytes %u bad blocks %s\n", spi->dev.bus_id, chip->mtd.name, DIV_ROUND_UP(chip->mtd.size, 1024), chip->nbb, read_only ? "[read only]" : "");
 965         return add_mtd_device(&chip->mtd);
 966 }
 967
 968 /*
 969  * nand_spi_er_remove
 970  */
 971 static int __devexit nand_spi_er_remove(struct spi_device *spi)
 972 {
 973         struct nand_spi_er *chip = spi_get_drvdata(spi);
 974         int status = 0;
 975
 976         DEBUG(MTD_DEBUG_LEVEL1, "%s: remove\n", spi->dev.bus_id);
 977         status = del_mtd_device(&chip->mtd);
 978         if (status == 0)
 979                 kfree(chip);
 980         return status;
 981 }
 982
 983 static struct spi_driver nand_spi_er_driver = {
 984         .driver = {
 985                 .name           = "nand-spi-er",
 986                 .bus            = &spi_bus_type,
 987                 .owner          = THIS_MODULE,
 988         },
 989
 990         .probe          = nand_spi_er_probe,
 991         .remove         = __devexit_p(nand_spi_er_remove),
 992
 993         /* FIXME:  investigate suspend and resume... */
 994 };
 995
 996 /*
 997  * nand_spi_er_init
 998  */
 999 static int __init nand_spi_er_init(void)
1000 {
1001         return spi_register_driver(&nand_spi_er_driver);
1002 }
1003 module_init(nand_spi_er_init);
1004
1005 /*
1006  * nand_spi_er_exit
1007  */
1008 static void __exit nand_spi_er_exit(void)
1009 {
1010         spi_unregister_driver(&nand_spi_er_driver);
1011 }
1012 module_exit(nand_spi_er_exit);
1013
1014
1015 MODULE_LICENSE("GPL");
1016 MODULE_AUTHOR("Patrick Tjin");
1017 MODULE_DESCRIPTION("MTD nand_spi_er driver");