[kernel] fix order fail in previous commit
[openwrt.git] / target / linux / ubicom32 / files / drivers / net / ubi32-eth.h
1 /*
2 * drivers/net/ubi32-eth.h
3 * Ubicom32 ethernet TIO interface driver definitions.
4 *
5 * (C) Copyright 2009, Ubicom, Inc.
6 *
7 * This file is part of the Ubicom32 Linux Kernel Port.
8 *
9 * The Ubicom32 Linux Kernel Port is free software: you can redistribute
10 * it and/or modify it under the terms of the GNU General Public License
11 * as published by the Free Software Foundation, either version 2 of the
12 * License, or (at your option) any later version.
13 *
14 * The Ubicom32 Linux Kernel Port is distributed in the hope that it
15 * will be useful, but WITHOUT ANY WARRANTY; without even the implied
16 * warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See
17 * the GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with the Ubicom32 Linux Kernel Port. If not,
21 * see <http://www.gnu.org/licenses/>.
22 *
23 * Ubicom32 implementation derived from (with many thanks):
24 * arch/m68knommu
25 * arch/blackfin
26 * arch/parisc
27 */
28 #ifndef _UBI32_ETH_H
29 #define _UBI32_ETH_H
30
31 #include <asm/devtree.h>
32
33 #define UBI32_ETH_NUM_OF_DEVICES 2
34
35 /*
36 * Number of bytes trashed beyond the packet data.
37 */
38 #define UBI32_ETH_TRASHED_MEMORY (CACHE_LINE_SIZE + ETH_HLEN - 1)
39
40 /*
41 * Linux already reserves NET_SKB_PAD bytes of headroom in each sk_buff.
42 * We want to be able to reserve at least one cache line to align Ethernet
43 * and IP header to cache line.
44 * Note that the TIO expects a CACHE_LINE_SIZE - ETH_HLEN aligned Ethernet
45 * header, while satisfies NET_IP_ALIGN (= 2) automatically.
46 * (NET_SKB_PAD is 16, NET_IP_ALIGN is 2, CACHE_LINE_SIZE is 32).
47 * You can add more space by making UBI32_ETH_RESERVE_EXTRA != 0.
48 */
49 #define UBI32_ETH_RESERVE_EXTRA (1 * CACHE_LINE_SIZE)
50 #define UBI32_ETH_RESERVE_SPACE (UBI32_ETH_RESERVE_EXTRA + CACHE_LINE_SIZE)
51
52 struct ubi32_eth_dma_desc {
53 volatile void *data_pointer; /* pointer to the buffer */
54 volatile u16 buffer_len; /* the buffer size */
55 volatile u16 data_len; /* actual frame length */
56 volatile u32 status; /* bit0: status to be update by VP; bit[31:1] time stamp */
57 };
58
59 #define TX_DMA_RING_SIZE (1<<8)
60 #define TX_DMA_RING_MASK (TX_DMA_RING_SIZE - 1)
61 #define RX_DMA_RING_SIZE (1<<8)
62 #define RX_DMA_RING_MASK (RX_DMA_RING_SIZE - 1)
63
64 #define RX_DMA_MAX_QUEUE_SIZE (RX_DMA_RING_SIZE - 1) /* no more than (RX_DMA_RING_SIZE - 1) */
65 #define RX_MAX_PKT_SIZE (ETH_DATA_LEN + ETH_HLEN + VLAN_HLEN)
66 #define RX_MIN_PKT_SIZE ETH_ZLEN
67 #define RX_BUF_SIZE (RX_MAX_PKT_SIZE + VLAN_HLEN) /* allow double VLAN tag */
68
69 #define UBI32_ETH_VP_TX_TIMEOUT (10*HZ)
70
71 struct ubi32_eth_vp_stats {
72 u32 rx_alloc_err;
73 u32 tx_q_full_cnt;
74 u32 rx_q_full_cnt;
75 u32 rx_throttle;
76 };
77
78 struct ubi32_eth_private {
79 struct net_device *dev;
80 struct ubi32_eth_vp_stats vp_stats;
81 spinlock_t lock;
82 #ifdef UBICOM32_USE_NAPI
83 struct napi_struct napi;
84 #else
85 struct tasklet_struct tsk;
86 #endif
87 struct ethtionode *regs;
88 u16 rx_tail;
89 u16 tx_tail;
90 u32 vp_int_bit;
91 };
92
93 struct ethtionode {
94 struct devtree_node dn;
95 volatile u16 command;
96 volatile u16 status;
97 volatile u16 int_mask; /* interrupt mask */
98 volatile u16 int_status; /* interrupt mask */
99 volatile u16 tx_in; /* owned by driver */
100 volatile u16 tx_out; /* owned by vp */
101 volatile u16 rx_in; /* owned by driver */
102 volatile u16 rx_out; /* owned by vp */
103 u16 tx_sz; /* owned by driver */
104 u16 rx_sz; /* owned by driver */
105 struct ubi32_eth_dma_desc **tx_dma_ring;
106 struct ubi32_eth_dma_desc **rx_dma_ring;
107 };
108
109 #define UBI32_ETH_VP_STATUS_LINK (1<<0)
110 #define UBI32_ETH_VP_STATUS_SPEED100 (0x1<<1)
111 #define UBI32_ETH_VP_STATUS_SPEED1000 (0x1<<2)
112 #define UBI32_ETH_VP_STATUS_DUPLEX (0x1<<3)
113 #define UBI32_ETH_VP_STATUS_FLOW_CTRL (0x1<<4)
114
115 #define UBI32_ETH_VP_STATUS_RX_STATE (0x1<<5)
116 #define UBI32_ETH_VP_STATUS_TX_STATE (0x1<<6)
117
118 #define UBI32_ETH_VP_STATUS_TX_Q_FULL (1<<8)
119
120 #define UBI32_ETH_VP_INT_RX (1<<0)
121 #define UBI32_ETH_VP_INT_TX (1<<1)
122
123 #define UBI32_ETH_VP_CMD_RX_ENABLE (1<<0)
124 #define UBI32_ETH_VP_CMD_TX_ENABLE (1<<1)
125
126 #define UBI32_ETH_VP_RX_OK (1<<0)
127 #define UBI32_ETH_VP_TX_OK (1<<1)
128
129 #define UBI32_TX_BOUND TX_DMA_RING_SIZE
130 #define UBI32_RX_BOUND 64
131 #define UBI32_ETH_NAPI_WEIGHT 64 /* for GigE */
132 #endif
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