target/linux/ramips/files/drivers/usb/dwc_otg/dwc_otg_cil.h

   1 /* ==========================================================================
   2  * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_cil.h $
   3  * $Revision: 1.2 $
   4  * $Date: 2008-11-21 05:39:15 $
   5  * $Change: 1099526 $
   6  *
   7  * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
   8  * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
   9  * otherwise expressly agreed to in writing between Synopsys and you.
  10  *
  11  * The Software IS NOT an item of Licensed Software or Licensed Product under
  12  * any End User Software License Agreement or Agreement for Licensed Product
  13  * with Synopsys or any supplement thereto. You are permitted to use and
  14  * redistribute this Software in source and binary forms, with or without
  15  * modification, provided that redistributions of source code must retain this
  16  * notice. You may not view, use, disclose, copy or distribute this file or
  17  * any information contained herein except pursuant to this license grant from
  18  * Synopsys. If you do not agree with this notice, including the disclaimer
  19  * below, then you are not authorized to use the Software.
  20  *
  21  * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
  22  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  23  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  24  * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
  25  * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  26  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
  27  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
  28  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  29  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  30  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
  31  * DAMAGE.
  32  * ========================================================================== */
  33
  34 #if !defined(__DWC_CIL_H__)
  35 #define __DWC_CIL_H__
  36
  37 #include <linux/workqueue.h>
  38 #include <linux/version.h>
  39 #include <asm/param.h>
  40
  41 #include "linux/dwc_otg_plat.h"
  42 #include "dwc_otg_regs.h"
  43 #ifdef DEBUG
  44 #include "linux/timer.h"
  45 #endif
  46
  47 /**
  48  * @file
  49  * This file contains the interface to the Core Interface Layer.
  50  */
  51
  52
  53 /** Macros defined for DWC OTG HW Release verison */
  54 #define OTG_CORE_REV_2_00       0x4F542000
  55 #define OTG_CORE_REV_2_60a      0x4F54260A
  56 #define OTG_CORE_REV_2_71a      0x4F54271A
  57 #define OTG_CORE_REV_2_72a      0x4F54272A
  58
  59 /**
  60 */
  61 typedef struct iso_pkt_info
  62 {
  63         uint32_t        offset;
  64         uint32_t        length;
  65         int32_t         status;
  66 } iso_pkt_info_t;
  67 /**
  68  * The <code>dwc_ep</code> structure represents the state of a single
  69  * endpoint when acting in device mode. It contains the data items
  70  * needed for an endpoint to be activated and transfer packets.
  71  */
  72 typedef struct dwc_ep
  73 {
  74         /** EP number used for register address lookup */
  75         uint8_t  num;
  76         /** EP direction 0 = OUT */
  77         unsigned is_in : 1;
  78         /** EP active. */
  79         unsigned active : 1;
  80
  81         /** Periodic Tx FIFO # for IN EPs For INTR EP set to 0 to use non-periodic Tx FIFO
  82                 If dedicated Tx FIFOs are enabled for all IN Eps - Tx FIFO # FOR IN EPs*/
  83         unsigned tx_fifo_num : 4;
  84         /** EP type: 0 - Control, 1 - ISOC,      2 - BULK,      3 - INTR */
  85         unsigned type : 2;
  86 #define DWC_OTG_EP_TYPE_CONTROL    0
  87 #define DWC_OTG_EP_TYPE_ISOC       1
  88 #define DWC_OTG_EP_TYPE_BULK       2
  89 #define DWC_OTG_EP_TYPE_INTR       3
  90
  91         /** DATA start PID for INTR and BULK EP */
  92         unsigned data_pid_start : 1;
  93         /** Frame (even/odd) for ISOC EP */
  94         unsigned even_odd_frame : 1;
  95         /** Max Packet bytes */
  96         unsigned maxpacket : 11;
  97
  98         /** Max Transfer size */
  99         unsigned maxxfer : 16;
 100
 101         /** @name Transfer state */
 102         /** @{ */
 103
 104         /**
 105          * Pointer to the beginning of the transfer buffer -- do not modify
 106          * during transfer.
 107          */
 108
 109         uint32_t dma_addr;
 110
 111         uint32_t dma_desc_addr;
 112         dwc_otg_dma_desc_t* desc_addr;
 113
 114
 115         uint8_t *start_xfer_buff;
 116         /** pointer to the transfer buffer */
 117         uint8_t *xfer_buff;
 118         /** Number of bytes to transfer */
 119         unsigned xfer_len : 19;
 120         /** Number of bytes transferred. */
 121         unsigned xfer_count : 19;
 122         /** Sent ZLP */
 123         unsigned sent_zlp : 1;
 124         /** Total len for control transfer */
 125         unsigned total_len : 19;
 126
 127         /** stall clear flag */
 128         unsigned stall_clear_flag : 1;
 129
 130         /** Allocated DMA Desc count */
 131         uint32_t        desc_cnt;
 132
 133 #ifdef DWC_EN_ISOC
 134         /**
 135          * Variables specific for ISOC EPs
 136          *
 137          */
 138         /** DMA addresses of ISOC buffers */
 139         uint32_t        dma_addr0;
 140         uint32_t        dma_addr1;
 141
 142         uint32_t        iso_dma_desc_addr;
 143         dwc_otg_dma_desc_t* iso_desc_addr;
 144
 145         /** pointer to the transfer buffers */
 146         uint8_t         *xfer_buff0;
 147         uint8_t         *xfer_buff1;
 148
 149         /** number of ISOC Buffer is processing */
 150         uint32_t        proc_buf_num;
 151         /** Interval of ISOC Buffer processing */
 152         uint32_t        buf_proc_intrvl;
 153         /** Data size for regular frame */
 154         uint32_t        data_per_frame;
 155
 156         /* todo - pattern data support is to be implemented in the future */
 157         /** Data size for pattern frame */
 158         uint32_t        data_pattern_frame;
 159         /** Frame number of pattern data */
 160         uint32_t        sync_frame;
 161
 162         /** bInterval */
 163         uint32_t        bInterval;
 164         /** ISO Packet number per frame */
 165         uint32_t        pkt_per_frm;
 166         /** Next frame num for which will be setup DMA Desc */
 167         uint32_t        next_frame;
 168         /** Number of packets per buffer processing */
 169         uint32_t        pkt_cnt;
 170         /** Info for all isoc packets */
 171         iso_pkt_info_t  *pkt_info;
 172         /** current pkt number */
 173         uint32_t        cur_pkt;
 174         /** current pkt number */
 175         uint8_t         *cur_pkt_addr;
 176         /** current pkt number */
 177         uint32_t        cur_pkt_dma_addr;
 178 #endif //DWC_EN_ISOC
 179 /** @} */
 180 } dwc_ep_t;
 181
 182 /*
 183  * Reasons for halting a host channel.
 184  */
 185 typedef enum dwc_otg_halt_status
 186 {
 187         DWC_OTG_HC_XFER_NO_HALT_STATUS,
 188         DWC_OTG_HC_XFER_COMPLETE,
 189         DWC_OTG_HC_XFER_URB_COMPLETE,
 190         DWC_OTG_HC_XFER_ACK,
 191         DWC_OTG_HC_XFER_NAK,
 192         DWC_OTG_HC_XFER_NYET,
 193         DWC_OTG_HC_XFER_STALL,
 194         DWC_OTG_HC_XFER_XACT_ERR,
 195         DWC_OTG_HC_XFER_FRAME_OVERRUN,
 196         DWC_OTG_HC_XFER_BABBLE_ERR,
 197         DWC_OTG_HC_XFER_DATA_TOGGLE_ERR,
 198         DWC_OTG_HC_XFER_AHB_ERR,
 199         DWC_OTG_HC_XFER_PERIODIC_INCOMPLETE,
 200         DWC_OTG_HC_XFER_URB_DEQUEUE
 201 } dwc_otg_halt_status_e;
 202
 203 /**
 204  * Host channel descriptor. This structure represents the state of a single
 205  * host channel when acting in host mode. It contains the data items needed to
 206  * transfer packets to an endpoint via a host channel.
 207  */
 208 typedef struct dwc_hc
 209 {
 210         /** Host channel number used for register address lookup */
 211         uint8_t  hc_num;
 212
 213         /** Device to access */
 214         unsigned dev_addr : 7;
 215
 216         /** EP to access */
 217         unsigned ep_num : 4;
 218
 219         /** EP direction. 0: OUT, 1: IN */
 220         unsigned ep_is_in : 1;
 221
 222         /**
 223          * EP speed.
 224          * One of the following values:
 225          *      - DWC_OTG_EP_SPEED_LOW
 226          *      - DWC_OTG_EP_SPEED_FULL
 227          *      - DWC_OTG_EP_SPEED_HIGH
 228          */
 229         unsigned speed : 2;
 230 #define DWC_OTG_EP_SPEED_LOW    0
 231 #define DWC_OTG_EP_SPEED_FULL   1
 232 #define DWC_OTG_EP_SPEED_HIGH   2
 233
 234         /**
 235          * Endpoint type.
 236          * One of the following values:
 237          *      - DWC_OTG_EP_TYPE_CONTROL: 0
 238          *      - DWC_OTG_EP_TYPE_ISOC: 1
 239          *      - DWC_OTG_EP_TYPE_BULK: 2
 240          *      - DWC_OTG_EP_TYPE_INTR: 3
 241          */
 242         unsigned ep_type : 2;
 243
 244         /** Max packet size in bytes */
 245         unsigned max_packet : 11;
 246
 247         /**
 248          * PID for initial transaction.
 249          * 0: DATA0,<br>
 250          * 1: DATA2,<br>
 251          * 2: DATA1,<br>
 252          * 3: MDATA (non-Control EP),
 253          *        SETUP (Control EP)
 254          */
 255         unsigned data_pid_start : 2;
 256 #define DWC_OTG_HC_PID_DATA0 0
 257 #define DWC_OTG_HC_PID_DATA2 1
 258 #define DWC_OTG_HC_PID_DATA1 2
 259 #define DWC_OTG_HC_PID_MDATA 3
 260 #define DWC_OTG_HC_PID_SETUP 3
 261
 262         /** Number of periodic transactions per (micro)frame */
 263         unsigned multi_count: 2;
 264
 265         /** @name Transfer State */
 266         /** @{ */
 267
 268         /** Pointer to the current transfer buffer position. */
 269         uint8_t *xfer_buff;
 270         /** Total number of bytes to transfer. */
 271         uint32_t xfer_len;
 272         /** Number of bytes transferred so far. */
 273         uint32_t xfer_count;
 274         /** Packet count at start of transfer.*/
 275         uint16_t start_pkt_count;
 276
 277         /**
 278          * Flag to indicate whether the transfer has been started. Set to 1 if
 279          * it has been started, 0 otherwise.
 280          */
 281         uint8_t xfer_started;
 282
 283         /**
 284          * Set to 1 to indicate that a PING request should be issued on this
 285          * channel. If 0, process normally.
 286          */
 287         uint8_t do_ping;
 288
 289         /**
 290          * Set to 1 to indicate that the error count for this transaction is
 291          * non-zero. Set to 0 if the error count is 0.
 292          */
 293         uint8_t error_state;
 294
 295         /**
 296          * Set to 1 to indicate that this channel should be halted the next
 297          * time a request is queued for the channel. This is necessary in
 298          * slave mode if no request queue space is available when an attempt
 299          * is made to halt the channel.
 300          */
 301         uint8_t halt_on_queue;
 302
 303         /**
 304          * Set to 1 if the host channel has been halted, but the core is not
 305          * finished flushing queued requests. Otherwise 0.
 306          */
 307         uint8_t halt_pending;
 308
 309         /**
 310          * Reason for halting the host channel.
 311          */
 312         dwc_otg_halt_status_e   halt_status;
 313
 314         /*
 315          * Split settings for the host channel
 316          */
 317         uint8_t do_split;                  /**< Enable split for the channel */
 318         uint8_t complete_split;    /**< Enable complete split */
 319         uint8_t hub_addr;                  /**< Address of high speed hub */
 320
 321         uint8_t port_addr;                 /**< Port of the low/full speed device */
 322         /** Split transaction position
 323          * One of the following values:
 324          *        - DWC_HCSPLIT_XACTPOS_MID
 325          *        - DWC_HCSPLIT_XACTPOS_BEGIN
 326          *        - DWC_HCSPLIT_XACTPOS_END
 327          *        - DWC_HCSPLIT_XACTPOS_ALL */
 328         uint8_t xact_pos;
 329
 330         /** Set when the host channel does a short read. */
 331         uint8_t short_read;
 332
 333         /**
 334          * Number of requests issued for this channel since it was assigned to
 335          * the current transfer (not counting PINGs).
 336          */
 337         uint8_t requests;
 338
 339         /**
 340          * Queue Head for the transfer being processed by this channel.
 341          */
 342         struct dwc_otg_qh *qh;
 343
 344         /** @} */
 345
 346         /** Entry in list of host channels. */
 347         struct list_head        hc_list_entry;
 348 } dwc_hc_t;
 349
 350 /**
 351  * The following parameters may be specified when starting the module. These
 352  * parameters define how the DWC_otg controller should be configured.
 353  * Parameter values are passed to the CIL initialization function
 354  * dwc_otg_cil_init.
 355  */
 356 typedef struct dwc_otg_core_params
 357 {
 358         int32_t opt;
 359 #define dwc_param_opt_default 1
 360
 361         /**
 362          * Specifies the OTG capabilities. The driver will automatically
 363          * detect the value for this parameter if none is specified.
 364          * 0 - HNP and SRP capable (default)
 365          * 1 - SRP Only capable
 366          * 2 - No HNP/SRP capable
 367          */
 368         int32_t otg_cap;
 369 #define DWC_OTG_CAP_PARAM_HNP_SRP_CAPABLE 0
 370 #define DWC_OTG_CAP_PARAM_SRP_ONLY_CAPABLE 1
 371 #define DWC_OTG_CAP_PARAM_NO_HNP_SRP_CAPABLE 2
 372 #define dwc_param_otg_cap_default DWC_OTG_CAP_PARAM_HNP_SRP_CAPABLE
 373
 374         /**
 375          * Specifies whether to use slave or DMA mode for accessing the data
 376          * FIFOs. The driver will automatically detect the value for this
 377          * parameter if none is specified.
 378          * 0 - Slave
 379          * 1 - DMA (default, if available)
 380          */
 381         int32_t dma_enable;
 382 #define dwc_param_dma_enable_default 1
 383
 384         /**
 385          * When DMA mode is enabled specifies whether to use address DMA or DMA Descritor mode for accessing the data
 386          * FIFOs in device mode. The driver will automatically detect the value for this
 387          * parameter if none is specified.
 388          * 0 - address DMA
 389          * 1 - DMA Descriptor(default, if available)
 390          */
 391         int32_t dma_desc_enable;
 392 #define dwc_param_dma_desc_enable_default 0
 393         /** The DMA Burst size (applicable only for External DMA
 394          * Mode). 1, 4, 8 16, 32, 64, 128, 256 (default 32)
 395          */
 396         int32_t dma_burst_size;  /* Translate this to GAHBCFG values */
 397 #define dwc_param_dma_burst_size_default 32
 398
 399         /**
 400          * Specifies the maximum speed of operation in host and device mode.
 401          * The actual speed depends on the speed of the attached device and
 402          * the value of phy_type. The actual speed depends on the speed of the
 403          * attached device.
 404          * 0 - High Speed (default)
 405          * 1 - Full Speed
 406          */
 407         int32_t speed;
 408 #define dwc_param_speed_default 0
 409 #define DWC_SPEED_PARAM_HIGH 0
 410 #define DWC_SPEED_PARAM_FULL 1
 411
 412         /** Specifies whether low power mode is supported when attached
 413          *      to a Full Speed or Low Speed device in host mode.
 414          * 0 - Don't support low power mode (default)
 415          * 1 - Support low power mode
 416          */
 417         int32_t host_support_fs_ls_low_power;
 418 #define dwc_param_host_support_fs_ls_low_power_default 0
 419
 420         /** Specifies the PHY clock rate in low power mode when connected to a
 421          * Low Speed device in host mode. This parameter is applicable only if
 422          * HOST_SUPPORT_FS_LS_LOW_POWER is enabled.      If PHY_TYPE is set to FS
 423          * then defaults to 6 MHZ otherwise 48 MHZ.
 424          *
 425          * 0 - 48 MHz
 426          * 1 - 6 MHz
 427          */
 428         int32_t host_ls_low_power_phy_clk;
 429 #define dwc_param_host_ls_low_power_phy_clk_default 0
 430 #define DWC_HOST_LS_LOW_POWER_PHY_CLK_PARAM_48MHZ 0
 431 #define DWC_HOST_LS_LOW_POWER_PHY_CLK_PARAM_6MHZ 1
 432
 433         /**
 434          * 0 - Use cC FIFO size parameters
 435          * 1 - Allow dynamic FIFO sizing (default)
 436          */
 437         int32_t enable_dynamic_fifo;
 438 #define dwc_param_enable_dynamic_fifo_default 1
 439
 440         /** Total number of 4-byte words in the data FIFO memory. This
 441          * memory includes the Rx FIFO, non-periodic Tx FIFO, and periodic
 442          * Tx FIFOs.
 443          * 32 to 32768 (default 8192)
 444          * Note: The total FIFO memory depth in the FPGA configuration is 8192.
 445          */
 446         int32_t data_fifo_size;
 447 #define dwc_param_data_fifo_size_default 8192
 448
 449         /** Number of 4-byte words in the Rx FIFO in device mode when dynamic
 450          * FIFO sizing is enabled.
 451          * 16 to 32768 (default 1064)
 452          */
 453         int32_t dev_rx_fifo_size;
 454 #define dwc_param_dev_rx_fifo_size_default  1064
 455
 456         /** Number of 4-byte words in the non-periodic Tx FIFO in device mode
 457          * when dynamic FIFO sizing is enabled.
 458          * 16 to 32768 (default 1024)
 459          */
 460         int32_t dev_nperio_tx_fifo_size;
 461 #define dwc_param_dev_nperio_tx_fifo_size_default 1024
 462
 463         /** Number of 4-byte words in each of the periodic Tx FIFOs in device
 464          * mode when dynamic FIFO sizing is enabled.
 465          * 4 to 768 (default 256)
 466          */
 467         uint32_t dev_perio_tx_fifo_size[MAX_PERIO_FIFOS];
 468 #define dwc_param_dev_perio_tx_fifo_size_default 256
 469
 470         /** Number of 4-byte words in the Rx FIFO in host mode when dynamic
 471          * FIFO sizing is enabled.
 472          * 16 to 32768 (default 1024)
 473          */
 474         int32_t host_rx_fifo_size;
 475 #define dwc_param_host_rx_fifo_size_default 1024
 476
 477         /** Number of 4-byte words in the non-periodic Tx FIFO in host mode
 478          * when Dynamic FIFO sizing is enabled in the core.
 479          * 16 to 32768 (default 1024)
 480          */
 481         int32_t host_nperio_tx_fifo_size;
 482 #define dwc_param_host_nperio_tx_fifo_size_default 1024
 483
 484         /** Number of 4-byte words in the host periodic Tx FIFO when dynamic
 485          * FIFO sizing is enabled.
 486          * 16 to 32768 (default 1024)
 487          */
 488         int32_t host_perio_tx_fifo_size;
 489 #define dwc_param_host_perio_tx_fifo_size_default 1024
 490
 491         /** The maximum transfer size supported in bytes.
 492          * 2047 to 65,535  (default 65,535)
 493          */
 494         int32_t max_transfer_size;
 495 #define dwc_param_max_transfer_size_default 65535
 496
 497         /** The maximum number of packets in a transfer.
 498          * 15 to 511  (default 511)
 499          */
 500         int32_t max_packet_count;
 501 #define dwc_param_max_packet_count_default 511
 502
 503         /** The number of host channel registers to use.
 504          * 1 to 16 (default 12)
 505          * Note: The FPGA configuration supports a maximum of 12 host channels.
 506          */
 507         int32_t host_channels;
 508 #define dwc_param_host_channels_default 12
 509
 510         /** The number of endpoints in addition to EP0 available for device
 511          * mode operations.
 512          * 1 to 15 (default 6 IN and OUT)
 513          * Note: The FPGA configuration supports a maximum of 6 IN and OUT
 514          * endpoints in addition to EP0.
 515          */
 516         int32_t dev_endpoints;
 517 #define dwc_param_dev_endpoints_default 6
 518
 519                 /**
 520                  * Specifies the type of PHY interface to use. By default, the driver
 521                  * will automatically detect the phy_type.
 522                  *
 523                  * 0 - Full Speed PHY
 524                  * 1 - UTMI+ (default)
 525                  * 2 - ULPI
 526                  */
 527         int32_t phy_type;
 528 #define DWC_PHY_TYPE_PARAM_FS 0
 529 #define DWC_PHY_TYPE_PARAM_UTMI 1
 530 #define DWC_PHY_TYPE_PARAM_ULPI 2
 531 #define dwc_param_phy_type_default DWC_PHY_TYPE_PARAM_UTMI
 532
 533         /**
 534          * Specifies the UTMI+ Data Width.      This parameter is
 535          * applicable for a PHY_TYPE of UTMI+ or ULPI. (For a ULPI
 536          * PHY_TYPE, this parameter indicates the data width between
 537          * the MAC and the ULPI Wrapper.) Also, this parameter is
 538          * applicable only if the OTG_HSPHY_WIDTH cC parameter was set
 539          * to "8 and 16 bits", meaning that the core has been
 540          * configured to work at either data path width.
 541          *
 542          * 8 or 16 bits (default 16)
 543          */
 544         int32_t phy_utmi_width;
 545 #define dwc_param_phy_utmi_width_default 16
 546
 547         /**
 548          * Specifies whether the ULPI operates at double or single
 549          * data rate. This parameter is only applicable if PHY_TYPE is
 550          * ULPI.
 551          *
 552          * 0 - single data rate ULPI interface with 8 bit wide data
 553          * bus (default)
 554          * 1 - double data rate ULPI interface with 4 bit wide data
 555          * bus
 556          */
 557         int32_t phy_ulpi_ddr;
 558 #define dwc_param_phy_ulpi_ddr_default 0
 559
 560         /**
 561          * Specifies whether to use the internal or external supply to
 562          * drive the vbus with a ULPI phy.
 563          */
 564         int32_t phy_ulpi_ext_vbus;
 565 #define DWC_PHY_ULPI_INTERNAL_VBUS 0
 566 #define DWC_PHY_ULPI_EXTERNAL_VBUS 1
 567 #define dwc_param_phy_ulpi_ext_vbus_default DWC_PHY_ULPI_INTERNAL_VBUS
 568
 569         /**
 570          * Specifies whether to use the I2Cinterface for full speed PHY. This
 571          * parameter is only applicable if PHY_TYPE is FS.
 572          * 0 - No (default)
 573          * 1 - Yes
 574          */
 575         int32_t i2c_enable;
 576 #define dwc_param_i2c_enable_default 0
 577
 578         int32_t ulpi_fs_ls;
 579 #define dwc_param_ulpi_fs_ls_default 0
 580
 581         int32_t ts_dline;
 582 #define dwc_param_ts_dline_default 0
 583
 584         /**
 585          * Specifies whether dedicated transmit FIFOs are
 586          * enabled for non periodic IN endpoints in device mode
 587          * 0 - No
 588          * 1 - Yes
 589          */
 590          int32_t en_multiple_tx_fifo;
 591 #define dwc_param_en_multiple_tx_fifo_default 1
 592
 593         /** Number of 4-byte words in each of the Tx FIFOs in device
 594          * mode when dynamic FIFO sizing is enabled.
 595          * 4 to 768 (default 256)
 596          */
 597         uint32_t dev_tx_fifo_size[MAX_TX_FIFOS];
 598 #define dwc_param_dev_tx_fifo_size_default 256
 599
 600         /** Thresholding enable flag-
 601          * bit 0 - enable non-ISO Tx thresholding
 602          * bit 1 - enable ISO Tx thresholding
 603          * bit 2 - enable Rx thresholding
 604          */
 605         uint32_t thr_ctl;
 606 #define dwc_param_thr_ctl_default 0
 607
 608         /** Thresholding length for Tx
 609          *      FIFOs in 32 bit DWORDs
 610          */
 611         uint32_t tx_thr_length;
 612 #define dwc_param_tx_thr_length_default 64
 613
 614         /** Thresholding length for Rx
 615          *      FIFOs in 32 bit DWORDs
 616          */
 617         uint32_t rx_thr_length;
 618 #define dwc_param_rx_thr_length_default 64
 619
 620         /** Per Transfer Interrupt
 621          *      mode enable flag
 622          * 1 - Enabled
 623          * 0 - Disabled
 624          */
 625         uint32_t pti_enable;
 626 #define dwc_param_pti_enable_default 0
 627
 628         /** Molti Processor Interrupt
 629          *      mode enable flag
 630          * 1 - Enabled
 631          * 0 - Disabled
 632          */
 633         uint32_t mpi_enable;
 634 #define dwc_param_mpi_enable_default 0
 635
 636 } dwc_otg_core_params_t;
 637
 638 #ifdef DEBUG
 639 struct dwc_otg_core_if;
 640 typedef struct hc_xfer_info
 641 {
 642         struct dwc_otg_core_if  *core_if;
 643         dwc_hc_t                *hc;
 644 } hc_xfer_info_t;
 645 #endif
 646
 647 /**
 648  * The <code>dwc_otg_core_if</code> structure contains information needed to manage
 649  * the DWC_otg controller acting in either host or device mode. It
 650  * represents the programming view of the controller as a whole.
 651  */
 652 typedef struct dwc_otg_core_if
 653 {
 654         /** Parameters that define how the core should be configured.*/
 655         dwc_otg_core_params_t      *core_params;
 656
 657         /** Core Global registers starting at offset 000h. */
 658         dwc_otg_core_global_regs_t *core_global_regs;
 659
 660         /** Device-specific information */
 661         dwc_otg_dev_if_t                   *dev_if;
 662         /** Host-specific information */
 663         dwc_otg_host_if_t                  *host_if;
 664
 665         /** Value from SNPSID register */
 666         uint32_t snpsid;
 667
 668         /*
 669          * Set to 1 if the core PHY interface bits in USBCFG have been
 670          * initialized.
 671          */
 672         uint8_t phy_init_done;
 673
 674         /*
 675          * SRP Success flag, set by srp success interrupt in FS I2C mode
 676          */
 677         uint8_t srp_success;
 678         uint8_t srp_timer_started;
 679
 680         /* Common configuration information */
 681         /** Power and Clock Gating Control Register */
 682         volatile uint32_t *pcgcctl;
 683 #define DWC_OTG_PCGCCTL_OFFSET 0xE00
 684
 685         /** Push/pop addresses for endpoints or host channels.*/
 686         uint32_t *data_fifo[MAX_EPS_CHANNELS];
 687 #define DWC_OTG_DATA_FIFO_OFFSET 0x1000
 688 #define DWC_OTG_DATA_FIFO_SIZE 0x1000
 689
 690         /** Total RAM for FIFOs (Bytes) */
 691         uint16_t total_fifo_size;
 692         /** Size of Rx FIFO (Bytes) */
 693         uint16_t rx_fifo_size;
 694         /** Size of Non-periodic Tx FIFO (Bytes) */
 695         uint16_t nperio_tx_fifo_size;
 696
 697
 698         /** 1 if DMA is enabled, 0 otherwise. */
 699         uint8_t dma_enable;
 700
 701         /** 1 if Descriptor DMA mode is enabled, 0 otherwise. */
 702         uint8_t dma_desc_enable;
 703
 704         /** 1 if PTI Enhancement mode is enabled, 0 otherwise. */
 705         uint8_t pti_enh_enable;
 706
 707         /** 1 if MPI Enhancement mode is enabled, 0 otherwise. */
 708         uint8_t multiproc_int_enable;
 709
 710         /** 1 if dedicated Tx FIFOs are enabled, 0 otherwise. */
 711         uint8_t en_multiple_tx_fifo;
 712
 713         /** Set to 1 if multiple packets of a high-bandwidth transfer is in
 714          * process of being queued */
 715         uint8_t queuing_high_bandwidth;
 716
 717         /** Hardware Configuration -- stored here for convenience.*/
 718         hwcfg1_data_t hwcfg1;
 719         hwcfg2_data_t hwcfg2;
 720         hwcfg3_data_t hwcfg3;
 721         hwcfg4_data_t hwcfg4;
 722
 723         /** Host and Device Configuration -- stored here for convenience.*/
 724         hcfg_data_t hcfg;
 725         dcfg_data_t dcfg;
 726
 727         /** The operational State, during transations
 728          * (a_host>>a_peripherial and b_device=>b_host) this may not
 729          * match the core but allows the software to determine
 730          * transitions.
 731          */
 732         uint8_t op_state;
 733
 734         /**
 735          * Set to 1 if the HCD needs to be restarted on a session request
 736          * interrupt. This is required if no connector ID status change has
 737          * occurred since the HCD was last disconnected.
 738          */
 739         uint8_t restart_hcd_on_session_req;
 740
 741         /** HCD callbacks */
 742         /** A-Device is a_host */
 743 #define A_HOST          (1)
 744         /** A-Device is a_suspend */
 745 #define A_SUSPEND       (2)
 746         /** A-Device is a_peripherial */
 747 #define A_PERIPHERAL    (3)
 748         /** B-Device is operating as a Peripheral. */
 749 #define B_PERIPHERAL    (4)
 750         /** B-Device is operating as a Host. */
 751 #define B_HOST          (5)
 752
 753         /** HCD callbacks */
 754         struct dwc_otg_cil_callbacks *hcd_cb;
 755         /** PCD callbacks */
 756         struct dwc_otg_cil_callbacks *pcd_cb;
 757
 758         /** Device mode Periodic Tx FIFO Mask */
 759         uint32_t p_tx_msk;
 760         /** Device mode Periodic Tx FIFO Mask */
 761         uint32_t tx_msk;
 762
 763         /** Workqueue object used for handling several interrupts */
 764         struct workqueue_struct *wq_otg;
 765
 766         /** Work object used for handling "Connector ID Status Change" Interrupt */
 767         struct work_struct      w_conn_id;
 768
 769         /** Work object used for handling "Wakeup Detected" Interrupt */
 770 #if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,20)
 771         struct work_struct      w_wkp;
 772 #else
 773         struct delayed_work     w_wkp;
 774 #endif
 775
 776 #ifdef DEBUG
 777         uint32_t                start_hcchar_val[MAX_EPS_CHANNELS];
 778
 779         hc_xfer_info_t          hc_xfer_info[MAX_EPS_CHANNELS];
 780         struct timer_list       hc_xfer_timer[MAX_EPS_CHANNELS];
 781
 782         uint32_t                hfnum_7_samples;
 783         uint64_t                hfnum_7_frrem_accum;
 784         uint32_t                hfnum_0_samples;
 785         uint64_t                hfnum_0_frrem_accum;
 786         uint32_t                hfnum_other_samples;
 787         uint64_t                hfnum_other_frrem_accum;
 788 #endif
 789
 790
 791 } dwc_otg_core_if_t;
 792
 793 /*We must clear S3C24XX_EINTPEND external interrupt register
 794  * because after clearing in this register trigerred IRQ from
 795  * H/W core in kernel interrupt can be occured again before OTG
 796  * handlers clear all IRQ sources of Core registers because of
 797  * timing latencies and Low Level IRQ Type.
 798  */
 799
 800 #ifdef CONFIG_MACH_IPMATE
 801 #define  S3C2410X_CLEAR_EINTPEND()   \
 802 do { \
 803         if (!dwc_otg_read_core_intr(core_if)) { \
 804         __raw_writel(1UL << 11,S3C24XX_EINTPEND); \
 805         } \
 806 } while (0)
 807 #else
 808 #define  S3C2410X_CLEAR_EINTPEND()   do { } while (0)
 809 #endif
 810
 811 /*
 812  * The following functions are functions for works
 813  * using during handling some interrupts
 814  */
 815 #if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,20)
 816
 817 extern void w_conn_id_status_change(void *p);
 818 extern void w_wakeup_detected(void *p);
 819
 820 #else
 821
 822 extern void w_conn_id_status_change(struct work_struct *p);
 823 extern void w_wakeup_detected(struct work_struct *p);
 824
 825 #endif
 826
 827
 828 /*
 829  * The following functions support initialization of the CIL driver component
 830  * and the DWC_otg controller.
 831  */
 832 extern dwc_otg_core_if_t *dwc_otg_cil_init(const uint32_t *_reg_base_addr,
 833                                            dwc_otg_core_params_t *_core_params);
 834 extern void dwc_otg_cil_remove(dwc_otg_core_if_t *_core_if);
 835 extern void dwc_otg_core_init(dwc_otg_core_if_t *_core_if);
 836 extern void dwc_otg_core_host_init(dwc_otg_core_if_t *_core_if);
 837 extern void dwc_otg_core_dev_init(dwc_otg_core_if_t *_core_if);
 838 extern void dwc_otg_enable_global_interrupts( dwc_otg_core_if_t *_core_if );
 839 extern void dwc_otg_disable_global_interrupts( dwc_otg_core_if_t *_core_if );
 840
 841 /** @name Device CIL Functions
 842  * The following functions support managing the DWC_otg controller in device
 843  * mode.
 844  */
 845 /**@{*/
 846 extern void dwc_otg_wakeup(dwc_otg_core_if_t *_core_if);
 847 extern void dwc_otg_read_setup_packet (dwc_otg_core_if_t *_core_if, uint32_t *_dest);
 848 extern uint32_t dwc_otg_get_frame_number(dwc_otg_core_if_t *_core_if);
 849 extern void dwc_otg_ep0_activate(dwc_otg_core_if_t *_core_if, dwc_ep_t *_ep);
 850 extern void dwc_otg_ep_activate(dwc_otg_core_if_t *_core_if, dwc_ep_t *_ep);
 851 extern void dwc_otg_ep_deactivate(dwc_otg_core_if_t *_core_if, dwc_ep_t *_ep);
 852 extern void dwc_otg_ep_start_transfer(dwc_otg_core_if_t *_core_if, dwc_ep_t *_ep);
 853 extern void dwc_otg_ep_start_zl_transfer(dwc_otg_core_if_t *_core_if, dwc_ep_t *_ep);
 854 extern void dwc_otg_ep0_start_transfer(dwc_otg_core_if_t *_core_if, dwc_ep_t *_ep);
 855 extern void dwc_otg_ep0_continue_transfer(dwc_otg_core_if_t *_core_if, dwc_ep_t *_ep);
 856 extern void dwc_otg_ep_write_packet(dwc_otg_core_if_t *_core_if, dwc_ep_t *_ep, int _dma);
 857 extern void dwc_otg_ep_set_stall(dwc_otg_core_if_t *_core_if, dwc_ep_t *_ep);
 858 extern void dwc_otg_ep_clear_stall(dwc_otg_core_if_t *_core_if, dwc_ep_t *_ep);
 859 extern void dwc_otg_enable_device_interrupts(dwc_otg_core_if_t *_core_if);
 860 extern void dwc_otg_dump_dev_registers(dwc_otg_core_if_t *_core_if);
 861 extern void dwc_otg_dump_spram(dwc_otg_core_if_t *_core_if);
 862 #ifdef DWC_EN_ISOC
 863 extern void dwc_otg_iso_ep_start_frm_transfer(dwc_otg_core_if_t *core_if, dwc_ep_t *ep);
 864 extern void dwc_otg_iso_ep_start_buf_transfer(dwc_otg_core_if_t *core_if, dwc_ep_t *ep);
 865 #endif //DWC_EN_ISOC
 866 /**@}*/
 867
 868 /** @name Host CIL Functions
 869  * The following functions support managing the DWC_otg controller in host
 870  * mode.
 871  */
 872 /**@{*/
 873 extern void dwc_otg_hc_init(dwc_otg_core_if_t *_core_if, dwc_hc_t *_hc);
 874 extern void dwc_otg_hc_halt(dwc_otg_core_if_t *_core_if,
 875                                 dwc_hc_t *_hc,
 876                                 dwc_otg_halt_status_e _halt_status);
 877 extern void dwc_otg_hc_cleanup(dwc_otg_core_if_t *_core_if, dwc_hc_t *_hc);
 878 extern void dwc_otg_hc_start_transfer(dwc_otg_core_if_t *_core_if, dwc_hc_t *_hc);
 879 extern int dwc_otg_hc_continue_transfer(dwc_otg_core_if_t *_core_if, dwc_hc_t *_hc);
 880 extern void dwc_otg_hc_do_ping(dwc_otg_core_if_t *_core_if, dwc_hc_t *_hc);
 881 extern void dwc_otg_hc_write_packet(dwc_otg_core_if_t *_core_if, dwc_hc_t *_hc);
 882 extern void dwc_otg_enable_host_interrupts(dwc_otg_core_if_t *_core_if);
 883 extern void dwc_otg_disable_host_interrupts(dwc_otg_core_if_t *_core_if);
 884
 885 /**
 886  * This function Reads HPRT0 in preparation to modify.  It keeps the
 887  * WC bits 0 so that if they are read as 1, they won't clear when you
 888  * write it back
 889  */
 890 static inline uint32_t dwc_otg_read_hprt0(dwc_otg_core_if_t *_core_if)
 891 {
 892         hprt0_data_t hprt0;
 893         hprt0.d32 = dwc_read_reg32(_core_if->host_if->hprt0);
 894         hprt0.b.prtena = 0;
 895         hprt0.b.prtconndet = 0;
 896         hprt0.b.prtenchng = 0;
 897         hprt0.b.prtovrcurrchng = 0;
 898         return hprt0.d32;
 899 }
 900
 901 extern void dwc_otg_dump_host_registers(dwc_otg_core_if_t *_core_if);
 902 /**@}*/
 903
 904 /** @name Common CIL Functions
 905  * The following functions support managing the DWC_otg controller in either
 906  * device or host mode.
 907  */
 908 /**@{*/
 909
 910 extern void dwc_otg_read_packet(dwc_otg_core_if_t *core_if,
 911                                 uint8_t *dest,
 912                                 uint16_t bytes);
 913
 914 extern void dwc_otg_dump_global_registers(dwc_otg_core_if_t *_core_if);
 915
 916 extern void dwc_otg_flush_tx_fifo( dwc_otg_core_if_t *_core_if,
 917                                                                    const int _num );
 918 extern void dwc_otg_flush_rx_fifo( dwc_otg_core_if_t *_core_if );
 919 extern void dwc_otg_core_reset( dwc_otg_core_if_t *_core_if );
 920
 921 extern dwc_otg_dma_desc_t* dwc_otg_ep_alloc_desc_chain(uint32_t * dma_desc_addr, uint32_t count);
 922 extern void dwc_otg_ep_free_desc_chain(dwc_otg_dma_desc_t* desc_addr, uint32_t dma_desc_addr, uint32_t count);
 923
 924 /**
 925  * This function returns the Core Interrupt register.
 926  */
 927 static inline uint32_t dwc_otg_read_core_intr(dwc_otg_core_if_t *_core_if)
 928 {
 929         return (dwc_read_reg32(&_core_if->core_global_regs->gintsts) &
 930                 dwc_read_reg32(&_core_if->core_global_regs->gintmsk));
 931 }
 932
 933 /**
 934  * This function returns the OTG Interrupt register.
 935  */
 936 static inline uint32_t dwc_otg_read_otg_intr (dwc_otg_core_if_t *_core_if)
 937 {
 938         return (dwc_read_reg32 (&_core_if->core_global_regs->gotgint));
 939 }
 940
 941 /**
 942  * This function reads the Device All Endpoints Interrupt register and
 943  * returns the IN endpoint interrupt bits.
 944  */
 945 static inline uint32_t dwc_otg_read_dev_all_in_ep_intr(dwc_otg_core_if_t *core_if)
 946 {
 947         uint32_t v;
 948
 949         if(core_if->multiproc_int_enable) {
 950                 v = dwc_read_reg32(&core_if->dev_if->dev_global_regs->deachint) &
 951                                 dwc_read_reg32(&core_if->dev_if->dev_global_regs->deachintmsk);
 952         } else {
 953                 v = dwc_read_reg32(&core_if->dev_if->dev_global_regs->daint) &
 954                                 dwc_read_reg32(&core_if->dev_if->dev_global_regs->daintmsk);
 955         }
 956         return (v & 0xffff);
 957
 958 }
 959
 960 /**
 961  * This function reads the Device All Endpoints Interrupt register and
 962  * returns the OUT endpoint interrupt bits.
 963  */
 964 static inline uint32_t dwc_otg_read_dev_all_out_ep_intr(dwc_otg_core_if_t *core_if)
 965 {
 966         uint32_t v;
 967
 968         if(core_if->multiproc_int_enable) {
 969                 v = dwc_read_reg32(&core_if->dev_if->dev_global_regs->deachint) &
 970                                 dwc_read_reg32(&core_if->dev_if->dev_global_regs->deachintmsk);
 971         } else {
 972                 v = dwc_read_reg32(&core_if->dev_if->dev_global_regs->daint) &
 973                                 dwc_read_reg32(&core_if->dev_if->dev_global_regs->daintmsk);
 974         }
 975
 976         return ((v & 0xffff0000) >> 16);
 977 }
 978
 979 /**
 980  * This function returns the Device IN EP Interrupt register
 981  */
 982 static inline uint32_t dwc_otg_read_dev_in_ep_intr(dwc_otg_core_if_t *core_if,
 983                                                         dwc_ep_t *ep)
 984 {
 985         dwc_otg_dev_if_t *dev_if = core_if->dev_if;
 986         uint32_t v, msk, emp;
 987
 988         if(core_if->multiproc_int_enable) {
 989                 msk = dwc_read_reg32(&dev_if->dev_global_regs->diepeachintmsk[ep->num]);
 990                 emp = dwc_read_reg32(&dev_if->dev_global_regs->dtknqr4_fifoemptymsk);
 991                 msk |= ((emp >> ep->num) & 0x1) << 7;
 992                 v = dwc_read_reg32(&dev_if->in_ep_regs[ep->num]->diepint) & msk;
 993         } else {
 994                 msk = dwc_read_reg32(&dev_if->dev_global_regs->diepmsk);
 995                 emp = dwc_read_reg32(&dev_if->dev_global_regs->dtknqr4_fifoemptymsk);
 996                 msk |= ((emp >> ep->num) & 0x1) << 7;
 997                 v = dwc_read_reg32(&dev_if->in_ep_regs[ep->num]->diepint) & msk;
 998         }
 999
1000
1001         return v;
1002 }
1003 /**
1004  * This function returns the Device OUT EP Interrupt register
1005  */
1006 static inline uint32_t dwc_otg_read_dev_out_ep_intr(dwc_otg_core_if_t *_core_if,
1007                                                         dwc_ep_t *_ep)
1008 {
1009         dwc_otg_dev_if_t *dev_if = _core_if->dev_if;
1010         uint32_t v;
1011         doepmsk_data_t msk = { .d32 = 0 };
1012
1013         if(_core_if->multiproc_int_enable) {
1014                 msk.d32 = dwc_read_reg32(&dev_if->dev_global_regs->doepeachintmsk[_ep->num]);
1015                 if(_core_if->pti_enh_enable) {
1016                         msk.b.pktdrpsts = 1;
1017                 }
1018                 v = dwc_read_reg32( &dev_if->out_ep_regs[_ep->num]->doepint) & msk.d32;
1019         } else {
1020                 msk.d32 = dwc_read_reg32(&dev_if->dev_global_regs->doepmsk);
1021                 if(_core_if->pti_enh_enable) {
1022                         msk.b.pktdrpsts = 1;
1023                 }
1024                 v = dwc_read_reg32( &dev_if->out_ep_regs[_ep->num]->doepint) & msk.d32;
1025         }
1026         return v;
1027 }
1028
1029 /**
1030  * This function returns the Host All Channel Interrupt register
1031  */
1032 static inline uint32_t dwc_otg_read_host_all_channels_intr (dwc_otg_core_if_t *_core_if)
1033 {
1034         return (dwc_read_reg32 (&_core_if->host_if->host_global_regs->haint));
1035 }
1036
1037 static inline uint32_t dwc_otg_read_host_channel_intr (dwc_otg_core_if_t *_core_if, dwc_hc_t *_hc)
1038 {
1039         return (dwc_read_reg32 (&_core_if->host_if->hc_regs[_hc->hc_num]->hcint));
1040 }
1041
1042
1043 /**
1044  * This function returns the mode of the operation, host or device.
1045  *
1046  * @return 0 - Device Mode, 1 - Host Mode
1047  */
1048 static inline uint32_t dwc_otg_mode(dwc_otg_core_if_t *_core_if)
1049 {
1050         return (dwc_read_reg32( &_core_if->core_global_regs->gintsts ) & 0x1);
1051 }
1052
1053 static inline uint8_t dwc_otg_is_device_mode(dwc_otg_core_if_t *_core_if)
1054 {
1055         return (dwc_otg_mode(_core_if) != DWC_HOST_MODE);
1056 }
1057 static inline uint8_t dwc_otg_is_host_mode(dwc_otg_core_if_t *_core_if)
1058 {
1059         return (dwc_otg_mode(_core_if) == DWC_HOST_MODE);
1060 }
1061
1062 extern int32_t dwc_otg_handle_common_intr( dwc_otg_core_if_t *_core_if );
1063
1064
1065 /**@}*/
1066
1067 /**
1068  * DWC_otg CIL callback structure.      This structure allows the HCD and
1069  * PCD to register functions used for starting and stopping the PCD
1070  * and HCD for role change on for a DRD.
1071  */
1072 typedef struct dwc_otg_cil_callbacks
1073 {
1074         /** Start function for role change */
1075         int (*start) (void *_p);
1076         /** Stop Function for role change */
1077         int (*stop) (void *_p);
1078         /** Disconnect Function for role change */
1079         int (*disconnect) (void *_p);
1080         /** Resume/Remote wakeup Function */
1081         int (*resume_wakeup) (void *_p);
1082         /** Suspend function */
1083         int (*suspend) (void *_p);
1084         /** Session Start (SRP) */
1085         int (*session_start) (void *_p);
1086         /** Pointer passed to start() and stop() */
1087         void *p;
1088 } dwc_otg_cil_callbacks_t;
1089
1090 extern void dwc_otg_cil_register_pcd_callbacks( dwc_otg_core_if_t *_core_if,
1091                                                 dwc_otg_cil_callbacks_t *_cb,
1092                                                 void *_p);
1093 extern void dwc_otg_cil_register_hcd_callbacks( dwc_otg_core_if_t *_core_if,
1094                                                 dwc_otg_cil_callbacks_t *_cb,
1095                                                 void *_p);
1096
1097 #endif
1098