target/linux/ramips/files/drivers/usb/dwc_otg/dwc_otg_driver.c

   1 /* ==========================================================================
   2  * $File: //dwh/usb_iip/dev/software/otg_ipmate/linux/drivers/dwc_otg_driver.c $
   3  * $Revision: 1.7 $
   4  * $Date: 2008-11-21 05:39:15 $
   5  * $Change: 791271 $
   6  *
   7  * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
   8  * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
   9  * otherwise expressly agreed to in writing between Synopsys and you.
  10  *
  11  * The Software IS NOT an item of Licensed Software or Licensed Product under
  12  * any End User Software License Agreement or Agreement for Licensed Product
  13  * with Synopsys or any supplement thereto. You are permitted to use and
  14  * redistribute this Software in source and binary forms, with or without
  15  * modification, provided that redistributions of source code must retain this
  16  * notice. You may not view, use, disclose, copy or distribute this file or
  17  * any information contained herein except pursuant to this license grant from
  18  * Synopsys. If you do not agree with this notice, including the disclaimer
  19  * below, then you are not authorized to use the Software.
  20  *
  21  * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
  22  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  23  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  24  * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
  25  * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  26  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
  27  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
  28  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  29  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  30  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
  31  * DAMAGE.
  32  * ========================================================================== */
  33
  34 /** @file
  35  * The dwc_otg_driver module provides the initialization and cleanup entry
  36  * points for the DWC_otg driver. This module will be dynamically installed
  37  * after Linux is booted using the insmod command. When the module is
  38  * installed, the dwc_otg_driver_init function is called. When the module is
  39  * removed (using rmmod), the dwc_otg_driver_cleanup function is called.
  40  *
  41  * This module also defines a data structure for the dwc_otg_driver, which is
  42  * used in conjunction with the standard ARM platform_device structure. These
  43  * structures allow the OTG driver to comply with the standard Linux driver
  44  * model in which devices and drivers are registered with a bus driver. This
  45  * has the benefit that Linux can expose attributes of the driver and device
  46  * in its special sysfs file system. Users can then read or write files in
  47  * this file system to perform diagnostics on the driver components or the
  48  * device.
  49  */
  50
  51 #include <linux/kernel.h>
  52 #include <linux/module.h>
  53 #include <linux/moduleparam.h>
  54 #include <linux/init.h>
  55 #include <linux/device.h>
  56 #include <linux/errno.h>
  57 #include <linux/types.h>
  58 #include <linux/stat.h>  /* permission constants */
  59 #include <linux/version.h>
  60 #include <linux/platform_device.h>
  61
  62 #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20)
  63 # include <linux/irq.h>
  64 #endif
  65
  66 #include <asm/io.h>
  67
  68 #if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,20)
  69 # include <asm/irq.h>
  70 #endif
  71
  72 #include "linux/dwc_otg_plat.h"
  73 #include "dwc_otg_attr.h"
  74 #include "dwc_otg_driver.h"
  75 #include "dwc_otg_cil.h"
  76 #include "dwc_otg_pcd.h"
  77 #include "dwc_otg_hcd.h"
  78
  79 #define DWC_DRIVER_VERSION      "2.72a 24-JUN-2008"
  80 #define DWC_DRIVER_DESC         "HS OTG USB Controller driver"
  81
  82 static const char dwc_driver_name[] = "dwc_otg";
  83
  84 /*-------------------------------------------------------------------------*/
  85 /* Encapsulate the module parameter settings */
  86
  87 static dwc_otg_core_params_t dwc_otg_module_params = {
  88         .opt = -1,
  89         .otg_cap = -1,
  90         .dma_enable = -1,
  91         .dma_desc_enable = -1,
  92         .dma_burst_size = -1,
  93         .speed = -1,
  94         .host_support_fs_ls_low_power = -1,
  95         .host_ls_low_power_phy_clk = -1,
  96         .enable_dynamic_fifo = -1,
  97         .data_fifo_size = -1,
  98         .dev_rx_fifo_size = -1,
  99         .dev_nperio_tx_fifo_size = -1,
 100         .dev_perio_tx_fifo_size = {
 101                 /* dev_perio_tx_fifo_size_1 */
 102                 -1,
 103                 -1,
 104                 -1,
 105                 -1,
 106                 -1,
 107                 -1,
 108                 -1,
 109                 -1,
 110                 -1,
 111                 -1,
 112                 -1,
 113                 -1,
 114                 -1,
 115                 -1,
 116                 -1
 117                 /* 15 */
 118         },
 119         .host_rx_fifo_size = -1,
 120         .host_nperio_tx_fifo_size = -1,
 121         .host_perio_tx_fifo_size = -1,
 122         .max_transfer_size = -1,
 123         .max_packet_count = -1,
 124         .host_channels = -1,
 125         .dev_endpoints = -1,
 126         .phy_type = -1,
 127         .phy_utmi_width = -1,
 128         .phy_ulpi_ddr = -1,
 129         .phy_ulpi_ext_vbus = -1,
 130         .i2c_enable = -1,
 131         .ulpi_fs_ls = -1,
 132         .ts_dline = -1,
 133         .en_multiple_tx_fifo = -1,
 134         .dev_tx_fifo_size = {
 135                 /* dev_tx_fifo_size */
 136                 -1,
 137                 -1,
 138                 -1,
 139                 -1,
 140                 -1,
 141                 -1,
 142                 -1,
 143                 -1,
 144                 -1,
 145                 -1,
 146                 -1,
 147                 -1,
 148                 -1,
 149                 -1,
 150                 -1
 151                 /* 15 */
 152         },
 153         .thr_ctl = -1,
 154         .tx_thr_length = -1,
 155         .rx_thr_length = -1,
 156         .pti_enable = -1,
 157         .mpi_enable = -1,
 158 };
 159
 160 /**
 161  * This function shows the Driver Version.
 162  */
 163 static ssize_t version_show(struct device_driver *dev, char *buf)
 164 {
 165         return snprintf(buf, sizeof(DWC_DRIVER_VERSION)+2, "%s\n",
 166                         DWC_DRIVER_VERSION);
 167 }
 168 static DRIVER_ATTR(version, S_IRUGO, version_show, NULL);
 169
 170 /**
 171  * Global Debug Level Mask.
 172  */
 173 uint32_t g_dbg_lvl = 0; /* OFF */
 174
 175 /**
 176  * This function shows the driver Debug Level.
 177  */
 178 static ssize_t dbg_level_show(struct device_driver *drv, char *buf)
 179 {
 180         return sprintf(buf, "0x%0x\n", g_dbg_lvl);
 181 }
 182
 183 /**
 184  * This function stores the driver Debug Level.
 185  */
 186 static ssize_t dbg_level_store(struct device_driver *drv, const char *buf,
 187                                size_t count)
 188 {
 189         g_dbg_lvl = simple_strtoul(buf, NULL, 16);
 190                 return count;
 191 }
 192 static DRIVER_ATTR(debuglevel, S_IRUGO|S_IWUSR, dbg_level_show, dbg_level_store);
 193
 194 /**
 195  * This function is called during module intialization to verify that
 196  * the module parameters are in a valid state.
 197  */
 198 static int check_parameters(dwc_otg_core_if_t *core_if)
 199 {
 200         int i;
 201         int retval = 0;
 202
 203 /* Checks if the parameter is outside of its valid range of values */
 204 #define DWC_OTG_PARAM_TEST(_param_, _low_, _high_) \
 205                 ((dwc_otg_module_params._param_ < (_low_)) || \
 206                 (dwc_otg_module_params._param_ > (_high_)))
 207
 208 /* If the parameter has been set by the user, check that the parameter value is
 209  * within the value range of values.  If not, report a module error. */
 210 #define DWC_OTG_PARAM_ERR(_param_, _low_, _high_, _string_) \
 211                 do { \
 212                         if (dwc_otg_module_params._param_ != -1) { \
 213                                 if (DWC_OTG_PARAM_TEST(_param_, (_low_), (_high_))) { \
 214                                         DWC_ERROR("`%d' invalid for parameter `%s'\n", \
 215                                                   dwc_otg_module_params._param_, _string_); \
 216                                         dwc_otg_module_params._param_ = dwc_param_##_param_##_default; \
 217                                         retval++; \
 218                                 } \
 219                         } \
 220                 } while (0)
 221
 222         DWC_OTG_PARAM_ERR(opt,0,1,"opt");
 223         DWC_OTG_PARAM_ERR(otg_cap,0,2,"otg_cap");
 224         DWC_OTG_PARAM_ERR(dma_enable,0,1,"dma_enable");
 225         DWC_OTG_PARAM_ERR(dma_desc_enable,0,1,"dma_desc_enable");
 226         DWC_OTG_PARAM_ERR(speed,0,1,"speed");
 227         DWC_OTG_PARAM_ERR(host_support_fs_ls_low_power,0,1,"host_support_fs_ls_low_power");
 228         DWC_OTG_PARAM_ERR(host_ls_low_power_phy_clk,0,1,"host_ls_low_power_phy_clk");
 229         DWC_OTG_PARAM_ERR(enable_dynamic_fifo,0,1,"enable_dynamic_fifo");
 230         DWC_OTG_PARAM_ERR(data_fifo_size,32,32768,"data_fifo_size");
 231         DWC_OTG_PARAM_ERR(dev_rx_fifo_size,16,32768,"dev_rx_fifo_size");
 232         DWC_OTG_PARAM_ERR(dev_nperio_tx_fifo_size,16,32768,"dev_nperio_tx_fifo_size");
 233         DWC_OTG_PARAM_ERR(host_rx_fifo_size,16,32768,"host_rx_fifo_size");
 234         DWC_OTG_PARAM_ERR(host_nperio_tx_fifo_size,16,32768,"host_nperio_tx_fifo_size");
 235         DWC_OTG_PARAM_ERR(host_perio_tx_fifo_size,16,32768,"host_perio_tx_fifo_size");
 236         DWC_OTG_PARAM_ERR(max_transfer_size,2047,524288,"max_transfer_size");
 237         DWC_OTG_PARAM_ERR(max_packet_count,15,511,"max_packet_count");
 238         DWC_OTG_PARAM_ERR(host_channels,1,16,"host_channels");
 239         DWC_OTG_PARAM_ERR(dev_endpoints,1,15,"dev_endpoints");
 240         DWC_OTG_PARAM_ERR(phy_type,0,2,"phy_type");
 241         DWC_OTG_PARAM_ERR(phy_ulpi_ddr,0,1,"phy_ulpi_ddr");
 242         DWC_OTG_PARAM_ERR(phy_ulpi_ext_vbus,0,1,"phy_ulpi_ext_vbus");
 243         DWC_OTG_PARAM_ERR(i2c_enable,0,1,"i2c_enable");
 244         DWC_OTG_PARAM_ERR(ulpi_fs_ls,0,1,"ulpi_fs_ls");
 245         DWC_OTG_PARAM_ERR(ts_dline,0,1,"ts_dline");
 246
 247         if (dwc_otg_module_params.dma_burst_size != -1) {
 248                 if (DWC_OTG_PARAM_TEST(dma_burst_size,1,1) &&
 249                     DWC_OTG_PARAM_TEST(dma_burst_size,4,4) &&
 250                     DWC_OTG_PARAM_TEST(dma_burst_size,8,8) &&
 251                     DWC_OTG_PARAM_TEST(dma_burst_size,16,16) &&
 252                     DWC_OTG_PARAM_TEST(dma_burst_size,32,32) &&
 253                     DWC_OTG_PARAM_TEST(dma_burst_size,64,64) &&
 254                     DWC_OTG_PARAM_TEST(dma_burst_size,128,128) &&
 255                     DWC_OTG_PARAM_TEST(dma_burst_size,256,256)) {
 256                         DWC_ERROR("`%d' invalid for parameter `dma_burst_size'\n",
 257                                   dwc_otg_module_params.dma_burst_size);
 258                         dwc_otg_module_params.dma_burst_size = 32;
 259                         retval++;
 260                 }
 261
 262                 {
 263                         uint8_t brst_sz = 0;
 264                         while(dwc_otg_module_params.dma_burst_size > 1) {
 265                                 brst_sz ++;
 266                                 dwc_otg_module_params.dma_burst_size >>= 1;
 267                         }
 268                         dwc_otg_module_params.dma_burst_size = brst_sz;
 269                 }
 270         }
 271
 272         if (dwc_otg_module_params.phy_utmi_width != -1) {
 273                 if (DWC_OTG_PARAM_TEST(phy_utmi_width, 8, 8) &&
 274                     DWC_OTG_PARAM_TEST(phy_utmi_width, 16, 16)) {
 275                         DWC_ERROR("`%d' invalid for parameter `phy_utmi_width'\n",
 276                                   dwc_otg_module_params.phy_utmi_width);
 277                         dwc_otg_module_params.phy_utmi_width = 16;
 278                         retval++;
 279                 }
 280         }
 281
 282         for (i = 0; i < 15; i++) {
 283                 /** @todo should be like above */
 284                 //DWC_OTG_PARAM_ERR(dev_perio_tx_fifo_size[i], 4, 768, "dev_perio_tx_fifo_size");
 285                 if (dwc_otg_module_params.dev_perio_tx_fifo_size[i] != -1) {
 286                         if (DWC_OTG_PARAM_TEST(dev_perio_tx_fifo_size[i], 4, 768)) {
 287                                 DWC_ERROR("`%d' invalid for parameter `%s_%d'\n",
 288                                           dwc_otg_module_params.dev_perio_tx_fifo_size[i], "dev_perio_tx_fifo_size", i);
 289                                 dwc_otg_module_params.dev_perio_tx_fifo_size[i] = dwc_param_dev_perio_tx_fifo_size_default;
 290                                 retval++;
 291                         }
 292                 }
 293         }
 294
 295         DWC_OTG_PARAM_ERR(en_multiple_tx_fifo, 0, 1, "en_multiple_tx_fifo");
 296
 297         for (i = 0; i < 15; i++) {
 298                 /** @todo should be like above */
 299                 //DWC_OTG_PARAM_ERR(dev_tx_fifo_size[i], 4, 768, "dev_tx_fifo_size");
 300                 if (dwc_otg_module_params.dev_tx_fifo_size[i] != -1) {
 301                         if (DWC_OTG_PARAM_TEST(dev_tx_fifo_size[i], 4, 768)) {
 302                                 DWC_ERROR("`%d' invalid for parameter `%s_%d'\n",
 303                                           dwc_otg_module_params.dev_tx_fifo_size[i], "dev_tx_fifo_size", i);
 304                                 dwc_otg_module_params.dev_tx_fifo_size[i] = dwc_param_dev_tx_fifo_size_default;
 305                                 retval++;
 306                         }
 307                 }
 308         }
 309
 310         DWC_OTG_PARAM_ERR(thr_ctl, 0, 7, "thr_ctl");
 311         DWC_OTG_PARAM_ERR(tx_thr_length, 8, 128, "tx_thr_length");
 312         DWC_OTG_PARAM_ERR(rx_thr_length, 8, 128, "rx_thr_length");
 313
 314         DWC_OTG_PARAM_ERR(pti_enable,0,1,"pti_enable");
 315         DWC_OTG_PARAM_ERR(mpi_enable,0,1,"mpi_enable");
 316
 317         /* At this point, all module parameters that have been set by the user
 318          * are valid, and those that have not are left unset.  Now set their
 319          * default values and/or check the parameters against the hardware
 320          * configurations of the OTG core. */
 321
 322 /* This sets the parameter to the default value if it has not been set by the
 323  * user */
 324 #define DWC_OTG_PARAM_SET_DEFAULT(_param_) \
 325         ({ \
 326                 int changed = 1; \
 327                 if (dwc_otg_module_params._param_ == -1) { \
 328                         changed = 0; \
 329                         dwc_otg_module_params._param_ = dwc_param_##_param_##_default; \
 330                 } \
 331                 changed; \
 332         })
 333
 334 /* This checks the macro agains the hardware configuration to see if it is
 335  * valid.  It is possible that the default value could be invalid. In this
 336  * case, it will report a module error if the user touched the parameter.
 337  * Otherwise it will adjust the value without any error. */
 338 #define DWC_OTG_PARAM_CHECK_VALID(_param_, _str_, _is_valid_, _set_valid_) \
 339         ({ \
 340                 int changed = DWC_OTG_PARAM_SET_DEFAULT(_param_); \
 341                 int error = 0; \
 342                 if (!(_is_valid_)) { \
 343                         if (changed) { \
 344                                 DWC_ERROR("`%d' invalid for parameter `%s'. Check HW configuration.\n", dwc_otg_module_params._param_, _str_); \
 345                                 error = 1; \
 346                         } \
 347                         dwc_otg_module_params._param_ = (_set_valid_); \
 348                 } \
 349                 error; \
 350         })
 351
 352         /* OTG Cap */
 353         retval += DWC_OTG_PARAM_CHECK_VALID(otg_cap, "otg_cap",
 354                                 ({
 355                                         int valid;
 356                                         valid = 1;
 357                                         switch (dwc_otg_module_params.otg_cap) {
 358                                         case DWC_OTG_CAP_PARAM_HNP_SRP_CAPABLE:
 359                                                 if (core_if->hwcfg2.b.op_mode != DWC_HWCFG2_OP_MODE_HNP_SRP_CAPABLE_OTG)
 360                                                         valid = 0;
 361                                                 break;
 362                                         case DWC_OTG_CAP_PARAM_SRP_ONLY_CAPABLE:
 363                                                 if ((core_if->hwcfg2.b.op_mode != DWC_HWCFG2_OP_MODE_HNP_SRP_CAPABLE_OTG) &&
 364                                                     (core_if->hwcfg2.b.op_mode != DWC_HWCFG2_OP_MODE_SRP_ONLY_CAPABLE_OTG) &&
 365                                                     (core_if->hwcfg2.b.op_mode != DWC_HWCFG2_OP_MODE_SRP_CAPABLE_DEVICE) &&
 366                                                     (core_if->hwcfg2.b.op_mode != DWC_HWCFG2_OP_MODE_SRP_CAPABLE_HOST)) {
 367                                                         valid = 0;
 368                                                 }
 369                                                 break;
 370                                         case DWC_OTG_CAP_PARAM_NO_HNP_SRP_CAPABLE:
 371                                                 /* always valid */
 372                                                 break;
 373                                         }
 374                                         valid;
 375                                 }),
 376                                 (((core_if->hwcfg2.b.op_mode == DWC_HWCFG2_OP_MODE_HNP_SRP_CAPABLE_OTG) ||
 377                                   (core_if->hwcfg2.b.op_mode == DWC_HWCFG2_OP_MODE_SRP_ONLY_CAPABLE_OTG) ||
 378                                   (core_if->hwcfg2.b.op_mode == DWC_HWCFG2_OP_MODE_SRP_CAPABLE_DEVICE) ||
 379                                   (core_if->hwcfg2.b.op_mode == DWC_HWCFG2_OP_MODE_SRP_CAPABLE_HOST)) ?
 380                                  DWC_OTG_CAP_PARAM_SRP_ONLY_CAPABLE :
 381                                  DWC_OTG_CAP_PARAM_NO_HNP_SRP_CAPABLE));
 382
 383         retval += DWC_OTG_PARAM_CHECK_VALID(dma_enable, "dma_enable",
 384                                 ((dwc_otg_module_params.dma_enable == 1) && (core_if->hwcfg2.b.architecture == 0)) ? 0 : 1,
 385                                 0);
 386
 387         retval += DWC_OTG_PARAM_CHECK_VALID(dma_desc_enable, "dma_desc_enable",
 388                                 ((dwc_otg_module_params.dma_desc_enable == 1) &&
 389                                  ((dwc_otg_module_params.dma_enable == 0) || (core_if->hwcfg4.b.desc_dma == 0))) ? 0 : 1,
 390                                 0);
 391
 392         retval += DWC_OTG_PARAM_CHECK_VALID(opt, "opt", 1, 0);
 393
 394         DWC_OTG_PARAM_SET_DEFAULT(dma_burst_size);
 395
 396         retval += DWC_OTG_PARAM_CHECK_VALID(host_support_fs_ls_low_power,
 397                                 "host_support_fs_ls_low_power",
 398                                 1, 0);
 399
 400         retval += DWC_OTG_PARAM_CHECK_VALID(enable_dynamic_fifo,
 401                                         "enable_dynamic_fifo",
 402                                         ((dwc_otg_module_params.enable_dynamic_fifo == 0) ||
 403                                         (core_if->hwcfg2.b.dynamic_fifo == 1)), 0);
 404
 405         retval += DWC_OTG_PARAM_CHECK_VALID(data_fifo_size,
 406                                         "data_fifo_size",
 407                                         (dwc_otg_module_params.data_fifo_size <= core_if->hwcfg3.b.dfifo_depth),
 408                                         core_if->hwcfg3.b.dfifo_depth);
 409
 410         retval += DWC_OTG_PARAM_CHECK_VALID(dev_rx_fifo_size,
 411                                         "dev_rx_fifo_size",
 412                                         (dwc_otg_module_params.dev_rx_fifo_size <= dwc_read_reg32(&core_if->core_global_regs->grxfsiz)),
 413                                         dwc_read_reg32(&core_if->core_global_regs->grxfsiz));
 414
 415         retval += DWC_OTG_PARAM_CHECK_VALID(dev_nperio_tx_fifo_size,
 416                                         "dev_nperio_tx_fifo_size",
 417                                         (dwc_otg_module_params.dev_nperio_tx_fifo_size <= (dwc_read_reg32(&core_if->core_global_regs->gnptxfsiz) >> 16)),
 418                                         (dwc_read_reg32(&core_if->core_global_regs->gnptxfsiz) >> 16));
 419
 420         retval += DWC_OTG_PARAM_CHECK_VALID(host_rx_fifo_size,
 421                                         "host_rx_fifo_size",
 422                                         (dwc_otg_module_params.host_rx_fifo_size <= dwc_read_reg32(&core_if->core_global_regs->grxfsiz)),
 423                                         dwc_read_reg32(&core_if->core_global_regs->grxfsiz));
 424
 425         retval += DWC_OTG_PARAM_CHECK_VALID(host_nperio_tx_fifo_size,
 426                                         "host_nperio_tx_fifo_size",
 427                                         (dwc_otg_module_params.host_nperio_tx_fifo_size <= (dwc_read_reg32(&core_if->core_global_regs->gnptxfsiz) >> 16)),
 428                                         (dwc_read_reg32(&core_if->core_global_regs->gnptxfsiz) >> 16));
 429
 430         retval += DWC_OTG_PARAM_CHECK_VALID(host_perio_tx_fifo_size,
 431                                         "host_perio_tx_fifo_size",
 432                                         (dwc_otg_module_params.host_perio_tx_fifo_size <= ((dwc_read_reg32(&core_if->core_global_regs->hptxfsiz) >> 16))),
 433                                         ((dwc_read_reg32(&core_if->core_global_regs->hptxfsiz) >> 16)));
 434
 435         retval += DWC_OTG_PARAM_CHECK_VALID(max_transfer_size,
 436                                         "max_transfer_size",
 437                                         (dwc_otg_module_params.max_transfer_size < (1 << (core_if->hwcfg3.b.xfer_size_cntr_width + 11))),
 438                                         ((1 << (core_if->hwcfg3.b.xfer_size_cntr_width + 11)) - 1));
 439
 440         retval += DWC_OTG_PARAM_CHECK_VALID(max_packet_count,
 441                                         "max_packet_count",
 442                                         (dwc_otg_module_params.max_packet_count < (1 << (core_if->hwcfg3.b.packet_size_cntr_width + 4))),
 443                                         ((1 << (core_if->hwcfg3.b.packet_size_cntr_width + 4)) - 1));
 444
 445         retval += DWC_OTG_PARAM_CHECK_VALID(host_channels,
 446                                         "host_channels",
 447                                         (dwc_otg_module_params.host_channels <= (core_if->hwcfg2.b.num_host_chan + 1)),
 448                                         (core_if->hwcfg2.b.num_host_chan + 1));
 449
 450         retval += DWC_OTG_PARAM_CHECK_VALID(dev_endpoints,
 451                                         "dev_endpoints",
 452                                         (dwc_otg_module_params.dev_endpoints <= (core_if->hwcfg2.b.num_dev_ep)),
 453                                         core_if->hwcfg2.b.num_dev_ep);
 454
 455 /*
 456  * Define the following to disable the FS PHY Hardware checking.  This is for
 457  * internal testing only.
 458  *
 459  * #define NO_FS_PHY_HW_CHECKS
 460  */
 461
 462 #ifdef NO_FS_PHY_HW_CHECKS
 463         retval += DWC_OTG_PARAM_CHECK_VALID(phy_type,
 464                                 "phy_type", 1, 0);
 465 #else
 466         retval += DWC_OTG_PARAM_CHECK_VALID(phy_type,
 467                                 "phy_type",
 468                                 ({
 469                                         int valid = 0;
 470                                         if ((dwc_otg_module_params.phy_type == DWC_PHY_TYPE_PARAM_UTMI) &&
 471                                         ((core_if->hwcfg2.b.hs_phy_type == 1) ||
 472                                          (core_if->hwcfg2.b.hs_phy_type == 3))) {
 473                                                 valid = 1;
 474                                         }
 475                                         else if ((dwc_otg_module_params.phy_type == DWC_PHY_TYPE_PARAM_ULPI) &&
 476                                                  ((core_if->hwcfg2.b.hs_phy_type == 2) ||
 477                                                   (core_if->hwcfg2.b.hs_phy_type == 3))) {
 478                                                 valid = 1;
 479                                         }
 480                                         else if ((dwc_otg_module_params.phy_type == DWC_PHY_TYPE_PARAM_FS) &&
 481                                                  (core_if->hwcfg2.b.fs_phy_type == 1)) {
 482                                                 valid = 1;
 483                                         }
 484                                         valid;
 485                                 }),
 486                                 ({
 487                                         int set = DWC_PHY_TYPE_PARAM_FS;
 488                                         if (core_if->hwcfg2.b.hs_phy_type) {
 489                                                 if ((core_if->hwcfg2.b.hs_phy_type == 3) ||
 490                                                 (core_if->hwcfg2.b.hs_phy_type == 1)) {
 491                                                         set = DWC_PHY_TYPE_PARAM_UTMI;
 492                                                 }
 493                                                 else {
 494                                                         set = DWC_PHY_TYPE_PARAM_ULPI;
 495                                                 }
 496                                         }
 497                                         set;
 498                                 }));
 499 #endif
 500
 501         retval += DWC_OTG_PARAM_CHECK_VALID(speed, "speed",
 502                                 (dwc_otg_module_params.speed == 0) && (dwc_otg_module_params.phy_type == DWC_PHY_TYPE_PARAM_FS) ? 0 : 1,
 503                                 dwc_otg_module_params.phy_type == DWC_PHY_TYPE_PARAM_FS ? 1 : 0);
 504
 505         retval += DWC_OTG_PARAM_CHECK_VALID(host_ls_low_power_phy_clk,
 506                                 "host_ls_low_power_phy_clk",
 507                                 ((dwc_otg_module_params.host_ls_low_power_phy_clk == DWC_HOST_LS_LOW_POWER_PHY_CLK_PARAM_48MHZ) && (dwc_otg_module_params.phy_type == DWC_PHY_TYPE_PARAM_FS) ? 0 : 1),
 508                                 ((dwc_otg_module_params.phy_type == DWC_PHY_TYPE_PARAM_FS) ? DWC_HOST_LS_LOW_POWER_PHY_CLK_PARAM_6MHZ : DWC_HOST_LS_LOW_POWER_PHY_CLK_PARAM_48MHZ));
 509
 510         DWC_OTG_PARAM_SET_DEFAULT(phy_ulpi_ddr);
 511         DWC_OTG_PARAM_SET_DEFAULT(phy_ulpi_ext_vbus);
 512         DWC_OTG_PARAM_SET_DEFAULT(phy_utmi_width);
 513         DWC_OTG_PARAM_SET_DEFAULT(ulpi_fs_ls);
 514         DWC_OTG_PARAM_SET_DEFAULT(ts_dline);
 515
 516 #ifdef NO_FS_PHY_HW_CHECKS
 517         retval += DWC_OTG_PARAM_CHECK_VALID(i2c_enable, "i2c_enable", 1, 0);
 518 #else
 519         retval += DWC_OTG_PARAM_CHECK_VALID(i2c_enable,
 520                                 "i2c_enable",
 521                                 (dwc_otg_module_params.i2c_enable == 1) && (core_if->hwcfg3.b.i2c == 0) ? 0 : 1,
 522                                 0);
 523 #endif
 524
 525         for (i = 0; i < 15; i++) {
 526                 int changed = 1;
 527                 int error = 0;
 528
 529                 if (dwc_otg_module_params.dev_perio_tx_fifo_size[i] == -1) {
 530                         changed = 0;
 531                         dwc_otg_module_params.dev_perio_tx_fifo_size[i] = dwc_param_dev_perio_tx_fifo_size_default;
 532                 }
 533                 if (!(dwc_otg_module_params.dev_perio_tx_fifo_size[i] <= (dwc_read_reg32(&core_if->core_global_regs->dptxfsiz_dieptxf[i])))) {
 534                         if (changed) {
 535                                 DWC_ERROR("`%d' invalid for parameter `dev_perio_fifo_size_%d'. Check HW configuration.\n", dwc_otg_module_params.dev_perio_tx_fifo_size[i], i);
 536                                 error = 1;
 537                         }
 538                         dwc_otg_module_params.dev_perio_tx_fifo_size[i] = dwc_read_reg32(&core_if->core_global_regs->dptxfsiz_dieptxf[i]);
 539                 }
 540                 retval += error;
 541         }
 542
 543         retval += DWC_OTG_PARAM_CHECK_VALID(en_multiple_tx_fifo, "en_multiple_tx_fifo",
 544                                                 ((dwc_otg_module_params.en_multiple_tx_fifo == 1) && (core_if->hwcfg4.b.ded_fifo_en == 0)) ? 0 : 1,
 545                                                 0);
 546
 547         for (i = 0; i < 15; i++) {
 548                 int changed = 1;
 549                 int error = 0;
 550
 551                 if (dwc_otg_module_params.dev_tx_fifo_size[i] == -1) {
 552                         changed = 0;
 553                         dwc_otg_module_params.dev_tx_fifo_size[i] = dwc_param_dev_tx_fifo_size_default;
 554                 }
 555                 if (!(dwc_otg_module_params.dev_tx_fifo_size[i] <= (dwc_read_reg32(&core_if->core_global_regs->dptxfsiz_dieptxf[i])))) {
 556                         if (changed) {
 557                                 DWC_ERROR("%d' invalid for parameter `dev_perio_fifo_size_%d'. Check HW configuration.\n", dwc_otg_module_params.dev_tx_fifo_size[i], i);
 558                                 error = 1;
 559                         }
 560                         dwc_otg_module_params.dev_tx_fifo_size[i] = dwc_read_reg32(&core_if->core_global_regs->dptxfsiz_dieptxf[i]);
 561                 }
 562                 retval += error;
 563         }
 564
 565         retval += DWC_OTG_PARAM_CHECK_VALID(thr_ctl, "thr_ctl",
 566                                 ((dwc_otg_module_params.thr_ctl != 0) && ((dwc_otg_module_params.dma_enable == 0) || (core_if->hwcfg4.b.ded_fifo_en == 0))) ? 0 : 1,
 567                                 0);
 568
 569         DWC_OTG_PARAM_SET_DEFAULT(tx_thr_length);
 570         DWC_OTG_PARAM_SET_DEFAULT(rx_thr_length);
 571
 572         retval += DWC_OTG_PARAM_CHECK_VALID(pti_enable, "pti_enable",
 573                 ((dwc_otg_module_params.pti_enable == 0) || ((dwc_otg_module_params.pti_enable == 1) && (core_if->snpsid >= 0x4F54272A))) ? 1 : 0,
 574                         0);
 575
 576         retval += DWC_OTG_PARAM_CHECK_VALID(mpi_enable, "mpi_enable",
 577                         ((dwc_otg_module_params.mpi_enable == 0) || ((dwc_otg_module_params.mpi_enable == 1) && (core_if->hwcfg2.b.multi_proc_int == 1))) ? 1 : 0,
 578                         0);
 579         return retval;
 580 }
 581
 582 /**
 583  * This function is the top level interrupt handler for the Common
 584  * (Device and host modes) interrupts.
 585  */
 586 static irqreturn_t dwc_otg_common_irq(int irq, void *dev
 587 #if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,19)
 588                                       , struct pt_regs *r
 589 #endif
 590                                      )
 591 {
 592         dwc_otg_device_t *otg_dev = dev;
 593         int32_t retval = IRQ_NONE;
 594
 595         retval = dwc_otg_handle_common_intr(otg_dev->core_if);
 596         return IRQ_RETVAL(retval);
 597 }
 598
 599 /**
 600  * This function is called when a platform_device is unregistered with the
 601  * dwc_otg_driver. This happens, for example, when the rmmod command is
 602  * executed. The device may or may not be electrically present. If it is
 603  * present, the driver stops device processing. Any resources used on behalf
 604  * of this device are freed.
 605  *
 606  * @param[in] pdev
 607  */
 608 static int dwc_otg_driver_remove(struct platform_device *pdev)
 609 {
 610         dwc_otg_device_t *otg_dev = platform_get_drvdata(pdev);
 611         DWC_DEBUGPL(DBG_ANY, "%s(%p)\n", __func__, pdev);
 612
 613         if (!otg_dev) {
 614                 /* Memory allocation for the dwc_otg_device failed. */
 615                 DWC_DEBUGPL(DBG_ANY, "%s: otg_dev NULL!\n", __func__);
 616                 return 0;
 617         }
 618
 619         /*
 620          * Free the IRQ
 621          */
 622         if (otg_dev->common_irq_installed) {
 623                 free_irq(otg_dev->irq, otg_dev);
 624         }
 625
 626 #ifndef DWC_DEVICE_ONLY
 627         if (otg_dev->hcd) {
 628                 dwc_otg_hcd_remove(&pdev->dev);
 629         } else {
 630                 DWC_DEBUGPL(DBG_ANY, "%s: otg_dev->hcd NULL!\n", __func__);
 631                 return 0;
 632         }
 633 #endif
 634
 635 #ifndef DWC_HOST_ONLY
 636         if (otg_dev->pcd) {
 637                 dwc_otg_pcd_remove(pdev);
 638         }
 639 #endif
 640         if (otg_dev->core_if) {
 641                 dwc_otg_cil_remove(otg_dev->core_if);
 642         }
 643
 644         /*
 645          * Remove the device attributes
 646          */
 647         dwc_otg_attr_remove(otg_dev->parent);
 648
 649         /* Disable USB port */
 650         dwc_write_reg32((uint32_t *)((uint8_t *)otg_dev->base + 0xe00), 0xf);
 651
 652         /*
 653          * Return the memory.
 654          */
 655         if (otg_dev->base) {
 656                 iounmap(otg_dev->base);
 657         }
 658
 659         if (otg_dev->phys_addr != 0) {
 660                 release_mem_region(otg_dev->phys_addr, otg_dev->base_len);
 661         }
 662
 663         kfree(otg_dev);
 664
 665         /*
 666          * Clear the drvdata pointer.
 667          */
 668         platform_set_drvdata(pdev, NULL);
 669
 670         return 0;
 671 }
 672
 673 /**
 674  * This function is called when an platform_device is bound to a
 675  * dwc_otg_driver. It creates the driver components required to
 676  * control the device (CIL, HCD, and PCD) and it initializes the
 677  * device. The driver components are stored in a dwc_otg_device
 678  * structure. A reference to the dwc_otg_device is saved in the
 679  * platform_device. This allows the driver to access the dwc_otg_device
 680  * structure on subsequent calls to driver methods for this device.
 681  *
 682  * @param[in] pdev  platform_device definition
 683  */
 684 static int dwc_otg_driver_probe(struct platform_device *pdev)
 685 {
 686         int retval = 0;
 687         uint32_t snpsid;
 688         dwc_otg_device_t *otg_dev;
 689         struct resource *res;
 690
 691         dev_dbg(&pdev->dev, "dwc_otg_driver_probe(%p)\n", pdev);
 692
 693         otg_dev= kzalloc(sizeof(dwc_otg_device_t), GFP_KERNEL);
 694         if (!otg_dev) {
 695                 dev_err(&pdev->dev, "kmalloc of dwc_otg_device failed\n");
 696                 retval = -ENOMEM;
 697                 goto fail;
 698         }
 699
 700         otg_dev->reg_offset = 0xFFFFFFFF;
 701
 702         /*
 703          * Retrieve the memory and IRQ resources.
 704          */
 705         otg_dev->irq = platform_get_irq(pdev, 0);
 706         if (otg_dev->irq <= 0) {
 707                 dev_err(&pdev->dev, "no device irq\n");
 708                 retval = -EINVAL;
 709                 goto fail;
 710         }
 711
 712         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 713         if (res == NULL) {
 714                 dev_err(&pdev->dev, "no CSR address\n");
 715                 retval = -EINVAL;
 716                 goto fail;
 717         }
 718
 719         otg_dev->parent = &pdev->dev;
 720         otg_dev->phys_addr = res->start;
 721         otg_dev->base_len = res->end - res->start + 1;
 722         if (request_mem_region(otg_dev->phys_addr,
 723                                otg_dev->base_len,
 724                                dwc_driver_name) == NULL) {
 725                 dev_err(&pdev->dev, "request_mem_region failed\n");
 726                 retval = -EBUSY;
 727                 goto fail;
 728         }
 729
 730         /*
 731          * Map the DWC_otg Core memory into virtual address space.
 732          */
 733         otg_dev->base = ioremap(otg_dev->phys_addr, otg_dev->base_len);
 734         if (!otg_dev->base) {
 735                 dev_err(&pdev->dev, "ioremap() failed\n");
 736                 retval = -ENOMEM;
 737                 goto fail;
 738         }
 739         dev_dbg(&pdev->dev, "mapped base=0x%08x\n", (unsigned) otg_dev->base);
 740
 741         /* Enable USB Port */
 742         dwc_write_reg32((uint32_t *)((uint8_t *)otg_dev->base + 0xe00), 0);
 743
 744         /*
 745          * Attempt to ensure this device is really a DWC_otg Controller.
 746          * Read and verify the SNPSID register contents. The value should be
 747          * 0x45F42XXX, which corresponds to "OT2", as in "OTG version 2.XX".
 748          */
 749         snpsid = dwc_read_reg32((uint32_t *)((uint8_t *)otg_dev->base + 0x40));
 750
 751         if ((snpsid & 0xFFFFF000) != OTG_CORE_REV_2_00) {
 752                 dev_err(&pdev->dev, "Bad value for SNPSID: 0x%08x\n", snpsid);
 753                 retval = -EINVAL;
 754                 goto fail;
 755         }
 756
 757         DWC_PRINT("Core Release: %x.%x%x%x\n",
 758                         (snpsid >> 12 & 0xF),
 759                         (snpsid >> 8 & 0xF),
 760                         (snpsid >> 4 & 0xF),
 761                         (snpsid & 0xF));
 762
 763         /*
 764          * Initialize driver data to point to the global DWC_otg
 765          * Device structure.
 766          */
 767         platform_set_drvdata(pdev, otg_dev);
 768         dev_dbg(&pdev->dev, "dwc_otg_device=0x%p\n", otg_dev);
 769
 770
 771         otg_dev->core_if = dwc_otg_cil_init(otg_dev->base,
 772                                                    &dwc_otg_module_params);
 773
 774         otg_dev->core_if->snpsid = snpsid;
 775
 776         if (!otg_dev->core_if) {
 777                 dev_err(&pdev->dev, "CIL initialization failed!\n");
 778                 retval = -ENOMEM;
 779                 goto fail;
 780         }
 781
 782         /*
 783          * Validate parameter values.
 784          */
 785         if (check_parameters(otg_dev->core_if)) {
 786                 retval = -EINVAL;
 787                 goto fail;
 788         }
 789
 790         /*
 791          * Create Device Attributes in sysfs
 792          */
 793         dwc_otg_attr_create(&pdev->dev);
 794
 795         /*
 796          * Disable the global interrupt until all the interrupt
 797          * handlers are installed.
 798          */
 799         dwc_otg_disable_global_interrupts(otg_dev->core_if);
 800
 801         /*
 802          * Install the interrupt handler for the common interrupts before
 803          * enabling common interrupts in core_init below.
 804          */
 805         DWC_DEBUGPL(DBG_CIL, "registering (common) handler for irq%d\n",
 806                     otg_dev->irq);
 807         retval = request_irq(otg_dev->irq, dwc_otg_common_irq,
 808                              IRQF_SHARED, "dwc_otg", otg_dev);
 809         if (retval) {
 810                 DWC_ERROR("request of irq%d failed\n", otg_dev->irq);
 811                 retval = -EBUSY;
 812                 goto fail;
 813         } else {
 814                 otg_dev->common_irq_installed = 1;
 815         }
 816
 817         /*
 818          * Initialize the DWC_otg core.
 819          */
 820         dwc_otg_core_init(otg_dev->core_if);
 821
 822 #ifndef DWC_HOST_ONLY
 823         /*
 824          * Initialize the PCD
 825          */
 826         retval = dwc_otg_pcd_init(pdev);
 827         if (retval != 0) {
 828                 DWC_ERROR("dwc_otg_pcd_init failed\n");
 829                 otg_dev->pcd = NULL;
 830                 goto fail;
 831         }
 832 #endif
 833 #ifndef DWC_DEVICE_ONLY
 834         /*
 835          * Initialize the HCD
 836          */
 837         retval = dwc_otg_hcd_init(&pdev->dev);
 838         if (retval != 0) {
 839                 DWC_ERROR("dwc_otg_hcd_init failed\n");
 840                 otg_dev->hcd = NULL;
 841                 goto fail;
 842         }
 843 #endif
 844
 845         /*
 846          * Enable the global interrupt after all the interrupt
 847          * handlers are installed.
 848          */
 849         dwc_otg_enable_global_interrupts(otg_dev->core_if);
 850
 851         return 0;
 852
 853  fail:
 854         dwc_otg_driver_remove(pdev);
 855         return retval;
 856 }
 857
 858 /**
 859  * This structure defines the methods to be called by a bus driver
 860  * during the lifecycle of a device on that bus. Both drivers and
 861  * devices are registered with a bus driver. The bus driver matches
 862  * devices to drivers based on information in the device and driver
 863  * structures.
 864  *
 865  * The probe function is called when the bus driver matches a device
 866  * to this driver. The remove function is called when a device is
 867  * unregistered with the bus driver.
 868  */
 869 static struct platform_driver dwc_otg_driver = {
 870         .driver = {
 871                 .name   = (char *)dwc_driver_name,
 872         },
 873         .probe          = dwc_otg_driver_probe,
 874         .remove         = dwc_otg_driver_remove,
 875 };
 876
 877 /**
 878  * This function is called when the dwc_otg_driver is installed with the
 879  * insmod command. It registers the dwc_otg_driver structure with the
 880  * appropriate bus driver. This will cause the dwc_otg_driver_probe function
 881  * to be called. In addition, the bus driver will automatically expose
 882  * attributes defined for the device and driver in the special sysfs file
 883  * system.
 884  *
 885  * @return
 886  */
 887 static int __init dwc_otg_driver_init(void)
 888 {
 889         int retval = 0;
 890         int error;
 891
 892         printk(KERN_INFO "%s: version %s\n", dwc_driver_name, DWC_DRIVER_VERSION);
 893
 894         retval = platform_driver_register(&dwc_otg_driver);
 895         if (retval) {
 896                 printk(KERN_ERR "%s retval=%d\n", __func__, retval);
 897                 return retval;
 898         }
 899
 900         error = driver_create_file(&dwc_otg_driver.driver, &driver_attr_version);
 901         error = driver_create_file(&dwc_otg_driver.driver, &driver_attr_debuglevel);
 902
 903         return retval;
 904 }
 905 module_init(dwc_otg_driver_init);
 906
 907 /**
 908  * This function is called when the driver is removed from the kernel
 909  * with the rmmod command. The driver unregisters itself with its bus
 910  * driver.
 911  *
 912  */
 913 static void __exit dwc_otg_driver_cleanup(void)
 914 {
 915         printk(KERN_DEBUG "dwc_otg_driver_cleanup()\n");
 916
 917         driver_remove_file(&dwc_otg_driver.driver, &driver_attr_debuglevel);
 918         driver_remove_file(&dwc_otg_driver.driver, &driver_attr_version);
 919
 920         platform_driver_unregister(&dwc_otg_driver);
 921
 922         printk(KERN_INFO "%s module removed\n", dwc_driver_name);
 923 }
 924 module_exit(dwc_otg_driver_cleanup);
 925
 926 MODULE_DESCRIPTION(DWC_DRIVER_DESC);
 927 MODULE_AUTHOR("Synopsys Inc.");
 928 MODULE_LICENSE("GPL");
 929
 930 module_param_named(otg_cap, dwc_otg_module_params.otg_cap, int, 0444);
 931 MODULE_PARM_DESC(otg_cap, "OTG Capabilities 0=HNP&SRP 1=SRP Only 2=None");
 932 module_param_named(opt, dwc_otg_module_params.opt, int, 0444);
 933 MODULE_PARM_DESC(opt, "OPT Mode");
 934 module_param_named(dma_enable, dwc_otg_module_params.dma_enable, int, 0444);
 935 MODULE_PARM_DESC(dma_enable, "DMA Mode 0=Slave 1=DMA enabled");
 936
 937 module_param_named(dma_desc_enable, dwc_otg_module_params.dma_desc_enable, int, 0444);
 938 MODULE_PARM_DESC(dma_desc_enable, "DMA Desc Mode 0=Address DMA 1=DMA Descriptor enabled");
 939
 940 module_param_named(dma_burst_size, dwc_otg_module_params.dma_burst_size, int, 0444);
 941 MODULE_PARM_DESC(dma_burst_size, "DMA Burst Size 1, 4, 8, 16, 32, 64, 128, 256");
 942 module_param_named(speed, dwc_otg_module_params.speed, int, 0444);
 943 MODULE_PARM_DESC(speed, "Speed 0=High Speed 1=Full Speed");
 944 module_param_named(host_support_fs_ls_low_power, dwc_otg_module_params.host_support_fs_ls_low_power, int, 0444);
 945 MODULE_PARM_DESC(host_support_fs_ls_low_power, "Support Low Power w/FS or LS 0=Support 1=Don't Support");
 946 module_param_named(host_ls_low_power_phy_clk, dwc_otg_module_params.host_ls_low_power_phy_clk, int, 0444);
 947 MODULE_PARM_DESC(host_ls_low_power_phy_clk, "Low Speed Low Power Clock 0=48Mhz 1=6Mhz");
 948 module_param_named(enable_dynamic_fifo, dwc_otg_module_params.enable_dynamic_fifo, int, 0444);
 949 MODULE_PARM_DESC(enable_dynamic_fifo, "0=cC Setting 1=Allow Dynamic Sizing");
 950 module_param_named(data_fifo_size, dwc_otg_module_params.data_fifo_size, int, 0444);
 951 MODULE_PARM_DESC(data_fifo_size, "Total number of words in the data FIFO memory 32-32768");
 952 module_param_named(dev_rx_fifo_size, dwc_otg_module_params.dev_rx_fifo_size, int, 0444);
 953 MODULE_PARM_DESC(dev_rx_fifo_size, "Number of words in the Rx FIFO 16-32768");
 954 module_param_named(dev_nperio_tx_fifo_size, dwc_otg_module_params.dev_nperio_tx_fifo_size, int, 0444);
 955 MODULE_PARM_DESC(dev_nperio_tx_fifo_size, "Number of words in the non-periodic Tx FIFO 16-32768");
 956 module_param_named(dev_perio_tx_fifo_size_1, dwc_otg_module_params.dev_perio_tx_fifo_size[0], int, 0444);
 957 MODULE_PARM_DESC(dev_perio_tx_fifo_size_1, "Number of words in the periodic Tx FIFO 4-768");
 958 module_param_named(dev_perio_tx_fifo_size_2, dwc_otg_module_params.dev_perio_tx_fifo_size[1], int, 0444);
 959 MODULE_PARM_DESC(dev_perio_tx_fifo_size_2, "Number of words in the periodic Tx FIFO 4-768");
 960 module_param_named(dev_perio_tx_fifo_size_3, dwc_otg_module_params.dev_perio_tx_fifo_size[2], int, 0444);
 961 MODULE_PARM_DESC(dev_perio_tx_fifo_size_3, "Number of words in the periodic Tx FIFO 4-768");
 962 module_param_named(dev_perio_tx_fifo_size_4, dwc_otg_module_params.dev_perio_tx_fifo_size[3], int, 0444);
 963 MODULE_PARM_DESC(dev_perio_tx_fifo_size_4, "Number of words in the periodic Tx FIFO 4-768");
 964 module_param_named(dev_perio_tx_fifo_size_5, dwc_otg_module_params.dev_perio_tx_fifo_size[4], int, 0444);
 965 MODULE_PARM_DESC(dev_perio_tx_fifo_size_5, "Number of words in the periodic Tx FIFO 4-768");
 966 module_param_named(dev_perio_tx_fifo_size_6, dwc_otg_module_params.dev_perio_tx_fifo_size[5], int, 0444);
 967 MODULE_PARM_DESC(dev_perio_tx_fifo_size_6, "Number of words in the periodic Tx FIFO 4-768");
 968 module_param_named(dev_perio_tx_fifo_size_7, dwc_otg_module_params.dev_perio_tx_fifo_size[6], int, 0444);
 969 MODULE_PARM_DESC(dev_perio_tx_fifo_size_7, "Number of words in the periodic Tx FIFO 4-768");
 970 module_param_named(dev_perio_tx_fifo_size_8, dwc_otg_module_params.dev_perio_tx_fifo_size[7], int, 0444);
 971 MODULE_PARM_DESC(dev_perio_tx_fifo_size_8, "Number of words in the periodic Tx FIFO 4-768");
 972 module_param_named(dev_perio_tx_fifo_size_9, dwc_otg_module_params.dev_perio_tx_fifo_size[8], int, 0444);
 973 MODULE_PARM_DESC(dev_perio_tx_fifo_size_9, "Number of words in the periodic Tx FIFO 4-768");
 974 module_param_named(dev_perio_tx_fifo_size_10, dwc_otg_module_params.dev_perio_tx_fifo_size[9], int, 0444);
 975 MODULE_PARM_DESC(dev_perio_tx_fifo_size_10, "Number of words in the periodic Tx FIFO 4-768");
 976 module_param_named(dev_perio_tx_fifo_size_11, dwc_otg_module_params.dev_perio_tx_fifo_size[10], int, 0444);
 977 MODULE_PARM_DESC(dev_perio_tx_fifo_size_11, "Number of words in the periodic Tx FIFO 4-768");
 978 module_param_named(dev_perio_tx_fifo_size_12, dwc_otg_module_params.dev_perio_tx_fifo_size[11], int, 0444);
 979 MODULE_PARM_DESC(dev_perio_tx_fifo_size_12, "Number of words in the periodic Tx FIFO 4-768");
 980 module_param_named(dev_perio_tx_fifo_size_13, dwc_otg_module_params.dev_perio_tx_fifo_size[12], int, 0444);
 981 MODULE_PARM_DESC(dev_perio_tx_fifo_size_13, "Number of words in the periodic Tx FIFO 4-768");
 982 module_param_named(dev_perio_tx_fifo_size_14, dwc_otg_module_params.dev_perio_tx_fifo_size[13], int, 0444);
 983 MODULE_PARM_DESC(dev_perio_tx_fifo_size_14, "Number of words in the periodic Tx FIFO 4-768");
 984 module_param_named(dev_perio_tx_fifo_size_15, dwc_otg_module_params.dev_perio_tx_fifo_size[14], int, 0444);
 985 MODULE_PARM_DESC(dev_perio_tx_fifo_size_15, "Number of words in the periodic Tx FIFO 4-768");
 986 module_param_named(host_rx_fifo_size, dwc_otg_module_params.host_rx_fifo_size, int, 0444);
 987 MODULE_PARM_DESC(host_rx_fifo_size, "Number of words in the Rx FIFO 16-32768");
 988 module_param_named(host_nperio_tx_fifo_size, dwc_otg_module_params.host_nperio_tx_fifo_size, int, 0444);
 989 MODULE_PARM_DESC(host_nperio_tx_fifo_size, "Number of words in the non-periodic Tx FIFO 16-32768");
 990 module_param_named(host_perio_tx_fifo_size, dwc_otg_module_params.host_perio_tx_fifo_size, int, 0444);
 991 MODULE_PARM_DESC(host_perio_tx_fifo_size, "Number of words in the host periodic Tx FIFO 16-32768");
 992 module_param_named(max_transfer_size, dwc_otg_module_params.max_transfer_size, int, 0444);
 993 /** @todo Set the max to 512K, modify checks */
 994 MODULE_PARM_DESC(max_transfer_size, "The maximum transfer size supported in bytes 2047-65535");
 995 module_param_named(max_packet_count, dwc_otg_module_params.max_packet_count, int, 0444);
 996 MODULE_PARM_DESC(max_packet_count, "The maximum number of packets in a transfer 15-511");
 997 module_param_named(host_channels, dwc_otg_module_params.host_channels, int, 0444);
 998 MODULE_PARM_DESC(host_channels, "The number of host channel registers to use 1-16");
 999 module_param_named(dev_endpoints, dwc_otg_module_params.dev_endpoints, int, 0444);
1000 MODULE_PARM_DESC(dev_endpoints, "The number of endpoints in addition to EP0 available for device mode 1-15");
1001 module_param_named(phy_type, dwc_otg_module_params.phy_type, int, 0444);
1002 MODULE_PARM_DESC(phy_type, "0=Reserved 1=UTMI+ 2=ULPI");
1003 module_param_named(phy_utmi_width, dwc_otg_module_params.phy_utmi_width, int, 0444);
1004 MODULE_PARM_DESC(phy_utmi_width, "Specifies the UTMI+ Data Width 8 or 16 bits");
1005 module_param_named(phy_ulpi_ddr, dwc_otg_module_params.phy_ulpi_ddr, int, 0444);
1006 MODULE_PARM_DESC(phy_ulpi_ddr, "ULPI at double or single data rate 0=Single 1=Double");
1007 module_param_named(phy_ulpi_ext_vbus, dwc_otg_module_params.phy_ulpi_ext_vbus, int, 0444);
1008 MODULE_PARM_DESC(phy_ulpi_ext_vbus, "ULPI PHY using internal or external vbus 0=Internal");
1009 module_param_named(i2c_enable, dwc_otg_module_params.i2c_enable, int, 0444);
1010 MODULE_PARM_DESC(i2c_enable, "FS PHY Interface");
1011 module_param_named(ulpi_fs_ls, dwc_otg_module_params.ulpi_fs_ls, int, 0444);
1012 MODULE_PARM_DESC(ulpi_fs_ls, "ULPI PHY FS/LS mode only");
1013 module_param_named(ts_dline, dwc_otg_module_params.ts_dline, int, 0444);
1014 MODULE_PARM_DESC(ts_dline, "Term select Dline pulsing for all PHYs");
1015 module_param_named(debug, g_dbg_lvl, int, 0444);
1016 MODULE_PARM_DESC(debug, "");
1017
1018 module_param_named(en_multiple_tx_fifo, dwc_otg_module_params.en_multiple_tx_fifo, int, 0444);
1019 MODULE_PARM_DESC(en_multiple_tx_fifo, "Dedicated Non Periodic Tx FIFOs 0=disabled 1=enabled");
1020 module_param_named(dev_tx_fifo_size_1, dwc_otg_module_params.dev_tx_fifo_size[0], int, 0444);
1021 MODULE_PARM_DESC(dev_tx_fifo_size_1, "Number of words in the Tx FIFO 4-768");
1022 module_param_named(dev_tx_fifo_size_2, dwc_otg_module_params.dev_tx_fifo_size[1], int, 0444);
1023 MODULE_PARM_DESC(dev_tx_fifo_size_2, "Number of words in the Tx FIFO 4-768");
1024 module_param_named(dev_tx_fifo_size_3, dwc_otg_module_params.dev_tx_fifo_size[2], int, 0444);
1025 MODULE_PARM_DESC(dev_tx_fifo_size_3, "Number of words in the Tx FIFO 4-768");
1026 module_param_named(dev_tx_fifo_size_4, dwc_otg_module_params.dev_tx_fifo_size[3], int, 0444);
1027 MODULE_PARM_DESC(dev_tx_fifo_size_4, "Number of words in the Tx FIFO 4-768");
1028 module_param_named(dev_tx_fifo_size_5, dwc_otg_module_params.dev_tx_fifo_size[4], int, 0444);
1029 MODULE_PARM_DESC(dev_tx_fifo_size_5, "Number of words in the Tx FIFO 4-768");
1030 module_param_named(dev_tx_fifo_size_6, dwc_otg_module_params.dev_tx_fifo_size[5], int, 0444);
1031 MODULE_PARM_DESC(dev_tx_fifo_size_6, "Number of words in the Tx FIFO 4-768");
1032 module_param_named(dev_tx_fifo_size_7, dwc_otg_module_params.dev_tx_fifo_size[6], int, 0444);
1033 MODULE_PARM_DESC(dev_tx_fifo_size_7, "Number of words in the Tx FIFO 4-768");
1034 module_param_named(dev_tx_fifo_size_8, dwc_otg_module_params.dev_tx_fifo_size[7], int, 0444);
1035 MODULE_PARM_DESC(dev_tx_fifo_size_8, "Number of words in the Tx FIFO 4-768");
1036 module_param_named(dev_tx_fifo_size_9, dwc_otg_module_params.dev_tx_fifo_size[8], int, 0444);
1037 MODULE_PARM_DESC(dev_tx_fifo_size_9, "Number of words in the Tx FIFO 4-768");
1038 module_param_named(dev_tx_fifo_size_10, dwc_otg_module_params.dev_tx_fifo_size[9], int, 0444);
1039 MODULE_PARM_DESC(dev_tx_fifo_size_10, "Number of words in the Tx FIFO 4-768");
1040 module_param_named(dev_tx_fifo_size_11, dwc_otg_module_params.dev_tx_fifo_size[10], int, 0444);
1041 MODULE_PARM_DESC(dev_tx_fifo_size_11, "Number of words in the Tx FIFO 4-768");
1042 module_param_named(dev_tx_fifo_size_12, dwc_otg_module_params.dev_tx_fifo_size[11], int, 0444);
1043 MODULE_PARM_DESC(dev_tx_fifo_size_12, "Number of words in the Tx FIFO 4-768");
1044 module_param_named(dev_tx_fifo_size_13, dwc_otg_module_params.dev_tx_fifo_size[12], int, 0444);
1045 MODULE_PARM_DESC(dev_tx_fifo_size_13, "Number of words in the Tx FIFO 4-768");
1046 module_param_named(dev_tx_fifo_size_14, dwc_otg_module_params.dev_tx_fifo_size[13], int, 0444);
1047 MODULE_PARM_DESC(dev_tx_fifo_size_14, "Number of words in the Tx FIFO 4-768");
1048 module_param_named(dev_tx_fifo_size_15, dwc_otg_module_params.dev_tx_fifo_size[14], int, 0444);
1049 MODULE_PARM_DESC(dev_tx_fifo_size_15, "Number of words in the Tx FIFO 4-768");
1050
1051 module_param_named(thr_ctl, dwc_otg_module_params.thr_ctl, int, 0444);
1052 MODULE_PARM_DESC(thr_ctl, "Thresholding enable flag bit 0 - non ISO Tx thr., 1 - ISO Tx thr., 2 - Rx thr.- bit 0=disabled 1=enabled");
1053 module_param_named(tx_thr_length, dwc_otg_module_params.tx_thr_length, int, 0444);
1054 MODULE_PARM_DESC(tx_thr_length, "Tx Threshold length in 32 bit DWORDs");
1055 module_param_named(rx_thr_length, dwc_otg_module_params.rx_thr_length, int, 0444);
1056 MODULE_PARM_DESC(rx_thr_length, "Rx Threshold length in 32 bit DWORDs");
1057
1058 module_param_named(pti_enable, dwc_otg_module_params.pti_enable, int, 0444);
1059 MODULE_PARM_DESC(pti_enable, "Per Transfer Interrupt mode 0=disabled 1=enabled");
1060
1061 module_param_named(mpi_enable, dwc_otg_module_params.mpi_enable, int, 0444);
1062 MODULE_PARM_DESC(mpi_enable, "Multiprocessor Interrupt mode 0=disabled 1=enabled");
1063
1064 /** @page "Module Parameters"
1065  *
1066  * The following parameters may be specified when starting the module.
1067  * These parameters define how the DWC_otg controller should be
1068  * configured. Parameter values are passed to the CIL initialization
1069  * function dwc_otg_cil_init
1070  *
1071  * Example: <code>modprobe dwc_otg speed=1 otg_cap=1</code>
1072  *
1073
1074  <table>
1075  <tr><td>Parameter Name</td><td>Meaning</td></tr>
1076
1077  <tr>
1078  <td>otg_cap</td>
1079  <td>Specifies the OTG capabilities. The driver will automatically detect the
1080  value for this parameter if none is specified.
1081  - 0: HNP and SRP capable (default, if available)
1082  - 1: SRP Only capable
1083  - 2: No HNP/SRP capable
1084  </td></tr>
1085
1086  <tr>
1087  <td>dma_enable</td>
1088  <td>Specifies whether to use slave or DMA mode for accessing the data FIFOs.
1089  The driver will automatically detect the value for this parameter if none is
1090  specified.
1091  - 0: Slave
1092  - 1: DMA (default, if available)
1093  </td></tr>
1094
1095  <tr>
1096  <td>dma_burst_size</td>
1097  <td>The DMA Burst size (applicable only for External DMA Mode).
1098  - Values: 1, 4, 8 16, 32, 64, 128, 256 (default 32)
1099  </td></tr>
1100
1101  <tr>
1102  <td>speed</td>
1103  <td>Specifies the maximum speed of operation in host and device mode. The
1104  actual speed depends on the speed of the attached device and the value of
1105  phy_type.
1106  - 0: High Speed (default)
1107  - 1: Full Speed
1108  </td></tr>
1109
1110  <tr>
1111  <td>host_support_fs_ls_low_power</td>
1112  <td>Specifies whether low power mode is supported when attached to a Full
1113  Speed or Low Speed device in host mode.
1114  - 0: Don't support low power mode (default)
1115  - 1: Support low power mode
1116  </td></tr>
1117
1118  <tr>
1119  <td>host_ls_low_power_phy_clk</td>
1120  <td>Specifies the PHY clock rate in low power mode when connected to a Low
1121  Speed device in host mode. This parameter is applicable only if
1122  HOST_SUPPORT_FS_LS_LOW_POWER is enabled.
1123  - 0: 48 MHz (default)
1124  - 1: 6 MHz
1125  </td></tr>
1126
1127  <tr>
1128  <td>enable_dynamic_fifo</td>
1129  <td> Specifies whether FIFOs may be resized by the driver software.
1130  - 0: Use cC FIFO size parameters
1131  - 1: Allow dynamic FIFO sizing (default)
1132  </td></tr>
1133
1134  <tr>
1135  <td>data_fifo_size</td>
1136  <td>Total number of 4-byte words in the data FIFO memory. This memory
1137  includes the Rx FIFO, non-periodic Tx FIFO, and periodic Tx FIFOs.
1138  - Values: 32 to 32768 (default 8192)
1139
1140  Note: The total FIFO memory depth in the FPGA configuration is 8192.
1141  </td></tr>
1142
1143  <tr>
1144  <td>dev_rx_fifo_size</td>
1145  <td>Number of 4-byte words in the Rx FIFO in device mode when dynamic
1146  FIFO sizing is enabled.
1147  - Values: 16 to 32768 (default 1064)
1148  </td></tr>
1149
1150  <tr>
1151  <td>dev_nperio_tx_fifo_size</td>
1152  <td>Number of 4-byte words in the non-periodic Tx FIFO in device mode when
1153  dynamic FIFO sizing is enabled.
1154  - Values: 16 to 32768 (default 1024)
1155  </td></tr>
1156
1157  <tr>
1158  <td>dev_perio_tx_fifo_size_n (n = 1 to 15)</td>
1159  <td>Number of 4-byte words in each of the periodic Tx FIFOs in device mode
1160  when dynamic FIFO sizing is enabled.
1161  - Values: 4 to 768 (default 256)
1162  </td></tr>
1163
1164  <tr>
1165  <td>host_rx_fifo_size</td>
1166  <td>Number of 4-byte words in the Rx FIFO in host mode when dynamic FIFO
1167  sizing is enabled.
1168  - Values: 16 to 32768 (default 1024)
1169  </td></tr>
1170
1171  <tr>
1172  <td>host_nperio_tx_fifo_size</td>
1173  <td>Number of 4-byte words in the non-periodic Tx FIFO in host mode when
1174  dynamic FIFO sizing is enabled in the core.
1175  - Values: 16 to 32768 (default 1024)
1176  </td></tr>
1177
1178  <tr>
1179  <td>host_perio_tx_fifo_size</td>
1180  <td>Number of 4-byte words in the host periodic Tx FIFO when dynamic FIFO
1181  sizing is enabled.
1182  - Values: 16 to 32768 (default 1024)
1183  </td></tr>
1184
1185  <tr>
1186  <td>max_transfer_size</td>
1187  <td>The maximum transfer size supported in bytes.
1188  - Values: 2047 to 65,535 (default 65,535)
1189  </td></tr>
1190
1191  <tr>
1192  <td>max_packet_count</td>
1193  <td>The maximum number of packets in a transfer.
1194  - Values: 15 to 511 (default 511)
1195  </td></tr>
1196
1197  <tr>
1198  <td>host_channels</td>
1199  <td>The number of host channel registers to use.
1200  - Values: 1 to 16 (default 12)
1201
1202  Note: The FPGA configuration supports a maximum of 12 host channels.
1203  </td></tr>
1204
1205  <tr>
1206  <td>dev_endpoints</td>
1207  <td>The number of endpoints in addition to EP0 available for device mode
1208  operations.
1209  - Values: 1 to 15 (default 6 IN and OUT)
1210
1211  Note: The FPGA configuration supports a maximum of 6 IN and OUT endpoints in
1212  addition to EP0.
1213  </td></tr>
1214
1215  <tr>
1216  <td>phy_type</td>
1217  <td>Specifies the type of PHY interface to use. By default, the driver will
1218  automatically detect the phy_type.
1219  - 0: Full Speed
1220  - 1: UTMI+ (default, if available)
1221  - 2: ULPI
1222  </td></tr>
1223
1224  <tr>
1225  <td>phy_utmi_width</td>
1226  <td>Specifies the UTMI+ Data Width. This parameter is applicable for a
1227  phy_type of UTMI+. Also, this parameter is applicable only if the
1228  OTG_HSPHY_WIDTH cC parameter was set to "8 and 16 bits", meaning that the
1229  core has been configured to work at either data path width.
1230  - Values: 8 or 16 bits (default 16)
1231  </td></tr>
1232
1233  <tr>
1234  <td>phy_ulpi_ddr</td>
1235  <td>Specifies whether the ULPI operates at double or single data rate. This
1236  parameter is only applicable if phy_type is ULPI.
1237  - 0: single data rate ULPI interface with 8 bit wide data bus (default)
1238  - 1: double data rate ULPI interface with 4 bit wide data bus
1239  </td></tr>
1240
1241  <tr>
1242  <td>i2c_enable</td>
1243  <td>Specifies whether to use the I2C interface for full speed PHY. This
1244  parameter is only applicable if PHY_TYPE is FS.
1245  - 0: Disabled (default)
1246  - 1: Enabled
1247  </td></tr>
1248
1249  <tr>
1250  <td>otg_en_multiple_tx_fifo</td>
1251  <td>Specifies whether dedicatedto tx fifos are enabled for non periodic IN EPs.
1252  The driver will automatically detect the value for this parameter if none is
1253  specified.
1254  - 0: Disabled
1255  - 1: Enabled (default, if available)
1256  </td></tr>
1257
1258  <tr>
1259  <td>dev_tx_fifo_size_n (n = 1 to 15)</td>
1260  <td>Number of 4-byte words in each of the Tx FIFOs in device mode
1261  when dynamic FIFO sizing is enabled.
1262  - Values: 4 to 768 (default 256)
1263  </td></tr>
1264
1265 */