package/uboot-ifxmips/files/include/boot.h

   1 #ifndef _BOOT_H
   2 #define _BOOT_H
   3
   4 /* All this should be defined somewhere in danube.h later... */
   5
   6 #define MPS_SRAM_BASE_ADDRESS   0xBF200000
   7 #define MPS_SRAM_BOOT_OFFSET    0x1C0
   8
   9 /* Offset for CPU1 (both CPUs have same register set) */
  10 #define BOOT_BASE_ADDRESS   (MPS_SRAM_BASE_ADDRESS + MPS_SRAM_BOOT_OFFSET)
  11 #define BOOT_CPU_OFFSET     0x20
  12
  13
  14 #ifdef __ASSEMBLY__
  15 #define BOOT_RVEC                     (BOOT_BASE_ADDRESS + 0x00)
  16 #define BOOT_NVEC                     (BOOT_BASE_ADDRESS + 0x04)
  17 #define BOOT_EVEC                     (BOOT_BASE_ADDRESS + 0x08)
  18 #define BOOT_CP0_CAUSE     (BOOT_BASE_ADDRESS + 0x0C)
  19 #define BOOT_CP0_EPC          (BOOT_BASE_ADDRESS + 0x10)
  20 #define BOOT_CP0_EEPC      (BOOT_BASE_ADDRESS + 0x14)
  21 #define BOOT_SIZE        (BOOT_BASE_ADDRESS + 0x18)   /* for CPU1 */
  22 #define BOOT_RCU_SR        (BOOT_BASE_ADDRESS + 0x18) /* for CPU0 */
  23 #define BOOT_CFG_STAT      (BOOT_BASE_ADDRESS + 0x1C)
  24 #else
  25 #define BOOT_RVEC(cpu)          (volatile u32*)(BOOT_BASE_ADDRESS + (cpu * BOOT_CPU_OFFSET) + 0x00)
  26 #define BOOT_NVEC(cpu)          (volatile u32*)(BOOT_BASE_ADDRESS + (cpu * BOOT_CPU_OFFSET) + 0x04)
  27 #define BOOT_EVEC(cpu)          (volatile u32*)(BOOT_BASE_ADDRESS + (cpu * BOOT_CPU_OFFSET) + 0x08)
  28 #define BOOT_CP0_STATUS(cpu)    (volatile u32*)(BOOT_BASE_ADDRESS + (cpu * BOOT_CPU_OFFSET) + 0x0C)
  29 #define BOOT_CP0_EPC(cpu)       (volatile u32*)(BOOT_BASE_ADDRESS + (cpu * BOOT_CPU_OFFSET) + 0x10)
  30 #define BOOT_CP0_EEPC(cpu)      (volatile u32*)(BOOT_BASE_ADDRESS + (cpu * BOOT_CPU_OFFSET) + 0x14)
  31 #define BOOT_SIZE(cpu)       (volatile u32*)(BOOT_BASE_ADDRESS + (cpu * BOOT_CPU_OFFSET) + 0x18)    /* for CPU1 */
  32 #define BOOT_RCU_SR(cpu)       (volatile u32*)(BOOT_BASE_ADDRESS + (cpu * BOOT_CPU_OFFSET) + 0x18)  /* for CPU0 */
  33 #define BOOT_CFG_STAT(cpu)      (volatile u32*)(BOOT_BASE_ADDRESS + (cpu * BOOT_CPU_OFFSET) + 0x1C)
  34 #endif
  35
  36 #define BOOT_CFG_NOR            0x01
  37 #define BOOT_CFG_MII            0x02
  38 #define BOOT_CFG_PCI            0x03
  39 #define BOOT_CFG_ASC            0x04
  40 #define BOOT_CFG_SFLASH         0x05
  41 #define BOOT_CFG_NAND           0x06
  42 #define BOOT_CFG_RMII           0x07
  43 #define BOOT_CFG_TEST           0x00
  44
  45 #define BOOT_NUM_RETRY  3
  46
  47 #define BOOT_STAT_MASK_ALL     0x0000FFFF
  48 #define BOOT_STAT_MASK_STAT    0x0000F000
  49 #define BOOT_STAT_MASK_BERR    0x00000F00
  50 #define BOOT_STAT_MASK_BSTRAP  0x000000F0
  51 #define BOOT_STAT_MASK_BMODULE 0x0000000F
  52
  53 #define BOOT_STAT_INIT         0x00000000
  54 #define BOOT_STAT_BSTRAP       0x00001000
  55 #define BOOT_STAT_RETRY        0x00002000
  56 #define BOOT_STAT_START        0x00003000
  57 #define BOOT_STAT_HALT         0x0000F000
  58
  59 #define BOOT_ERR_NO_RVEC       0x00000100
  60 #define BOOT_ERR_NO_NVEC       0x00000200
  61 #define BOOT_ERR_NO_EVEC       0x00000300
  62 #define BOOT_ERR_BSTRAP        0x00000400
  63 #define BOOT_ERR_EXC           0x00000800
  64
  65 #ifndef __ASSEMBLY__
  66 void boot_set_status( u32 status, u32 mask);
  67 void boot_set_config( u32 config);
  68 void boot_set_rvec( u32 vector);
  69 void boot_set_size( u32 size);
  70 void boot_sdbg( u8* string, u32 value);
  71 void boot_error( u32 berr);
  72 int boot_from_ebu(void);
  73 void _boot_rvec(void);
  74 typedef struct
  75 {
  76         u32   cpu;              /** CPU number */
  77         u32   config;           /** Boot configuration */
  78    u32   endian;           /** CPU endianess */
  79    u32   debug;            /** Debug mode */
  80         u32     (*exit)(void);     /** application vector */
  81 } boot_data;
  82
  83 extern boot_data bootrom;
  84 #endif
  85
  86 #endif /* #ifdef _BOOT_H */