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mac80211: update to wireless-testing 2010-11-10 + some pending work
[openwrt.git] / package / mac80211 / patches / 510-pending_work.patch
1 --- a/drivers/net/wireless/ath/ath9k/ar5008_phy.c
2 +++ b/drivers/net/wireless/ath/ath9k/ar5008_phy.c
3 @@ -1579,6 +1579,37 @@ static void ar5008_hw_set_nf_limits(stru
4 ah->nf_5g.nominal = AR_PHY_CCA_NOM_VAL_5416_5GHZ;
5 }
6
7 +static void ar5008_hw_set_radar_params(struct ath_hw *ah,
8 + struct ath_hw_radar_conf *conf)
9 +{
10 + u32 radar_0 = 0, radar_1 = 0;
11 +
12 + if (!conf) {
13 + REG_CLR_BIT(ah, AR_PHY_RADAR_0, AR_PHY_RADAR_0_ENA);
14 + return;
15 + }
16 +
17 + radar_0 |= AR_PHY_RADAR_0_ENA | AR_PHY_RADAR_0_FFT_ENA;
18 + radar_0 |= SM(conf->fir_power, AR_PHY_RADAR_0_FIRPWR);
19 + radar_0 |= SM(conf->radar_rssi, AR_PHY_RADAR_0_RRSSI);
20 + radar_0 |= SM(conf->pulse_height, AR_PHY_RADAR_0_HEIGHT);
21 + radar_0 |= SM(conf->pulse_rssi, AR_PHY_RADAR_0_PRSSI);
22 + radar_0 |= SM(conf->pulse_inband, AR_PHY_RADAR_0_INBAND);
23 +
24 + radar_1 |= AR_PHY_RADAR_1_MAX_RRSSI;
25 + radar_1 |= AR_PHY_RADAR_1_BLOCK_CHECK;
26 + radar_1 |= SM(conf->pulse_maxlen, AR_PHY_RADAR_1_MAXLEN);
27 + radar_1 |= SM(conf->pulse_inband_step, AR_PHY_RADAR_1_RELSTEP_THRESH);
28 + radar_1 |= SM(conf->radar_inband, AR_PHY_RADAR_1_RELPWR_THRESH);
29 +
30 + REG_WRITE(ah, AR_PHY_RADAR_0, radar_0);
31 + REG_WRITE(ah, AR_PHY_RADAR_1, radar_1);
32 + if (conf->ext_channel)
33 + REG_SET_BIT(ah, AR_PHY_RADAR_EXT, AR_PHY_RADAR_EXT_ENA);
34 + else
35 + REG_CLR_BIT(ah, AR_PHY_RADAR_EXT, AR_PHY_RADAR_EXT_ENA);
36 +}
37 +
38 void ar5008_hw_attach_phy_ops(struct ath_hw *ah)
39 {
40 struct ath_hw_private_ops *priv_ops = ath9k_hw_private_ops(ah);
41 @@ -1609,6 +1640,7 @@ void ar5008_hw_attach_phy_ops(struct ath
42 priv_ops->restore_chainmask = ar5008_restore_chainmask;
43 priv_ops->set_diversity = ar5008_set_diversity;
44 priv_ops->do_getnf = ar5008_hw_do_getnf;
45 + priv_ops->set_radar_params = ar5008_hw_set_radar_params;
46
47 if (modparam_force_new_ani) {
48 priv_ops->ani_control = ar5008_hw_ani_control_new;
49 --- a/drivers/net/wireless/ath/ath9k/ar9003_calib.c
50 +++ b/drivers/net/wireless/ath/ath9k/ar9003_calib.c
51 @@ -718,12 +718,19 @@ static bool ar9003_hw_init_cal(struct at
52 struct ath9k_channel *chan)
53 {
54 struct ath_common *common = ath9k_hw_common(ah);
55 + int val;
56
57 - /*
58 - * 0x7 = 0b111 , AR9003 needs to be configured for 3-chain mode before
59 - * running AGC/TxIQ cals
60 - */
61 - ar9003_hw_set_chain_masks(ah, 0x7, 0x7);
62 + val = REG_READ(ah, AR_ENT_OTP);
63 + ath_print(common, ATH_DBG_CALIBRATE, "ath9k: AR_ENT_OTP 0x%x\n", val);
64 +
65 + if (val & AR_ENT_OTP_CHAIN2_DISABLE)
66 + ar9003_hw_set_chain_masks(ah, 0x3, 0x3);
67 + else
68 + /*
69 + * 0x7 = 0b111 , AR9003 needs to be configured for 3-chain
70 + * mode before running AGC/TxIQ cals
71 + */
72 + ar9003_hw_set_chain_masks(ah, 0x7, 0x7);
73
74 /* Do Tx IQ Calibration */
75 ar9003_hw_tx_iq_cal(ah);
76 --- a/drivers/net/wireless/ath/ath9k/ar9003_eeprom.c
77 +++ b/drivers/net/wireless/ath/ath9k/ar9003_eeprom.c
78 @@ -22,12 +22,14 @@
79 #define COMP_CKSUM_LEN 2
80
81 #define AR_CH0_TOP (0x00016288)
82 -#define AR_CH0_TOP_XPABIASLVL (0x3)
83 +#define AR_CH0_TOP_XPABIASLVL (0x300)
84 #define AR_CH0_TOP_XPABIASLVL_S (8)
85
86 #define AR_CH0_THERM (0x00016290)
87 -#define AR_CH0_THERM_SPARE (0x3f)
88 -#define AR_CH0_THERM_SPARE_S (0)
89 +#define AR_CH0_THERM_XPABIASLVL_MSB 0x3
90 +#define AR_CH0_THERM_XPABIASLVL_MSB_S 0
91 +#define AR_CH0_THERM_XPASHORT2GND 0x4
92 +#define AR_CH0_THERM_XPASHORT2GND_S 2
93
94 #define AR_SWITCH_TABLE_COM_ALL (0xffff)
95 #define AR_SWITCH_TABLE_COM_ALL_S (0)
96 @@ -55,15 +57,2327 @@
97 #define SUB_NUM_CTL_MODES_AT_5G_40 2 /* excluding HT40, EXT-OFDM */
98 #define SUB_NUM_CTL_MODES_AT_2G_40 3 /* excluding HT40, EXT-OFDM, EXT-CCK */
99
100 +static int ar9003_hw_power_interpolate(int32_t x,
101 + int32_t *px, int32_t *py, u_int16_t np);
102 static const struct ar9300_eeprom ar9300_default = {
103 .eepromVersion = 2,
104 - .templateVersion = 2,
105 - .macAddr = {1, 2, 3, 4, 5, 6},
106 - .custData = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
107 - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
108 + .templateVersion = 2,
109 + .macAddr = {1, 2, 3, 4, 5, 6},
110 + .custData = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
111 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
112 + .baseEepHeader = {
113 + .regDmn = { LE16(0), LE16(0x1f) },
114 + .txrxMask = 0x77, /* 4 bits tx and 4 bits rx */
115 + .opCapFlags = {
116 + .opFlags = AR9300_OPFLAGS_11G | AR9300_OPFLAGS_11A,
117 + .eepMisc = 0,
118 + },
119 + .rfSilent = 0,
120 + .blueToothOptions = 0,
121 + .deviceCap = 0,
122 + .deviceType = 5, /* takes lower byte in eeprom location */
123 + .pwrTableOffset = AR9300_PWR_TABLE_OFFSET,
124 + .params_for_tuning_caps = {0, 0},
125 + .featureEnable = 0x0c,
126 + /*
127 + * bit0 - enable tx temp comp - disabled
128 + * bit1 - enable tx volt comp - disabled
129 + * bit2 - enable fastClock - enabled
130 + * bit3 - enable doubling - enabled
131 + * bit4 - enable internal regulator - disabled
132 + * bit5 - enable pa predistortion - disabled
133 + */
134 + .miscConfiguration = 0, /* bit0 - turn down drivestrength */
135 + .eepromWriteEnableGpio = 3,
136 + .wlanDisableGpio = 0,
137 + .wlanLedGpio = 8,
138 + .rxBandSelectGpio = 0xff,
139 + .txrxgain = 0,
140 + .swreg = 0,
141 + },
142 + .modalHeader2G = {
143 + /* ar9300_modal_eep_header 2g */
144 + /* 4 idle,t1,t2,b(4 bits per setting) */
145 + .antCtrlCommon = LE32(0x110),
146 + /* 4 ra1l1, ra2l1, ra1l2, ra2l2, ra12 */
147 + .antCtrlCommon2 = LE32(0x22222),
148 +
149 + /*
150 + * antCtrlChain[AR9300_MAX_CHAINS]; 6 idle, t, r,
151 + * rx1, rx12, b (2 bits each)
152 + */
153 + .antCtrlChain = { LE16(0x150), LE16(0x150), LE16(0x150) },
154 +
155 + /*
156 + * xatten1DB[AR9300_MAX_CHAINS]; 3 xatten1_db
157 + * for ar9280 (0xa20c/b20c 5:0)
158 + */
159 + .xatten1DB = {0, 0, 0},
160 +
161 + /*
162 + * xatten1Margin[AR9300_MAX_CHAINS]; 3 xatten1_margin
163 + * for ar9280 (0xa20c/b20c 16:12
164 + */
165 + .xatten1Margin = {0, 0, 0},
166 + .tempSlope = 36,
167 + .voltSlope = 0,
168 +
169 + /*
170 + * spurChans[OSPREY_EEPROM_MODAL_SPURS]; spur
171 + * channels in usual fbin coding format
172 + */
173 + .spurChans = {0, 0, 0, 0, 0},
174 +
175 + /*
176 + * noiseFloorThreshCh[AR9300_MAX_CHAINS]; 3 Check
177 + * if the register is per chain
178 + */
179 + .noiseFloorThreshCh = {-1, 0, 0},
180 + .ob = {1, 1, 1},/* 3 chain */
181 + .db_stage2 = {1, 1, 1}, /* 3 chain */
182 + .db_stage3 = {0, 0, 0},
183 + .db_stage4 = {0, 0, 0},
184 + .xpaBiasLvl = 0,
185 + .txFrameToDataStart = 0x0e,
186 + .txFrameToPaOn = 0x0e,
187 + .txClip = 3, /* 4 bits tx_clip, 4 bits dac_scale_cck */
188 + .antennaGain = 0,
189 + .switchSettling = 0x2c,
190 + .adcDesiredSize = -30,
191 + .txEndToXpaOff = 0,
192 + .txEndToRxOn = 0x2,
193 + .txFrameToXpaOn = 0xe,
194 + .thresh62 = 28,
195 + .papdRateMaskHt20 = LE32(0x0cf0e0e0),
196 + .papdRateMaskHt40 = LE32(0x6cf0e0e0),
197 + .futureModal = {
198 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
199 + },
200 + },
201 + .base_ext1 = {
202 + .ant_div_control = 0,
203 + .future = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}
204 + },
205 + .calFreqPier2G = {
206 + FREQ2FBIN(2412, 1),
207 + FREQ2FBIN(2437, 1),
208 + FREQ2FBIN(2472, 1),
209 + },
210 + /* ar9300_cal_data_per_freq_op_loop 2g */
211 + .calPierData2G = {
212 + { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
213 + { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
214 + { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
215 + },
216 + .calTarget_freqbin_Cck = {
217 + FREQ2FBIN(2412, 1),
218 + FREQ2FBIN(2484, 1),
219 + },
220 + .calTarget_freqbin_2G = {
221 + FREQ2FBIN(2412, 1),
222 + FREQ2FBIN(2437, 1),
223 + FREQ2FBIN(2472, 1)
224 + },
225 + .calTarget_freqbin_2GHT20 = {
226 + FREQ2FBIN(2412, 1),
227 + FREQ2FBIN(2437, 1),
228 + FREQ2FBIN(2472, 1)
229 + },
230 + .calTarget_freqbin_2GHT40 = {
231 + FREQ2FBIN(2412, 1),
232 + FREQ2FBIN(2437, 1),
233 + FREQ2FBIN(2472, 1)
234 + },
235 + .calTargetPowerCck = {
236 + /* 1L-5L,5S,11L,11S */
237 + { {36, 36, 36, 36} },
238 + { {36, 36, 36, 36} },
239 + },
240 + .calTargetPower2G = {
241 + /* 6-24,36,48,54 */
242 + { {32, 32, 28, 24} },
243 + { {32, 32, 28, 24} },
244 + { {32, 32, 28, 24} },
245 + },
246 + .calTargetPower2GHT20 = {
247 + { {32, 32, 32, 32, 28, 20, 32, 32, 28, 20, 32, 32, 28, 20} },
248 + { {32, 32, 32, 32, 28, 20, 32, 32, 28, 20, 32, 32, 28, 20} },
249 + { {32, 32, 32, 32, 28, 20, 32, 32, 28, 20, 32, 32, 28, 20} },
250 + },
251 + .calTargetPower2GHT40 = {
252 + { {32, 32, 32, 32, 28, 20, 32, 32, 28, 20, 32, 32, 28, 20} },
253 + { {32, 32, 32, 32, 28, 20, 32, 32, 28, 20, 32, 32, 28, 20} },
254 + { {32, 32, 32, 32, 28, 20, 32, 32, 28, 20, 32, 32, 28, 20} },
255 + },
256 + .ctlIndex_2G = {
257 + 0x11, 0x12, 0x15, 0x17, 0x41, 0x42,
258 + 0x45, 0x47, 0x31, 0x32, 0x35, 0x37,
259 + },
260 + .ctl_freqbin_2G = {
261 + {
262 + FREQ2FBIN(2412, 1),
263 + FREQ2FBIN(2417, 1),
264 + FREQ2FBIN(2457, 1),
265 + FREQ2FBIN(2462, 1)
266 + },
267 + {
268 + FREQ2FBIN(2412, 1),
269 + FREQ2FBIN(2417, 1),
270 + FREQ2FBIN(2462, 1),
271 + 0xFF,
272 + },
273 +
274 + {
275 + FREQ2FBIN(2412, 1),
276 + FREQ2FBIN(2417, 1),
277 + FREQ2FBIN(2462, 1),
278 + 0xFF,
279 + },
280 + {
281 + FREQ2FBIN(2422, 1),
282 + FREQ2FBIN(2427, 1),
283 + FREQ2FBIN(2447, 1),
284 + FREQ2FBIN(2452, 1)
285 + },
286 +
287 + {
288 + /* Data[4].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
289 + /* Data[4].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
290 + /* Data[4].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
291 + /* Data[4].ctlEdges[3].bChannel */ FREQ2FBIN(2484, 1),
292 + },
293 +
294 + {
295 + /* Data[5].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
296 + /* Data[5].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
297 + /* Data[5].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
298 + 0,
299 + },
300 +
301 + {
302 + /* Data[6].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
303 + /* Data[6].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
304 + FREQ2FBIN(2472, 1),
305 + 0,
306 + },
307 +
308 + {
309 + /* Data[7].ctlEdges[0].bChannel */ FREQ2FBIN(2422, 1),
310 + /* Data[7].ctlEdges[1].bChannel */ FREQ2FBIN(2427, 1),
311 + /* Data[7].ctlEdges[2].bChannel */ FREQ2FBIN(2447, 1),
312 + /* Data[7].ctlEdges[3].bChannel */ FREQ2FBIN(2462, 1),
313 + },
314 +
315 + {
316 + /* Data[8].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
317 + /* Data[8].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
318 + /* Data[8].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
319 + },
320 +
321 + {
322 + /* Data[9].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
323 + /* Data[9].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
324 + /* Data[9].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
325 + 0
326 + },
327 +
328 + {
329 + /* Data[10].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
330 + /* Data[10].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
331 + /* Data[10].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
332 + 0
333 + },
334 +
335 + {
336 + /* Data[11].ctlEdges[0].bChannel */ FREQ2FBIN(2422, 1),
337 + /* Data[11].ctlEdges[1].bChannel */ FREQ2FBIN(2427, 1),
338 + /* Data[11].ctlEdges[2].bChannel */ FREQ2FBIN(2447, 1),
339 + /* Data[11].ctlEdges[3].bChannel */ FREQ2FBIN(2462, 1),
340 + }
341 + },
342 + .ctlPowerData_2G = {
343 + { { {60, 0}, {60, 1}, {60, 0}, {60, 0} } },
344 + { { {60, 0}, {60, 1}, {60, 0}, {60, 0} } },
345 + { { {60, 1}, {60, 0}, {60, 0}, {60, 1} } },
346 +
347 + { { {60, 1}, {60, 0}, {0, 0}, {0, 0} } },
348 + { { {60, 0}, {60, 1}, {60, 0}, {60, 0} } },
349 + { { {60, 0}, {60, 1}, {60, 0}, {60, 0} } },
350 +
351 + { { {60, 0}, {60, 1}, {60, 1}, {60, 0} } },
352 + { { {60, 0}, {60, 1}, {60, 0}, {60, 0} } },
353 + { { {60, 0}, {60, 1}, {60, 0}, {60, 0} } },
354 +
355 + { { {60, 0}, {60, 1}, {60, 0}, {60, 0} } },
356 + { { {60, 0}, {60, 1}, {60, 1}, {60, 1} } },
357 + { { {60, 0}, {60, 1}, {60, 1}, {60, 1} } },
358 + },
359 + .modalHeader5G = {
360 + /* 4 idle,t1,t2,b (4 bits per setting) */
361 + .antCtrlCommon = LE32(0x110),
362 + /* 4 ra1l1, ra2l1, ra1l2,ra2l2,ra12 */
363 + .antCtrlCommon2 = LE32(0x22222),
364 + /* antCtrlChain 6 idle, t,r,rx1,rx12,b (2 bits each) */
365 + .antCtrlChain = {
366 + LE16(0x000), LE16(0x000), LE16(0x000),
367 + },
368 + /* xatten1DB 3 xatten1_db for AR9280 (0xa20c/b20c 5:0) */
369 + .xatten1DB = {0, 0, 0},
370 +
371 + /*
372 + * xatten1Margin[AR9300_MAX_CHAINS]; 3 xatten1_margin
373 + * for merlin (0xa20c/b20c 16:12
374 + */
375 + .xatten1Margin = {0, 0, 0},
376 + .tempSlope = 68,
377 + .voltSlope = 0,
378 + /* spurChans spur channels in usual fbin coding format */
379 + .spurChans = {0, 0, 0, 0, 0},
380 + /* noiseFloorThreshCh Check if the register is per chain */
381 + .noiseFloorThreshCh = {-1, 0, 0},
382 + .ob = {3, 3, 3}, /* 3 chain */
383 + .db_stage2 = {3, 3, 3}, /* 3 chain */
384 + .db_stage3 = {3, 3, 3}, /* doesn't exist for 2G */
385 + .db_stage4 = {3, 3, 3}, /* don't exist for 2G */
386 + .xpaBiasLvl = 0,
387 + .txFrameToDataStart = 0x0e,
388 + .txFrameToPaOn = 0x0e,
389 + .txClip = 3, /* 4 bits tx_clip, 4 bits dac_scale_cck */
390 + .antennaGain = 0,
391 + .switchSettling = 0x2d,
392 + .adcDesiredSize = -30,
393 + .txEndToXpaOff = 0,
394 + .txEndToRxOn = 0x2,
395 + .txFrameToXpaOn = 0xe,
396 + .thresh62 = 28,
397 + .papdRateMaskHt20 = LE32(0x0c80c080),
398 + .papdRateMaskHt40 = LE32(0x0080c080),
399 + .futureModal = {
400 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
401 + },
402 + },
403 + .base_ext2 = {
404 + .tempSlopeLow = 0,
405 + .tempSlopeHigh = 0,
406 + .xatten1DBLow = {0, 0, 0},
407 + .xatten1MarginLow = {0, 0, 0},
408 + .xatten1DBHigh = {0, 0, 0},
409 + .xatten1MarginHigh = {0, 0, 0}
410 + },
411 + .calFreqPier5G = {
412 + FREQ2FBIN(5180, 0),
413 + FREQ2FBIN(5220, 0),
414 + FREQ2FBIN(5320, 0),
415 + FREQ2FBIN(5400, 0),
416 + FREQ2FBIN(5500, 0),
417 + FREQ2FBIN(5600, 0),
418 + FREQ2FBIN(5725, 0),
419 + FREQ2FBIN(5825, 0)
420 + },
421 + .calPierData5G = {
422 + {
423 + {0, 0, 0, 0, 0},
424 + {0, 0, 0, 0, 0},
425 + {0, 0, 0, 0, 0},
426 + {0, 0, 0, 0, 0},
427 + {0, 0, 0, 0, 0},
428 + {0, 0, 0, 0, 0},
429 + {0, 0, 0, 0, 0},
430 + {0, 0, 0, 0, 0},
431 + },
432 + {
433 + {0, 0, 0, 0, 0},
434 + {0, 0, 0, 0, 0},
435 + {0, 0, 0, 0, 0},
436 + {0, 0, 0, 0, 0},
437 + {0, 0, 0, 0, 0},
438 + {0, 0, 0, 0, 0},
439 + {0, 0, 0, 0, 0},
440 + {0, 0, 0, 0, 0},
441 + },
442 + {
443 + {0, 0, 0, 0, 0},
444 + {0, 0, 0, 0, 0},
445 + {0, 0, 0, 0, 0},
446 + {0, 0, 0, 0, 0},
447 + {0, 0, 0, 0, 0},
448 + {0, 0, 0, 0, 0},
449 + {0, 0, 0, 0, 0},
450 + {0, 0, 0, 0, 0},
451 + },
452 +
453 + },
454 + .calTarget_freqbin_5G = {
455 + FREQ2FBIN(5180, 0),
456 + FREQ2FBIN(5220, 0),
457 + FREQ2FBIN(5320, 0),
458 + FREQ2FBIN(5400, 0),
459 + FREQ2FBIN(5500, 0),
460 + FREQ2FBIN(5600, 0),
461 + FREQ2FBIN(5725, 0),
462 + FREQ2FBIN(5825, 0)
463 + },
464 + .calTarget_freqbin_5GHT20 = {
465 + FREQ2FBIN(5180, 0),
466 + FREQ2FBIN(5240, 0),
467 + FREQ2FBIN(5320, 0),
468 + FREQ2FBIN(5500, 0),
469 + FREQ2FBIN(5700, 0),
470 + FREQ2FBIN(5745, 0),
471 + FREQ2FBIN(5725, 0),
472 + FREQ2FBIN(5825, 0)
473 + },
474 + .calTarget_freqbin_5GHT40 = {
475 + FREQ2FBIN(5180, 0),
476 + FREQ2FBIN(5240, 0),
477 + FREQ2FBIN(5320, 0),
478 + FREQ2FBIN(5500, 0),
479 + FREQ2FBIN(5700, 0),
480 + FREQ2FBIN(5745, 0),
481 + FREQ2FBIN(5725, 0),
482 + FREQ2FBIN(5825, 0)
483 + },
484 + .calTargetPower5G = {
485 + /* 6-24,36,48,54 */
486 + { {20, 20, 20, 10} },
487 + { {20, 20, 20, 10} },
488 + { {20, 20, 20, 10} },
489 + { {20, 20, 20, 10} },
490 + { {20, 20, 20, 10} },
491 + { {20, 20, 20, 10} },
492 + { {20, 20, 20, 10} },
493 + { {20, 20, 20, 10} },
494 + },
495 + .calTargetPower5GHT20 = {
496 + /*
497 + * 0_8_16,1-3_9-11_17-19,
498 + * 4,5,6,7,12,13,14,15,20,21,22,23
499 + */
500 + { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
501 + { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
502 + { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
503 + { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
504 + { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
505 + { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
506 + { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
507 + { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
508 + },
509 + .calTargetPower5GHT40 = {
510 + /*
511 + * 0_8_16,1-3_9-11_17-19,
512 + * 4,5,6,7,12,13,14,15,20,21,22,23
513 + */
514 + { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
515 + { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
516 + { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
517 + { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
518 + { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
519 + { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
520 + { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
521 + { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
522 + },
523 + .ctlIndex_5G = {
524 + 0x10, 0x16, 0x18, 0x40, 0x46,
525 + 0x48, 0x30, 0x36, 0x38
526 + },
527 + .ctl_freqbin_5G = {
528 + {
529 + /* Data[0].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
530 + /* Data[0].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
531 + /* Data[0].ctlEdges[2].bChannel */ FREQ2FBIN(5280, 0),
532 + /* Data[0].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0),
533 + /* Data[0].ctlEdges[4].bChannel */ FREQ2FBIN(5600, 0),
534 + /* Data[0].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
535 + /* Data[0].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0),
536 + /* Data[0].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0)
537 + },
538 + {
539 + /* Data[1].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
540 + /* Data[1].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
541 + /* Data[1].ctlEdges[2].bChannel */ FREQ2FBIN(5280, 0),
542 + /* Data[1].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0),
543 + /* Data[1].ctlEdges[4].bChannel */ FREQ2FBIN(5520, 0),
544 + /* Data[1].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
545 + /* Data[1].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0),
546 + /* Data[1].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0)
547 + },
548 +
549 + {
550 + /* Data[2].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0),
551 + /* Data[2].ctlEdges[1].bChannel */ FREQ2FBIN(5230, 0),
552 + /* Data[2].ctlEdges[2].bChannel */ FREQ2FBIN(5270, 0),
553 + /* Data[2].ctlEdges[3].bChannel */ FREQ2FBIN(5310, 0),
554 + /* Data[2].ctlEdges[4].bChannel */ FREQ2FBIN(5510, 0),
555 + /* Data[2].ctlEdges[5].bChannel */ FREQ2FBIN(5550, 0),
556 + /* Data[2].ctlEdges[6].bChannel */ FREQ2FBIN(5670, 0),
557 + /* Data[2].ctlEdges[7].bChannel */ FREQ2FBIN(5755, 0)
558 + },
559 +
560 + {
561 + /* Data[3].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
562 + /* Data[3].ctlEdges[1].bChannel */ FREQ2FBIN(5200, 0),
563 + /* Data[3].ctlEdges[2].bChannel */ FREQ2FBIN(5260, 0),
564 + /* Data[3].ctlEdges[3].bChannel */ FREQ2FBIN(5320, 0),
565 + /* Data[3].ctlEdges[4].bChannel */ FREQ2FBIN(5500, 0),
566 + /* Data[3].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
567 + /* Data[3].ctlEdges[6].bChannel */ 0xFF,
568 + /* Data[3].ctlEdges[7].bChannel */ 0xFF,
569 + },
570 +
571 + {
572 + /* Data[4].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
573 + /* Data[4].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
574 + /* Data[4].ctlEdges[2].bChannel */ FREQ2FBIN(5500, 0),
575 + /* Data[4].ctlEdges[3].bChannel */ FREQ2FBIN(5700, 0),
576 + /* Data[4].ctlEdges[4].bChannel */ 0xFF,
577 + /* Data[4].ctlEdges[5].bChannel */ 0xFF,
578 + /* Data[4].ctlEdges[6].bChannel */ 0xFF,
579 + /* Data[4].ctlEdges[7].bChannel */ 0xFF,
580 + },
581 +
582 + {
583 + /* Data[5].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0),
584 + /* Data[5].ctlEdges[1].bChannel */ FREQ2FBIN(5270, 0),
585 + /* Data[5].ctlEdges[2].bChannel */ FREQ2FBIN(5310, 0),
586 + /* Data[5].ctlEdges[3].bChannel */ FREQ2FBIN(5510, 0),
587 + /* Data[5].ctlEdges[4].bChannel */ FREQ2FBIN(5590, 0),
588 + /* Data[5].ctlEdges[5].bChannel */ FREQ2FBIN(5670, 0),
589 + /* Data[5].ctlEdges[6].bChannel */ 0xFF,
590 + /* Data[5].ctlEdges[7].bChannel */ 0xFF
591 + },
592 +
593 + {
594 + /* Data[6].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
595 + /* Data[6].ctlEdges[1].bChannel */ FREQ2FBIN(5200, 0),
596 + /* Data[6].ctlEdges[2].bChannel */ FREQ2FBIN(5220, 0),
597 + /* Data[6].ctlEdges[3].bChannel */ FREQ2FBIN(5260, 0),
598 + /* Data[6].ctlEdges[4].bChannel */ FREQ2FBIN(5500, 0),
599 + /* Data[6].ctlEdges[5].bChannel */ FREQ2FBIN(5600, 0),
600 + /* Data[6].ctlEdges[6].bChannel */ FREQ2FBIN(5700, 0),
601 + /* Data[6].ctlEdges[7].bChannel */ FREQ2FBIN(5745, 0)
602 + },
603 +
604 + {
605 + /* Data[7].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
606 + /* Data[7].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
607 + /* Data[7].ctlEdges[2].bChannel */ FREQ2FBIN(5320, 0),
608 + /* Data[7].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0),
609 + /* Data[7].ctlEdges[4].bChannel */ FREQ2FBIN(5560, 0),
610 + /* Data[7].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
611 + /* Data[7].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0),
612 + /* Data[7].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0)
613 + },
614 +
615 + {
616 + /* Data[8].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0),
617 + /* Data[8].ctlEdges[1].bChannel */ FREQ2FBIN(5230, 0),
618 + /* Data[8].ctlEdges[2].bChannel */ FREQ2FBIN(5270, 0),
619 + /* Data[8].ctlEdges[3].bChannel */ FREQ2FBIN(5510, 0),
620 + /* Data[8].ctlEdges[4].bChannel */ FREQ2FBIN(5550, 0),
621 + /* Data[8].ctlEdges[5].bChannel */ FREQ2FBIN(5670, 0),
622 + /* Data[8].ctlEdges[6].bChannel */ FREQ2FBIN(5755, 0),
623 + /* Data[8].ctlEdges[7].bChannel */ FREQ2FBIN(5795, 0)
624 + }
625 + },
626 + .ctlPowerData_5G = {
627 + {
628 + {
629 + {60, 1}, {60, 1}, {60, 1}, {60, 1},
630 + {60, 1}, {60, 1}, {60, 1}, {60, 0},
631 + }
632 + },
633 + {
634 + {
635 + {60, 1}, {60, 1}, {60, 1}, {60, 1},
636 + {60, 1}, {60, 1}, {60, 1}, {60, 0},
637 + }
638 + },
639 + {
640 + {
641 + {60, 0}, {60, 1}, {60, 0}, {60, 1},
642 + {60, 1}, {60, 1}, {60, 1}, {60, 1},
643 + }
644 + },
645 + {
646 + {
647 + {60, 0}, {60, 1}, {60, 1}, {60, 0},
648 + {60, 1}, {60, 0}, {60, 0}, {60, 0},
649 + }
650 + },
651 + {
652 + {
653 + {60, 1}, {60, 1}, {60, 1}, {60, 0},
654 + {60, 0}, {60, 0}, {60, 0}, {60, 0},
655 + }
656 + },
657 + {
658 + {
659 + {60, 1}, {60, 1}, {60, 1}, {60, 1},
660 + {60, 1}, {60, 0}, {60, 0}, {60, 0},
661 + }
662 + },
663 + {
664 + {
665 + {60, 1}, {60, 1}, {60, 1}, {60, 1},
666 + {60, 1}, {60, 1}, {60, 1}, {60, 1},
667 + }
668 + },
669 + {
670 + {
671 + {60, 1}, {60, 1}, {60, 0}, {60, 1},
672 + {60, 1}, {60, 1}, {60, 1}, {60, 0},
673 + }
674 + },
675 + {
676 + {
677 + {60, 1}, {60, 0}, {60, 1}, {60, 1},
678 + {60, 1}, {60, 1}, {60, 0}, {60, 1},
679 + }
680 + },
681 + }
682 +};
683 +
684 +static const struct ar9300_eeprom ar9300_x113 = {
685 + .eepromVersion = 2,
686 + .templateVersion = 6,
687 + .macAddr = {0x00, 0x03, 0x7f, 0x0, 0x0, 0x0},
688 + .custData = {"x113-023-f0000"},
689 + .baseEepHeader = {
690 + .regDmn = { LE16(0), LE16(0x1f) },
691 + .txrxMask = 0x77, /* 4 bits tx and 4 bits rx */
692 + .opCapFlags = {
693 + .opFlags = AR9300_OPFLAGS_11G | AR9300_OPFLAGS_11A,
694 + .eepMisc = 0,
695 + },
696 + .rfSilent = 0,
697 + .blueToothOptions = 0,
698 + .deviceCap = 0,
699 + .deviceType = 5, /* takes lower byte in eeprom location */
700 + .pwrTableOffset = AR9300_PWR_TABLE_OFFSET,
701 + .params_for_tuning_caps = {0, 0},
702 + .featureEnable = 0x0d,
703 + /*
704 + * bit0 - enable tx temp comp - disabled
705 + * bit1 - enable tx volt comp - disabled
706 + * bit2 - enable fastClock - enabled
707 + * bit3 - enable doubling - enabled
708 + * bit4 - enable internal regulator - disabled
709 + * bit5 - enable pa predistortion - disabled
710 + */
711 + .miscConfiguration = 0, /* bit0 - turn down drivestrength */
712 + .eepromWriteEnableGpio = 6,
713 + .wlanDisableGpio = 0,
714 + .wlanLedGpio = 8,
715 + .rxBandSelectGpio = 0xff,
716 + .txrxgain = 0x21,
717 + .swreg = 0,
718 + },
719 + .modalHeader2G = {
720 + /* ar9300_modal_eep_header 2g */
721 + /* 4 idle,t1,t2,b(4 bits per setting) */
722 + .antCtrlCommon = LE32(0x110),
723 + /* 4 ra1l1, ra2l1, ra1l2, ra2l2, ra12 */
724 + .antCtrlCommon2 = LE32(0x44444),
725 +
726 + /*
727 + * antCtrlChain[AR9300_MAX_CHAINS]; 6 idle, t, r,
728 + * rx1, rx12, b (2 bits each)
729 + */
730 + .antCtrlChain = { LE16(0x150), LE16(0x150), LE16(0x150) },
731 +
732 + /*
733 + * xatten1DB[AR9300_MAX_CHAINS]; 3 xatten1_db
734 + * for ar9280 (0xa20c/b20c 5:0)
735 + */
736 + .xatten1DB = {0, 0, 0},
737 +
738 + /*
739 + * xatten1Margin[AR9300_MAX_CHAINS]; 3 xatten1_margin
740 + * for ar9280 (0xa20c/b20c 16:12
741 + */
742 + .xatten1Margin = {0, 0, 0},
743 + .tempSlope = 25,
744 + .voltSlope = 0,
745 +
746 + /*
747 + * spurChans[OSPREY_EEPROM_MODAL_SPURS]; spur
748 + * channels in usual fbin coding format
749 + */
750 + .spurChans = {FREQ2FBIN(2464, 1), 0, 0, 0, 0},
751 +
752 + /*
753 + * noiseFloorThreshCh[AR9300_MAX_CHAINS]; 3 Check
754 + * if the register is per chain
755 + */
756 + .noiseFloorThreshCh = {-1, 0, 0},
757 + .ob = {1, 1, 1},/* 3 chain */
758 + .db_stage2 = {1, 1, 1}, /* 3 chain */
759 + .db_stage3 = {0, 0, 0},
760 + .db_stage4 = {0, 0, 0},
761 + .xpaBiasLvl = 0,
762 + .txFrameToDataStart = 0x0e,
763 + .txFrameToPaOn = 0x0e,
764 + .txClip = 3, /* 4 bits tx_clip, 4 bits dac_scale_cck */
765 + .antennaGain = 0,
766 + .switchSettling = 0x2c,
767 + .adcDesiredSize = -30,
768 + .txEndToXpaOff = 0,
769 + .txEndToRxOn = 0x2,
770 + .txFrameToXpaOn = 0xe,
771 + .thresh62 = 28,
772 + .papdRateMaskHt20 = LE32(0x0c80c080),
773 + .papdRateMaskHt40 = LE32(0x0080c080),
774 + .futureModal = {
775 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
776 + },
777 + },
778 + .base_ext1 = {
779 + .ant_div_control = 0,
780 + .future = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}
781 + },
782 + .calFreqPier2G = {
783 + FREQ2FBIN(2412, 1),
784 + FREQ2FBIN(2437, 1),
785 + FREQ2FBIN(2472, 1),
786 + },
787 + /* ar9300_cal_data_per_freq_op_loop 2g */
788 + .calPierData2G = {
789 + { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
790 + { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
791 + { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
792 + },
793 + .calTarget_freqbin_Cck = {
794 + FREQ2FBIN(2412, 1),
795 + FREQ2FBIN(2472, 1),
796 + },
797 + .calTarget_freqbin_2G = {
798 + FREQ2FBIN(2412, 1),
799 + FREQ2FBIN(2437, 1),
800 + FREQ2FBIN(2472, 1)
801 + },
802 + .calTarget_freqbin_2GHT20 = {
803 + FREQ2FBIN(2412, 1),
804 + FREQ2FBIN(2437, 1),
805 + FREQ2FBIN(2472, 1)
806 + },
807 + .calTarget_freqbin_2GHT40 = {
808 + FREQ2FBIN(2412, 1),
809 + FREQ2FBIN(2437, 1),
810 + FREQ2FBIN(2472, 1)
811 + },
812 + .calTargetPowerCck = {
813 + /* 1L-5L,5S,11L,11S */
814 + { {34, 34, 34, 34} },
815 + { {34, 34, 34, 34} },
816 + },
817 + .calTargetPower2G = {
818 + /* 6-24,36,48,54 */
819 + { {34, 34, 32, 32} },
820 + { {34, 34, 32, 32} },
821 + { {34, 34, 32, 32} },
822 + },
823 + .calTargetPower2GHT20 = {
824 + { {32, 32, 32, 32, 32, 28, 32, 32, 30, 28, 0, 0, 0, 0} },
825 + { {32, 32, 32, 32, 32, 28, 32, 32, 30, 28, 0, 0, 0, 0} },
826 + { {32, 32, 32, 32, 32, 28, 32, 32, 30, 28, 0, 0, 0, 0} },
827 + },
828 + .calTargetPower2GHT40 = {
829 + { {30, 30, 30, 30, 30, 28, 30, 30, 28, 26, 0, 0, 0, 0} },
830 + { {30, 30, 30, 30, 30, 28, 30, 30, 28, 26, 0, 0, 0, 0} },
831 + { {30, 30, 30, 30, 30, 28, 30, 30, 28, 26, 0, 0, 0, 0} },
832 + },
833 + .ctlIndex_2G = {
834 + 0x11, 0x12, 0x15, 0x17, 0x41, 0x42,
835 + 0x45, 0x47, 0x31, 0x32, 0x35, 0x37,
836 + },
837 + .ctl_freqbin_2G = {
838 + {
839 + FREQ2FBIN(2412, 1),
840 + FREQ2FBIN(2417, 1),
841 + FREQ2FBIN(2457, 1),
842 + FREQ2FBIN(2462, 1)
843 + },
844 + {
845 + FREQ2FBIN(2412, 1),
846 + FREQ2FBIN(2417, 1),
847 + FREQ2FBIN(2462, 1),
848 + 0xFF,
849 + },
850 +
851 + {
852 + FREQ2FBIN(2412, 1),
853 + FREQ2FBIN(2417, 1),
854 + FREQ2FBIN(2462, 1),
855 + 0xFF,
856 + },
857 + {
858 + FREQ2FBIN(2422, 1),
859 + FREQ2FBIN(2427, 1),
860 + FREQ2FBIN(2447, 1),
861 + FREQ2FBIN(2452, 1)
862 + },
863 +
864 + {
865 + /* Data[4].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
866 + /* Data[4].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
867 + /* Data[4].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
868 + /* Data[4].ctlEdges[3].bChannel */ FREQ2FBIN(2484, 1),
869 + },
870 +
871 + {
872 + /* Data[5].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
873 + /* Data[5].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
874 + /* Data[5].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
875 + 0,
876 + },
877 +
878 + {
879 + /* Data[6].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
880 + /* Data[6].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
881 + FREQ2FBIN(2472, 1),
882 + 0,
883 + },
884 +
885 + {
886 + /* Data[7].ctlEdges[0].bChannel */ FREQ2FBIN(2422, 1),
887 + /* Data[7].ctlEdges[1].bChannel */ FREQ2FBIN(2427, 1),
888 + /* Data[7].ctlEdges[2].bChannel */ FREQ2FBIN(2447, 1),
889 + /* Data[7].ctlEdges[3].bChannel */ FREQ2FBIN(2462, 1),
890 + },
891 +
892 + {
893 + /* Data[8].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
894 + /* Data[8].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
895 + /* Data[8].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
896 + },
897 +
898 + {
899 + /* Data[9].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
900 + /* Data[9].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
901 + /* Data[9].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
902 + 0
903 + },
904 +
905 + {
906 + /* Data[10].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
907 + /* Data[10].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
908 + /* Data[10].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
909 + 0
910 + },
911 +
912 + {
913 + /* Data[11].ctlEdges[0].bChannel */ FREQ2FBIN(2422, 1),
914 + /* Data[11].ctlEdges[1].bChannel */ FREQ2FBIN(2427, 1),
915 + /* Data[11].ctlEdges[2].bChannel */ FREQ2FBIN(2447, 1),
916 + /* Data[11].ctlEdges[3].bChannel */ FREQ2FBIN(2462, 1),
917 + }
918 + },
919 + .ctlPowerData_2G = {
920 + { { {60, 0}, {60, 1}, {60, 0}, {60, 0} } },
921 + { { {60, 0}, {60, 1}, {60, 0}, {60, 0} } },
922 + { { {60, 1}, {60, 0}, {60, 0}, {60, 1} } },
923 +
924 + { { {60, 1}, {60, 0}, {0, 0}, {0, 0} } },
925 + { { {60, 0}, {60, 1}, {60, 0}, {60, 0} } },
926 + { { {60, 0}, {60, 1}, {60, 0}, {60, 0} } },
927 +
928 + { { {60, 0}, {60, 1}, {60, 1}, {60, 0} } },
929 + { { {60, 0}, {60, 1}, {60, 0}, {60, 0} } },
930 + { { {60, 0}, {60, 1}, {60, 0}, {60, 0} } },
931 +
932 + { { {60, 0}, {60, 1}, {60, 0}, {60, 0} } },
933 + { { {60, 0}, {60, 1}, {60, 1}, {60, 1} } },
934 + { { {60, 0}, {60, 1}, {60, 1}, {60, 1} } },
935 + },
936 + .modalHeader5G = {
937 + /* 4 idle,t1,t2,b (4 bits per setting) */
938 + .antCtrlCommon = LE32(0x220),
939 + /* 4 ra1l1, ra2l1, ra1l2,ra2l2,ra12 */
940 + .antCtrlCommon2 = LE32(0x11111),
941 + /* antCtrlChain 6 idle, t,r,rx1,rx12,b (2 bits each) */
942 + .antCtrlChain = {
943 + LE16(0x150), LE16(0x150), LE16(0x150),
944 + },
945 + /* xatten1DB 3 xatten1_db for AR9280 (0xa20c/b20c 5:0) */
946 + .xatten1DB = {0, 0, 0},
947 +
948 + /*
949 + * xatten1Margin[AR9300_MAX_CHAINS]; 3 xatten1_margin
950 + * for merlin (0xa20c/b20c 16:12
951 + */
952 + .xatten1Margin = {0, 0, 0},
953 + .tempSlope = 68,
954 + .voltSlope = 0,
955 + /* spurChans spur channels in usual fbin coding format */
956 + .spurChans = {FREQ2FBIN(5500, 0), 0, 0, 0, 0},
957 + /* noiseFloorThreshCh Check if the register is per chain */
958 + .noiseFloorThreshCh = {-1, 0, 0},
959 + .ob = {3, 3, 3}, /* 3 chain */
960 + .db_stage2 = {3, 3, 3}, /* 3 chain */
961 + .db_stage3 = {3, 3, 3}, /* doesn't exist for 2G */
962 + .db_stage4 = {3, 3, 3}, /* don't exist for 2G */
963 + .xpaBiasLvl = 0,
964 + .txFrameToDataStart = 0x0e,
965 + .txFrameToPaOn = 0x0e,
966 + .txClip = 3, /* 4 bits tx_clip, 4 bits dac_scale_cck */
967 + .antennaGain = 0,
968 + .switchSettling = 0x2d,
969 + .adcDesiredSize = -30,
970 + .txEndToXpaOff = 0,
971 + .txEndToRxOn = 0x2,
972 + .txFrameToXpaOn = 0xe,
973 + .thresh62 = 28,
974 + .papdRateMaskHt20 = LE32(0x0cf0e0e0),
975 + .papdRateMaskHt40 = LE32(0x6cf0e0e0),
976 + .futureModal = {
977 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
978 + },
979 + },
980 + .base_ext2 = {
981 + .tempSlopeLow = 72,
982 + .tempSlopeHigh = 105,
983 + .xatten1DBLow = {0, 0, 0},
984 + .xatten1MarginLow = {0, 0, 0},
985 + .xatten1DBHigh = {0, 0, 0},
986 + .xatten1MarginHigh = {0, 0, 0}
987 + },
988 + .calFreqPier5G = {
989 + FREQ2FBIN(5180, 0),
990 + FREQ2FBIN(5240, 0),
991 + FREQ2FBIN(5320, 0),
992 + FREQ2FBIN(5400, 0),
993 + FREQ2FBIN(5500, 0),
994 + FREQ2FBIN(5600, 0),
995 + FREQ2FBIN(5745, 0),
996 + FREQ2FBIN(5785, 0)
997 + },
998 + .calPierData5G = {
999 + {
1000 + {0, 0, 0, 0, 0},
1001 + {0, 0, 0, 0, 0},
1002 + {0, 0, 0, 0, 0},
1003 + {0, 0, 0, 0, 0},
1004 + {0, 0, 0, 0, 0},
1005 + {0, 0, 0, 0, 0},
1006 + {0, 0, 0, 0, 0},
1007 + {0, 0, 0, 0, 0},
1008 + },
1009 + {
1010 + {0, 0, 0, 0, 0},
1011 + {0, 0, 0, 0, 0},
1012 + {0, 0, 0, 0, 0},
1013 + {0, 0, 0, 0, 0},
1014 + {0, 0, 0, 0, 0},
1015 + {0, 0, 0, 0, 0},
1016 + {0, 0, 0, 0, 0},
1017 + {0, 0, 0, 0, 0},
1018 + },
1019 + {
1020 + {0, 0, 0, 0, 0},
1021 + {0, 0, 0, 0, 0},
1022 + {0, 0, 0, 0, 0},
1023 + {0, 0, 0, 0, 0},
1024 + {0, 0, 0, 0, 0},
1025 + {0, 0, 0, 0, 0},
1026 + {0, 0, 0, 0, 0},
1027 + {0, 0, 0, 0, 0},
1028 + },
1029 +
1030 + },
1031 + .calTarget_freqbin_5G = {
1032 + FREQ2FBIN(5180, 0),
1033 + FREQ2FBIN(5220, 0),
1034 + FREQ2FBIN(5320, 0),
1035 + FREQ2FBIN(5400, 0),
1036 + FREQ2FBIN(5500, 0),
1037 + FREQ2FBIN(5600, 0),
1038 + FREQ2FBIN(5745, 0),
1039 + FREQ2FBIN(5785, 0)
1040 + },
1041 + .calTarget_freqbin_5GHT20 = {
1042 + FREQ2FBIN(5180, 0),
1043 + FREQ2FBIN(5240, 0),
1044 + FREQ2FBIN(5320, 0),
1045 + FREQ2FBIN(5400, 0),
1046 + FREQ2FBIN(5500, 0),
1047 + FREQ2FBIN(5700, 0),
1048 + FREQ2FBIN(5745, 0),
1049 + FREQ2FBIN(5825, 0)
1050 + },
1051 + .calTarget_freqbin_5GHT40 = {
1052 + FREQ2FBIN(5190, 0),
1053 + FREQ2FBIN(5230, 0),
1054 + FREQ2FBIN(5320, 0),
1055 + FREQ2FBIN(5410, 0),
1056 + FREQ2FBIN(5510, 0),
1057 + FREQ2FBIN(5670, 0),
1058 + FREQ2FBIN(5755, 0),
1059 + FREQ2FBIN(5825, 0)
1060 + },
1061 + .calTargetPower5G = {
1062 + /* 6-24,36,48,54 */
1063 + { {42, 40, 40, 34} },
1064 + { {42, 40, 40, 34} },
1065 + { {42, 40, 40, 34} },
1066 + { {42, 40, 40, 34} },
1067 + { {42, 40, 40, 34} },
1068 + { {42, 40, 40, 34} },
1069 + { {42, 40, 40, 34} },
1070 + { {42, 40, 40, 34} },
1071 + },
1072 + .calTargetPower5GHT20 = {
1073 + /*
1074 + * 0_8_16,1-3_9-11_17-19,
1075 + * 4,5,6,7,12,13,14,15,20,21,22,23
1076 + */
1077 + { {40, 40, 40, 40, 32, 28, 40, 40, 32, 28, 40, 40, 32, 20} },
1078 + { {40, 40, 40, 40, 32, 28, 40, 40, 32, 28, 40, 40, 32, 20} },
1079 + { {40, 40, 40, 40, 32, 28, 40, 40, 32, 28, 40, 40, 32, 20} },
1080 + { {40, 40, 40, 40, 32, 28, 40, 40, 32, 28, 40, 40, 32, 20} },
1081 + { {40, 40, 40, 40, 32, 28, 40, 40, 32, 28, 40, 40, 32, 20} },
1082 + { {40, 40, 40, 40, 32, 28, 40, 40, 32, 28, 40, 40, 32, 20} },
1083 + { {38, 38, 38, 38, 32, 28, 38, 38, 32, 28, 38, 38, 32, 26} },
1084 + { {36, 36, 36, 36, 32, 28, 36, 36, 32, 28, 36, 36, 32, 26} },
1085 + },
1086 + .calTargetPower5GHT40 = {
1087 + /*
1088 + * 0_8_16,1-3_9-11_17-19,
1089 + * 4,5,6,7,12,13,14,15,20,21,22,23
1090 + */
1091 + { {40, 40, 40, 38, 30, 26, 40, 40, 30, 26, 40, 40, 30, 24} },
1092 + { {40, 40, 40, 38, 30, 26, 40, 40, 30, 26, 40, 40, 30, 24} },
1093 + { {40, 40, 40, 38, 30, 26, 40, 40, 30, 26, 40, 40, 30, 24} },
1094 + { {40, 40, 40, 38, 30, 26, 40, 40, 30, 26, 40, 40, 30, 24} },
1095 + { {40, 40, 40, 38, 30, 26, 40, 40, 30, 26, 40, 40, 30, 24} },
1096 + { {40, 40, 40, 38, 30, 26, 40, 40, 30, 26, 40, 40, 30, 24} },
1097 + { {36, 36, 36, 36, 30, 26, 36, 36, 30, 26, 36, 36, 30, 24} },
1098 + { {34, 34, 34, 34, 30, 26, 34, 34, 30, 26, 34, 34, 30, 24} },
1099 + },
1100 + .ctlIndex_5G = {
1101 + 0x10, 0x16, 0x18, 0x40, 0x46,
1102 + 0x48, 0x30, 0x36, 0x38
1103 + },
1104 + .ctl_freqbin_5G = {
1105 + {
1106 + /* Data[0].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
1107 + /* Data[0].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
1108 + /* Data[0].ctlEdges[2].bChannel */ FREQ2FBIN(5280, 0),
1109 + /* Data[0].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0),
1110 + /* Data[0].ctlEdges[4].bChannel */ FREQ2FBIN(5600, 0),
1111 + /* Data[0].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
1112 + /* Data[0].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0),
1113 + /* Data[0].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0)
1114 + },
1115 + {
1116 + /* Data[1].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
1117 + /* Data[1].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
1118 + /* Data[1].ctlEdges[2].bChannel */ FREQ2FBIN(5280, 0),
1119 + /* Data[1].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0),
1120 + /* Data[1].ctlEdges[4].bChannel */ FREQ2FBIN(5520, 0),
1121 + /* Data[1].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
1122 + /* Data[1].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0),
1123 + /* Data[1].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0)
1124 + },
1125 +
1126 + {
1127 + /* Data[2].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0),
1128 + /* Data[2].ctlEdges[1].bChannel */ FREQ2FBIN(5230, 0),
1129 + /* Data[2].ctlEdges[2].bChannel */ FREQ2FBIN(5270, 0),
1130 + /* Data[2].ctlEdges[3].bChannel */ FREQ2FBIN(5310, 0),
1131 + /* Data[2].ctlEdges[4].bChannel */ FREQ2FBIN(5510, 0),
1132 + /* Data[2].ctlEdges[5].bChannel */ FREQ2FBIN(5550, 0),
1133 + /* Data[2].ctlEdges[6].bChannel */ FREQ2FBIN(5670, 0),
1134 + /* Data[2].ctlEdges[7].bChannel */ FREQ2FBIN(5755, 0)
1135 + },
1136 +
1137 + {
1138 + /* Data[3].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
1139 + /* Data[3].ctlEdges[1].bChannel */ FREQ2FBIN(5200, 0),
1140 + /* Data[3].ctlEdges[2].bChannel */ FREQ2FBIN(5260, 0),
1141 + /* Data[3].ctlEdges[3].bChannel */ FREQ2FBIN(5320, 0),
1142 + /* Data[3].ctlEdges[4].bChannel */ FREQ2FBIN(5500, 0),
1143 + /* Data[3].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
1144 + /* Data[3].ctlEdges[6].bChannel */ 0xFF,
1145 + /* Data[3].ctlEdges[7].bChannel */ 0xFF,
1146 + },
1147 +
1148 + {
1149 + /* Data[4].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
1150 + /* Data[4].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
1151 + /* Data[4].ctlEdges[2].bChannel */ FREQ2FBIN(5500, 0),
1152 + /* Data[4].ctlEdges[3].bChannel */ FREQ2FBIN(5700, 0),
1153 + /* Data[4].ctlEdges[4].bChannel */ 0xFF,
1154 + /* Data[4].ctlEdges[5].bChannel */ 0xFF,
1155 + /* Data[4].ctlEdges[6].bChannel */ 0xFF,
1156 + /* Data[4].ctlEdges[7].bChannel */ 0xFF,
1157 + },
1158 +
1159 + {
1160 + /* Data[5].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0),
1161 + /* Data[5].ctlEdges[1].bChannel */ FREQ2FBIN(5270, 0),
1162 + /* Data[5].ctlEdges[2].bChannel */ FREQ2FBIN(5310, 0),
1163 + /* Data[5].ctlEdges[3].bChannel */ FREQ2FBIN(5510, 0),
1164 + /* Data[5].ctlEdges[4].bChannel */ FREQ2FBIN(5590, 0),
1165 + /* Data[5].ctlEdges[5].bChannel */ FREQ2FBIN(5670, 0),
1166 + /* Data[5].ctlEdges[6].bChannel */ 0xFF,
1167 + /* Data[5].ctlEdges[7].bChannel */ 0xFF
1168 + },
1169 +
1170 + {
1171 + /* Data[6].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
1172 + /* Data[6].ctlEdges[1].bChannel */ FREQ2FBIN(5200, 0),
1173 + /* Data[6].ctlEdges[2].bChannel */ FREQ2FBIN(5220, 0),
1174 + /* Data[6].ctlEdges[3].bChannel */ FREQ2FBIN(5260, 0),
1175 + /* Data[6].ctlEdges[4].bChannel */ FREQ2FBIN(5500, 0),
1176 + /* Data[6].ctlEdges[5].bChannel */ FREQ2FBIN(5600, 0),
1177 + /* Data[6].ctlEdges[6].bChannel */ FREQ2FBIN(5700, 0),
1178 + /* Data[6].ctlEdges[7].bChannel */ FREQ2FBIN(5745, 0)
1179 + },
1180 +
1181 + {
1182 + /* Data[7].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
1183 + /* Data[7].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
1184 + /* Data[7].ctlEdges[2].bChannel */ FREQ2FBIN(5320, 0),
1185 + /* Data[7].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0),
1186 + /* Data[7].ctlEdges[4].bChannel */ FREQ2FBIN(5560, 0),
1187 + /* Data[7].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
1188 + /* Data[7].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0),
1189 + /* Data[7].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0)
1190 + },
1191 +
1192 + {
1193 + /* Data[8].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0),
1194 + /* Data[8].ctlEdges[1].bChannel */ FREQ2FBIN(5230, 0),
1195 + /* Data[8].ctlEdges[2].bChannel */ FREQ2FBIN(5270, 0),
1196 + /* Data[8].ctlEdges[3].bChannel */ FREQ2FBIN(5510, 0),
1197 + /* Data[8].ctlEdges[4].bChannel */ FREQ2FBIN(5550, 0),
1198 + /* Data[8].ctlEdges[5].bChannel */ FREQ2FBIN(5670, 0),
1199 + /* Data[8].ctlEdges[6].bChannel */ FREQ2FBIN(5755, 0),
1200 + /* Data[8].ctlEdges[7].bChannel */ FREQ2FBIN(5795, 0)
1201 + }
1202 + },
1203 + .ctlPowerData_5G = {
1204 + {
1205 + {
1206 + {60, 1}, {60, 1}, {60, 1}, {60, 1},
1207 + {60, 1}, {60, 1}, {60, 1}, {60, 0},
1208 + }
1209 + },
1210 + {
1211 + {
1212 + {60, 1}, {60, 1}, {60, 1}, {60, 1},
1213 + {60, 1}, {60, 1}, {60, 1}, {60, 0},
1214 + }
1215 + },
1216 + {
1217 + {
1218 + {60, 0}, {60, 1}, {60, 0}, {60, 1},
1219 + {60, 1}, {60, 1}, {60, 1}, {60, 1},
1220 + }
1221 + },
1222 + {
1223 + {
1224 + {60, 0}, {60, 1}, {60, 1}, {60, 0},
1225 + {60, 1}, {60, 0}, {60, 0}, {60, 0},
1226 + }
1227 + },
1228 + {
1229 + {
1230 + {60, 1}, {60, 1}, {60, 1}, {60, 0},
1231 + {60, 0}, {60, 0}, {60, 0}, {60, 0},
1232 + }
1233 + },
1234 + {
1235 + {
1236 + {60, 1}, {60, 1}, {60, 1}, {60, 1},
1237 + {60, 1}, {60, 0}, {60, 0}, {60, 0},
1238 + }
1239 + },
1240 + {
1241 + {
1242 + {60, 1}, {60, 1}, {60, 1}, {60, 1},
1243 + {60, 1}, {60, 1}, {60, 1}, {60, 1},
1244 + }
1245 + },
1246 + {
1247 + {
1248 + {60, 1}, {60, 1}, {60, 0}, {60, 1},
1249 + {60, 1}, {60, 1}, {60, 1}, {60, 0},
1250 + }
1251 + },
1252 + {
1253 + {
1254 + {60, 1}, {60, 0}, {60, 1}, {60, 1},
1255 + {60, 1}, {60, 1}, {60, 0}, {60, 1},
1256 + }
1257 + },
1258 + }
1259 +};
1260 +
1261 +
1262 +static const struct ar9300_eeprom ar9300_h112 = {
1263 + .eepromVersion = 2,
1264 + .templateVersion = 3,
1265 + .macAddr = {0x00, 0x03, 0x7f, 0x0, 0x0, 0x0},
1266 + .custData = {"h112-241-f0000"},
1267 + .baseEepHeader = {
1268 + .regDmn = { LE16(0), LE16(0x1f) },
1269 + .txrxMask = 0x77, /* 4 bits tx and 4 bits rx */
1270 + .opCapFlags = {
1271 + .opFlags = AR9300_OPFLAGS_11G | AR9300_OPFLAGS_11A,
1272 + .eepMisc = 0,
1273 + },
1274 + .rfSilent = 0,
1275 + .blueToothOptions = 0,
1276 + .deviceCap = 0,
1277 + .deviceType = 5, /* takes lower byte in eeprom location */
1278 + .pwrTableOffset = AR9300_PWR_TABLE_OFFSET,
1279 + .params_for_tuning_caps = {0, 0},
1280 + .featureEnable = 0x0d,
1281 + /*
1282 + * bit0 - enable tx temp comp - disabled
1283 + * bit1 - enable tx volt comp - disabled
1284 + * bit2 - enable fastClock - enabled
1285 + * bit3 - enable doubling - enabled
1286 + * bit4 - enable internal regulator - disabled
1287 + * bit5 - enable pa predistortion - disabled
1288 + */
1289 + .miscConfiguration = 0, /* bit0 - turn down drivestrength */
1290 + .eepromWriteEnableGpio = 6,
1291 + .wlanDisableGpio = 0,
1292 + .wlanLedGpio = 8,
1293 + .rxBandSelectGpio = 0xff,
1294 + .txrxgain = 0x10,
1295 + .swreg = 0,
1296 + },
1297 + .modalHeader2G = {
1298 + /* ar9300_modal_eep_header 2g */
1299 + /* 4 idle,t1,t2,b(4 bits per setting) */
1300 + .antCtrlCommon = LE32(0x110),
1301 + /* 4 ra1l1, ra2l1, ra1l2, ra2l2, ra12 */
1302 + .antCtrlCommon2 = LE32(0x44444),
1303 +
1304 + /*
1305 + * antCtrlChain[AR9300_MAX_CHAINS]; 6 idle, t, r,
1306 + * rx1, rx12, b (2 bits each)
1307 + */
1308 + .antCtrlChain = { LE16(0x150), LE16(0x150), LE16(0x150) },
1309 +
1310 + /*
1311 + * xatten1DB[AR9300_MAX_CHAINS]; 3 xatten1_db
1312 + * for ar9280 (0xa20c/b20c 5:0)
1313 + */
1314 + .xatten1DB = {0, 0, 0},
1315 +
1316 + /*
1317 + * xatten1Margin[AR9300_MAX_CHAINS]; 3 xatten1_margin
1318 + * for ar9280 (0xa20c/b20c 16:12
1319 + */
1320 + .xatten1Margin = {0, 0, 0},
1321 + .tempSlope = 25,
1322 + .voltSlope = 0,
1323 +
1324 + /*
1325 + * spurChans[OSPREY_EEPROM_MODAL_SPURS]; spur
1326 + * channels in usual fbin coding format
1327 + */
1328 + .spurChans = {FREQ2FBIN(2464, 1), 0, 0, 0, 0},
1329 +
1330 + /*
1331 + * noiseFloorThreshCh[AR9300_MAX_CHAINS]; 3 Check
1332 + * if the register is per chain
1333 + */
1334 + .noiseFloorThreshCh = {-1, 0, 0},
1335 + .ob = {1, 1, 1},/* 3 chain */
1336 + .db_stage2 = {1, 1, 1}, /* 3 chain */
1337 + .db_stage3 = {0, 0, 0},
1338 + .db_stage4 = {0, 0, 0},
1339 + .xpaBiasLvl = 0,
1340 + .txFrameToDataStart = 0x0e,
1341 + .txFrameToPaOn = 0x0e,
1342 + .txClip = 3, /* 4 bits tx_clip, 4 bits dac_scale_cck */
1343 + .antennaGain = 0,
1344 + .switchSettling = 0x2c,
1345 + .adcDesiredSize = -30,
1346 + .txEndToXpaOff = 0,
1347 + .txEndToRxOn = 0x2,
1348 + .txFrameToXpaOn = 0xe,
1349 + .thresh62 = 28,
1350 + .papdRateMaskHt20 = LE32(0x80c080),
1351 + .papdRateMaskHt40 = LE32(0x80c080),
1352 + .futureModal = {
1353 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
1354 + },
1355 + },
1356 + .base_ext1 = {
1357 + .ant_div_control = 0,
1358 + .future = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}
1359 + },
1360 + .calFreqPier2G = {
1361 + FREQ2FBIN(2412, 1),
1362 + FREQ2FBIN(2437, 1),
1363 + FREQ2FBIN(2472, 1),
1364 + },
1365 + /* ar9300_cal_data_per_freq_op_loop 2g */
1366 + .calPierData2G = {
1367 + { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
1368 + { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
1369 + { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
1370 + },
1371 + .calTarget_freqbin_Cck = {
1372 + FREQ2FBIN(2412, 1),
1373 + FREQ2FBIN(2484, 1),
1374 + },
1375 + .calTarget_freqbin_2G = {
1376 + FREQ2FBIN(2412, 1),
1377 + FREQ2FBIN(2437, 1),
1378 + FREQ2FBIN(2472, 1)
1379 + },
1380 + .calTarget_freqbin_2GHT20 = {
1381 + FREQ2FBIN(2412, 1),
1382 + FREQ2FBIN(2437, 1),
1383 + FREQ2FBIN(2472, 1)
1384 + },
1385 + .calTarget_freqbin_2GHT40 = {
1386 + FREQ2FBIN(2412, 1),
1387 + FREQ2FBIN(2437, 1),
1388 + FREQ2FBIN(2472, 1)
1389 + },
1390 + .calTargetPowerCck = {
1391 + /* 1L-5L,5S,11L,11S */
1392 + { {34, 34, 34, 34} },
1393 + { {34, 34, 34, 34} },
1394 + },
1395 + .calTargetPower2G = {
1396 + /* 6-24,36,48,54 */
1397 + { {34, 34, 32, 32} },
1398 + { {34, 34, 32, 32} },
1399 + { {34, 34, 32, 32} },
1400 + },
1401 + .calTargetPower2GHT20 = {
1402 + { {32, 32, 32, 32, 32, 30, 32, 32, 30, 28, 28, 28, 28, 24} },
1403 + { {32, 32, 32, 32, 32, 30, 32, 32, 30, 28, 28, 28, 28, 24} },
1404 + { {32, 32, 32, 32, 32, 30, 32, 32, 30, 28, 28, 28, 28, 24} },
1405 + },
1406 + .calTargetPower2GHT40 = {
1407 + { {30, 30, 30, 30, 30, 28, 30, 30, 28, 26, 26, 26, 26, 22} },
1408 + { {30, 30, 30, 30, 30, 28, 30, 30, 28, 26, 26, 26, 26, 22} },
1409 + { {30, 30, 30, 30, 30, 28, 30, 30, 28, 26, 26, 26, 26, 22} },
1410 + },
1411 + .ctlIndex_2G = {
1412 + 0x11, 0x12, 0x15, 0x17, 0x41, 0x42,
1413 + 0x45, 0x47, 0x31, 0x32, 0x35, 0x37,
1414 + },
1415 + .ctl_freqbin_2G = {
1416 + {
1417 + FREQ2FBIN(2412, 1),
1418 + FREQ2FBIN(2417, 1),
1419 + FREQ2FBIN(2457, 1),
1420 + FREQ2FBIN(2462, 1)
1421 + },
1422 + {
1423 + FREQ2FBIN(2412, 1),
1424 + FREQ2FBIN(2417, 1),
1425 + FREQ2FBIN(2462, 1),
1426 + 0xFF,
1427 + },
1428 +
1429 + {
1430 + FREQ2FBIN(2412, 1),
1431 + FREQ2FBIN(2417, 1),
1432 + FREQ2FBIN(2462, 1),
1433 + 0xFF,
1434 + },
1435 + {
1436 + FREQ2FBIN(2422, 1),
1437 + FREQ2FBIN(2427, 1),
1438 + FREQ2FBIN(2447, 1),
1439 + FREQ2FBIN(2452, 1)
1440 + },
1441 +
1442 + {
1443 + /* Data[4].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
1444 + /* Data[4].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
1445 + /* Data[4].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
1446 + /* Data[4].ctlEdges[3].bChannel */ FREQ2FBIN(2484, 1),
1447 + },
1448 +
1449 + {
1450 + /* Data[5].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
1451 + /* Data[5].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
1452 + /* Data[5].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
1453 + 0,
1454 + },
1455 +
1456 + {
1457 + /* Data[6].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
1458 + /* Data[6].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
1459 + FREQ2FBIN(2472, 1),
1460 + 0,
1461 + },
1462 +
1463 + {
1464 + /* Data[7].ctlEdges[0].bChannel */ FREQ2FBIN(2422, 1),
1465 + /* Data[7].ctlEdges[1].bChannel */ FREQ2FBIN(2427, 1),
1466 + /* Data[7].ctlEdges[2].bChannel */ FREQ2FBIN(2447, 1),
1467 + /* Data[7].ctlEdges[3].bChannel */ FREQ2FBIN(2462, 1),
1468 + },
1469 +
1470 + {
1471 + /* Data[8].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
1472 + /* Data[8].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
1473 + /* Data[8].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
1474 + },
1475 +
1476 + {
1477 + /* Data[9].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
1478 + /* Data[9].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
1479 + /* Data[9].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
1480 + 0
1481 + },
1482 +
1483 + {
1484 + /* Data[10].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
1485 + /* Data[10].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
1486 + /* Data[10].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
1487 + 0
1488 + },
1489 +
1490 + {
1491 + /* Data[11].ctlEdges[0].bChannel */ FREQ2FBIN(2422, 1),
1492 + /* Data[11].ctlEdges[1].bChannel */ FREQ2FBIN(2427, 1),
1493 + /* Data[11].ctlEdges[2].bChannel */ FREQ2FBIN(2447, 1),
1494 + /* Data[11].ctlEdges[3].bChannel */ FREQ2FBIN(2462, 1),
1495 + }
1496 + },
1497 + .ctlPowerData_2G = {
1498 + { { {60, 0}, {60, 1}, {60, 0}, {60, 0} } },
1499 + { { {60, 0}, {60, 1}, {60, 0}, {60, 0} } },
1500 + { { {60, 1}, {60, 0}, {60, 0}, {60, 1} } },
1501 +
1502 + { { {60, 1}, {60, 0}, {0, 0}, {0, 0} } },
1503 + { { {60, 0}, {60, 1}, {60, 0}, {60, 0} } },
1504 + { { {60, 0}, {60, 1}, {60, 0}, {60, 0} } },
1505 +
1506 + { { {60, 0}, {60, 1}, {60, 1}, {60, 0} } },
1507 + { { {60, 0}, {60, 1}, {60, 0}, {60, 0} } },
1508 + { { {60, 0}, {60, 1}, {60, 0}, {60, 0} } },
1509 +
1510 + { { {60, 0}, {60, 1}, {60, 0}, {60, 0} } },
1511 + { { {60, 0}, {60, 1}, {60, 1}, {60, 1} } },
1512 + { { {60, 0}, {60, 1}, {60, 1}, {60, 1} } },
1513 + },
1514 + .modalHeader5G = {
1515 + /* 4 idle,t1,t2,b (4 bits per setting) */
1516 + .antCtrlCommon = LE32(0x220),
1517 + /* 4 ra1l1, ra2l1, ra1l2,ra2l2,ra12 */
1518 + .antCtrlCommon2 = LE32(0x44444),
1519 + /* antCtrlChain 6 idle, t,r,rx1,rx12,b (2 bits each) */
1520 + .antCtrlChain = {
1521 + LE16(0x150), LE16(0x150), LE16(0x150),
1522 + },
1523 + /* xatten1DB 3 xatten1_db for AR9280 (0xa20c/b20c 5:0) */
1524 + .xatten1DB = {0, 0, 0},
1525 +
1526 + /*
1527 + * xatten1Margin[AR9300_MAX_CHAINS]; 3 xatten1_margin
1528 + * for merlin (0xa20c/b20c 16:12
1529 + */
1530 + .xatten1Margin = {0, 0, 0},
1531 + .tempSlope = 45,
1532 + .voltSlope = 0,
1533 + /* spurChans spur channels in usual fbin coding format */
1534 + .spurChans = {0, 0, 0, 0, 0},
1535 + /* noiseFloorThreshCh Check if the register is per chain */
1536 + .noiseFloorThreshCh = {-1, 0, 0},
1537 + .ob = {3, 3, 3}, /* 3 chain */
1538 + .db_stage2 = {3, 3, 3}, /* 3 chain */
1539 + .db_stage3 = {3, 3, 3}, /* doesn't exist for 2G */
1540 + .db_stage4 = {3, 3, 3}, /* don't exist for 2G */
1541 + .xpaBiasLvl = 0,
1542 + .txFrameToDataStart = 0x0e,
1543 + .txFrameToPaOn = 0x0e,
1544 + .txClip = 3, /* 4 bits tx_clip, 4 bits dac_scale_cck */
1545 + .antennaGain = 0,
1546 + .switchSettling = 0x2d,
1547 + .adcDesiredSize = -30,
1548 + .txEndToXpaOff = 0,
1549 + .txEndToRxOn = 0x2,
1550 + .txFrameToXpaOn = 0xe,
1551 + .thresh62 = 28,
1552 + .papdRateMaskHt20 = LE32(0x0cf0e0e0),
1553 + .papdRateMaskHt40 = LE32(0x6cf0e0e0),
1554 + .futureModal = {
1555 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
1556 + },
1557 + },
1558 + .base_ext2 = {
1559 + .tempSlopeLow = 40,
1560 + .tempSlopeHigh = 50,
1561 + .xatten1DBLow = {0, 0, 0},
1562 + .xatten1MarginLow = {0, 0, 0},
1563 + .xatten1DBHigh = {0, 0, 0},
1564 + .xatten1MarginHigh = {0, 0, 0}
1565 + },
1566 + .calFreqPier5G = {
1567 + FREQ2FBIN(5180, 0),
1568 + FREQ2FBIN(5220, 0),
1569 + FREQ2FBIN(5320, 0),
1570 + FREQ2FBIN(5400, 0),
1571 + FREQ2FBIN(5500, 0),
1572 + FREQ2FBIN(5600, 0),
1573 + FREQ2FBIN(5700, 0),
1574 + FREQ2FBIN(5825, 0)
1575 + },
1576 + .calPierData5G = {
1577 + {
1578 + {0, 0, 0, 0, 0},
1579 + {0, 0, 0, 0, 0},
1580 + {0, 0, 0, 0, 0},
1581 + {0, 0, 0, 0, 0},
1582 + {0, 0, 0, 0, 0},
1583 + {0, 0, 0, 0, 0},
1584 + {0, 0, 0, 0, 0},
1585 + {0, 0, 0, 0, 0},
1586 + },
1587 + {
1588 + {0, 0, 0, 0, 0},
1589 + {0, 0, 0, 0, 0},
1590 + {0, 0, 0, 0, 0},
1591 + {0, 0, 0, 0, 0},
1592 + {0, 0, 0, 0, 0},
1593 + {0, 0, 0, 0, 0},
1594 + {0, 0, 0, 0, 0},
1595 + {0, 0, 0, 0, 0},
1596 + },
1597 + {
1598 + {0, 0, 0, 0, 0},
1599 + {0, 0, 0, 0, 0},
1600 + {0, 0, 0, 0, 0},
1601 + {0, 0, 0, 0, 0},
1602 + {0, 0, 0, 0, 0},
1603 + {0, 0, 0, 0, 0},
1604 + {0, 0, 0, 0, 0},
1605 + {0, 0, 0, 0, 0},
1606 + },
1607 +
1608 + },
1609 + .calTarget_freqbin_5G = {
1610 + FREQ2FBIN(5180, 0),
1611 + FREQ2FBIN(5240, 0),
1612 + FREQ2FBIN(5320, 0),
1613 + FREQ2FBIN(5400, 0),
1614 + FREQ2FBIN(5500, 0),
1615 + FREQ2FBIN(5600, 0),
1616 + FREQ2FBIN(5700, 0),
1617 + FREQ2FBIN(5825, 0)
1618 + },
1619 + .calTarget_freqbin_5GHT20 = {
1620 + FREQ2FBIN(5180, 0),
1621 + FREQ2FBIN(5240, 0),
1622 + FREQ2FBIN(5320, 0),
1623 + FREQ2FBIN(5400, 0),
1624 + FREQ2FBIN(5500, 0),
1625 + FREQ2FBIN(5700, 0),
1626 + FREQ2FBIN(5745, 0),
1627 + FREQ2FBIN(5825, 0)
1628 + },
1629 + .calTarget_freqbin_5GHT40 = {
1630 + FREQ2FBIN(5180, 0),
1631 + FREQ2FBIN(5240, 0),
1632 + FREQ2FBIN(5320, 0),
1633 + FREQ2FBIN(5400, 0),
1634 + FREQ2FBIN(5500, 0),
1635 + FREQ2FBIN(5700, 0),
1636 + FREQ2FBIN(5745, 0),
1637 + FREQ2FBIN(5825, 0)
1638 + },
1639 + .calTargetPower5G = {
1640 + /* 6-24,36,48,54 */
1641 + { {30, 30, 28, 24} },
1642 + { {30, 30, 28, 24} },
1643 + { {30, 30, 28, 24} },
1644 + { {30, 30, 28, 24} },
1645 + { {30, 30, 28, 24} },
1646 + { {30, 30, 28, 24} },
1647 + { {30, 30, 28, 24} },
1648 + { {30, 30, 28, 24} },
1649 + },
1650 + .calTargetPower5GHT20 = {
1651 + /*
1652 + * 0_8_16,1-3_9-11_17-19,
1653 + * 4,5,6,7,12,13,14,15,20,21,22,23
1654 + */
1655 + { {30, 30, 30, 28, 24, 20, 30, 28, 24, 20, 20, 20, 20, 16} },
1656 + { {30, 30, 30, 28, 24, 20, 30, 28, 24, 20, 20, 20, 20, 16} },
1657 + { {30, 30, 30, 26, 22, 18, 30, 26, 22, 18, 18, 18, 18, 16} },
1658 + { {30, 30, 30, 26, 22, 18, 30, 26, 22, 18, 18, 18, 18, 16} },
1659 + { {30, 30, 30, 24, 20, 16, 30, 24, 20, 16, 16, 16, 16, 14} },
1660 + { {30, 30, 30, 24, 20, 16, 30, 24, 20, 16, 16, 16, 16, 14} },
1661 + { {30, 30, 30, 22, 18, 14, 30, 22, 18, 14, 14, 14, 14, 12} },
1662 + { {30, 30, 30, 22, 18, 14, 30, 22, 18, 14, 14, 14, 14, 12} },
1663 + },
1664 + .calTargetPower5GHT40 = {
1665 + /*
1666 + * 0_8_16,1-3_9-11_17-19,
1667 + * 4,5,6,7,12,13,14,15,20,21,22,23
1668 + */
1669 + { {28, 28, 28, 26, 22, 18, 28, 26, 22, 18, 18, 18, 18, 14} },
1670 + { {28, 28, 28, 26, 22, 18, 28, 26, 22, 18, 18, 18, 18, 14} },
1671 + { {28, 28, 28, 24, 20, 16, 28, 24, 20, 16, 16, 16, 16, 12} },
1672 + { {28, 28, 28, 24, 20, 16, 28, 24, 20, 16, 16, 16, 16, 12} },
1673 + { {28, 28, 28, 22, 18, 14, 28, 22, 18, 14, 14, 14, 14, 10} },
1674 + { {28, 28, 28, 22, 18, 14, 28, 22, 18, 14, 14, 14, 14, 10} },
1675 + { {28, 28, 28, 20, 16, 12, 28, 20, 16, 12, 12, 12, 12, 8} },
1676 + { {28, 28, 28, 20, 16, 12, 28, 20, 16, 12, 12, 12, 12, 8} },
1677 + },
1678 + .ctlIndex_5G = {
1679 + 0x10, 0x16, 0x18, 0x40, 0x46,
1680 + 0x48, 0x30, 0x36, 0x38
1681 + },
1682 + .ctl_freqbin_5G = {
1683 + {
1684 + /* Data[0].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
1685 + /* Data[0].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
1686 + /* Data[0].ctlEdges[2].bChannel */ FREQ2FBIN(5280, 0),
1687 + /* Data[0].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0),
1688 + /* Data[0].ctlEdges[4].bChannel */ FREQ2FBIN(5600, 0),
1689 + /* Data[0].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
1690 + /* Data[0].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0),
1691 + /* Data[0].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0)
1692 + },
1693 + {
1694 + /* Data[1].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
1695 + /* Data[1].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
1696 + /* Data[1].ctlEdges[2].bChannel */ FREQ2FBIN(5280, 0),
1697 + /* Data[1].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0),
1698 + /* Data[1].ctlEdges[4].bChannel */ FREQ2FBIN(5520, 0),
1699 + /* Data[1].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
1700 + /* Data[1].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0),
1701 + /* Data[1].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0)
1702 + },
1703 +
1704 + {
1705 + /* Data[2].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0),
1706 + /* Data[2].ctlEdges[1].bChannel */ FREQ2FBIN(5230, 0),
1707 + /* Data[2].ctlEdges[2].bChannel */ FREQ2FBIN(5270, 0),
1708 + /* Data[2].ctlEdges[3].bChannel */ FREQ2FBIN(5310, 0),
1709 + /* Data[2].ctlEdges[4].bChannel */ FREQ2FBIN(5510, 0),
1710 + /* Data[2].ctlEdges[5].bChannel */ FREQ2FBIN(5550, 0),
1711 + /* Data[2].ctlEdges[6].bChannel */ FREQ2FBIN(5670, 0),
1712 + /* Data[2].ctlEdges[7].bChannel */ FREQ2FBIN(5755, 0)
1713 + },
1714 +
1715 + {
1716 + /* Data[3].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
1717 + /* Data[3].ctlEdges[1].bChannel */ FREQ2FBIN(5200, 0),
1718 + /* Data[3].ctlEdges[2].bChannel */ FREQ2FBIN(5260, 0),
1719 + /* Data[3].ctlEdges[3].bChannel */ FREQ2FBIN(5320, 0),
1720 + /* Data[3].ctlEdges[4].bChannel */ FREQ2FBIN(5500, 0),
1721 + /* Data[3].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
1722 + /* Data[3].ctlEdges[6].bChannel */ 0xFF,
1723 + /* Data[3].ctlEdges[7].bChannel */ 0xFF,
1724 + },
1725 +
1726 + {
1727 + /* Data[4].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
1728 + /* Data[4].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
1729 + /* Data[4].ctlEdges[2].bChannel */ FREQ2FBIN(5500, 0),
1730 + /* Data[4].ctlEdges[3].bChannel */ FREQ2FBIN(5700, 0),
1731 + /* Data[4].ctlEdges[4].bChannel */ 0xFF,
1732 + /* Data[4].ctlEdges[5].bChannel */ 0xFF,
1733 + /* Data[4].ctlEdges[6].bChannel */ 0xFF,
1734 + /* Data[4].ctlEdges[7].bChannel */ 0xFF,
1735 + },
1736 +
1737 + {
1738 + /* Data[5].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0),
1739 + /* Data[5].ctlEdges[1].bChannel */ FREQ2FBIN(5270, 0),
1740 + /* Data[5].ctlEdges[2].bChannel */ FREQ2FBIN(5310, 0),
1741 + /* Data[5].ctlEdges[3].bChannel */ FREQ2FBIN(5510, 0),
1742 + /* Data[5].ctlEdges[4].bChannel */ FREQ2FBIN(5590, 0),
1743 + /* Data[5].ctlEdges[5].bChannel */ FREQ2FBIN(5670, 0),
1744 + /* Data[5].ctlEdges[6].bChannel */ 0xFF,
1745 + /* Data[5].ctlEdges[7].bChannel */ 0xFF
1746 + },
1747 +
1748 + {
1749 + /* Data[6].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
1750 + /* Data[6].ctlEdges[1].bChannel */ FREQ2FBIN(5200, 0),
1751 + /* Data[6].ctlEdges[2].bChannel */ FREQ2FBIN(5220, 0),
1752 + /* Data[6].ctlEdges[3].bChannel */ FREQ2FBIN(5260, 0),
1753 + /* Data[6].ctlEdges[4].bChannel */ FREQ2FBIN(5500, 0),
1754 + /* Data[6].ctlEdges[5].bChannel */ FREQ2FBIN(5600, 0),
1755 + /* Data[6].ctlEdges[6].bChannel */ FREQ2FBIN(5700, 0),
1756 + /* Data[6].ctlEdges[7].bChannel */ FREQ2FBIN(5745, 0)
1757 + },
1758 +
1759 + {
1760 + /* Data[7].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
1761 + /* Data[7].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
1762 + /* Data[7].ctlEdges[2].bChannel */ FREQ2FBIN(5320, 0),
1763 + /* Data[7].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0),
1764 + /* Data[7].ctlEdges[4].bChannel */ FREQ2FBIN(5560, 0),
1765 + /* Data[7].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
1766 + /* Data[7].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0),
1767 + /* Data[7].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0)
1768 + },
1769 +
1770 + {
1771 + /* Data[8].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0),
1772 + /* Data[8].ctlEdges[1].bChannel */ FREQ2FBIN(5230, 0),
1773 + /* Data[8].ctlEdges[2].bChannel */ FREQ2FBIN(5270, 0),
1774 + /* Data[8].ctlEdges[3].bChannel */ FREQ2FBIN(5510, 0),
1775 + /* Data[8].ctlEdges[4].bChannel */ FREQ2FBIN(5550, 0),
1776 + /* Data[8].ctlEdges[5].bChannel */ FREQ2FBIN(5670, 0),
1777 + /* Data[8].ctlEdges[6].bChannel */ FREQ2FBIN(5755, 0),
1778 + /* Data[8].ctlEdges[7].bChannel */ FREQ2FBIN(5795, 0)
1779 + }
1780 + },
1781 + .ctlPowerData_5G = {
1782 + {
1783 + {
1784 + {60, 1}, {60, 1}, {60, 1}, {60, 1},
1785 + {60, 1}, {60, 1}, {60, 1}, {60, 0},
1786 + }
1787 + },
1788 + {
1789 + {
1790 + {60, 1}, {60, 1}, {60, 1}, {60, 1},
1791 + {60, 1}, {60, 1}, {60, 1}, {60, 0},
1792 + }
1793 + },
1794 + {
1795 + {
1796 + {60, 0}, {60, 1}, {60, 0}, {60, 1},
1797 + {60, 1}, {60, 1}, {60, 1}, {60, 1},
1798 + }
1799 + },
1800 + {
1801 + {
1802 + {60, 0}, {60, 1}, {60, 1}, {60, 0},
1803 + {60, 1}, {60, 0}, {60, 0}, {60, 0},
1804 + }
1805 + },
1806 + {
1807 + {
1808 + {60, 1}, {60, 1}, {60, 1}, {60, 0},
1809 + {60, 0}, {60, 0}, {60, 0}, {60, 0},
1810 + }
1811 + },
1812 + {
1813 + {
1814 + {60, 1}, {60, 1}, {60, 1}, {60, 1},
1815 + {60, 1}, {60, 0}, {60, 0}, {60, 0},
1816 + }
1817 + },
1818 + {
1819 + {
1820 + {60, 1}, {60, 1}, {60, 1}, {60, 1},
1821 + {60, 1}, {60, 1}, {60, 1}, {60, 1},
1822 + }
1823 + },
1824 + {
1825 + {
1826 + {60, 1}, {60, 1}, {60, 0}, {60, 1},
1827 + {60, 1}, {60, 1}, {60, 1}, {60, 0},
1828 + }
1829 + },
1830 + {
1831 + {
1832 + {60, 1}, {60, 0}, {60, 1}, {60, 1},
1833 + {60, 1}, {60, 1}, {60, 0}, {60, 1},
1834 + }
1835 + },
1836 + }
1837 +};
1838 +
1839 +
1840 +static const struct ar9300_eeprom ar9300_x112 = {
1841 + .eepromVersion = 2,
1842 + .templateVersion = 5,
1843 + .macAddr = {0x00, 0x03, 0x7f, 0x0, 0x0, 0x0},
1844 + .custData = {"x112-041-f0000"},
1845 + .baseEepHeader = {
1846 + .regDmn = { LE16(0), LE16(0x1f) },
1847 + .txrxMask = 0x77, /* 4 bits tx and 4 bits rx */
1848 + .opCapFlags = {
1849 + .opFlags = AR9300_OPFLAGS_11G | AR9300_OPFLAGS_11A,
1850 + .eepMisc = 0,
1851 + },
1852 + .rfSilent = 0,
1853 + .blueToothOptions = 0,
1854 + .deviceCap = 0,
1855 + .deviceType = 5, /* takes lower byte in eeprom location */
1856 + .pwrTableOffset = AR9300_PWR_TABLE_OFFSET,
1857 + .params_for_tuning_caps = {0, 0},
1858 + .featureEnable = 0x0d,
1859 + /*
1860 + * bit0 - enable tx temp comp - disabled
1861 + * bit1 - enable tx volt comp - disabled
1862 + * bit2 - enable fastclock - enabled
1863 + * bit3 - enable doubling - enabled
1864 + * bit4 - enable internal regulator - disabled
1865 + * bit5 - enable pa predistortion - disabled
1866 + */
1867 + .miscConfiguration = 0, /* bit0 - turn down drivestrength */
1868 + .eepromWriteEnableGpio = 6,
1869 + .wlanDisableGpio = 0,
1870 + .wlanLedGpio = 8,
1871 + .rxBandSelectGpio = 0xff,
1872 + .txrxgain = 0x0,
1873 + .swreg = 0,
1874 + },
1875 + .modalHeader2G = {
1876 + /* ar9300_modal_eep_header 2g */
1877 + /* 4 idle,t1,t2,b(4 bits per setting) */
1878 + .antCtrlCommon = LE32(0x110),
1879 + /* 4 ra1l1, ra2l1, ra1l2, ra2l2, ra12 */
1880 + .antCtrlCommon2 = LE32(0x22222),
1881 +
1882 + /*
1883 + * antCtrlChain[ar9300_max_chains]; 6 idle, t, r,
1884 + * rx1, rx12, b (2 bits each)
1885 + */
1886 + .antCtrlChain = { LE16(0x10), LE16(0x10), LE16(0x10) },
1887 +
1888 + /*
1889 + * xatten1DB[AR9300_max_chains]; 3 xatten1_db
1890 + * for ar9280 (0xa20c/b20c 5:0)
1891 + */
1892 + .xatten1DB = {0x1b, 0x1b, 0x1b},
1893 +
1894 + /*
1895 + * xatten1Margin[ar9300_max_chains]; 3 xatten1_margin
1896 + * for ar9280 (0xa20c/b20c 16:12
1897 + */
1898 + .xatten1Margin = {0x15, 0x15, 0x15},
1899 + .tempSlope = 50,
1900 + .voltSlope = 0,
1901 +
1902 + /*
1903 + * spurChans[OSPrey_eeprom_modal_sPURS]; spur
1904 + * channels in usual fbin coding format
1905 + */
1906 + .spurChans = {FREQ2FBIN(2464, 1), 0, 0, 0, 0},
1907 +
1908 + /*
1909 + * noiseFloorThreshch[ar9300_max_cHAINS]; 3 Check
1910 + * if the register is per chain
1911 + */
1912 + .noiseFloorThreshCh = {-1, 0, 0},
1913 + .ob = {1, 1, 1},/* 3 chain */
1914 + .db_stage2 = {1, 1, 1}, /* 3 chain */
1915 + .db_stage3 = {0, 0, 0},
1916 + .db_stage4 = {0, 0, 0},
1917 + .xpaBiasLvl = 0,
1918 + .txFrameToDataStart = 0x0e,
1919 + .txFrameToPaOn = 0x0e,
1920 + .txClip = 3, /* 4 bits tx_clip, 4 bits dac_scale_cck */
1921 + .antennaGain = 0,
1922 + .switchSettling = 0x2c,
1923 + .adcDesiredSize = -30,
1924 + .txEndToXpaOff = 0,
1925 + .txEndToRxOn = 0x2,
1926 + .txFrameToXpaOn = 0xe,
1927 + .thresh62 = 28,
1928 + .papdRateMaskHt20 = LE32(0x0c80c080),
1929 + .papdRateMaskHt40 = LE32(0x0080c080),
1930 + .futureModal = {
1931 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
1932 + },
1933 + },
1934 + .base_ext1 = {
1935 + .ant_div_control = 0,
1936 + .future = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}
1937 + },
1938 + .calFreqPier2G = {
1939 + FREQ2FBIN(2412, 1),
1940 + FREQ2FBIN(2437, 1),
1941 + FREQ2FBIN(2472, 1),
1942 + },
1943 + /* ar9300_cal_data_per_freq_op_loop 2g */
1944 + .calPierData2G = {
1945 + { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
1946 + { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
1947 + { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
1948 + },
1949 + .calTarget_freqbin_Cck = {
1950 + FREQ2FBIN(2412, 1),
1951 + FREQ2FBIN(2472, 1),
1952 + },
1953 + .calTarget_freqbin_2G = {
1954 + FREQ2FBIN(2412, 1),
1955 + FREQ2FBIN(2437, 1),
1956 + FREQ2FBIN(2472, 1)
1957 + },
1958 + .calTarget_freqbin_2GHT20 = {
1959 + FREQ2FBIN(2412, 1),
1960 + FREQ2FBIN(2437, 1),
1961 + FREQ2FBIN(2472, 1)
1962 + },
1963 + .calTarget_freqbin_2GHT40 = {
1964 + FREQ2FBIN(2412, 1),
1965 + FREQ2FBIN(2437, 1),
1966 + FREQ2FBIN(2472, 1)
1967 + },
1968 + .calTargetPowerCck = {
1969 + /* 1L-5L,5S,11L,11s */
1970 + { {38, 38, 38, 38} },
1971 + { {38, 38, 38, 38} },
1972 + },
1973 + .calTargetPower2G = {
1974 + /* 6-24,36,48,54 */
1975 + { {38, 38, 36, 34} },
1976 + { {38, 38, 36, 34} },
1977 + { {38, 38, 34, 32} },
1978 + },
1979 + .calTargetPower2GHT20 = {
1980 + { {36, 36, 36, 36, 36, 34, 34, 32, 30, 28, 28, 28, 28, 26} },
1981 + { {36, 36, 36, 36, 36, 34, 36, 34, 32, 30, 30, 30, 28, 26} },
1982 + { {36, 36, 36, 36, 36, 34, 34, 32, 30, 28, 28, 28, 28, 26} },
1983 + },
1984 + .calTargetPower2GHT40 = {
1985 + { {36, 36, 36, 36, 34, 32, 32, 30, 28, 26, 26, 26, 26, 24} },
1986 + { {36, 36, 36, 36, 34, 32, 34, 32, 30, 28, 28, 28, 28, 24} },
1987 + { {36, 36, 36, 36, 34, 32, 32, 30, 28, 26, 26, 26, 26, 24} },
1988 + },
1989 + .ctlIndex_2G = {
1990 + 0x11, 0x12, 0x15, 0x17, 0x41, 0x42,
1991 + 0x45, 0x47, 0x31, 0x32, 0x35, 0x37,
1992 + },
1993 + .ctl_freqbin_2G = {
1994 + {
1995 + FREQ2FBIN(2412, 1),
1996 + FREQ2FBIN(2417, 1),
1997 + FREQ2FBIN(2457, 1),
1998 + FREQ2FBIN(2462, 1)
1999 + },
2000 + {
2001 + FREQ2FBIN(2412, 1),
2002 + FREQ2FBIN(2417, 1),
2003 + FREQ2FBIN(2462, 1),
2004 + 0xFF,
2005 + },
2006 +
2007 + {
2008 + FREQ2FBIN(2412, 1),
2009 + FREQ2FBIN(2417, 1),
2010 + FREQ2FBIN(2462, 1),
2011 + 0xFF,
2012 + },
2013 + {
2014 + FREQ2FBIN(2422, 1),
2015 + FREQ2FBIN(2427, 1),
2016 + FREQ2FBIN(2447, 1),
2017 + FREQ2FBIN(2452, 1)
2018 + },
2019 +
2020 + {
2021 + /* Data[4].ctledges[0].bchannel */ FREQ2FBIN(2412, 1),
2022 + /* Data[4].ctledges[1].bchannel */ FREQ2FBIN(2417, 1),
2023 + /* Data[4].ctledges[2].bchannel */ FREQ2FBIN(2472, 1),
2024 + /* Data[4].ctledges[3].bchannel */ FREQ2FBIN(2484, 1),
2025 + },
2026 +
2027 + {
2028 + /* Data[5].ctledges[0].bchannel */ FREQ2FBIN(2412, 1),
2029 + /* Data[5].ctledges[1].bchannel */ FREQ2FBIN(2417, 1),
2030 + /* Data[5].ctledges[2].bchannel */ FREQ2FBIN(2472, 1),
2031 + 0,
2032 + },
2033 +
2034 + {
2035 + /* Data[6].ctledges[0].bchannel */ FREQ2FBIN(2412, 1),
2036 + /* Data[6].ctledges[1].bchannel */ FREQ2FBIN(2417, 1),
2037 + FREQ2FBIN(2472, 1),
2038 + 0,
2039 + },
2040 +
2041 + {
2042 + /* Data[7].ctledges[0].bchannel */ FREQ2FBIN(2422, 1),
2043 + /* Data[7].ctledges[1].bchannel */ FREQ2FBIN(2427, 1),
2044 + /* Data[7].ctledges[2].bchannel */ FREQ2FBIN(2447, 1),
2045 + /* Data[7].ctledges[3].bchannel */ FREQ2FBIN(2462, 1),
2046 + },
2047 +
2048 + {
2049 + /* Data[8].ctledges[0].bchannel */ FREQ2FBIN(2412, 1),
2050 + /* Data[8].ctledges[1].bchannel */ FREQ2FBIN(2417, 1),
2051 + /* Data[8].ctledges[2].bchannel */ FREQ2FBIN(2472, 1),
2052 + },
2053 +
2054 + {
2055 + /* Data[9].ctledges[0].bchannel */ FREQ2FBIN(2412, 1),
2056 + /* Data[9].ctledges[1].bchannel */ FREQ2FBIN(2417, 1),
2057 + /* Data[9].ctledges[2].bchannel */ FREQ2FBIN(2472, 1),
2058 + 0
2059 + },
2060 +
2061 + {
2062 + /* Data[10].ctledges[0].bchannel */ FREQ2FBIN(2412, 1),
2063 + /* Data[10].ctledges[1].bchannel */ FREQ2FBIN(2417, 1),
2064 + /* Data[10].ctledges[2].bchannel */ FREQ2FBIN(2472, 1),
2065 + 0
2066 + },
2067 +
2068 + {
2069 + /* Data[11].ctledges[0].bchannel */ FREQ2FBIN(2422, 1),
2070 + /* Data[11].ctledges[1].bchannel */ FREQ2FBIN(2427, 1),
2071 + /* Data[11].ctledges[2].bchannel */ FREQ2FBIN(2447, 1),
2072 + /* Data[11].ctledges[3].bchannel */ FREQ2FBIN(2462, 1),
2073 + }
2074 + },
2075 + .ctlPowerData_2G = {
2076 + { { {60, 0}, {60, 1}, {60, 0}, {60, 0} } },
2077 + { { {60, 0}, {60, 1}, {60, 0}, {60, 0} } },
2078 + { { {60, 1}, {60, 0}, {60, 0}, {60, 1} } },
2079 +
2080 + { { {60, 1}, {60, 0}, {0, 0}, {0, 0} } },
2081 + { { {60, 0}, {60, 1}, {60, 0}, {60, 0} } },
2082 + { { {60, 0}, {60, 1}, {60, 0}, {60, 0} } },
2083 +
2084 + { { {60, 0}, {60, 1}, {60, 1}, {60, 0} } },
2085 + { { {60, 0}, {60, 1}, {60, 0}, {60, 0} } },
2086 + { { {60, 0}, {60, 1}, {60, 0}, {60, 0} } },
2087 +
2088 + { { {60, 0}, {60, 1}, {60, 0}, {60, 0} } },
2089 + { { {60, 0}, {60, 1}, {60, 1}, {60, 1} } },
2090 + { { {60, 0}, {60, 1}, {60, 1}, {60, 1} } },
2091 + },
2092 + .modalHeader5G = {
2093 + /* 4 idle,t1,t2,b (4 bits per setting) */
2094 + .antCtrlCommon = LE32(0x110),
2095 + /* 4 ra1l1, ra2l1, ra1l2,ra2l2,ra12 */
2096 + .antCtrlCommon2 = LE32(0x22222),
2097 + /* antCtrlChain 6 idle, t,r,rx1,rx12,b (2 bits each) */
2098 + .antCtrlChain = {
2099 + LE16(0x0), LE16(0x0), LE16(0x0),
2100 + },
2101 + /* xatten1DB 3 xatten1_db for ar9280 (0xa20c/b20c 5:0) */
2102 + .xatten1DB = {0x13, 0x19, 0x17},
2103 +
2104 + /*
2105 + * xatten1Margin[ar9300_max_chains]; 3 xatten1_margin
2106 + * for merlin (0xa20c/b20c 16:12
2107 + */
2108 + .xatten1Margin = {0x19, 0x19, 0x19},
2109 + .tempSlope = 70,
2110 + .voltSlope = 15,
2111 + /* spurChans spur channels in usual fbin coding format */
2112 + .spurChans = {0, 0, 0, 0, 0},
2113 + /* noiseFloorThreshch check if the register is per chain */
2114 + .noiseFloorThreshCh = {-1, 0, 0},
2115 + .ob = {3, 3, 3}, /* 3 chain */
2116 + .db_stage2 = {3, 3, 3}, /* 3 chain */
2117 + .db_stage3 = {3, 3, 3}, /* doesn't exist for 2G */
2118 + .db_stage4 = {3, 3, 3}, /* don't exist for 2G */
2119 + .xpaBiasLvl = 0,
2120 + .txFrameToDataStart = 0x0e,
2121 + .txFrameToPaOn = 0x0e,
2122 + .txClip = 3, /* 4 bits tx_clip, 4 bits dac_scale_cck */
2123 + .antennaGain = 0,
2124 + .switchSettling = 0x2d,
2125 + .adcDesiredSize = -30,
2126 + .txEndToXpaOff = 0,
2127 + .txEndToRxOn = 0x2,
2128 + .txFrameToXpaOn = 0xe,
2129 + .thresh62 = 28,
2130 + .papdRateMaskHt20 = LE32(0x0cf0e0e0),
2131 + .papdRateMaskHt40 = LE32(0x6cf0e0e0),
2132 + .futureModal = {
2133 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2134 + },
2135 + },
2136 + .base_ext2 = {
2137 + .tempSlopeLow = 72,
2138 + .tempSlopeHigh = 105,
2139 + .xatten1DBLow = {0x10, 0x14, 0x10},
2140 + .xatten1MarginLow = {0x19, 0x19 , 0x19},
2141 + .xatten1DBHigh = {0x1d, 0x20, 0x24},
2142 + .xatten1MarginHigh = {0x10, 0x10, 0x10}
2143 + },
2144 + .calFreqPier5G = {
2145 + FREQ2FBIN(5180, 0),
2146 + FREQ2FBIN(5220, 0),
2147 + FREQ2FBIN(5320, 0),
2148 + FREQ2FBIN(5400, 0),
2149 + FREQ2FBIN(5500, 0),
2150 + FREQ2FBIN(5600, 0),
2151 + FREQ2FBIN(5700, 0),
2152 + FREQ2FBIN(5785, 0)
2153 + },
2154 + .calPierData5G = {
2155 + {
2156 + {0, 0, 0, 0, 0},
2157 + {0, 0, 0, 0, 0},
2158 + {0, 0, 0, 0, 0},
2159 + {0, 0, 0, 0, 0},
2160 + {0, 0, 0, 0, 0},
2161 + {0, 0, 0, 0, 0},
2162 + {0, 0, 0, 0, 0},
2163 + {0, 0, 0, 0, 0},
2164 + },
2165 + {
2166 + {0, 0, 0, 0, 0},
2167 + {0, 0, 0, 0, 0},
2168 + {0, 0, 0, 0, 0},
2169 + {0, 0, 0, 0, 0},
2170 + {0, 0, 0, 0, 0},
2171 + {0, 0, 0, 0, 0},
2172 + {0, 0, 0, 0, 0},
2173 + {0, 0, 0, 0, 0},
2174 + },
2175 + {
2176 + {0, 0, 0, 0, 0},
2177 + {0, 0, 0, 0, 0},
2178 + {0, 0, 0, 0, 0},
2179 + {0, 0, 0, 0, 0},
2180 + {0, 0, 0, 0, 0},
2181 + {0, 0, 0, 0, 0},
2182 + {0, 0, 0, 0, 0},
2183 + {0, 0, 0, 0, 0},
2184 + },
2185 +
2186 + },
2187 + .calTarget_freqbin_5G = {
2188 + FREQ2FBIN(5180, 0),
2189 + FREQ2FBIN(5220, 0),
2190 + FREQ2FBIN(5320, 0),
2191 + FREQ2FBIN(5400, 0),
2192 + FREQ2FBIN(5500, 0),
2193 + FREQ2FBIN(5600, 0),
2194 + FREQ2FBIN(5725, 0),
2195 + FREQ2FBIN(5825, 0)
2196 + },
2197 + .calTarget_freqbin_5GHT20 = {
2198 + FREQ2FBIN(5180, 0),
2199 + FREQ2FBIN(5220, 0),
2200 + FREQ2FBIN(5320, 0),
2201 + FREQ2FBIN(5400, 0),
2202 + FREQ2FBIN(5500, 0),
2203 + FREQ2FBIN(5600, 0),
2204 + FREQ2FBIN(5725, 0),
2205 + FREQ2FBIN(5825, 0)
2206 + },
2207 + .calTarget_freqbin_5GHT40 = {
2208 + FREQ2FBIN(5180, 0),
2209 + FREQ2FBIN(5220, 0),
2210 + FREQ2FBIN(5320, 0),
2211 + FREQ2FBIN(5400, 0),
2212 + FREQ2FBIN(5500, 0),
2213 + FREQ2FBIN(5600, 0),
2214 + FREQ2FBIN(5725, 0),
2215 + FREQ2FBIN(5825, 0)
2216 + },
2217 + .calTargetPower5G = {
2218 + /* 6-24,36,48,54 */
2219 + { {32, 32, 28, 26} },
2220 + { {32, 32, 28, 26} },
2221 + { {32, 32, 28, 26} },
2222 + { {32, 32, 26, 24} },
2223 + { {32, 32, 26, 24} },
2224 + { {32, 32, 24, 22} },
2225 + { {30, 30, 24, 22} },
2226 + { {30, 30, 24, 22} },
2227 + },
2228 + .calTargetPower5GHT20 = {
2229 + /*
2230 + * 0_8_16,1-3_9-11_17-19,
2231 + * 4,5,6,7,12,13,14,15,20,21,22,23
2232 + */
2233 + { {32, 32, 32, 32, 28, 26, 32, 28, 26, 24, 24, 24, 22, 22} },
2234 + { {32, 32, 32, 32, 28, 26, 32, 28, 26, 24, 24, 24, 22, 22} },
2235 + { {32, 32, 32, 32, 28, 26, 32, 28, 26, 24, 24, 24, 22, 22} },
2236 + { {32, 32, 32, 32, 28, 26, 32, 26, 24, 22, 22, 22, 20, 20} },
2237 + { {32, 32, 32, 32, 28, 26, 32, 26, 24, 22, 20, 18, 16, 16} },
2238 + { {32, 32, 32, 32, 28, 26, 32, 24, 20, 16, 18, 16, 14, 14} },
2239 + { {30, 30, 30, 30, 28, 26, 30, 24, 20, 16, 18, 16, 14, 14} },
2240 + { {30, 30, 30, 30, 28, 26, 30, 24, 20, 16, 18, 16, 14, 14} },
2241 + },
2242 + .calTargetPower5GHT40 = {
2243 + /*
2244 + * 0_8_16,1-3_9-11_17-19,
2245 + * 4,5,6,7,12,13,14,15,20,21,22,23
2246 + */
2247 + { {32, 32, 32, 30, 28, 26, 30, 28, 26, 24, 24, 24, 22, 22} },
2248 + { {32, 32, 32, 30, 28, 26, 30, 28, 26, 24, 24, 24, 22, 22} },
2249 + { {32, 32, 32, 30, 28, 26, 30, 28, 26, 24, 24, 24, 22, 22} },
2250 + { {32, 32, 32, 30, 28, 26, 30, 26, 24, 22, 22, 22, 20, 20} },
2251 + { {32, 32, 32, 30, 28, 26, 30, 26, 24, 22, 20, 18, 16, 16} },
2252 + { {32, 32, 32, 30, 28, 26, 30, 22, 20, 16, 18, 16, 14, 14} },
2253 + { {30, 30, 30, 30, 28, 26, 30, 22, 20, 16, 18, 16, 14, 14} },
2254 + { {30, 30, 30, 30, 28, 26, 30, 22, 20, 16, 18, 16, 14, 14} },
2255 + },
2256 + .ctlIndex_5G = {
2257 + 0x10, 0x16, 0x18, 0x40, 0x46,
2258 + 0x48, 0x30, 0x36, 0x38
2259 + },
2260 + .ctl_freqbin_5G = {
2261 + {
2262 + /* Data[0].ctledges[0].bchannel */ FREQ2FBIN(5180, 0),
2263 + /* Data[0].ctledges[1].bchannel */ FREQ2FBIN(5260, 0),
2264 + /* Data[0].ctledges[2].bchannel */ FREQ2FBIN(5280, 0),
2265 + /* Data[0].ctledges[3].bchannel */ FREQ2FBIN(5500, 0),
2266 + /* Data[0].ctledges[4].bchannel */ FREQ2FBIN(5600, 0),
2267 + /* Data[0].ctledges[5].bchannel */ FREQ2FBIN(5700, 0),
2268 + /* Data[0].ctledges[6].bchannel */ FREQ2FBIN(5745, 0),
2269 + /* Data[0].ctledges[7].bchannel */ FREQ2FBIN(5825, 0)
2270 + },
2271 + {
2272 + /* Data[1].ctledges[0].bchannel */ FREQ2FBIN(5180, 0),
2273 + /* Data[1].ctledges[1].bchannel */ FREQ2FBIN(5260, 0),
2274 + /* Data[1].ctledges[2].bchannel */ FREQ2FBIN(5280, 0),
2275 + /* Data[1].ctledges[3].bchannel */ FREQ2FBIN(5500, 0),
2276 + /* Data[1].ctledges[4].bchannel */ FREQ2FBIN(5520, 0),
2277 + /* Data[1].ctledges[5].bchannel */ FREQ2FBIN(5700, 0),
2278 + /* Data[1].ctledges[6].bchannel */ FREQ2FBIN(5745, 0),
2279 + /* Data[1].ctledges[7].bchannel */ FREQ2FBIN(5825, 0)
2280 + },
2281 +
2282 + {
2283 + /* Data[2].ctledges[0].bchannel */ FREQ2FBIN(5190, 0),
2284 + /* Data[2].ctledges[1].bchannel */ FREQ2FBIN(5230, 0),
2285 + /* Data[2].ctledges[2].bchannel */ FREQ2FBIN(5270, 0),
2286 + /* Data[2].ctledges[3].bchannel */ FREQ2FBIN(5310, 0),
2287 + /* Data[2].ctledges[4].bchannel */ FREQ2FBIN(5510, 0),
2288 + /* Data[2].ctledges[5].bchannel */ FREQ2FBIN(5550, 0),
2289 + /* Data[2].ctledges[6].bchannel */ FREQ2FBIN(5670, 0),
2290 + /* Data[2].ctledges[7].bchannel */ FREQ2FBIN(5755, 0)
2291 + },
2292 +
2293 + {
2294 + /* Data[3].ctledges[0].bchannel */ FREQ2FBIN(5180, 0),
2295 + /* Data[3].ctledges[1].bchannel */ FREQ2FBIN(5200, 0),
2296 + /* Data[3].ctledges[2].bchannel */ FREQ2FBIN(5260, 0),
2297 + /* Data[3].ctledges[3].bchannel */ FREQ2FBIN(5320, 0),
2298 + /* Data[3].ctledges[4].bchannel */ FREQ2FBIN(5500, 0),
2299 + /* Data[3].ctledges[5].bchannel */ FREQ2FBIN(5700, 0),
2300 + /* Data[3].ctledges[6].bchannel */ 0xFF,
2301 + /* Data[3].ctledges[7].bchannel */ 0xFF,
2302 + },
2303 +
2304 + {
2305 + /* Data[4].ctledges[0].bchannel */ FREQ2FBIN(5180, 0),
2306 + /* Data[4].ctledges[1].bchannel */ FREQ2FBIN(5260, 0),
2307 + /* Data[4].ctledges[2].bchannel */ FREQ2FBIN(5500, 0),
2308 + /* Data[4].ctledges[3].bchannel */ FREQ2FBIN(5700, 0),
2309 + /* Data[4].ctledges[4].bchannel */ 0xFF,
2310 + /* Data[4].ctledges[5].bchannel */ 0xFF,
2311 + /* Data[4].ctledges[6].bchannel */ 0xFF,
2312 + /* Data[4].ctledges[7].bchannel */ 0xFF,
2313 + },
2314 +
2315 + {
2316 + /* Data[5].ctledges[0].bchannel */ FREQ2FBIN(5190, 0),
2317 + /* Data[5].ctledges[1].bchannel */ FREQ2FBIN(5270, 0),
2318 + /* Data[5].ctledges[2].bchannel */ FREQ2FBIN(5310, 0),
2319 + /* Data[5].ctledges[3].bchannel */ FREQ2FBIN(5510, 0),
2320 + /* Data[5].ctledges[4].bchannel */ FREQ2FBIN(5590, 0),
2321 + /* Data[5].ctledges[5].bchannel */ FREQ2FBIN(5670, 0),
2322 + /* Data[5].ctledges[6].bchannel */ 0xFF,
2323 + /* Data[5].ctledges[7].bchannel */ 0xFF
2324 + },
2325 +
2326 + {
2327 + /* Data[6].ctledges[0].bchannel */ FREQ2FBIN(5180, 0),
2328 + /* Data[6].ctledges[1].bchannel */ FREQ2FBIN(5200, 0),
2329 + /* Data[6].ctledges[2].bchannel */ FREQ2FBIN(5220, 0),
2330 + /* Data[6].ctledges[3].bchannel */ FREQ2FBIN(5260, 0),
2331 + /* Data[6].ctledges[4].bchannel */ FREQ2FBIN(5500, 0),
2332 + /* Data[6].ctledges[5].bchannel */ FREQ2FBIN(5600, 0),
2333 + /* Data[6].ctledges[6].bchannel */ FREQ2FBIN(5700, 0),
2334 + /* Data[6].ctledges[7].bchannel */ FREQ2FBIN(5745, 0)
2335 + },
2336 +
2337 + {
2338 + /* Data[7].ctledges[0].bchannel */ FREQ2FBIN(5180, 0),
2339 + /* Data[7].ctledges[1].bchannel */ FREQ2FBIN(5260, 0),
2340 + /* Data[7].ctledges[2].bchannel */ FREQ2FBIN(5320, 0),
2341 + /* Data[7].ctledges[3].bchannel */ FREQ2FBIN(5500, 0),
2342 + /* Data[7].ctledges[4].bchannel */ FREQ2FBIN(5560, 0),
2343 + /* Data[7].ctledges[5].bchannel */ FREQ2FBIN(5700, 0),
2344 + /* Data[7].ctledges[6].bchannel */ FREQ2FBIN(5745, 0),
2345 + /* Data[7].ctledges[7].bchannel */ FREQ2FBIN(5825, 0)
2346 + },
2347 +
2348 + {
2349 + /* Data[8].ctledges[0].bchannel */ FREQ2FBIN(5190, 0),
2350 + /* Data[8].ctledges[1].bchannel */ FREQ2FBIN(5230, 0),
2351 + /* Data[8].ctledges[2].bchannel */ FREQ2FBIN(5270, 0),
2352 + /* Data[8].ctledges[3].bchannel */ FREQ2FBIN(5510, 0),
2353 + /* Data[8].ctledges[4].bchannel */ FREQ2FBIN(5550, 0),
2354 + /* Data[8].ctledges[5].bchannel */ FREQ2FBIN(5670, 0),
2355 + /* Data[8].ctledges[6].bchannel */ FREQ2FBIN(5755, 0),
2356 + /* Data[8].ctledges[7].bchannel */ FREQ2FBIN(5795, 0)
2357 + }
2358 + },
2359 + .ctlPowerData_5G = {
2360 + {
2361 + {
2362 + {60, 1}, {60, 1}, {60, 1}, {60, 1},
2363 + {60, 1}, {60, 1}, {60, 1}, {60, 0},
2364 + }
2365 + },
2366 + {
2367 + {
2368 + {60, 1}, {60, 1}, {60, 1}, {60, 1},
2369 + {60, 1}, {60, 1}, {60, 1}, {60, 0},
2370 + }
2371 + },
2372 + {
2373 + {
2374 + {60, 0}, {60, 1}, {60, 0}, {60, 1},
2375 + {60, 1}, {60, 1}, {60, 1}, {60, 1},
2376 + }
2377 + },
2378 + {
2379 + {
2380 + {60, 0}, {60, 1}, {60, 1}, {60, 0},
2381 + {60, 1}, {60, 0}, {60, 0}, {60, 0},
2382 + }
2383 + },
2384 + {
2385 + {
2386 + {60, 1}, {60, 1}, {60, 1}, {60, 0},
2387 + {60, 0}, {60, 0}, {60, 0}, {60, 0},
2388 + }
2389 + },
2390 + {
2391 + {
2392 + {60, 1}, {60, 1}, {60, 1}, {60, 1},
2393 + {60, 1}, {60, 0}, {60, 0}, {60, 0},
2394 + }
2395 + },
2396 + {
2397 + {
2398 + {60, 1}, {60, 1}, {60, 1}, {60, 1},
2399 + {60, 1}, {60, 1}, {60, 1}, {60, 1},
2400 + }
2401 + },
2402 + {
2403 + {
2404 + {60, 1}, {60, 1}, {60, 0}, {60, 1},
2405 + {60, 1}, {60, 1}, {60, 1}, {60, 0},
2406 + }
2407 + },
2408 + {
2409 + {
2410 + {60, 1}, {60, 0}, {60, 1}, {60, 1},
2411 + {60, 1}, {60, 1}, {60, 0}, {60, 1},
2412 + }
2413 + },
2414 + }
2415 +};
2416 +
2417 +static const struct ar9300_eeprom ar9300_h116 = {
2418 + .eepromVersion = 2,
2419 + .templateVersion = 4,
2420 + .macAddr = {0x00, 0x03, 0x7f, 0x0, 0x0, 0x0},
2421 + .custData = {"h116-041-f0000"},
2422 .baseEepHeader = {
2423 .regDmn = { LE16(0), LE16(0x1f) },
2424 - .txrxMask = 0x77, /* 4 bits tx and 4 bits rx */
2425 + .txrxMask = 0x33, /* 4 bits tx and 4 bits rx */
2426 .opCapFlags = {
2427 .opFlags = AR9300_OPFLAGS_11G | AR9300_OPFLAGS_11A,
2428 .eepMisc = 0,
2429 @@ -74,7 +2388,7 @@ static const struct ar9300_eeprom ar9300
2430 .deviceType = 5, /* takes lower byte in eeprom location */
2431 .pwrTableOffset = AR9300_PWR_TABLE_OFFSET,
2432 .params_for_tuning_caps = {0, 0},
2433 - .featureEnable = 0x0c,
2434 + .featureEnable = 0x0d,
2435 /*
2436 * bit0 - enable tx temp comp - disabled
2437 * bit1 - enable tx volt comp - disabled
2438 @@ -84,11 +2398,11 @@ static const struct ar9300_eeprom ar9300
2439 * bit5 - enable pa predistortion - disabled
2440 */
2441 .miscConfiguration = 0, /* bit0 - turn down drivestrength */
2442 - .eepromWriteEnableGpio = 3,
2443 + .eepromWriteEnableGpio = 6,
2444 .wlanDisableGpio = 0,
2445 .wlanLedGpio = 8,
2446 .rxBandSelectGpio = 0xff,
2447 - .txrxgain = 0,
2448 + .txrxgain = 0x10,
2449 .swreg = 0,
2450 },
2451 .modalHeader2G = {
2452 @@ -96,33 +2410,33 @@ static const struct ar9300_eeprom ar9300
2453 /* 4 idle,t1,t2,b(4 bits per setting) */
2454 .antCtrlCommon = LE32(0x110),
2455 /* 4 ra1l1, ra2l1, ra1l2, ra2l2, ra12 */
2456 - .antCtrlCommon2 = LE32(0x22222),
2457 + .antCtrlCommon2 = LE32(0x44444),
2458
2459 /*
2460 * antCtrlChain[AR9300_MAX_CHAINS]; 6 idle, t, r,
2461 * rx1, rx12, b (2 bits each)
2462 */
2463 - .antCtrlChain = { LE16(0x150), LE16(0x150), LE16(0x150) },
2464 + .antCtrlChain = { LE16(0x10), LE16(0x10), LE16(0x10) },
2465
2466 /*
2467 * xatten1DB[AR9300_MAX_CHAINS]; 3 xatten1_db
2468 * for ar9280 (0xa20c/b20c 5:0)
2469 */
2470 - .xatten1DB = {0, 0, 0},
2471 + .xatten1DB = {0x1f, 0x1f, 0x1f},
2472
2473 /*
2474 * xatten1Margin[AR9300_MAX_CHAINS]; 3 xatten1_margin
2475 * for ar9280 (0xa20c/b20c 16:12
2476 */
2477 - .xatten1Margin = {0, 0, 0},
2478 - .tempSlope = 36,
2479 + .xatten1Margin = {0x12, 0x12, 0x12},
2480 + .tempSlope = 25,
2481 .voltSlope = 0,
2482
2483 /*
2484 * spurChans[OSPREY_EEPROM_MODAL_SPURS]; spur
2485 * channels in usual fbin coding format
2486 */
2487 - .spurChans = {0, 0, 0, 0, 0},
2488 + .spurChans = {FREQ2FBIN(2464, 1), 0, 0, 0, 0},
2489
2490 /*
2491 * noiseFloorThreshCh[AR9300_MAX_CHAINS]; 3 Check
2492 @@ -144,13 +2458,16 @@ static const struct ar9300_eeprom ar9300
2493 .txEndToRxOn = 0x2,
2494 .txFrameToXpaOn = 0xe,
2495 .thresh62 = 28,
2496 - .papdRateMaskHt20 = LE32(0x80c080),
2497 - .papdRateMaskHt40 = LE32(0x80c080),
2498 + .papdRateMaskHt20 = LE32(0x0c80C080),
2499 + .papdRateMaskHt40 = LE32(0x0080C080),
2500 .futureModal = {
2501 - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2502 - 0, 0, 0, 0, 0, 0, 0, 0
2503 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2504 },
2505 },
2506 + .base_ext1 = {
2507 + .ant_div_control = 0,
2508 + .future = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}
2509 + },
2510 .calFreqPier2G = {
2511 FREQ2FBIN(2412, 1),
2512 FREQ2FBIN(2437, 1),
2513 @@ -164,7 +2481,7 @@ static const struct ar9300_eeprom ar9300
2514 },
2515 .calTarget_freqbin_Cck = {
2516 FREQ2FBIN(2412, 1),
2517 - FREQ2FBIN(2484, 1),
2518 + FREQ2FBIN(2472, 1),
2519 },
2520 .calTarget_freqbin_2G = {
2521 FREQ2FBIN(2412, 1),
2522 @@ -183,24 +2500,24 @@ static const struct ar9300_eeprom ar9300
2523 },
2524 .calTargetPowerCck = {
2525 /* 1L-5L,5S,11L,11S */
2526 - { {36, 36, 36, 36} },
2527 - { {36, 36, 36, 36} },
2528 + { {34, 34, 34, 34} },
2529 + { {34, 34, 34, 34} },
2530 },
2531 .calTargetPower2G = {
2532 /* 6-24,36,48,54 */
2533 - { {32, 32, 28, 24} },
2534 - { {32, 32, 28, 24} },
2535 - { {32, 32, 28, 24} },
2536 + { {34, 34, 32, 32} },
2537 + { {34, 34, 32, 32} },
2538 + { {34, 34, 32, 32} },
2539 },
2540 .calTargetPower2GHT20 = {
2541 - { {32, 32, 32, 32, 28, 20, 32, 32, 28, 20, 32, 32, 28, 20} },
2542 - { {32, 32, 32, 32, 28, 20, 32, 32, 28, 20, 32, 32, 28, 20} },
2543 - { {32, 32, 32, 32, 28, 20, 32, 32, 28, 20, 32, 32, 28, 20} },
2544 + { {32, 32, 32, 32, 32, 30, 32, 32, 30, 28, 0, 0, 0, 0} },
2545 + { {32, 32, 32, 32, 32, 30, 32, 32, 30, 28, 0, 0, 0, 0} },
2546 + { {32, 32, 32, 32, 32, 30, 32, 32, 30, 28, 0, 0, 0, 0} },
2547 },
2548 .calTargetPower2GHT40 = {
2549 - { {32, 32, 32, 32, 28, 20, 32, 32, 28, 20, 32, 32, 28, 20} },
2550 - { {32, 32, 32, 32, 28, 20, 32, 32, 28, 20, 32, 32, 28, 20} },
2551 - { {32, 32, 32, 32, 28, 20, 32, 32, 28, 20, 32, 32, 28, 20} },
2552 + { {30, 30, 30, 30, 30, 28, 30, 30, 28, 26, 0, 0, 0, 0} },
2553 + { {30, 30, 30, 30, 30, 28, 30, 30, 28, 26, 0, 0, 0, 0} },
2554 + { {30, 30, 30, 30, 30, 28, 30, 30, 28, 26, 0, 0, 0, 0} },
2555 },
2556 .ctlIndex_2G = {
2557 0x11, 0x12, 0x15, 0x17, 0x41, 0x42,
2558 @@ -285,8 +2602,7 @@ static const struct ar9300_eeprom ar9300
2559 /* Data[11].ctlEdges[0].bChannel */ FREQ2FBIN(2422, 1),
2560 /* Data[11].ctlEdges[1].bChannel */ FREQ2FBIN(2427, 1),
2561 /* Data[11].ctlEdges[2].bChannel */ FREQ2FBIN(2447, 1),
2562 - /* Data[11].ctlEdges[3].bChannel */
2563 - FREQ2FBIN(2462, 1),
2564 + /* Data[11].ctlEdges[3].bChannel */ FREQ2FBIN(2462, 1),
2565 }
2566 },
2567 .ctlPowerData_2G = {
2568 @@ -304,25 +2620,26 @@ static const struct ar9300_eeprom ar9300
2569
2570 { { {60, 0}, {60, 1}, {60, 0}, {60, 0} } },
2571 { { {60, 0}, {60, 1}, {60, 1}, {60, 1} } },
2572 + { { {60, 0}, {60, 1}, {60, 1}, {60, 1} } },
2573 },
2574 .modalHeader5G = {
2575 /* 4 idle,t1,t2,b (4 bits per setting) */
2576 - .antCtrlCommon = LE32(0x110),
2577 + .antCtrlCommon = LE32(0x220),
2578 /* 4 ra1l1, ra2l1, ra1l2,ra2l2,ra12 */
2579 - .antCtrlCommon2 = LE32(0x22222),
2580 + .antCtrlCommon2 = LE32(0x44444),
2581 /* antCtrlChain 6 idle, t,r,rx1,rx12,b (2 bits each) */
2582 .antCtrlChain = {
2583 - LE16(0x000), LE16(0x000), LE16(0x000),
2584 + LE16(0x150), LE16(0x150), LE16(0x150),
2585 },
2586 /* xatten1DB 3 xatten1_db for AR9280 (0xa20c/b20c 5:0) */
2587 - .xatten1DB = {0, 0, 0},
2588 + .xatten1DB = {0x19, 0x19, 0x19},
2589
2590 /*
2591 * xatten1Margin[AR9300_MAX_CHAINS]; 3 xatten1_margin
2592 * for merlin (0xa20c/b20c 16:12
2593 */
2594 - .xatten1Margin = {0, 0, 0},
2595 - .tempSlope = 68,
2596 + .xatten1Margin = {0x14, 0x14, 0x14},
2597 + .tempSlope = 70,
2598 .voltSlope = 0,
2599 /* spurChans spur channels in usual fbin coding format */
2600 .spurChans = {0, 0, 0, 0, 0},
2601 @@ -343,13 +2660,20 @@ static const struct ar9300_eeprom ar9300
2602 .txEndToRxOn = 0x2,
2603 .txFrameToXpaOn = 0xe,
2604 .thresh62 = 28,
2605 - .papdRateMaskHt20 = LE32(0xf0e0e0),
2606 - .papdRateMaskHt40 = LE32(0xf0e0e0),
2607 + .papdRateMaskHt20 = LE32(0x0cf0e0e0),
2608 + .papdRateMaskHt40 = LE32(0x6cf0e0e0),
2609 .futureModal = {
2610 - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2611 - 0, 0, 0, 0, 0, 0, 0, 0
2612 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2613 },
2614 },
2615 + .base_ext2 = {
2616 + .tempSlopeLow = 35,
2617 + .tempSlopeHigh = 50,
2618 + .xatten1DBLow = {0, 0, 0},
2619 + .xatten1MarginLow = {0, 0, 0},
2620 + .xatten1DBHigh = {0, 0, 0},
2621 + .xatten1MarginHigh = {0, 0, 0}
2622 + },
2623 .calFreqPier5G = {
2624 FREQ2FBIN(5180, 0),
2625 FREQ2FBIN(5220, 0),
2626 @@ -357,8 +2681,8 @@ static const struct ar9300_eeprom ar9300
2627 FREQ2FBIN(5400, 0),
2628 FREQ2FBIN(5500, 0),
2629 FREQ2FBIN(5600, 0),
2630 - FREQ2FBIN(5725, 0),
2631 - FREQ2FBIN(5825, 0)
2632 + FREQ2FBIN(5700, 0),
2633 + FREQ2FBIN(5785, 0)
2634 },
2635 .calPierData5G = {
2636 {
2637 @@ -395,72 +2719,72 @@ static const struct ar9300_eeprom ar9300
2638 },
2639 .calTarget_freqbin_5G = {
2640 FREQ2FBIN(5180, 0),
2641 - FREQ2FBIN(5220, 0),
2642 + FREQ2FBIN(5240, 0),
2643 FREQ2FBIN(5320, 0),
2644 FREQ2FBIN(5400, 0),
2645 FREQ2FBIN(5500, 0),
2646 FREQ2FBIN(5600, 0),
2647 - FREQ2FBIN(5725, 0),
2648 + FREQ2FBIN(5700, 0),
2649 FREQ2FBIN(5825, 0)
2650 },
2651 .calTarget_freqbin_5GHT20 = {
2652 FREQ2FBIN(5180, 0),
2653 FREQ2FBIN(5240, 0),
2654 FREQ2FBIN(5320, 0),
2655 + FREQ2FBIN(5400, 0),
2656 FREQ2FBIN(5500, 0),
2657 FREQ2FBIN(5700, 0),
2658 FREQ2FBIN(5745, 0),
2659 - FREQ2FBIN(5725, 0),
2660 FREQ2FBIN(5825, 0)
2661 },
2662 .calTarget_freqbin_5GHT40 = {
2663 FREQ2FBIN(5180, 0),
2664 FREQ2FBIN(5240, 0),
2665 FREQ2FBIN(5320, 0),
2666 + FREQ2FBIN(5400, 0),
2667 FREQ2FBIN(5500, 0),
2668 FREQ2FBIN(5700, 0),
2669 FREQ2FBIN(5745, 0),
2670 - FREQ2FBIN(5725, 0),
2671 FREQ2FBIN(5825, 0)
2672 },
2673 .calTargetPower5G = {
2674 /* 6-24,36,48,54 */
2675 - { {20, 20, 20, 10} },
2676 - { {20, 20, 20, 10} },
2677 - { {20, 20, 20, 10} },
2678 - { {20, 20, 20, 10} },
2679 - { {20, 20, 20, 10} },
2680 - { {20, 20, 20, 10} },
2681 - { {20, 20, 20, 10} },
2682 - { {20, 20, 20, 10} },
2683 + { {30, 30, 28, 24} },
2684 + { {30, 30, 28, 24} },
2685 + { {30, 30, 28, 24} },
2686 + { {30, 30, 28, 24} },
2687 + { {30, 30, 28, 24} },
2688 + { {30, 30, 28, 24} },
2689 + { {30, 30, 28, 24} },
2690 + { {30, 30, 28, 24} },
2691 },
2692 .calTargetPower5GHT20 = {
2693 /*
2694 * 0_8_16,1-3_9-11_17-19,
2695 * 4,5,6,7,12,13,14,15,20,21,22,23
2696 */
2697 - { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
2698 - { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
2699 - { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
2700 - { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
2701 - { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
2702 - { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
2703 - { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
2704 - { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
2705 + { {30, 30, 30, 28, 24, 20, 30, 28, 24, 20, 0, 0, 0, 0} },
2706 + { {30, 30, 30, 28, 24, 20, 30, 28, 24, 20, 0, 0, 0, 0} },
2707 + { {30, 30, 30, 26, 22, 18, 30, 26, 22, 18, 0, 0, 0, 0} },
2708 + { {30, 30, 30, 26, 22, 18, 30, 26, 22, 18, 0, 0, 0, 0} },
2709 + { {30, 30, 30, 24, 20, 16, 30, 24, 20, 16, 0, 0, 0, 0} },
2710 + { {30, 30, 30, 24, 20, 16, 30, 24, 20, 16, 0, 0, 0, 0} },
2711 + { {30, 30, 30, 22, 18, 14, 30, 22, 18, 14, 0, 0, 0, 0} },
2712 + { {30, 30, 30, 22, 18, 14, 30, 22, 18, 14, 0, 0, 0, 0} },
2713 },
2714 .calTargetPower5GHT40 = {
2715 /*
2716 * 0_8_16,1-3_9-11_17-19,
2717 * 4,5,6,7,12,13,14,15,20,21,22,23
2718 */
2719 - { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
2720 - { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
2721 - { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
2722 - { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
2723 - { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
2724 - { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
2725 - { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
2726 - { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
2727 + { {28, 28, 28, 26, 22, 18, 28, 26, 22, 18, 0, 0, 0, 0} },
2728 + { {28, 28, 28, 26, 22, 18, 28, 26, 22, 18, 0, 0, 0, 0} },
2729 + { {28, 28, 28, 24, 20, 16, 28, 24, 20, 16, 0, 0, 0, 0} },
2730 + { {28, 28, 28, 24, 20, 16, 28, 24, 20, 16, 0, 0, 0, 0} },
2731 + { {28, 28, 28, 22, 18, 14, 28, 22, 18, 14, 0, 0, 0, 0} },
2732 + { {28, 28, 28, 22, 18, 14, 28, 22, 18, 14, 0, 0, 0, 0} },
2733 + { {28, 28, 28, 20, 16, 12, 28, 20, 16, 12, 0, 0, 0, 0} },
2734 + { {28, 28, 28, 20, 16, 12, 28, 20, 16, 12, 0, 0, 0, 0} },
2735 },
2736 .ctlIndex_5G = {
2737 0x10, 0x16, 0x18, 0x40, 0x46,
2738 @@ -623,6 +2947,28 @@ static const struct ar9300_eeprom ar9300
2739 }
2740 };
2741
2742 +
2743 +static const struct ar9300_eeprom *ar9300_eep_templates[] = {
2744 + &ar9300_default,
2745 + &ar9300_x112,
2746 + &ar9300_h116,
2747 + &ar9300_h112,
2748 + &ar9300_x113,
2749 +};
2750 +
2751 +static const struct ar9300_eeprom *ar9003_eeprom_struct_find_by_id(int id)
2752 +{
2753 +#define N_LOOP (sizeof(ar9300_eep_templates) / sizeof(ar9300_eep_templates[0]))
2754 + int it;
2755 +
2756 + for (it = 0; it < N_LOOP; it++)
2757 + if (ar9300_eep_templates[it]->templateVersion == id)
2758 + return ar9300_eep_templates[it];
2759 + return NULL;
2760 +#undef N_LOOP
2761 +}
2762 +
2763 +
2764 static u16 ath9k_hw_fbin2freq(u8 fbin, bool is2GHz)
2765 {
2766 if (fbin == AR9300_BCHAN_UNUSED)
2767 @@ -636,6 +2982,16 @@ static int ath9k_hw_ar9300_check_eeprom(
2768 return 0;
2769 }
2770
2771 +static int interpolate(int x, int xa, int xb, int ya, int yb)
2772 +{
2773 + int bf, factor, plus;
2774 +
2775 + bf = 2 * (yb - ya) * (x - xa) / (xb - xa);
2776 + factor = bf / 2;
2777 + plus = bf % 2;
2778 + return ya + factor + plus;
2779 +}
2780 +
2781 static u32 ath9k_hw_ar9300_get_eeprom(struct ath_hw *ah,
2782 enum eeprom_param param)
2783 {
2784 @@ -824,6 +3180,7 @@ static int ar9300_compress_decision(stru
2785 {
2786 struct ath_common *common = ath9k_hw_common(ah);
2787 u8 *dptr;
2788 + const struct ar9300_eeprom *eep = NULL;
2789
2790 switch (code) {
2791 case _CompressNone:
2792 @@ -841,13 +3198,14 @@ static int ar9300_compress_decision(stru
2793 if (reference == 0) {
2794 dptr = mptr;
2795 } else {
2796 - if (reference != 2) {
2797 + eep = ar9003_eeprom_struct_find_by_id(reference);
2798 + if (eep == NULL) {
2799 ath_print(common, ATH_DBG_EEPROM,
2800 "cant find reference eeprom"
2801 "struct %d\n", reference);
2802 return -1;
2803 }
2804 - memcpy(mptr, &ar9300_default, mdata_size);
2805 + memcpy(mptr, eep, mdata_size);
2806 }
2807 ath_print(common, ATH_DBG_EEPROM,
2808 "restore eeprom %d: block, reference %d,"
2809 @@ -992,9 +3350,9 @@ static s32 ar9003_hw_xpa_bias_level_get(
2810 static void ar9003_hw_xpa_bias_level_apply(struct ath_hw *ah, bool is2ghz)
2811 {
2812 int bias = ar9003_hw_xpa_bias_level_get(ah, is2ghz);
2813 - REG_RMW_FIELD(ah, AR_CH0_TOP, AR_CH0_TOP_XPABIASLVL, (bias & 0x3));
2814 - REG_RMW_FIELD(ah, AR_CH0_THERM, AR_CH0_THERM_SPARE,
2815 - ((bias >> 2) & 0x3));
2816 + REG_RMW_FIELD(ah, AR_CH0_TOP, AR_CH0_TOP_XPABIASLVL, bias);
2817 + REG_RMW_FIELD(ah, AR_CH0_THERM, AR_CH0_THERM_XPABIASLVL_MSB, bias >> 2);
2818 + REG_RMW_FIELD(ah, AR_CH0_THERM, AR_CH0_THERM_XPASHORT2GND, 1);
2819 }
2820
2821 static u32 ar9003_hw_ant_ctrl_common_get(struct ath_hw *ah, bool is2ghz)
2822 @@ -1097,6 +3455,82 @@ static void ar9003_hw_drive_strength_app
2823 REG_WRITE(ah, AR_PHY_65NM_CH0_BIAS4, reg);
2824 }
2825
2826 +static u16 ar9003_hw_atten_chain_get(struct ath_hw *ah, int chain,
2827 + struct ath9k_channel *chan)
2828 +{
2829 + int f[3], t[3];
2830 + u16 value;
2831 + struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
2832 +
2833 + if (chain >= 0 && chain < 3) {
2834 + if (IS_CHAN_2GHZ(chan))
2835 + return eep->modalHeader2G.xatten1DB[chain];
2836 + else if (eep->base_ext2.xatten1DBLow[chain] != 0) {
2837 + t[0] = eep->base_ext2.xatten1DBLow[chain];
2838 + f[0] = 5180;
2839 + t[1] = eep->modalHeader5G.xatten1DB[chain];
2840 + f[1] = 5500;
2841 + t[2] = eep->base_ext2.xatten1DBHigh[chain];
2842 + f[2] = 5785;
2843 + value = ar9003_hw_power_interpolate((s32) chan->channel,
2844 + f, t, 3);
2845 + return value;
2846 + } else
2847 + return eep->modalHeader5G.xatten1DB[chain];
2848 + }
2849 +
2850 + return 0;
2851 +}
2852 +
2853 +
2854 +static u16 ar9003_hw_atten_chain_get_margin(struct ath_hw *ah, int chain,
2855 + struct ath9k_channel *chan)
2856 +{
2857 + int f[3], t[3];
2858 + u16 value;
2859 + struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
2860 +
2861 + if (chain >= 0 && chain < 3) {
2862 + if (IS_CHAN_2GHZ(chan))
2863 + return eep->modalHeader2G.xatten1Margin[chain];
2864 + else if (eep->base_ext2.xatten1MarginLow[chain] != 0) {
2865 + t[0] = eep->base_ext2.xatten1MarginLow[chain];
2866 + f[0] = 5180;
2867 + t[1] = eep->modalHeader5G.xatten1Margin[chain];
2868 + f[1] = 5500;
2869 + t[2] = eep->base_ext2.xatten1MarginHigh[chain];
2870 + f[2] = 5785;
2871 + value = ar9003_hw_power_interpolate((s32) chan->channel,
2872 + f, t, 3);
2873 + return value;
2874 + } else
2875 + return eep->modalHeader5G.xatten1Margin[chain];
2876 + }
2877 +
2878 + return 0;
2879 +}
2880 +
2881 +static void ar9003_hw_atten_apply(struct ath_hw *ah, struct ath9k_channel *chan)
2882 +{
2883 + int i;
2884 + u16 value;
2885 + unsigned long ext_atten_reg[3] = {AR_PHY_EXT_ATTEN_CTL_0,
2886 + AR_PHY_EXT_ATTEN_CTL_1,
2887 + AR_PHY_EXT_ATTEN_CTL_2,
2888 + };
2889 +
2890 + /* Test value. if 0 then attenuation is unused. Don't load anything. */
2891 + for (i = 0; i < 3; i++) {
2892 + value = ar9003_hw_atten_chain_get(ah, i, chan);
2893 + REG_RMW_FIELD(ah, ext_atten_reg[i],
2894 + AR_PHY_EXT_ATTEN_CTL_XATTEN1_DB, value);
2895 +
2896 + value = ar9003_hw_atten_chain_get_margin(ah, i, chan);
2897 + REG_RMW_FIELD(ah, ext_atten_reg[i],
2898 + AR_PHY_EXT_ATTEN_CTL_XATTEN1_MARGIN, value);
2899 + }
2900 +}
2901 +
2902 static void ar9003_hw_internal_regulator_apply(struct ath_hw *ah)
2903 {
2904 int internal_regulator =
2905 @@ -1128,6 +3562,7 @@ static void ath9k_hw_ar9300_set_board_va
2906 ar9003_hw_xpa_bias_level_apply(ah, IS_CHAN_2GHZ(chan));
2907 ar9003_hw_ant_ctrl_apply(ah, IS_CHAN_2GHZ(chan));
2908 ar9003_hw_drive_strength_apply(ah);
2909 + ar9003_hw_atten_apply(ah, chan);
2910 ar9003_hw_internal_regulator_apply(ah);
2911 }
2912
2913 @@ -1189,7 +3624,7 @@ static int ar9003_hw_power_interpolate(i
2914 if (hx == lx)
2915 y = ly;
2916 else /* interpolate */
2917 - y = ly + (((x - lx) * (hy - ly)) / (hx - lx));
2918 + y = interpolate(x, lx, hx, ly, hy);
2919 } else /* only low is good, use it */
2920 y = ly;
2921 } else if (hhave) /* only high is good, use it */
2922 @@ -1637,6 +4072,7 @@ static int ar9003_hw_power_control_overr
2923 {
2924 int tempSlope = 0;
2925 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
2926 + int f[3], t[3];
2927
2928 REG_RMW(ah, AR_PHY_TPC_11_B0,
2929 (correction[0] << AR_PHY_TPC_OLPC_GAIN_DELTA_S),
2930 @@ -1665,7 +4101,16 @@ static int ar9003_hw_power_control_overr
2931 */
2932 if (frequency < 4000)
2933 tempSlope = eep->modalHeader2G.tempSlope;
2934 - else
2935 + else if (eep->base_ext2.tempSlopeLow != 0) {
2936 + t[0] = eep->base_ext2.tempSlopeLow;
2937 + f[0] = 5180;
2938 + t[1] = eep->modalHeader5G.tempSlope;
2939 + f[1] = 5500;
2940 + t[2] = eep->base_ext2.tempSlopeHigh;
2941 + f[2] = 5785;
2942 + tempSlope = ar9003_hw_power_interpolate((s32) frequency,
2943 + f, t, 3);
2944 + } else
2945 tempSlope = eep->modalHeader5G.tempSlope;
2946
2947 REG_RMW_FIELD(ah, AR_PHY_TPC_19, AR_PHY_TPC_19_ALPHA_THERM, tempSlope);
2948 @@ -1769,25 +4214,23 @@ static int ar9003_hw_calibration_apply(s
2949 /* so is the high frequency, interpolate */
2950 if (hfrequency[ichain] - frequency < 1000) {
2951
2952 - correction[ichain] = lcorrection[ichain] +
2953 - (((frequency - lfrequency[ichain]) *
2954 - (hcorrection[ichain] -
2955 - lcorrection[ichain])) /
2956 - (hfrequency[ichain] - lfrequency[ichain]));
2957 -
2958 - temperature[ichain] = ltemperature[ichain] +
2959 - (((frequency - lfrequency[ichain]) *
2960 - (htemperature[ichain] -
2961 - ltemperature[ichain])) /
2962 - (hfrequency[ichain] - lfrequency[ichain]));
2963 -
2964 - voltage[ichain] =
2965 - lvoltage[ichain] +
2966 - (((frequency -
2967 - lfrequency[ichain]) * (hvoltage[ichain] -
2968 - lvoltage[ichain]))
2969 - / (hfrequency[ichain] -
2970 - lfrequency[ichain]));
2971 + correction[ichain] = interpolate(frequency,
2972 + lfrequency[ichain],
2973 + hfrequency[ichain],
2974 + lcorrection[ichain],
2975 + hcorrection[ichain]);
2976 +
2977 + temperature[ichain] = interpolate(frequency,
2978 + lfrequency[ichain],
2979 + hfrequency[ichain],
2980 + ltemperature[ichain],
2981 + htemperature[ichain]);
2982 +
2983 + voltage[ichain] = interpolate(frequency,
2984 + lfrequency[ichain],
2985 + hfrequency[ichain],
2986 + lvoltage[ichain],
2987 + hvoltage[ichain]);
2988 }
2989 /* only low is good, use it */
2990 else {
2991 --- a/drivers/net/wireless/ath/ath9k/ar9003_eeprom.h
2992 +++ b/drivers/net/wireless/ath/ath9k/ar9003_eeprom.h
2993 @@ -236,7 +236,7 @@ struct ar9300_modal_eep_header {
2994 u8 thresh62;
2995 __le32 papdRateMaskHt20;
2996 __le32 papdRateMaskHt40;
2997 - u8 futureModal[24];
2998 + u8 futureModal[10];
2999 } __packed;
3000
3001 struct ar9300_cal_data_per_freq_op_loop {
3002 @@ -274,6 +274,20 @@ struct cal_ctl_data_5g {
3003 struct cal_ctl_edge_pwr ctlEdges[AR9300_NUM_BAND_EDGES_5G];
3004 } __packed;
3005
3006 +struct ar9300_BaseExtension_1 {
3007 + u8 ant_div_control;
3008 + u8 future[13];
3009 +} __packed;
3010 +
3011 +struct ar9300_BaseExtension_2 {
3012 + int8_t tempSlopeLow;
3013 + int8_t tempSlopeHigh;
3014 + u8 xatten1DBLow[AR9300_MAX_CHAINS];
3015 + u8 xatten1MarginLow[AR9300_MAX_CHAINS];
3016 + u8 xatten1DBHigh[AR9300_MAX_CHAINS];
3017 + u8 xatten1MarginHigh[AR9300_MAX_CHAINS];
3018 +} __packed;
3019 +
3020 struct ar9300_eeprom {
3021 u8 eepromVersion;
3022 u8 templateVersion;
3023 @@ -283,6 +297,7 @@ struct ar9300_eeprom {
3024 struct ar9300_base_eep_hdr baseEepHeader;
3025
3026 struct ar9300_modal_eep_header modalHeader2G;
3027 + struct ar9300_BaseExtension_1 base_ext1;
3028 u8 calFreqPier2G[AR9300_NUM_2G_CAL_PIERS];
3029 struct ar9300_cal_data_per_freq_op_loop
3030 calPierData2G[AR9300_MAX_CHAINS][AR9300_NUM_2G_CAL_PIERS];
3031 @@ -302,6 +317,7 @@ struct ar9300_eeprom {
3032 u8 ctl_freqbin_2G[AR9300_NUM_CTLS_2G][AR9300_NUM_BAND_EDGES_2G];
3033 struct cal_ctl_data_2g ctlPowerData_2G[AR9300_NUM_CTLS_2G];
3034 struct ar9300_modal_eep_header modalHeader5G;
3035 + struct ar9300_BaseExtension_2 base_ext2;
3036 u8 calFreqPier5G[AR9300_NUM_5G_CAL_PIERS];
3037 struct ar9300_cal_data_per_freq_op_loop
3038 calPierData5G[AR9300_MAX_CHAINS][AR9300_NUM_5G_CAL_PIERS];
3039 --- a/drivers/net/wireless/ath/ath9k/ar9003_mac.c
3040 +++ b/drivers/net/wireless/ath/ath9k/ar9003_mac.c
3041 @@ -410,12 +410,36 @@ static void ar9003_hw_set11n_ratescenari
3042 static void ar9003_hw_set11n_aggr_first(struct ath_hw *ah, void *ds,
3043 u32 aggrLen)
3044 {
3045 +#define FIRST_DESC_NDELIMS 60
3046 struct ar9003_txc *ads = (struct ar9003_txc *) ds;
3047
3048 ads->ctl12 |= (AR_IsAggr | AR_MoreAggr);
3049
3050 - ads->ctl17 &= ~AR_AggrLen;
3051 - ads->ctl17 |= SM(aggrLen, AR_AggrLen);
3052 + if (ah->ent_mode & AR_ENT_OTP_MPSD) {
3053 + u32 ctl17, ndelim;
3054 + /*
3055 + * Add delimiter when using RTS/CTS with aggregation
3056 + * and non enterprise AR9003 card
3057 + */
3058 + ctl17 = ads->ctl17;
3059 + ndelim = MS(ctl17, AR_PadDelim);
3060 +
3061 + if (ndelim < FIRST_DESC_NDELIMS) {
3062 + aggrLen += (FIRST_DESC_NDELIMS - ndelim) * 4;
3063 + ndelim = FIRST_DESC_NDELIMS;
3064 + }
3065 +
3066 + ctl17 &= ~AR_AggrLen;
3067 + ctl17 |= SM(aggrLen, AR_AggrLen);
3068 +
3069 + ctl17 &= ~AR_PadDelim;
3070 + ctl17 |= SM(ndelim, AR_PadDelim);
3071 +
3072 + ads->ctl17 = ctl17;
3073 + } else {
3074 + ads->ctl17 &= ~AR_AggrLen;
3075 + ads->ctl17 |= SM(aggrLen, AR_AggrLen);
3076 + }
3077 }
3078
3079 static void ar9003_hw_set11n_aggr_middle(struct ath_hw *ah, void *ds,
3080 --- a/drivers/net/wireless/ath/ath9k/ar9003_phy.c
3081 +++ b/drivers/net/wireless/ath/ath9k/ar9003_phy.c
3082 @@ -1113,6 +1113,37 @@ static void ar9003_hw_ani_cache_ini_regs
3083 aniState->mrcCCKOff = !ATH9K_ANI_ENABLE_MRC_CCK;
3084 }
3085
3086 +static void ar9003_hw_set_radar_params(struct ath_hw *ah,
3087 + struct ath_hw_radar_conf *conf)
3088 +{
3089 + u32 radar_0 = 0, radar_1 = 0;
3090 +
3091 + if (!conf) {
3092 + REG_CLR_BIT(ah, AR_PHY_RADAR_0, AR_PHY_RADAR_0_ENA);
3093 + return;
3094 + }
3095 +
3096 + radar_0 |= AR_PHY_RADAR_0_ENA | AR_PHY_RADAR_0_FFT_ENA;
3097 + radar_0 |= SM(conf->fir_power, AR_PHY_RADAR_0_FIRPWR);
3098 + radar_0 |= SM(conf->radar_rssi, AR_PHY_RADAR_0_RRSSI);
3099 + radar_0 |= SM(conf->pulse_height, AR_PHY_RADAR_0_HEIGHT);
3100 + radar_0 |= SM(conf->pulse_rssi, AR_PHY_RADAR_0_PRSSI);
3101 + radar_0 |= SM(conf->pulse_inband, AR_PHY_RADAR_0_INBAND);
3102 +
3103 + radar_1 |= AR_PHY_RADAR_1_MAX_RRSSI;
3104 + radar_1 |= AR_PHY_RADAR_1_BLOCK_CHECK;
3105 + radar_1 |= SM(conf->pulse_maxlen, AR_PHY_RADAR_1_MAXLEN);
3106 + radar_1 |= SM(conf->pulse_inband_step, AR_PHY_RADAR_1_RELSTEP_THRESH);
3107 + radar_1 |= SM(conf->radar_inband, AR_PHY_RADAR_1_RELPWR_THRESH);
3108 +
3109 + REG_WRITE(ah, AR_PHY_RADAR_0, radar_0);
3110 + REG_WRITE(ah, AR_PHY_RADAR_1, radar_1);
3111 + if (conf->ext_channel)
3112 + REG_SET_BIT(ah, AR_PHY_RADAR_EXT, AR_PHY_RADAR_EXT_ENA);
3113 + else
3114 + REG_CLR_BIT(ah, AR_PHY_RADAR_EXT, AR_PHY_RADAR_EXT_ENA);
3115 +}
3116 +
3117 void ar9003_hw_attach_phy_ops(struct ath_hw *ah)
3118 {
3119 struct ath_hw_private_ops *priv_ops = ath9k_hw_private_ops(ah);
3120 @@ -1141,6 +1172,7 @@ void ar9003_hw_attach_phy_ops(struct ath
3121 priv_ops->ani_control = ar9003_hw_ani_control;
3122 priv_ops->do_getnf = ar9003_hw_do_getnf;
3123 priv_ops->ani_cache_ini_regs = ar9003_hw_ani_cache_ini_regs;
3124 + priv_ops->set_radar_params = ar9003_hw_set_radar_params;
3125
3126 ar9003_hw_set_nf_limits(ah);
3127 memcpy(ah->nf_regs, ar9300_cca_regs, sizeof(ah->nf_regs));
3128 --- a/drivers/net/wireless/ath/ath9k/ath9k.h
3129 +++ b/drivers/net/wireless/ath/ath9k/ath9k.h
3130 @@ -177,8 +177,8 @@ void ath_descdma_cleanup(struct ath_soft
3131
3132 /* returns delimiter padding required given the packet length */
3133 #define ATH_AGGR_GET_NDELIM(_len) \
3134 - (((((_len) + ATH_AGGR_DELIM_SZ) < ATH_AGGR_MINPLEN) ? \
3135 - (ATH_AGGR_MINPLEN - (_len) - ATH_AGGR_DELIM_SZ) : 0) >> 2)
3136 + (((_len) >= ATH_AGGR_MINPLEN) ? 0 : \
3137 + DIV_ROUND_UP(ATH_AGGR_MINPLEN - (_len), ATH_AGGR_DELIM_SZ))
3138
3139 #define BAW_WITHIN(_start, _bawsz, _seqno) \
3140 ((((_seqno) - (_start)) & 4095) < (_bawsz))
3141 @@ -229,6 +229,7 @@ struct ath_buf_state {
3142 unsigned long bfs_paprd_timestamp;
3143 u32 bfs_keyix;
3144 enum ath9k_key_type bfs_keytype;
3145 + enum ath9k_internal_frame_type bfs_ftype;
3146 };
3147
3148 struct ath_buf {
3149 @@ -712,7 +713,7 @@ void ath9k_ps_restore(struct ath_softc *
3150 void ath9k_set_bssid_mask(struct ieee80211_hw *hw, struct ieee80211_vif *vif);
3151 int ath9k_wiphy_add(struct ath_softc *sc);
3152 int ath9k_wiphy_del(struct ath_wiphy *aphy);
3153 -void ath9k_tx_status(struct ieee80211_hw *hw, struct sk_buff *skb);
3154 +void ath9k_tx_status(struct ieee80211_hw *hw, struct sk_buff *skb, int ftype);
3155 int ath9k_wiphy_pause(struct ath_wiphy *aphy);
3156 int ath9k_wiphy_unpause(struct ath_wiphy *aphy);
3157 int ath9k_wiphy_select(struct ath_wiphy *aphy);
3158 --- a/drivers/net/wireless/ath/ath9k/hw.c
3159 +++ b/drivers/net/wireless/ath/ath9k/hw.c
3160 @@ -1991,6 +1991,9 @@ int ath9k_hw_fill_cap_info(struct ath_hw
3161 if (AR_SREV_9300_20_OR_LATER(ah))
3162 pCap->hw_caps |= ATH9K_HW_CAP_RAC_SUPPORTED;
3163
3164 + if (AR_SREV_9300_20_OR_LATER(ah))
3165 + ah->ent_mode = REG_READ(ah, AR_ENT_OTP);
3166 +
3167 if (AR_SREV_9287_11_OR_LATER(ah) || AR_SREV_9271(ah))
3168 pCap->hw_caps |= ATH9K_HW_CAP_SGI_20;
3169
3170 --- a/drivers/net/wireless/ath/ath9k/hw.h
3171 +++ b/drivers/net/wireless/ath/ath9k/hw.h
3172 @@ -485,6 +485,40 @@ struct ath_hw_antcomb_conf {
3173 };
3174
3175 /**
3176 + * struct ath_hw_radar_conf - radar detection initialization parameters
3177 + *
3178 + * @pulse_inband: threshold for checking the ratio of in-band power
3179 + * to total power for short radar pulses (half dB steps)
3180 + * @pulse_inband_step: threshold for checking an in-band power to total
3181 + * power ratio increase for short radar pulses (half dB steps)
3182 + * @pulse_height: threshold for detecting the beginning of a short
3183 + * radar pulse (dB step)
3184 + * @pulse_rssi: threshold for detecting if a short radar pulse is
3185 + * gone (dB step)
3186 + * @pulse_maxlen: maximum pulse length (0.8 us steps)
3187 + *
3188 + * @radar_rssi: RSSI threshold for starting long radar detection (dB steps)
3189 + * @radar_inband: threshold for checking the ratio of in-band power
3190 + * to total power for long radar pulses (half dB steps)
3191 + * @fir_power: threshold for detecting the end of a long radar pulse (dB)
3192 + *
3193 + * @ext_channel: enable extension channel radar detection
3194 + */
3195 +struct ath_hw_radar_conf {
3196 + unsigned int pulse_inband;
3197 + unsigned int pulse_inband_step;
3198 + unsigned int pulse_height;
3199 + unsigned int pulse_rssi;
3200 + unsigned int pulse_maxlen;
3201 +
3202 + unsigned int radar_rssi;
3203 + unsigned int radar_inband;
3204 + int fir_power;
3205 +
3206 + bool ext_channel;
3207 +};
3208 +
3209 +/**
3210 * struct ath_hw_private_ops - callbacks used internally by hardware code
3211 *
3212 * This structure contains private callbacks designed to only be used internally
3213 @@ -549,6 +583,8 @@ struct ath_hw_private_ops {
3214 bool (*ani_control)(struct ath_hw *ah, enum ath9k_ani_cmd cmd,
3215 int param);
3216 void (*do_getnf)(struct ath_hw *ah, int16_t nfarray[NUM_NF_READINGS]);
3217 + void (*set_radar_params)(struct ath_hw *ah,
3218 + struct ath_hw_radar_conf *conf);
3219
3220 /* ANI */
3221 void (*ani_cache_ini_regs)(struct ath_hw *ah);
3222 @@ -806,6 +842,9 @@ struct ath_hw {
3223 * this register when in sleep states.
3224 */
3225 u32 WARegVal;
3226 +
3227 + /* Enterprise mode cap */
3228 + u32 ent_mode;
3229 };
3230
3231 static inline struct ath_common *ath9k_hw_common(struct ath_hw *ah)
3232 --- a/drivers/net/wireless/ath/ath9k/rc.c
3233 +++ b/drivers/net/wireless/ath/ath9k/rc.c
3234 @@ -1354,23 +1354,7 @@ static void ath_tx_status(void *priv, st
3235 tx_info->status.ampdu_len = 1;
3236 }
3237
3238 - /*
3239 - * If an underrun error is seen assume it as an excessive retry only
3240 - * if max frame trigger level has been reached (2 KB for singel stream,
3241 - * and 4 KB for dual stream). Adjust the long retry as if the frame was
3242 - * tried hw->max_rate_tries times to affect how ratectrl updates PER for
3243 - * the failed rate. In case of congestion on the bus penalizing these
3244 - * type of underruns should help hardware actually transmit new frames
3245 - * successfully by eventually preferring slower rates. This itself
3246 - * should also alleviate congestion on the bus.
3247 - */
3248 - if ((tx_info->pad[0] & ATH_TX_INFO_UNDERRUN) &&
3249 - (sc->sc_ah->tx_trig_level >= ath_rc_priv->tx_triglevel_max)) {
3250 - tx_status = 1;
3251 - is_underrun = 1;
3252 - }
3253 -
3254 - if (tx_info->pad[0] & ATH_TX_INFO_XRETRY)
3255 + if (!(tx_info->flags & IEEE80211_TX_STAT_ACK))
3256 tx_status = 1;
3257
3258 ath_rc_tx_status(sc, ath_rc_priv, tx_info, final_ts_idx, tx_status,
3259 @@ -1596,8 +1580,6 @@ static void *ath_rate_alloc_sta(void *pr
3260 return NULL;
3261 }
3262
3263 - rate_priv->tx_triglevel_max = sc->sc_ah->caps.tx_triglevel_max;
3264 -
3265 return rate_priv;
3266 }
3267
3268 --- a/drivers/net/wireless/ath/ath9k/rc.h
3269 +++ b/drivers/net/wireless/ath/ath9k/rc.h
3270 @@ -215,7 +215,6 @@ struct ath_rate_priv {
3271 u32 per_down_time;
3272 u32 probe_interval;
3273 u32 prev_data_rix;
3274 - u32 tx_triglevel_max;
3275 struct ath_rateset neg_rates;
3276 struct ath_rateset neg_ht_rates;
3277 struct ath_rate_softc *asc;
3278 @@ -225,11 +224,6 @@ struct ath_rate_priv {
3279 struct ath_rc_stats rcstats[RATE_TABLE_SIZE];
3280 };
3281
3282 -#define ATH_TX_INFO_FRAME_TYPE_INTERNAL (1 << 0)
3283 -#define ATH_TX_INFO_FRAME_TYPE_PAUSE (1 << 1)
3284 -#define ATH_TX_INFO_XRETRY (1 << 3)
3285 -#define ATH_TX_INFO_UNDERRUN (1 << 4)
3286 -
3287 enum ath9k_internal_frame_type {
3288 ATH9K_IFT_NOT_INTERNAL,
3289 ATH9K_IFT_PAUSE,
3290 --- a/drivers/net/wireless/ath/ath9k/reg.h
3291 +++ b/drivers/net/wireless/ath/ath9k/reg.h
3292 @@ -1066,6 +1066,9 @@ enum {
3293 #define AR_INTR_PRIO_ASYNC_MASK 0x40c8
3294 #define AR_INTR_PRIO_SYNC_MASK 0x40cc
3295 #define AR_INTR_PRIO_ASYNC_ENABLE 0x40d4
3296 +#define AR_ENT_OTP 0x40d8
3297 +#define AR_ENT_OTP_CHAIN2_DISABLE 0x00020000
3298 +#define AR_ENT_OTP_MPSD 0x00800000
3299
3300 #define AR_RTC_9300_PLL_DIV 0x000003ff
3301 #define AR_RTC_9300_PLL_DIV_S 0
3302 --- a/drivers/net/wireless/ath/ath9k/virtual.c
3303 +++ b/drivers/net/wireless/ath/ath9k/virtual.c
3304 @@ -305,13 +305,12 @@ void ath9k_wiphy_chan_work(struct work_s
3305 * ath9k version of ieee80211_tx_status() for TX frames that are generated
3306 * internally in the driver.
3307 */
3308 -void ath9k_tx_status(struct ieee80211_hw *hw, struct sk_buff *skb)
3309 +void ath9k_tx_status(struct ieee80211_hw *hw, struct sk_buff *skb, int ftype)
3310 {
3311 struct ath_wiphy *aphy = hw->priv;
3312 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
3313
3314 - if ((tx_info->pad[0] & ATH_TX_INFO_FRAME_TYPE_PAUSE) &&
3315 - aphy->state == ATH_WIPHY_PAUSING) {
3316 + if (ftype == ATH9K_IFT_PAUSE && aphy->state == ATH_WIPHY_PAUSING) {
3317 if (!(tx_info->flags & IEEE80211_TX_STAT_ACK)) {
3318 printk(KERN_DEBUG "ath9k: %s: no ACK for pause "
3319 "frame\n", wiphy_name(hw->wiphy));
3320 --- a/drivers/net/wireless/ath/ath9k/xmit.c
3321 +++ b/drivers/net/wireless/ath/ath9k/xmit.c
3322 @@ -48,9 +48,9 @@ static u16 bits_per_symbol[][2] = {
3323
3324 #define IS_HT_RATE(_rate) ((_rate) & 0x80)
3325
3326 -static void ath_tx_send_ht_normal(struct ath_softc *sc, struct ath_txq *txq,
3327 - struct ath_atx_tid *tid,
3328 - struct list_head *bf_head);
3329 +static void ath_tx_send_normal(struct ath_softc *sc, struct ath_txq *txq,
3330 + struct ath_atx_tid *tid,
3331 + struct list_head *bf_head);
3332 static void ath_tx_complete_buf(struct ath_softc *sc, struct ath_buf *bf,
3333 struct ath_txq *txq, struct list_head *bf_q,
3334 struct ath_tx_status *ts, int txok, int sendbar);
3335 @@ -160,7 +160,7 @@ static void ath_tx_flush_tid(struct ath_
3336 ath_tx_update_baw(sc, tid, bf->bf_seqno);
3337 ath_tx_complete_buf(sc, bf, txq, &bf_head, &ts, 0, 0);
3338 } else {
3339 - ath_tx_send_ht_normal(sc, txq, tid, &bf_head);
3340 + ath_tx_send_normal(sc, txq, tid, &bf_head);
3341 }
3342 }
3343
3344 @@ -1322,9 +1322,9 @@ static void ath_tx_send_ampdu(struct ath
3345 ath_tx_txqaddbuf(sc, txctl->txq, bf_head);
3346 }
3347
3348 -static void ath_tx_send_ht_normal(struct ath_softc *sc, struct ath_txq *txq,
3349 - struct ath_atx_tid *tid,
3350 - struct list_head *bf_head)
3351 +static void ath_tx_send_normal(struct ath_softc *sc, struct ath_txq *txq,
3352 + struct ath_atx_tid *tid,
3353 + struct list_head *bf_head)
3354 {
3355 struct ath_buf *bf;
3356
3357 @@ -1332,7 +1332,8 @@ static void ath_tx_send_ht_normal(struct
3358 bf->bf_state.bf_type &= ~BUF_AMPDU;
3359
3360 /* update starting sequence number for subsequent ADDBA request */
3361 - INCR(tid->seq_start, IEEE80211_SEQ_MAX);
3362 + if (tid)
3363 + INCR(tid->seq_start, IEEE80211_SEQ_MAX);
3364
3365 bf->bf_nframes = 1;
3366 bf->bf_lastbf = bf;
3367 @@ -1341,20 +1342,6 @@ static void ath_tx_send_ht_normal(struct
3368 TX_STAT_INC(txq->axq_qnum, queued);
3369 }
3370
3371 -static void ath_tx_send_normal(struct ath_softc *sc, struct ath_txq *txq,
3372 - struct list_head *bf_head)
3373 -{
3374 - struct ath_buf *bf;
3375 -
3376 - bf = list_first_entry(bf_head, struct ath_buf, list);
3377 -
3378 - bf->bf_lastbf = bf;
3379 - bf->bf_nframes = 1;
3380 - ath_buf_set_rate(sc, bf);
3381 - ath_tx_txqaddbuf(sc, txq, bf_head);
3382 - TX_STAT_INC(txq->axq_qnum, queued);
3383 -}
3384 -
3385 static enum ath9k_pkt_type get_hw_packet_type(struct sk_buff *skb)
3386 {
3387 struct ieee80211_hdr *hdr;
3388 @@ -1411,7 +1398,7 @@ static void assign_aggr_tid_seqno(struct
3389 INCR(tid->seq_next, IEEE80211_SEQ_MAX);
3390 }
3391
3392 -static int setup_tx_flags(struct sk_buff *skb, bool use_ldpc)
3393 +static int setup_tx_flags(struct sk_buff *skb)
3394 {
3395 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
3396 int flags = 0;
3397 @@ -1422,7 +1409,7 @@ static int setup_tx_flags(struct sk_buff
3398 if (tx_info->flags & IEEE80211_TX_CTL_NO_ACK)
3399 flags |= ATH9K_TXDESC_NOACK;
3400
3401 - if (use_ldpc)
3402 + if (tx_info->flags & IEEE80211_TX_CTL_LDPC)
3403 flags |= ATH9K_TXDESC_LDPC;
3404
3405 return flags;
3406 @@ -1567,30 +1554,25 @@ static void ath_buf_set_rate(struct ath_
3407 ath9k_hw_set11n_burstduration(sc->sc_ah, bf->bf_desc, 8192);
3408 }
3409
3410 -static int ath_tx_setup_buffer(struct ieee80211_hw *hw, struct ath_buf *bf,
3411 - struct sk_buff *skb,
3412 - struct ath_tx_control *txctl)
3413 +static struct ath_buf *ath_tx_setup_buffer(struct ieee80211_hw *hw,
3414 + struct sk_buff *skb)
3415 {
3416 struct ath_wiphy *aphy = hw->priv;
3417 struct ath_softc *sc = aphy->sc;
3418 + struct ath_common *common = ath9k_hw_common(sc->sc_ah);
3419 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
3420 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
3421 + struct ath_buf *bf;
3422 int hdrlen;
3423 __le16 fc;
3424 int padpos, padsize;
3425 - bool use_ldpc = false;
3426
3427 - tx_info->pad[0] = 0;
3428 - switch (txctl->frame_type) {
3429 - case ATH9K_IFT_NOT_INTERNAL:
3430 - break;
3431 - case ATH9K_IFT_PAUSE:
3432 - tx_info->pad[0] |= ATH_TX_INFO_FRAME_TYPE_PAUSE;
3433 - /* fall through */
3434 - case ATH9K_IFT_UNPAUSE:
3435 - tx_info->pad[0] |= ATH_TX_INFO_FRAME_TYPE_INTERNAL;
3436 - break;
3437 + bf = ath_tx_get_buffer(sc);
3438 + if (!bf) {
3439 + ath_print(common, ATH_DBG_XMIT, "TX buffers are full\n");
3440 + return NULL;
3441 }
3442 +
3443 hdrlen = ieee80211_get_hdrlen_from_skb(skb);
3444 fc = hdr->frame_control;
3445
3446 @@ -1605,16 +1587,13 @@ static int ath_tx_setup_buffer(struct ie
3447 bf->bf_frmlen -= padsize;
3448 }
3449
3450 - if (!txctl->paprd && conf_is_ht(&hw->conf)) {
3451 + if (ieee80211_is_data_qos(fc) && conf_is_ht(&hw->conf)) {
3452 bf->bf_state.bf_type |= BUF_HT;
3453 - if (tx_info->flags & IEEE80211_TX_CTL_LDPC)
3454 - use_ldpc = true;
3455 + if (sc->sc_flags & SC_OP_TXAGGR)
3456 + assign_aggr_tid_seqno(skb, bf);
3457 }
3458
3459 - bf->bf_state.bfs_paprd = txctl->paprd;
3460 - if (txctl->paprd)
3461 - bf->bf_state.bfs_paprd_timestamp = jiffies;
3462 - bf->bf_flags = setup_tx_flags(skb, use_ldpc);
3463 + bf->bf_flags = setup_tx_flags(skb);
3464
3465 bf->bf_keytype = ath9k_cmn_get_hw_crypto_keytype(skb);
3466 if (bf->bf_keytype != ATH9K_KEY_TYPE_CLEAR) {
3467 @@ -1624,10 +1603,6 @@ static int ath_tx_setup_buffer(struct ie
3468 bf->bf_keyix = ATH9K_TXKEYIX_INVALID;
3469 }
3470
3471 - if (ieee80211_is_data_qos(fc) && bf_isht(bf) &&
3472 - (sc->sc_flags & SC_OP_TXAGGR))
3473 - assign_aggr_tid_seqno(skb, bf);
3474 -
3475 bf->bf_mpdu = skb;
3476
3477 bf->bf_buf_addr = dma_map_single(sc->dev, skb->data,
3478 @@ -1637,12 +1612,13 @@ static int ath_tx_setup_buffer(struct ie
3479 bf->bf_buf_addr = 0;
3480 ath_print(ath9k_hw_common(sc->sc_ah), ATH_DBG_FATAL,
3481 "dma_mapping_error() on TX\n");
3482 - return -ENOMEM;
3483 + ath_tx_return_buffer(sc, bf);
3484 + return NULL;
3485 }
3486
3487 bf->bf_tx_aborted = false;
3488
3489 - return 0;
3490 + return bf;
3491 }
3492
3493 /* FIXME: tx power */
3494 @@ -1690,11 +1666,6 @@ static void ath_tx_start_dma(struct ath_
3495 an = (struct ath_node *)tx_info->control.sta->drv_priv;
3496 tid = ATH_AN_2_TID(an, bf->bf_tidno);
3497
3498 - if (!ieee80211_is_data_qos(fc)) {
3499 - ath_tx_send_normal(sc, txctl->txq, &bf_head);
3500 - goto tx_done;
3501 - }
3502 -
3503 WARN_ON(tid->ac->txq != txctl->txq);
3504 if (tx_info->flags & IEEE80211_TX_CTL_AMPDU) {
3505 /*
3506 @@ -1707,14 +1678,18 @@ static void ath_tx_start_dma(struct ath_
3507 * Send this frame as regular when ADDBA
3508 * exchange is neither complete nor pending.
3509 */
3510 - ath_tx_send_ht_normal(sc, txctl->txq,
3511 - tid, &bf_head);
3512 + ath_tx_send_normal(sc, txctl->txq, tid, &bf_head);
3513 }
3514 } else {
3515 - ath_tx_send_normal(sc, txctl->txq, &bf_head);
3516 + bf->bf_state.bfs_ftype = txctl->frame_type;
3517 + bf->bf_state.bfs_paprd = txctl->paprd;
3518 +
3519 + if (txctl->paprd)
3520 + bf->bf_state.bfs_paprd_timestamp = jiffies;
3521 +
3522 + ath_tx_send_normal(sc, txctl->txq, NULL, &bf_head);
3523 }
3524
3525 -tx_done:
3526 spin_unlock_bh(&txctl->txq->axq_lock);
3527 }
3528
3529 @@ -1724,39 +1699,15 @@ int ath_tx_start(struct ieee80211_hw *hw
3530 {
3531 struct ath_wiphy *aphy = hw->priv;
3532 struct ath_softc *sc = aphy->sc;
3533 - struct ath_common *common = ath9k_hw_common(sc->sc_ah);
3534 struct ath_txq *txq = txctl->txq;
3535 struct ath_buf *bf;
3536 - int q, r;
3537 + int q;
3538
3539 - bf = ath_tx_get_buffer(sc);
3540 - if (!bf) {
3541 - ath_print(common, ATH_DBG_XMIT, "TX buffers are full\n");
3542 - return -1;
3543 - }
3544 + bf = ath_tx_setup_buffer(hw, skb);
3545 + if (unlikely(!bf))
3546 + return -ENOMEM;
3547
3548 q = skb_get_queue_mapping(skb);
3549 - r = ath_tx_setup_buffer(hw, bf, skb, txctl);
3550 - if (unlikely(r)) {
3551 - ath_print(common, ATH_DBG_FATAL, "TX mem alloc failure\n");
3552 -
3553 - /* upon ath_tx_processq() this TX queue will be resumed, we
3554 - * guarantee this will happen by knowing beforehand that
3555 - * we will at least have to run TX completionon one buffer
3556 - * on the queue */
3557 - spin_lock_bh(&txq->axq_lock);
3558 - if (txq == sc->tx.txq_map[q] && !txq->stopped &&
3559 - txq->axq_depth > 1) {
3560 - ath_mac80211_stop_queue(sc, q);
3561 - txq->stopped = 1;
3562 - }
3563 - spin_unlock_bh(&txq->axq_lock);
3564 -
3565 - ath_tx_return_buffer(sc, bf);
3566 -
3567 - return r;
3568 - }
3569 -
3570 spin_lock_bh(&txq->axq_lock);
3571 if (txq == sc->tx.txq_map[q] &&
3572 ++txq->pending_frames > ATH_MAX_QDEPTH && !txq->stopped) {
3573 @@ -1828,7 +1779,7 @@ exit:
3574 /*****************/
3575
3576 static void ath_tx_complete(struct ath_softc *sc, struct sk_buff *skb,
3577 - struct ath_wiphy *aphy, int tx_flags,
3578 + struct ath_wiphy *aphy, int tx_flags, int ftype,
3579 struct ath_txq *txq)
3580 {
3581 struct ieee80211_hw *hw = sc->hw;
3582 @@ -1872,8 +1823,8 @@ static void ath_tx_complete(struct ath_s
3583 PS_WAIT_FOR_TX_ACK));
3584 }
3585
3586 - if (unlikely(tx_info->pad[0] & ATH_TX_INFO_FRAME_TYPE_INTERNAL))
3587 - ath9k_tx_status(hw, skb);
3588 + if (unlikely(ftype))
3589 + ath9k_tx_status(hw, skb, ftype);
3590 else {
3591 q = skb_get_queue_mapping(skb);
3592 if (txq == sc->tx.txq_map[q]) {
3593 @@ -1917,7 +1868,8 @@ static void ath_tx_complete_buf(struct a
3594 complete(&sc->paprd_complete);
3595 } else {
3596 ath_debug_stat_tx(sc, bf, ts);
3597 - ath_tx_complete(sc, skb, bf->aphy, tx_flags, txq);
3598 + ath_tx_complete(sc, skb, bf->aphy, tx_flags,
3599 + bf->bf_state.bfs_ftype, txq);
3600 }
3601 /* At this point, skb (bf->bf_mpdu) is consumed...make sure we don't
3602 * accidentally reference it later.
3603 @@ -1968,6 +1920,8 @@ static void ath_tx_rc_status(struct ath_
3604 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
3605 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
3606 struct ieee80211_hw *hw = bf->aphy->hw;
3607 + struct ath_softc *sc = bf->aphy->sc;
3608 + struct ath_hw *ah = sc->sc_ah;
3609 u8 i, tx_rateindex;
3610
3611 if (txok)
3612 @@ -1989,14 +1943,24 @@ static void ath_tx_rc_status(struct ath_
3613
3614 if ((ts->ts_status & ATH9K_TXERR_FILT) == 0 &&
3615 (bf->bf_flags & ATH9K_TXDESC_NOACK) == 0 && update_rc) {
3616 - if (ieee80211_is_data(hdr->frame_control)) {
3617 - if (ts->ts_flags &
3618 - (ATH9K_TX_DATA_UNDERRUN | ATH9K_TX_DELIM_UNDERRUN))
3619 - tx_info->pad[0] |= ATH_TX_INFO_UNDERRUN;
3620 - if ((ts->ts_status & ATH9K_TXERR_XRETRY) ||
3621 - (ts->ts_status & ATH9K_TXERR_FIFO))
3622 - tx_info->pad[0] |= ATH_TX_INFO_XRETRY;
3623 - }
3624 + /*
3625 + * If an underrun error is seen assume it as an excessive
3626 + * retry only if max frame trigger level has been reached
3627 + * (2 KB for single stream, and 4 KB for dual stream).
3628 + * Adjust the long retry as if the frame was tried
3629 + * hw->max_rate_tries times to affect how rate control updates
3630 + * PER for the failed rate.
3631 + * In case of congestion on the bus penalizing this type of
3632 + * underruns should help hardware actually transmit new frames
3633 + * successfully by eventually preferring slower rates.
3634 + * This itself should also alleviate congestion on the bus.
3635 + */
3636 + if (ieee80211_is_data(hdr->frame_control) &&
3637 + (ts->ts_flags & (ATH9K_TX_DATA_UNDERRUN |
3638 + ATH9K_TX_DELIM_UNDERRUN)) &&
3639 + ah->tx_trig_level >= sc->sc_ah->caps.tx_triglevel_max)
3640 + tx_info->status.rates[tx_rateindex].count =
3641 + hw->max_rate_tries;
3642 }
3643
3644 for (i = tx_rateindex + 1; i < hw->max_rates; i++) {
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