target/linux/rb532/files/arch/mips/rb500/devices.c

   1 /*
   2  *  RouterBoard 500 Platform devices
   3  *
   4  *  Copyright (C) 2006 Felix Fietkau <nbd@openwrt.org>
   5  *  Copyright (C) 2007 Florian Fainelli <florian@openwrt.org>
   6  *
   7  *  This program is free software; you can redistribute it and/or modify
   8  *  it under the terms of the GNU General Public License as published by
   9  *  the Free Software Foundation; either version 2 of the License, or
  10  *  (at your option) any later version.
  11  *
  12  *  This program is distributed in the hope that it will be useful,
  13  *  but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  15  *  GNU General Public License for more details.
  16  */
  17 #include <linux/kernel.h>
  18 #include <linux/init.h>
  19 #include <linux/ctype.h>
  20 #include <linux/string.h>
  21 #include <linux/platform_device.h>
  22 #include <linux/mtd/nand.h>
  23 #include <linux/mtd/mtd.h>
  24 #include <linux/mtd/partitions.h>
  25
  26 #include <asm/bootinfo.h>
  27
  28 #include <asm/rc32434/rc32434.h>
  29 #include <asm/rc32434/dma.h>
  30 #include <asm/rc32434/dma_v.h>
  31 #include <asm/rc32434/eth.h>
  32 #include <asm/rc32434/rb.h>
  33
  34 #define ETH0_DMA_RX_IRQ         GROUP1_IRQ_BASE + 0
  35 #define ETH0_DMA_TX_IRQ         GROUP1_IRQ_BASE + 1
  36 #define ETH0_RX_OVR_IRQ         GROUP3_IRQ_BASE + 9
  37 #define ETH0_TX_UND_IRQ         GROUP3_IRQ_BASE + 10
  38
  39 #define ETH0_RX_DMA_ADDR  (DMA0_PhysicalAddress + 0*DMA_CHAN_OFFSET)
  40 #define ETH0_TX_DMA_ADDR  (DMA0_PhysicalAddress + 1*DMA_CHAN_OFFSET)
  41
  42 /* NAND definitions */
  43 #define MEM32(x) *((volatile unsigned *) (x))
  44
  45 #define GPIO_RDY (1 << 0x08)
  46 #define GPIO_WPX (1 << 0x09)
  47 #define GPIO_ALE (1 << 0x0a)
  48 #define GPIO_CLE (1 << 0x0b)
  49
  50 extern char* board_type;
  51
  52 static struct resource korina_dev0_res[] = {
  53         {
  54                 .name = "korina_regs",
  55                 .start = ETH0_PhysicalAddress,
  56                 .end = ETH0_PhysicalAddress + sizeof(ETH_t),
  57                 .flags = IORESOURCE_MEM,
  58          }, {
  59                 .name = "korina_rx",
  60                 .start = ETH0_DMA_RX_IRQ,
  61                 .end = ETH0_DMA_RX_IRQ,
  62                 .flags = IORESOURCE_IRQ
  63         }, {
  64                 .name = "korina_tx",
  65                 .start = ETH0_DMA_TX_IRQ,
  66                 .end = ETH0_DMA_TX_IRQ,
  67                 .flags = IORESOURCE_IRQ
  68         }, {
  69                 .name = "korina_ovr",
  70                 .start = ETH0_RX_OVR_IRQ,
  71                 .end = ETH0_RX_OVR_IRQ,
  72                 .flags = IORESOURCE_IRQ
  73         }, {
  74                 .name = "korina_und",
  75                 .start = ETH0_TX_UND_IRQ,
  76                 .end = ETH0_TX_UND_IRQ,
  77                 .flags = IORESOURCE_IRQ
  78         }, {
  79                 .name = "korina_dma_rx",
  80                 .start = ETH0_RX_DMA_ADDR,
  81                 .end = ETH0_RX_DMA_ADDR + DMA_CHAN_OFFSET - 1,
  82                 .flags = IORESOURCE_MEM,
  83          }, {
  84                 .name = "korina_dma_tx",
  85                 .start = ETH0_TX_DMA_ADDR,
  86                 .end = ETH0_TX_DMA_ADDR + DMA_CHAN_OFFSET - 1,
  87                 .flags = IORESOURCE_MEM,
  88          }
  89 };
  90
  91 static struct korina_device korina_dev0_data = {
  92         .name = "korina0",
  93         .mac = {0xde, 0xca, 0xff, 0xc0, 0xff, 0xee}
  94 };
  95
  96 static struct platform_device korina_dev0 = {
  97         .id = 0,
  98         .name = "korina",
  99         .dev.platform_data = &korina_dev0_data,
 100         .resource = korina_dev0_res,
 101         .num_resources = ARRAY_SIZE(korina_dev0_res),
 102 };
 103
 104 #define CF_GPIO_NUM 13
 105
 106 static struct resource cf_slot0_res[] = {
 107         {
 108                 .name = "cf_membase",
 109                 .flags = IORESOURCE_MEM
 110         }, {
 111                 .name = "cf_irq",
 112                 .start = (8 + 4 * 32 + CF_GPIO_NUM),    /* 149 */
 113                 .end = (8 + 4 * 32 + CF_GPIO_NUM),
 114                 .flags = IORESOURCE_IRQ
 115         }
 116 };
 117
 118 static struct cf_device cf_slot0_data = {
 119         .gpio_pin = 13
 120 };
 121
 122 static struct platform_device cf_slot0 = {
 123         .id = 0,
 124         .name = "rb500-cf",
 125         .dev.platform_data = &cf_slot0_data,
 126         .resource = cf_slot0_res,
 127         .num_resources = ARRAY_SIZE(cf_slot0_res),
 128 };
 129
 130 /* Resources and device for NAND.  There is no data needed and no irqs, so just define the memory used. */
 131 int rb500_dev_ready(struct mtd_info *mtd)
 132 {
 133         return MEM32(IDT434_REG_BASE + GPIOD) & GPIO_RDY;
 134 }
 135
 136 void rb500_cmd_ctrl(struct mtd_info *mtd, int cmd, unsigned int ctrl)
 137 {
 138         struct nand_chip *chip = mtd->priv;
 139         unsigned char orbits, nandbits;
 140
 141         if (ctrl & NAND_CTRL_CHANGE) {
 142
 143                 orbits = (ctrl & NAND_CLE) << 1;
 144                 orbits |= (ctrl & NAND_ALE) >> 1;
 145
 146                 nandbits = (~ctrl & NAND_CLE) << 1;
 147                 nandbits |= (~ctrl & NAND_ALE) >> 1;
 148
 149                 changeLatchU5(orbits, nandbits);
 150         }
 151         if (cmd != NAND_CMD_NONE)
 152                 writeb(cmd, chip->IO_ADDR_W);
 153 }
 154
 155 static struct resource nand_slot0_res[] = {
 156         [0] = {
 157                 .name = "nand_membase",
 158                 .flags = IORESOURCE_MEM
 159         }
 160 };
 161
 162 struct platform_nand_data rb500_nand_data = {
 163         .ctrl.dev_ready = rb500_dev_ready,
 164         .ctrl.cmd_ctrl  = rb500_cmd_ctrl,
 165 };
 166
 167 static struct platform_device nand_slot0 = {
 168         .name = "gen_nand",
 169         .id = -1,
 170         .resource = nand_slot0_res,
 171         .num_resources = ARRAY_SIZE(nand_slot0_res),
 172         .dev.platform_data = &rb500_nand_data,
 173 };
 174
 175 static struct mtd_partition rb500_partition_info[] = {
 176         {
 177                 .name = "Routerboard NAND boot",
 178                 .offset = 0,
 179                 .size = 4 * 1024 * 1024,
 180         }, {
 181                 .name = "rootfs",
 182                 .offset = MTDPART_OFS_NXTBLK,
 183                 .size = MTDPART_SIZ_FULL,
 184         }
 185 };
 186
 187
 188 static struct platform_device *rb500_devs[] = {
 189         &korina_dev0,
 190         &nand_slot0,
 191         &cf_slot0
 192 };
 193
 194 static void __init parse_mac_addr(char *macstr)
 195 {
 196         int i, j;
 197         unsigned char result, value;
 198
 199         for (i = 0; i < 6; i++) {
 200                 result = 0;
 201
 202                 if (i != 5 && *(macstr + 2) != ':')
 203                         return;
 204
 205                 for (j = 0; j < 2; j++) {
 206                         if (isxdigit(*macstr)
 207                             && (value =
 208                                 isdigit(*macstr) ? *macstr -
 209                                 '0' : toupper(*macstr) - 'A' + 10) < 16) {
 210                                 result = result * 16 + value;
 211                                 macstr++;
 212                         } else
 213                                 return;
 214                 }
 215
 216                 macstr++;
 217                 korina_dev0_data.mac[i] = result;
 218         }
 219 }
 220
 221
 222 /* DEVICE CONTROLLER 1 */
 223 #define CFG_DC_DEV1 (void*)0xb8010010
 224 #define CFG_DC_DEV2 (void*)0xb8010020
 225 #define CFG_DC_DEVBASE    0x0
 226 #define CFG_DC_DEVMASK    0x4
 227 #define CFG_DC_DEVC       0x8
 228 #define CFG_DC_DEVTC      0xC
 229
 230 /* NAND definitions */
 231 #define NAND_CHIP_DELAY 25
 232
 233 static void __init rb500_nand_setup(void)
 234 {
 235         switch (mips_machtype) {
 236         case MACH_MIKROTIK_RB532A:
 237                 changeLatchU5(LO_FOFF | LO_CEX, LO_ULED | LO_ALE | LO_CLE | LO_WPX);
 238                 break;
 239         default:
 240                 changeLatchU5(LO_WPX | LO_FOFF | LO_CEX, LO_ULED | LO_ALE | LO_CLE);
 241                 break;
 242         }
 243
 244         /* Setup NAND specific settings */
 245         rb500_nand_data.chip.nr_chips = 1;
 246         rb500_nand_data.chip.nr_partitions = ARRAY_SIZE(rb500_partition_info);
 247         rb500_nand_data.chip.partitions = rb500_partition_info;
 248         rb500_nand_data.chip.chip_delay = NAND_CHIP_DELAY;
 249         rb500_nand_data.chip.options = NAND_NO_AUTOINCR;
 250 }
 251
 252
 253 static int __init plat_setup_devices(void)
 254 {
 255         /* Look for the CF card reader */
 256         if (!readl(CFG_DC_DEV1 + CFG_DC_DEVMASK))
 257                 rb500_devs[1] = NULL;
 258         else {
 259                 cf_slot0_res[0].start =
 260                     readl(CFG_DC_DEV1 + CFG_DC_DEVBASE);
 261                 cf_slot0_res[0].end = cf_slot0_res[0].start + 0x1000;
 262         }
 263
 264         /* Read the NAND resources from the device controller */
 265         nand_slot0_res[0].start = readl(CFG_DC_DEV2 + CFG_DC_DEVBASE);
 266         nand_slot0_res[0].end = nand_slot0_res[0].start + 0x1000;
 267
 268         /* Initialise the NAND device */
 269         rb500_nand_setup();
 270
 271         return platform_add_devices(rb500_devs, ARRAY_SIZE(rb500_devs));
 272 }
 273
 274 static int __init setup_kmac(char *s)
 275 {
 276         printk("korina mac = %s\n", s);
 277         parse_mac_addr(s);
 278         return 0;
 279 }
 280
 281 __setup("kmac=", setup_kmac);
 282
 283 arch_initcall(plat_setup_devices);