package/ltq-dsl/src/ifxmips_atm_core.h

   1 /******************************************************************************
   2 **
   3 ** FILE NAME    : ifxmips_atm_core.h
   4 ** PROJECT      : UEIP
   5 ** MODULES      : ATM
   6 **
   7 ** DATE         : 7 Jul 2009
   8 ** AUTHOR       : Xu Liang
   9 ** DESCRIPTION  : ATM driver header file (core functions)
  10 ** COPYRIGHT    :       Copyright (c) 2006
  11 **                      Infineon Technologies AG
  12 **                      Am Campeon 1-12, 85579 Neubiberg, Germany
  13 **
  14 **    This program is free software; you can redistribute it and/or modify
  15 **    it under the terms of the GNU General Public License as published by
  16 **    the Free Software Foundation; either version 2 of the License, or
  17 **    (at your option) any later version.
  18 **
  19 ** HISTORY
  20 ** $Date        $Author         $Comment
  21 ** 17 JUN 2009  Xu Liang        Init Version
  22 *******************************************************************************/
  23
  24 #ifndef IFXMIPS_ATM_CORE_H
  25 #define IFXMIPS_ATM_CORE_H
  26
  27
  28 #include "ifxmips_compat.h"
  29 #include "ifx_atm.h"
  30 #include "ifxmips_atm_ppe_common.h"
  31 #include "ifxmips_atm_fw_regs_common.h"
  32
  33
  34
  35 /*
  36  * ####################################
  37  *              Definition
  38  * ####################################
  39  */
  40
  41 /*
  42  *  Compile Options
  43  */
  44
  45 #define ENABLE_DEBUG                    1
  46
  47 #define ENABLE_ASSERT                   1
  48
  49 #define INLINE
  50
  51 #define DEBUG_DUMP_SKB                  1
  52
  53 #define DEBUG_QOS                       1
  54
  55 #define DISABLE_QOS_WORKAROUND          0
  56
  57 #define ENABLE_DBG_PROC                 1
  58
  59 #define ENABLE_FW_PROC                  1
  60
  61 #ifdef CONFIG_IFX_ATM_TASKLET
  62   #define ENABLE_TASKLET                1
  63 #endif
  64
  65 #ifdef CONFIG_IFX_ATM_RETX
  66   #define ENABLE_ATM_RETX               1
  67 #endif
  68
  69 #if defined(CONFIG_DSL_MEI_CPE_DRV) && !defined(CONFIG_IFXMIPS_DSL_CPE_MEI)
  70   #define CONFIG_IFXMIPS_DSL_CPE_MEI    1
  71 #endif
  72
  73 /*
  74  *  Debug/Assert/Error Message
  75  */
  76
  77 #define DBG_ENABLE_MASK_ERR             (1 << 0)
  78 #define DBG_ENABLE_MASK_DEBUG_PRINT     (1 << 1)
  79 #define DBG_ENABLE_MASK_ASSERT          (1 << 2)
  80 #define DBG_ENABLE_MASK_DUMP_SKB_RX     (1 << 8)
  81 #define DBG_ENABLE_MASK_DUMP_SKB_TX     (1 << 9)
  82 #define DBG_ENABLE_MASK_DUMP_QOS        (1 << 10)
  83 #define DBG_ENABLE_MASK_DUMP_INIT       (1 << 11)
  84 #define DBG_ENABLE_MASK_MAC_SWAP        (1 << 12)
  85 #define DBG_ENABLE_MASK_ALL             (DBG_ENABLE_MASK_ERR | DBG_ENABLE_MASK_DEBUG_PRINT | DBG_ENABLE_MASK_ASSERT | DBG_ENABLE_MASK_DUMP_SKB_RX | DBG_ENABLE_MASK_DUMP_SKB_TX | DBG_ENABLE_MASK_DUMP_QOS | DBG_ENABLE_MASK_DUMP_INIT | DBG_ENABLE_MASK_MAC_SWAP)
  86
  87 #define err(format, arg...)             do { if ( (ifx_atm_dbg_enable & DBG_ENABLE_MASK_ERR) ) printk(KERN_ERR __FILE__ ":%d:%s: " format "\n", __LINE__, __FUNCTION__, ##arg); } while ( 0 )
  88
  89 #if defined(ENABLE_DEBUG) && ENABLE_DEBUG
  90   #undef  dbg
  91   #define dbg(format, arg...)           do { if ( (ifx_atm_dbg_enable & DBG_ENABLE_MASK_DEBUG_PRINT) ) printk(KERN_WARNING __FILE__ ":%d:%s: " format "\n", __LINE__, __FUNCTION__, ##arg); } while ( 0 )
  92 #else
  93   #if !defined(dbg)
  94     #define dbg(format, arg...)
  95   #endif
  96 #endif
  97
  98 #if defined(ENABLE_ASSERT) && ENABLE_ASSERT
  99   #define ASSERT(cond, format, arg...)  do { if ( (ifx_atm_dbg_enable & DBG_ENABLE_MASK_ASSERT) && !(cond) ) printk(KERN_ERR __FILE__ ":%d:%s: " format "\n", __LINE__, __FUNCTION__, ##arg); } while ( 0 )
 100 #else
 101   #define ASSERT(cond, format, arg...)
 102 #endif
 103
 104
 105 /*
 106  *  Constants
 107  */
 108 #define DEFAULT_TX_LINK_RATE            3200    //  in cells
 109
 110 /*
 111  *  ATM Port, QSB Queue, DMA RX/TX Channel Parameters
 112  */
 113 #define ATM_PORT_NUMBER                 2
 114 #define MAX_QUEUE_NUMBER                16
 115 #define OAM_RX_QUEUE                    15
 116 #define QSB_RESERVE_TX_QUEUE            0
 117 #define FIRST_QSB_QID                   1
 118 #define MAX_PVC_NUMBER                  (MAX_QUEUE_NUMBER - FIRST_QSB_QID)
 119 #define MAX_RX_DMA_CHANNEL_NUMBER       8
 120 #define MAX_TX_DMA_CHANNEL_NUMBER       16
 121 #define DATA_BUFFER_ALIGNMENT           EMA_ALIGNMENT
 122 #define DESC_ALIGNMENT                  8
 123 #define DEFAULT_RX_HUNT_BITTH           4
 124
 125 /*
 126  *  RX DMA Channel Allocation
 127  */
 128 #define RX_DMA_CH_OAM                   0
 129 #define RX_DMA_CH_AAL                   1
 130 #define RX_DMA_CH_TOTAL                 2
 131 #define RX_DMA_CH_OAM_DESC_LEN          32
 132 #define RX_DMA_CH_OAM_BUF_SIZE          (CELL_SIZE & ~15)
 133 #define RX_DMA_CH_AAL_BUF_SIZE          (2048 - 48)
 134
 135 /*
 136  *  OAM Constants
 137  */
 138 #define OAM_HTU_ENTRY_NUMBER            3
 139 #define OAM_F4_SEG_HTU_ENTRY            0
 140 #define OAM_F4_TOT_HTU_ENTRY            1
 141 #define OAM_F5_HTU_ENTRY                2
 142 #define OAM_F4_CELL_ID                  0
 143 #define OAM_F5_CELL_ID                  15
 144 #if defined(ENABLE_ATM_RETX) && ENABLE_ATM_RETX
 145   #undef  OAM_HTU_ENTRY_NUMBER
 146   #define OAM_HTU_ENTRY_NUMBER          4
 147   #define OAM_ARQ_HTU_ENTRY             3
 148 #endif
 149
 150 /*
 151  *  RX Frame Definitions
 152  */
 153 #define MAX_RX_PACKET_ALIGN_BYTES       3
 154 #define MAX_RX_PACKET_PADDING_BYTES     3
 155 #define RX_INBAND_TRAILER_LENGTH        8
 156 #define MAX_RX_FRAME_EXTRA_BYTES        (RX_INBAND_TRAILER_LENGTH + MAX_RX_PACKET_ALIGN_BYTES + MAX_RX_PACKET_PADDING_BYTES)
 157
 158 /*
 159  *  TX Frame Definitions
 160  */
 161 #define MAX_TX_HEADER_ALIGN_BYTES       12
 162 #define MAX_TX_PACKET_ALIGN_BYTES       3
 163 #define MAX_TX_PACKET_PADDING_BYTES     3
 164 #define TX_INBAND_HEADER_LENGTH         8
 165 #define MAX_TX_FRAME_EXTRA_BYTES        (TX_INBAND_HEADER_LENGTH + MAX_TX_HEADER_ALIGN_BYTES + MAX_TX_PACKET_ALIGN_BYTES + MAX_TX_PACKET_PADDING_BYTES)
 166
 167 /*
 168  *  Cell Constant
 169  */
 170 #define CELL_SIZE                       ATM_AAL0_SDU
 171
 172 /*
 173  *  ReTX Constant
 174  */
 175 #if defined(ENABLE_ATM_RETX) && ENABLE_ATM_RETX
 176   #define RETX_PLAYOUT_BUFFER_ORDER     6
 177   #define RETX_PLAYOUT_BUFFER_SIZE      (PAGE_SIZE * (1 << RETX_PLAYOUT_BUFFER_ORDER))
 178   #define RETX_PLAYOUT_FW_BUFF_SIZE     (RETX_PLAYOUT_BUFFER_SIZE / (32 * 56 /* cell size */))
 179   #define RETX_POLLING_INTERVAL         (HZ / 100 > 0 ? HZ / 100 : 1)
 180 #endif
 181
 182
 183
 184 /*
 185  * ####################################
 186  *              Data Type
 187  * ####################################
 188  */
 189
 190 typedef struct {
 191     unsigned int            h;
 192     unsigned int            l;
 193 } ppe_u64_t;
 194
 195 struct port {
 196     unsigned int            tx_max_cell_rate;
 197     unsigned int            tx_current_cell_rate;
 198
 199     struct atm_dev         *dev;
 200 };
 201
 202 struct connection {
 203     struct atm_vcc         *vcc;
 204
 205     volatile struct tx_descriptor
 206                            *tx_desc;
 207     unsigned int            tx_desc_pos;
 208     struct sk_buff        **tx_skb;
 209
 210     unsigned int            aal5_vcc_crc_err;       /*  number of packets with CRC error        */
 211     unsigned int            aal5_vcc_oversize_sdu;  /*  number of packets with oversize error   */
 212
 213     unsigned int            port;
 214 };
 215
 216 struct atm_priv_data {
 217     unsigned long           conn_table;
 218     struct connection       conn[MAX_PVC_NUMBER];
 219
 220     volatile struct rx_descriptor
 221                            *aal_desc;
 222     unsigned int            aal_desc_pos;
 223
 224     volatile struct rx_descriptor
 225                            *oam_desc;
 226     unsigned char          *oam_buf;
 227     unsigned int            oam_desc_pos;
 228
 229     struct port             port[ATM_PORT_NUMBER];
 230
 231     unsigned int            wrx_pdu;        /*  successfully received AAL5 packet       */
 232     unsigned int            wrx_drop_pdu;   /*  AAL5 packet dropped by driver on RX     */
 233     unsigned int            wtx_pdu;        /*  successfully tranmitted AAL5 packet     */
 234     unsigned int            wtx_err_pdu;    /*  error AAL5 packet                       */
 235     unsigned int            wtx_drop_pdu;   /*  AAL5 packet dropped by driver on TX     */
 236
 237     ppe_u64_t               wrx_total_byte;
 238     ppe_u64_t               wtx_total_byte;
 239     unsigned int            prev_wrx_total_byte;
 240     unsigned int            prev_wtx_total_byte;
 241
 242     void                   *aal_desc_base;
 243     void                   *oam_desc_base;
 244     void                   *oam_buf_base;
 245     void                   *tx_desc_base;
 246     void                   *tx_skb_base;
 247 };
 248
 249
 250
 251 /*
 252  * ####################################
 253  *             Declaration
 254  * ####################################
 255  */
 256
 257 extern unsigned int ifx_atm_dbg_enable;
 258
 259 extern void ifx_atm_get_fw_ver(unsigned int *major, unsigned int *minor);
 260
 261 extern void ifx_atm_init_chip(void);
 262 extern void ifx_atm_uninit_chip(void);
 263
 264 extern int ifx_pp32_start(int pp32);
 265 extern void ifx_pp32_stop(int pp32);
 266
 267 extern void ifx_reset_ppe(void);
 268
 269
 270
 271 #endif  //  IFXMIPS_ATM_CORE_H