package/ltq-dsl/src/ifxmips_atm_ppe_vr9.h

   1 /******************************************************************************
   2 **
   3 ** FILE NAME    : ifxmips_atm_ppe_vr9.h
   4 ** PROJECT      : UEIP
   5 ** MODULES      : ATM (ADSL)
   6 **
   7 ** DATE         : 1 AUG 2005
   8 ** AUTHOR       : Xu Liang
   9 ** DESCRIPTION  : ATM Driver (PPE Registers)
  10 ** COPYRIGHT    :       Copyright (c) 2006
  11 **                      Infineon Technologies AG
  12 **                      Am Campeon 1-12, 85579 Neubiberg, Germany
  13 **
  14 **    This program is free software; you can redistribute it and/or modify
  15 **    it under the terms of the GNU General Public License as published by
  16 **    the Free Software Foundation; either version 2 of the License, or
  17 **    (at your option) any later version.
  18 **
  19 ** HISTORY
  20 ** $Date        $Author         $Comment
  21 **  4 AUG 2005  Xu Liang        Initiate Version
  22 ** 23 OCT 2006  Xu Liang        Add GPL header.
  23 **  9 JAN 2007  Xu Liang        First version got from Anand (IC designer)
  24 *******************************************************************************/
  25
  26
  27
  28 #ifndef IFXMIPS_ATM_PPE_VR9_H
  29 #define IFXMIPS_ATM_PPE_VR9_H
  30
  31
  32
  33 /*
  34  *  FPI Configuration Bus Register and Memory Address Mapping
  35  */
  36 #define IFX_PPE                         (KSEG1 | 0x1E200000)
  37 #define PP32_DEBUG_REG_ADDR(i, x)       ((volatile unsigned int*)(IFX_PPE + (((x) + 0x000000 + (i) * 0x00010000) << 2)))
  38 #define CDM_CODE_MEMORY(i, x)           ((volatile unsigned int*)(IFX_PPE + (((x) + 0x001000 + (i) * 0x00010000) << 2)))
  39 #define CDM_DATA_MEMORY(i, x)           ((volatile unsigned int*)(IFX_PPE + (((x) + 0x004000 + (i) * 0x00010000) << 2)))
  40 #define SB_RAM0_ADDR(x)                 ((volatile unsigned int*)(IFX_PPE + (((x) + 0x008000) << 2)))
  41 #define SB_RAM1_ADDR(x)                 ((volatile unsigned int*)(IFX_PPE + (((x) + 0x009000) << 2)))
  42 #define SB_RAM2_ADDR(x)                 ((volatile unsigned int*)(IFX_PPE + (((x) + 0x00A000) << 2)))
  43 #define SB_RAM3_ADDR(x)                 ((volatile unsigned int*)(IFX_PPE + (((x) + 0x00B000) << 2)))
  44 #define PPE_REG_ADDR(x)                 ((volatile unsigned int*)(IFX_PPE + (((x) + 0x00D000) << 2)))
  45 #define QSB_CONF_REG_ADDR(x)            ((volatile unsigned int*)(IFX_PPE + (((x) + 0x00E000) << 2)))
  46 #define SB_RAM6_ADDR(x)                 ((volatile unsigned int*)(IFX_PPE + (((x) + 0x018000) << 2)))
  47
  48 /*
  49  *  DWORD-Length of Memory Blocks
  50  */
  51 #define PP32_DEBUG_REG_DWLEN            0x0030
  52 #define CDM_CODE_MEMORYn_DWLEN(n)       ((n) == 0 ? 0x1000 : 0x0800)
  53 #define CDM_DATA_MEMORY_DWLEN           CDM_CODE_MEMORYn_DWLEN(1)
  54 #define SB_RAM0_DWLEN                   0x1000
  55 #define SB_RAM1_DWLEN                   0x1000
  56 #define SB_RAM2_DWLEN                   0x1000
  57 #define SB_RAM3_DWLEN                   0x1000
  58 #define SB_RAM6_DWLEN                   0x8000
  59 #define QSB_CONF_REG_DWLEN              0x0100
  60
  61 /*
  62  *  PP32 to FPI Address Mapping
  63  */
  64 #define SB_BUFFER(__sb_addr)            ((volatile unsigned int *)((((__sb_addr) >= 0x0000) && ((__sb_addr) <= 0x1FFF)) ? PPE_REG_ADDR((__sb_addr)) :           \
  65                                                                    (((__sb_addr) >= 0x2000) && ((__sb_addr) <= 0x2FFF)) ? SB_RAM0_ADDR((__sb_addr) - 0x2000) :  \
  66                                                                    (((__sb_addr) >= 0x3000) && ((__sb_addr) <= 0x3FFF)) ? SB_RAM1_ADDR((__sb_addr) - 0x3000) :  \
  67                                                                    (((__sb_addr) >= 0x4000) && ((__sb_addr) <= 0x4FFF)) ? SB_RAM2_ADDR((__sb_addr) - 0x4000) :  \
  68                                                                    (((__sb_addr) >= 0x5000) && ((__sb_addr) <= 0x5FFF)) ? SB_RAM3_ADDR((__sb_addr) - 0x5000) :  \
  69                                                                    (((__sb_addr) >= 0x7000) && ((__sb_addr) <= 0x7FFF)) ? PPE_REG_ADDR((__sb_addr) - 0x7000) :  \
  70                                                                    (((__sb_addr) >= 0x8000) && ((__sb_addr) <= 0xFFFF)) ? SB_RAM6_ADDR((__sb_addr) - 0x8000) :  \
  71                                                                 0))
  72
  73 /*
  74  *  PP32 Debug Control Register
  75  */
  76 #define NUM_OF_PP32                             2
  77
  78 #define PP32_FREEZE                             PPE_REG_ADDR(0x0000)
  79 #define PP32_SRST                               PPE_REG_ADDR(0x0020)
  80
  81 #define PP32_DBG_CTRL(n)                        PP32_DEBUG_REG_ADDR(n, 0x0000)
  82
  83 #define DBG_CTRL_RESTART                        0
  84 #define DBG_CTRL_STOP                           1
  85
  86 #define PP32_CTRL_CMD(n)                        PP32_DEBUG_REG_ADDR(n, 0x0B00)
  87   #define PP32_CTRL_CMD_RESTART                 (1 << 0)
  88   #define PP32_CTRL_CMD_STOP                    (1 << 1)
  89   #define PP32_CTRL_CMD_STEP                    (1 << 2)
  90   #define PP32_CTRL_CMD_BREAKOUT                (1 << 3)
  91
  92 #define PP32_CTRL_OPT(n)                        PP32_DEBUG_REG_ADDR(n, 0x0C00)
  93   #define PP32_CTRL_OPT_BREAKOUT_ON_STOP_ON     (3 << 0)
  94   #define PP32_CTRL_OPT_BREAKOUT_ON_STOP_OFF    (2 << 0)
  95   #define PP32_CTRL_OPT_BREAKOUT_ON_BREAKIN_ON  (3 << 2)
  96   #define PP32_CTRL_OPT_BREAKOUT_ON_BREAKIN_OFF (2 << 2)
  97   #define PP32_CTRL_OPT_STOP_ON_BREAKIN_ON      (3 << 4)
  98   #define PP32_CTRL_OPT_STOP_ON_BREAKIN_OFF     (2 << 4)
  99   #define PP32_CTRL_OPT_STOP_ON_BREAKPOINT_ON   (3 << 6)
 100   #define PP32_CTRL_OPT_STOP_ON_BREAKPOINT_OFF  (2 << 6)
 101   #define PP32_CTRL_OPT_BREAKOUT_ON_STOP(n)     (*PP32_CTRL_OPT(n) & (1 << 0))
 102   #define PP32_CTRL_OPT_BREAKOUT_ON_BREAKIN(n)  (*PP32_CTRL_OPT(n) & (1 << 2))
 103   #define PP32_CTRL_OPT_STOP_ON_BREAKIN(n)      (*PP32_CTRL_OPT(n) & (1 << 4))
 104   #define PP32_CTRL_OPT_STOP_ON_BREAKPOINT(n)   (*PP32_CTRL_OPT(n) & (1 << 6))
 105
 106 #define PP32_BRK_PC(n, i)                       PP32_DEBUG_REG_ADDR(n, 0x0900 + (i) * 2)
 107 #define PP32_BRK_PC_MASK(n, i)                  PP32_DEBUG_REG_ADDR(n, 0x0901 + (i) * 2)
 108 #define PP32_BRK_DATA_ADDR(n, i)                PP32_DEBUG_REG_ADDR(n, 0x0904 + (i) * 2)
 109 #define PP32_BRK_DATA_ADDR_MASK(n, i)           PP32_DEBUG_REG_ADDR(n, 0x0905 + (i) * 2)
 110 #define PP32_BRK_DATA_VALUE_RD(n, i)            PP32_DEBUG_REG_ADDR(n, 0x0908 + (i) * 2)
 111 #define PP32_BRK_DATA_VALUE_RD_MASK(n, i)       PP32_DEBUG_REG_ADDR(n, 0x0909 + (i) * 2)
 112 #define PP32_BRK_DATA_VALUE_WR(n, i)            PP32_DEBUG_REG_ADDR(n, 0x090C + (i) * 2)
 113 #define PP32_BRK_DATA_VALUE_WR_MASK(n, i)       PP32_DEBUG_REG_ADDR(n, 0x090D + (i) * 2)
 114   #define PP32_BRK_CONTEXT_MASK(i)              (1 << (i))
 115   #define PP32_BRK_CONTEXT_MASK_EN              (1 << 4)
 116   #define PP32_BRK_COMPARE_GREATER_EQUAL        (1 << 5)    //  valid for break data value rd/wr only
 117   #define PP32_BRK_COMPARE_LOWER_EQUAL          (1 << 6)
 118   #define PP32_BRK_COMPARE_EN                   (1 << 7)
 119
 120 #define PP32_BRK_TRIG(n)                        PP32_DEBUG_REG_ADDR(n, 0x0F00)
 121   #define PP32_BRK_GRPi_PCn_ON(i, n)            ((3 << ((n) * 2)) << ((i) * 16))
 122   #define PP32_BRK_GRPi_PCn_OFF(i, n)           ((2 << ((n) * 2)) << ((i) * 16))
 123   #define PP32_BRK_GRPi_DATA_ADDRn_ON(i, n)     ((3 << ((n) * 2 + 4)) << ((i) * 16))
 124   #define PP32_BRK_GRPi_DATA_ADDRn_OFF(i, n)    ((2 << ((n) * 2 + 4)) << ((i) * 16))
 125   #define PP32_BRK_GRPi_DATA_VALUE_RDn_ON(i, n) ((3 << ((n) * 2 + 8)) << ((i) * 16))
 126   #define PP32_BRK_GRPi_DATA_VALUE_RDn_OFF(i, n)((2 << ((n) * 2 + 8)) << ((i) * 16))
 127   #define PP32_BRK_GRPi_DATA_VALUE_WRn_ON(i, n) ((3 << ((n) * 2 + 12)) << ((i) * 16))
 128   #define PP32_BRK_GRPi_DATA_VALUE_WRn_OFF(i, n)((2 << ((n) * 2 + 12)) << ((i) * 16))
 129   #define PP32_BRK_GRPi_PCn(k, i, n)            (*PP32_BRK_TRIG(k) & ((1 << ((n))) << ((i) * 8)))
 130   #define PP32_BRK_GRPi_DATA_ADDRn(k, i, n)     (*PP32_BRK_TRIG(k) & ((1 << ((n) + 2)) << ((i) * 8)))
 131   #define PP32_BRK_GRPi_DATA_VALUE_RDn(k, i, n) (*PP32_BRK_TRIG(k) & ((1 << ((n) + 4)) << ((i) * 8)))
 132   #define PP32_BRK_GRPi_DATA_VALUE_WRn(k, i, n) (*PP32_BRK_TRIG(k) & ((1 << ((n) + 6)) << ((i) * 8)))
 133
 134 #define PP32_CPU_STATUS(n)                      PP32_DEBUG_REG_ADDR(n, 0x0D00)
 135 #define PP32_HALT_STAT(n)                       PP32_CPU_STATUS(n)
 136 #define PP32_DBG_CUR_PC(n)                      PP32_CPU_STATUS(n)
 137   #define PP32_CPU_USER_STOPPED(n)              (*PP32_CPU_STATUS(n) & (1 << 0))
 138   #define PP32_CPU_USER_BREAKIN_RCV(n)          (*PP32_CPU_STATUS(n) & (1 << 1))
 139   #define PP32_CPU_USER_BREAKPOINT_MET(n)       (*PP32_CPU_STATUS(n) & (1 << 2))
 140   #define PP32_CPU_CUR_PC(n)                    (*PP32_CPU_STATUS(n) >> 16)
 141
 142 #define PP32_BREAKPOINT_REASONS(n)              PP32_DEBUG_REG_ADDR(n, 0x0A00)
 143   #define PP32_BRK_PC_MET(n, i)                 (*PP32_BREAKPOINT_REASONS(n) & (1 << (i)))
 144   #define PP32_BRK_DATA_ADDR_MET(n, i)          (*PP32_BREAKPOINT_REASONS(n) & (1 << ((i) + 2)))
 145   #define PP32_BRK_DATA_VALUE_RD_MET(n, i)      (*PP32_BREAKPOINT_REASONS(n) & (1 << ((i) + 4)))
 146   #define PP32_BRK_DATA_VALUE_WR_MET(n, i)      (*PP32_BREAKPOINT_REASONS(n) & (1 << ((i) + 6)))
 147   #define PP32_BRK_DATA_VALUE_RD_LO_EQ(n, i)    (*PP32_BREAKPOINT_REASONS(n) & (1 << ((i) * 2 + 8)))
 148   #define PP32_BRK_DATA_VALUE_RD_GT_EQ(n, i)    (*PP32_BREAKPOINT_REASONS(n) & (1 << ((i) * 2 + 9)))
 149   #define PP32_BRK_DATA_VALUE_WR_LO_EQ(n, i)    (*PP32_BREAKPOINT_REASONS(n) & (1 << ((i) * 2 + 12)))
 150   #define PP32_BRK_DATA_VALUE_WR_GT_EQ(n, i)    (*PP32_BREAKPOINT_REASONS(n) & (1 << ((i) * 2 + 13)))
 151   #define PP32_BRK_CUR_CONTEXT(n)               ((*PP32_BREAKPOINT_REASONS(n) >> 16) & 0x03)
 152
 153 #define PP32_GP_REG_BASE(n)                     PP32_DEBUG_REG_ADDR(n, 0x0E00)
 154 #define PP32_GP_CONTEXTi_REGn(n, i, j)          PP32_DEBUG_REG_ADDR(n, 0x0E00 + (i) * 16 + (j))
 155
 156 /*
 157  *  PDMA/EMA Registers
 158  */
 159 #define PDMA_CFG                        PPE_REG_ADDR(0x0A00)
 160 #define PDMA_RX_CMDCNT                  PPE_REG_ADDR(0x0A01)
 161 #define PDMA_TX_CMDCNT                  PPE_REG_ADDR(0x0A02)
 162 #define PDMA_RX_FWDATACNT               PPE_REG_ADDR(0x0A03)
 163 #define PDMA_TX_FWDATACNT               PPE_REG_ADDR(0x0A04)
 164 #define PDMA_RX_CTX_CFG                 PPE_REG_ADDR(0x0A05)
 165 #define PDMA_TX_CTX_CFG                 PPE_REG_ADDR(0x0A06)
 166 #define PDMA_RX_MAX_LEN_REG             PPE_REG_ADDR(0x0A07)
 167 #define PDMA_RX_DELAY_CFG               PPE_REG_ADDR(0x0A08)
 168 #define PDMA_INT_FIFO_RD                PPE_REG_ADDR(0x0A09)
 169 #define PDMA_ISR                        PPE_REG_ADDR(0x0A0A)
 170 #define PDMA_IER                        PPE_REG_ADDR(0x0A0B)
 171 #define PDMA_SUBID                      PPE_REG_ADDR(0x0A0C)
 172 #define PDMA_BAR0                       PPE_REG_ADDR(0x0A0D)
 173 #define PDMA_BAR1                       PPE_REG_ADDR(0x0A0E)
 174
 175 #define SAR_PDMA_RX_CMDBUF_CFG          PPE_REG_ADDR(0x0F00)
 176 #define SAR_PDMA_TX_CMDBUF_CFG          PPE_REG_ADDR(0x0F01)
 177 #define SAR_PDMA_RX_FW_CMDBUF_CFG       PPE_REG_ADDR(0x0F02)
 178 #define SAR_PDMA_TX_FW_CMDBUF_CFG       PPE_REG_ADDR(0x0F03)
 179 #define SAR_PDMA_RX_CMDBUF_STATUS       PPE_REG_ADDR(0x0F04)
 180 #define SAR_PDMA_TX_CMDBUF_STATUS       PPE_REG_ADDR(0x0F05)
 181
 182 #define PDMA_ALIGNMENT                  4
 183 #define EMA_ALIGNMENT                   PDMA_ALIGNMENT
 184
 185 /*
 186  *  Mailbox IGU1 Interrupt
 187  */
 188 #define PPE_MAILBOX_IGU1_INT            INT_NUM_IM2_IRL0 + 24
 189
 190
 191
 192 #endif  //  IFXMIPS_ATM_PPE_VR9_H