package/uboot-xburst/files/cpu/mips/jz_lcd.c

   1 /*
   2  * JzRISC lcd controller
   3  *
   4  * xiangfu liu <xiangfu.z@gmail.com>
   5  *
   6  * This program is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU General Public License as
   8  * published by the Free Software Foundation; either version 2 of
   9  * the License, or (at your option) any later version.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU General Public License
  17  * along with this program; if not, write to the Free Software
  18  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  19  * MA 02111-1307 USA
  20  */
  21
  22 /*
  23  * Fallowing macro may be used:
  24  *  CONFIG_LCD                        : LCD support
  25  *  LCD_BPP                           : Bits per pixel, 0 = 1, 1 = 2, 2 = 4, 3 = 8
  26  *  CONFIG_LCD_LOGO                   : show logo
  27  */
  28
  29 #include <config.h>
  30 #include <common.h>
  31 #include <lcd.h>
  32
  33 #include <asm/io.h>               /* virt_to_phys() */
  34
  35 #if defined(CONFIG_LCD) && !defined(CONFIG_SLCD)
  36
  37 #if defined(CONFIG_JZ4740)
  38 #include <asm/jz4740.h>
  39 #endif
  40
  41 #include "jz_lcd.h"
  42
  43
  44 struct jzfb_info {
  45         unsigned int cfg;       /* panel mode and pin usage etc. */
  46         unsigned int w;
  47         unsigned int h;
  48         unsigned int bpp;       /* bit per pixel */
  49         unsigned int fclk;      /* frame clk */
  50         unsigned int hsw;       /* hsync width, in pclk */
  51         unsigned int vsw;       /* vsync width, in line count */
  52         unsigned int elw;       /* end of line, in pclk */
  53         unsigned int blw;       /* begin of line, in pclk */
  54         unsigned int efw;       /* end of frame, in line count */
  55         unsigned int bfw;       /* begin of frame, in line count */
  56 };
  57
  58 static struct jzfb_info jzfb = {
  59    #if defined(CONFIG_NANONOTE)
  60         MODE_8BIT_SERIAL_TFT | PCLK_N | HSYNC_N | VSYNC_N,
  61         320, 240, 32, 70, 1, 1, 273, 140, 1, 20
  62    #endif
  63
  64 };
  65
  66 /************************************************************************/
  67
  68 vidinfo_t panel_info = {
  69 #if defined(CONFIG_JZLCD_FOXCONN_PT035TN01)
  70         320, 240, LCD_BPP,
  71 #endif
  72 };
  73
  74 /*----------------------------------------------------------------------*/
  75
  76 int lcd_line_length;
  77
  78 int lcd_color_fg;
  79 int lcd_color_bg;
  80
  81 /*
  82  * Frame buffer memory information
  83  */
  84 void *lcd_base;                 /* Start of framebuffer memory  */
  85 void *lcd_console_address;      /* Start of console buffer      */
  86
  87 short console_col;
  88 short console_row;
  89
  90 /*----------------------------------------------------------------------*/
  91
  92 void lcd_ctrl_init (void *lcdbase);
  93
  94 void lcd_enable (void);
  95 void lcd_disable (void);
  96
  97 /*----------------------------------------------------------------------*/
  98
  99 static int  jz_lcd_init_mem(void *lcdbase, vidinfo_t *vid);
 100 static void jz_lcd_desc_init(vidinfo_t *vid);
 101 static int  jz_lcd_hw_init( vidinfo_t *vid );
 102 extern int flush_cache_all(void);
 103
 104 #if LCD_BPP == LCD_COLOR8
 105 void lcd_setcolreg (ushort regno, ushort red, ushort green, ushort blue);
 106 #endif
 107 #if LCD_BPP == LCD_MONOCHROME
 108 void lcd_initcolregs (void);
 109 #endif
 110
 111 /*-----------------------------------------------------------------------*/
 112
 113 void lcd_ctrl_init (void *lcdbase)
 114 {
 115         __lcd_display_pin_init();
 116
 117         jz_lcd_init_mem(lcdbase, &panel_info);
 118         jz_lcd_desc_init(&panel_info);
 119         jz_lcd_hw_init(&panel_info);
 120
 121         __lcd_display_on() ;
 122 }
 123
 124 /*----------------------------------------------------------------------*/
 125 #if LCD_BPP == LCD_COLOR8
 126 void
 127 lcd_setcolreg (ushort regno, ushort red, ushort green, ushort blue)
 128 {
 129 }
 130 #endif
 131 /*----------------------------------------------------------------------*/
 132
 133 #if LCD_BPP == LCD_MONOCHROME
 134 static
 135 void lcd_initcolregs (void)
 136 {
 137 }
 138 #endif
 139
 140 /*
 141  * Before enabled lcd controller, lcd registers should be configured correctly.
 142  */
 143
 144 void lcd_enable (void)
 145 {
 146         REG_LCD_CTRL &= ~(1<<4); /* LCDCTRL.DIS */
 147         REG_LCD_CTRL |= 1<<3;    /* LCDCTRL.ENA*/
 148 }
 149
 150 void lcd_disable (void)
 151 {
 152         REG_LCD_CTRL |= (1<<4); /* LCDCTRL.DIS, regular disable */
 153         /* REG_LCD_CTRL |= (1<<3); */  /* LCDCTRL.DIS, quikly disable */
 154 }
 155
 156 static int jz_lcd_init_mem(void *lcdbase, vidinfo_t *vid)
 157 {
 158         u_long palette_mem_size;
 159         struct jz_fb_info *fbi = &vid->jz_fb;
 160         int fb_size = vid->vl_row * (vid->vl_col * NBITS (vid->vl_bpix)) / 8;
 161
 162         fbi->screen = (u_long)lcdbase;
 163         fbi->palette_size = 256;
 164         palette_mem_size = fbi->palette_size * sizeof(u16);
 165
 166         debug("jz_lcd.c palette_mem_size = 0x%08lx\n", (u_long) palette_mem_size);
 167         /* locate palette and descs at end of page following fb */
 168         fbi->palette = (u_long)lcdbase + fb_size + PAGE_SIZE - palette_mem_size;
 169
 170         return 0;
 171 }
 172
 173 static void jz_lcd_desc_init(vidinfo_t *vid)
 174 {
 175         struct jz_fb_info * fbi;
 176         fbi = &vid->jz_fb;
 177         fbi->dmadesc_fblow = (struct jz_fb_dma_descriptor *)((unsigned int)fbi->palette - 3*16);
 178         fbi->dmadesc_fbhigh = (struct jz_fb_dma_descriptor *)((unsigned int)fbi->palette - 2*16);
 179         fbi->dmadesc_palette = (struct jz_fb_dma_descriptor *)((unsigned int)fbi->palette - 1*16);
 180
 181         #define BYTES_PER_PANEL  (vid->vl_col * vid->vl_row * NBITS(vid->vl_bpix) / 8)
 182
 183         /* populate descriptors */
 184         fbi->dmadesc_fblow->fdadr = virt_to_phys(fbi->dmadesc_fblow);
 185         fbi->dmadesc_fblow->fsadr = virt_to_phys((void *)(fbi->screen + BYTES_PER_PANEL));
 186         fbi->dmadesc_fblow->fidr  = 0;
 187         fbi->dmadesc_fblow->ldcmd = BYTES_PER_PANEL / 4 ;
 188
 189         fbi->fdadr1 = virt_to_phys(fbi->dmadesc_fblow); /* only used in dual-panel mode */
 190
 191         fbi->dmadesc_fbhigh->fsadr = virt_to_phys((void *)fbi->screen);
 192         fbi->dmadesc_fbhigh->fidr = 0;
 193         fbi->dmadesc_fbhigh->ldcmd =  BYTES_PER_PANEL / 4; /* length in word */
 194
 195         fbi->dmadesc_palette->fsadr = virt_to_phys((void *)fbi->palette);
 196         fbi->dmadesc_palette->fidr  = 0;
 197         fbi->dmadesc_palette->ldcmd = (fbi->palette_size * 2)/4 | (1<<28);
 198
 199         if( NBITS(vid->vl_bpix) < 12)
 200         {
 201                 /* assume any mode with <12 bpp is palette driven */
 202                 fbi->dmadesc_palette->fdadr = virt_to_phys(fbi->dmadesc_fbhigh);
 203                 fbi->dmadesc_fbhigh->fdadr = virt_to_phys(fbi->dmadesc_palette);
 204                 /* flips back and forth between pal and fbhigh */
 205                 fbi->fdadr0 = virt_to_phys(fbi->dmadesc_palette);
 206         } else {
 207                 /* palette shouldn't be loaded in true-color mode */
 208                 fbi->dmadesc_fbhigh->fdadr = virt_to_phys((void *)fbi->dmadesc_fbhigh);
 209                 fbi->fdadr0 = virt_to_phys(fbi->dmadesc_fbhigh); /* no pal just fbhigh */
 210         }
 211
 212         flush_cache_all();
 213 }
 214
 215 static int  jz_lcd_hw_init(vidinfo_t *vid)
 216 {
 217         struct jz_fb_info *fbi = &vid->jz_fb;
 218         unsigned int val = 0;
 219         unsigned int pclk;
 220         unsigned int stnH;
 221 #if defined(CONFIG_MIPS_JZ4740)
 222         int pll_div;
 223 #endif
 224
 225         /* Setting Control register */
 226         switch (jzfb.bpp) {
 227         case 1:
 228                 val |= LCD_CTRL_BPP_1;
 229                 break;
 230         case 2:
 231                 val |= LCD_CTRL_BPP_2;
 232                 break;
 233         case 4:
 234                 val |= LCD_CTRL_BPP_4;
 235                 break;
 236         case 8:
 237                 val |= LCD_CTRL_BPP_8;
 238                 break;
 239         case 15:
 240                 val |= LCD_CTRL_RGB555;
 241         case 16:
 242                 val |= LCD_CTRL_BPP_16;
 243                 break;
 244 #if defined(CONFIG_MIPS_JZ4740)
 245         case 17 ... 32:
 246                 val |= LCD_CTRL_BPP_18_24;      /* target is 4bytes/pixel */
 247                 break;
 248 #endif
 249         default:
 250                 printf("jz_lcd.c The BPP %d is not supported\n", jzfb.bpp);
 251                 val |= LCD_CTRL_BPP_16;
 252                 break;
 253         }
 254
 255         switch (jzfb.cfg & MODE_MASK) {
 256         case MODE_STN_MONO_DUAL:
 257         case MODE_STN_COLOR_DUAL:
 258         case MODE_STN_MONO_SINGLE:
 259         case MODE_STN_COLOR_SINGLE:
 260                 switch (jzfb.bpp) {
 261                 case 1:
 262                         /* val |= LCD_CTRL_PEDN; */
 263                 case 2:
 264                         val |= LCD_CTRL_FRC_2;
 265                         break;
 266                 case 4:
 267                         val |= LCD_CTRL_FRC_4;
 268                         break;
 269                 case 8:
 270                 default:
 271                         val |= LCD_CTRL_FRC_16;
 272                         break;
 273                 }
 274                 break;
 275         }
 276
 277         val |= LCD_CTRL_BST_16;         /* Burst Length is 16WORD=64Byte */
 278         val |= LCD_CTRL_OFUP;           /* OutFIFO underrun protect */
 279
 280         switch (jzfb.cfg & MODE_MASK) {
 281         case MODE_STN_MONO_DUAL:
 282         case MODE_STN_COLOR_DUAL:
 283         case MODE_STN_MONO_SINGLE:
 284         case MODE_STN_COLOR_SINGLE:
 285                 switch (jzfb.cfg & STN_DAT_PINMASK) {
 286 #define align2(n) (n)=((((n)+1)>>1)<<1)
 287 #define align4(n) (n)=((((n)+3)>>2)<<2)
 288 #define align8(n) (n)=((((n)+7)>>3)<<3)
 289                 case STN_DAT_PIN1:
 290                         /* Do not adjust the hori-param value. */
 291                         break;
 292                 case STN_DAT_PIN2:
 293                         align2(jzfb.hsw);
 294                         align2(jzfb.elw);
 295                         align2(jzfb.blw);
 296                         break;
 297                 case STN_DAT_PIN4:
 298                         align4(jzfb.hsw);
 299                         align4(jzfb.elw);
 300                         align4(jzfb.blw);
 301                         break;
 302                 case STN_DAT_PIN8:
 303                         align8(jzfb.hsw);
 304                         align8(jzfb.elw);
 305                         align8(jzfb.blw);
 306                         break;
 307                 }
 308                 break;
 309         }
 310
 311         REG_LCD_CTRL = val;
 312
 313         switch (jzfb.cfg & MODE_MASK) {
 314         case MODE_STN_MONO_DUAL:
 315         case MODE_STN_COLOR_DUAL:
 316         case MODE_STN_MONO_SINGLE:
 317         case MODE_STN_COLOR_SINGLE:
 318                 if (((jzfb.cfg & MODE_MASK) == MODE_STN_MONO_DUAL) ||
 319                     ((jzfb.cfg & MODE_MASK) == MODE_STN_COLOR_DUAL))
 320                         stnH = jzfb.h >> 1;
 321                 else
 322                         stnH = jzfb.h;
 323
 324                 REG_LCD_VSYNC = (0 << 16) | jzfb.vsw;
 325                 REG_LCD_HSYNC = ((jzfb.blw+jzfb.w) << 16) | (jzfb.blw+jzfb.w+jzfb.hsw);
 326
 327                 /* Screen setting */
 328                 REG_LCD_VAT = ((jzfb.blw + jzfb.w + jzfb.hsw + jzfb.elw) << 16) | (stnH + jzfb.vsw + jzfb.bfw + jzfb.efw);
 329                 REG_LCD_DAH = (jzfb.blw << 16) | (jzfb.blw + jzfb.w);
 330                 REG_LCD_DAV = (0 << 16) | (stnH);
 331
 332                 /* AC BIAs signal */
 333                 REG_LCD_PS = (0 << 16) | (stnH+jzfb.vsw+jzfb.efw+jzfb.bfw);
 334
 335                 break;
 336
 337         case MODE_TFT_GEN:
 338         case MODE_TFT_SHARP:
 339         case MODE_TFT_CASIO:
 340         case MODE_TFT_SAMSUNG:
 341         case MODE_8BIT_SERIAL_TFT:
 342         case MODE_TFT_18BIT:
 343                 REG_LCD_VSYNC = (0 << 16) | jzfb.vsw;
 344                 REG_LCD_HSYNC = (0 << 16) | jzfb.hsw;
 345 #if defined(CONFIG_JZLCD_INNOLUX_AT080TN42)
 346                 REG_LCD_DAV = (0 << 16) | ( jzfb.h );
 347 #else
 348                 REG_LCD_DAV =((jzfb.vsw+jzfb.bfw) << 16) | (jzfb.vsw +jzfb.bfw+jzfb.h);
 349 #endif /*#if defined(CONFIG_JZLCD_INNOLUX_AT080TN42)*/
 350                 REG_LCD_DAH = ((jzfb.hsw + jzfb.blw) << 16) | (jzfb.hsw + jzfb.blw + jzfb.w );
 351                 REG_LCD_VAT = (((jzfb.blw + jzfb.w + jzfb.elw + jzfb.hsw)) << 16) \
 352                         | (jzfb.vsw + jzfb.bfw + jzfb.h + jzfb.efw);
 353                 break;
 354         }
 355
 356         switch (jzfb.cfg & MODE_MASK) {
 357         case MODE_TFT_SAMSUNG:
 358         {
 359                 unsigned int total, tp_s, tp_e, ckv_s, ckv_e;
 360                 unsigned int rev_s, rev_e, inv_s, inv_e;
 361
 362                 pclk = val * (jzfb.w + jzfb.hsw + jzfb.elw + jzfb.blw) *
 363                         (jzfb.h + jzfb.vsw + jzfb.efw + jzfb.bfw); /* Pixclk */
 364
 365                 total = jzfb.blw + jzfb.w + jzfb.elw + jzfb.hsw;
 366                 tp_s = jzfb.blw + jzfb.w + 1;
 367                 tp_e = tp_s + 1;
 368                 /* ckv_s = tp_s - jz_clocks.pixclk/(1000000000/4100); */
 369                 ckv_s = tp_s - pclk/(1000000000/4100);
 370                 ckv_e = tp_s + total;
 371                 rev_s = tp_s - 11;      /* -11.5 clk */
 372                 rev_e = rev_s + total;
 373                 inv_s = tp_s;
 374                 inv_e = inv_s + total;
 375                 REG_LCD_CLS = (tp_s << 16) | tp_e;
 376                 REG_LCD_PS = (ckv_s << 16) | ckv_e;
 377                 REG_LCD_SPL = (rev_s << 16) | rev_e;
 378                 REG_LCD_REV = (inv_s << 16) | inv_e;
 379                 jzfb.cfg |= STFT_REVHI | STFT_SPLHI;
 380                 break;
 381         }
 382         case MODE_TFT_SHARP:
 383         {
 384                 unsigned int total, cls_s, cls_e, ps_s, ps_e;
 385                 unsigned int spl_s, spl_e, rev_s, rev_e;
 386                 total = jzfb.blw + jzfb.w + jzfb.elw + jzfb.hsw;
 387 #if !defined(CONFIG_JZLCD_INNOLUX_AT080TN42)
 388                 spl_s = 1;
 389                 spl_e = spl_s + 1;
 390                 cls_s = 0;
 391                 cls_e = total - 60;     /* > 4us (pclk = 80ns) */
 392                 ps_s = cls_s;
 393                 ps_e = cls_e;
 394                 rev_s = total - 40;     /* > 3us (pclk = 80ns) */
 395                 rev_e = rev_s + total;
 396                 jzfb.cfg |= STFT_PSHI;
 397 #else           /*#if defined(CONFIG_JZLCD_INNOLUX_AT080TN42)*/
 398                 spl_s = total - 5; /* LD */
 399                 spl_e = total -3;
 400                 cls_s = 32;     /* CKV */
 401                 cls_e = 145;
 402                 ps_s  = 0;      /* OEV */
 403                 ps_e  = 45;
 404                 rev_s = 0;      /* POL */
 405                 rev_e = 0;
 406 #endif          /*#if defined(CONFIG_JZLCD_INNOLUX_AT080TN42)*/
 407                 REG_LCD_SPL = (spl_s << 16) | spl_e;
 408                 REG_LCD_CLS = (cls_s << 16) | cls_e;
 409                 REG_LCD_PS = (ps_s << 16) | ps_e;
 410                 REG_LCD_REV = (rev_s << 16) | rev_e;
 411                 break;
 412         }
 413         case MODE_TFT_CASIO:
 414                 break;
 415         }
 416
 417         /* Configure the LCD panel */
 418         REG_LCD_CFG = jzfb.cfg;
 419
 420         /* Timing setting */
 421         __cpm_stop_lcd();
 422
 423         val = jzfb.fclk; /* frame clk */
 424         if ( (jzfb.cfg & MODE_MASK) != MODE_8BIT_SERIAL_TFT) {
 425                 pclk = val * (jzfb.w + jzfb.hsw + jzfb.elw + jzfb.blw) *
 426                         (jzfb.h + jzfb.vsw + jzfb.efw + jzfb.bfw); /* Pixclk */
 427         }
 428         else {
 429                 /* serial mode: Hsync period = 3*Width_Pixel */
 430                 pclk = val * (jzfb.w*3 + jzfb.hsw + jzfb.elw + jzfb.blw) *
 431                         (jzfb.h + jzfb.vsw + jzfb.efw + jzfb.bfw); /* Pixclk */
 432         }
 433
 434         if (((jzfb.cfg & MODE_MASK) == MODE_STN_COLOR_SINGLE) ||
 435             ((jzfb.cfg & MODE_MASK) == MODE_STN_COLOR_DUAL))
 436                 pclk = (pclk * 3);
 437
 438         if (((jzfb.cfg & MODE_MASK) == MODE_STN_COLOR_SINGLE) ||
 439             ((jzfb.cfg & MODE_MASK) == MODE_STN_COLOR_DUAL) ||
 440             ((jzfb.cfg & MODE_MASK) == MODE_STN_MONO_SINGLE) ||
 441             ((jzfb.cfg & MODE_MASK) == MODE_STN_MONO_DUAL))
 442                 pclk = pclk >> ((jzfb.cfg & STN_DAT_PINMASK) >> 4);
 443
 444         if (((jzfb.cfg & MODE_MASK) == MODE_STN_COLOR_DUAL) ||
 445             ((jzfb.cfg & MODE_MASK) == MODE_STN_MONO_DUAL))
 446                 pclk >>= 1;
 447
 448         pll_div = ( REG_CPM_CPCCR & CPM_CPCCR_PCS ); /* clock source,0:pllout/2 1: pllout */
 449         pll_div = pll_div ? 1 : 2 ;
 450         val = ( __cpm_get_pllout()/pll_div ) / pclk;
 451         val--;
 452         if ( val > 0x1ff ) {
 453                 printf("CPM_LPCDR too large, set it to 0x1ff\n");
 454                 val = 0x1ff;
 455         }
 456         __cpm_set_pixdiv(val);
 457
 458         val = pclk * 3 ;        /* LCDClock > 2.5*Pixclock */
 459         if ( val > 150000000 ) {
 460                 printf("Warning: LCDClock=%d\n, LCDClock must less or equal to 150MHz.\n", val);
 461                 printf("Change LCDClock to 150MHz\n");
 462                 val = 150000000;
 463         }
 464         val = ( __cpm_get_pllout()/pll_div ) / val;
 465         val--;
 466         if ( val > 0x1f ) {
 467                 printf("CPM_CPCCR.LDIV too large, set it to 0x1f\n");
 468                 val = 0x1f;
 469         }
 470         __cpm_set_ldiv( val );
 471         REG_CPM_CPCCR |= CPM_CPCCR_CE ; /* update divide */
 472
 473         __cpm_start_lcd();
 474         udelay(1000);
 475
 476         REG_LCD_DA0 = fbi->fdadr0; /* frame descripter*/
 477
 478         if (((jzfb.cfg & MODE_MASK) == MODE_STN_COLOR_DUAL) ||
 479             ((jzfb.cfg & MODE_MASK) == MODE_STN_MONO_DUAL))
 480                 REG_LCD_DA1 = fbi->fdadr1; /* frame descripter*/
 481
 482         return 0;
 483 }
 484