ar71xx: ag71xx: make switch register access atomic
[openwrt.git] / package / uboot-xburst / files / cpu / mips / nanonote_gpm940b0.h
1 /*
2 * JzRISC lcd controller
3 *
4 * xiangfu liu <xiangfu.z@gmail.com>
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation; either version 2 of
9 * the License, or (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
19 * MA 02111-1307 USA
20 */
21
22 #ifndef __QI_LB60_GPM940B0_H__
23 #define __QI_LB60_GPM940B0_H__
24
25 #include <asm/io.h>
26
27 #define mdelay(n) udelay((n)*1000)
28
29 #define NR_PALETTE 256
30
31 struct lcd_desc{
32 unsigned int next_desc; /* LCDDAx */
33 unsigned int databuf; /* LCDSAx */
34 unsigned int frame_id; /* LCDFIDx */
35 unsigned int cmd; /* LCDCMDx */
36 };
37
38 #define MODE_MASK 0x0f
39 #define MODE_TFT_GEN 0x00
40 #define MODE_TFT_SHARP 0x01
41 #define MODE_TFT_CASIO 0x02
42 #define MODE_TFT_SAMSUNG 0x03
43 #define MODE_CCIR656_NONINT 0x04
44 #define MODE_CCIR656_INT 0x05
45 #define MODE_STN_COLOR_SINGLE 0x08
46 #define MODE_STN_MONO_SINGLE 0x09
47 #define MODE_STN_COLOR_DUAL 0x0a
48 #define MODE_STN_MONO_DUAL 0x0b
49 #define MODE_8BIT_SERIAL_TFT 0x0c
50
51 #define MODE_TFT_18BIT (1<<7)
52
53 #define STN_DAT_PIN1 (0x00 << 4)
54 #define STN_DAT_PIN2 (0x01 << 4)
55 #define STN_DAT_PIN4 (0x02 << 4)
56 #define STN_DAT_PIN8 (0x03 << 4)
57 #define STN_DAT_PINMASK STN_DAT_PIN8
58
59 #define STFT_PSHI (1 << 15)
60 #define STFT_CLSHI (1 << 14)
61 #define STFT_SPLHI (1 << 13)
62 #define STFT_REVHI (1 << 12)
63
64 #define SYNC_MASTER (0 << 16)
65 #define SYNC_SLAVE (1 << 16)
66
67 #define DE_P (0 << 9)
68 #define DE_N (1 << 9)
69
70 #define PCLK_P (0 << 10)
71 #define PCLK_N (1 << 10)
72
73 #define HSYNC_P (0 << 11)
74 #define HSYNC_N (1 << 11)
75
76 #define VSYNC_P (0 << 8)
77 #define VSYNC_N (1 << 8)
78
79 #define DATA_NORMAL (0 << 17)
80 #define DATA_INVERSE (1 << 17)
81
82
83 /* Jz LCDFB supported I/O controls. */
84 #define FBIOSETBACKLIGHT 0x4688
85 #define FBIODISPON 0x4689
86 #define FBIODISPOFF 0x468a
87 #define FBIORESET 0x468b
88 #define FBIOPRINT_REG 0x468c
89
90 /*
91 * LCD panel specific definition
92 */
93 #define MODE 0xc9 /* 8bit serial RGB */
94 #define SPEN (32*2+21) /*LCD_SPL */
95 #define SPCK (32*2+23) /*LCD_CLS */
96 #define SPDA (32*2+22) /*LCD_D12 */
97 #define LCD_RET (32*3+27)
98
99 #define __spi_write_reg1(reg, val) \
100 do { \
101 unsigned char no;\
102 unsigned short value;\
103 unsigned char a=0;\
104 unsigned char b=0;\
105 a=reg;\
106 b=val;\
107 __gpio_set_pin(SPEN);\
108 __gpio_set_pin(SPCK);\
109 __gpio_clear_pin(SPDA);\
110 __gpio_clear_pin(SPEN);\
111 udelay(25);\
112 value=((a<<8)|(b&0xFF));\
113 for(no=0;no<16;no++)\
114 {\
115 __gpio_clear_pin(SPCK);\
116 if((value&0x8000)==0x8000)\
117 __gpio_set_pin(SPDA);\
118 else\
119 __gpio_clear_pin(SPDA);\
120 udelay(25);\
121 __gpio_set_pin(SPCK);\
122 value=(value<<1); \
123 udelay(25);\
124 }\
125 __gpio_set_pin(SPEN);\
126 udelay(100);\
127 } while (0)
128
129 #define __spi_write_reg(reg, val) \
130 do {\
131 __spi_write_reg1((reg<<2|2), val);\
132 udelay(100); \
133 }while(0)
134
135 #define __lcd_special_pin_init() \
136 do { \
137 __gpio_as_output(SPEN); /* use SPDA */\
138 __gpio_as_output(SPCK); /* use SPCK */\
139 __gpio_as_output(SPDA); /* use SPDA */\
140 __gpio_as_output(LCD_RET);\
141 } while (0)
142
143 #define __lcd_special_on() \
144 do { \
145 __spi_write_reg1(0x05, 0x1e); \
146 udelay(50);\
147 __spi_write_reg1(0x05, 0x5d); \
148 __spi_write_reg1(0x0B, 0x81); \
149 __spi_write_reg1(0x01, 0x95); \
150 __spi_write_reg1(0x00, 0x07); \
151 __spi_write_reg1(0x06, 0x15); \
152 __spi_write_reg1(0x07, 0x8d); \
153 __spi_write_reg1(0x04, 0x0f); \
154 __spi_write_reg1(0x0d, 0x3d); \
155 __spi_write_reg1(0x10, 0x42); \
156 __spi_write_reg1(0x11, 0x3a); \
157 __spi_write_reg1(0x05, 0x5f); \
158 } while (0)
159
160 #define __lcd_special_off() \
161 do { \
162 __spi_write_reg1(0x05, 0x5e); \
163 } while (0)
164
165 #define __lcd_display_pin_init() \
166 do { \
167 __lcd_special_pin_init();\
168 __gpio_as_pwm();\
169 __lcd_set_backlight_level(8);\
170 } while (0)
171
172 #define __lcd_display_on() \
173 do { \
174 __lcd_set_backlight_level(8); \
175 __lcd_special_on();\
176 } while (0)
177
178 #define __lcd_display_off() \
179 do { \
180 __lcd_set_backlight_level(0); \
181 __lcd_special_off();\
182 } while (0)
183
184 #define __lcd_set_backlight_level(n)\
185 do { \
186 __gpio_as_output(LCD_RET); \
187 __gpio_set_pin(LCD_RET); \
188 } while (0)
189
190 #if defined(CONFIG_SAKC)
191 #define __lcd_close_backlight() \
192 do { \
193 __gpio_as_output(GPIO_PWM); \
194 __gpio_clear_pin(GPIO_PWM); \
195 } while (0)
196 #endif
197
198 #if defined(CONFIG_SAKC)
199 #define __lcd_display_pin_init() \
200 do { \
201 __cpm_start_tcu(); \
202 __lcd_special_pin_init(); \
203 } while (0)
204
205 #define __lcd_display_on() \
206 do { \
207 __lcd_special_on(); \
208 } while (0)
209
210 #define __lcd_display_off() \
211 do { \
212 __lcd_special_off(); \
213 } while (0)
214 #else
215 #define __lcd_display_pin_init() \
216 do { \
217 __cpm_start_tcu(); \
218 __lcd_special_pin_init(); \
219 } while (0)
220
221 #define __lcd_display_on() \
222 do { \
223 __gpio_set_pin(GPIO_DISP_OFF_N); \
224 __lcd_special_on(); \
225 } while (0)
226
227 #define __lcd_display_off() \
228 do { \
229 __lcd_special_off(); \
230 __gpio_clear_pin(GPIO_DISP_OFF_N); \
231 } while (0)
232 #endif
233
234 #endif /* __QI_LB60_GPM940B0_H__ */
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