ar71xx: ag71xx: make switch register access atomic
[openwrt.git] / package / uboot-xburst / files / include / asm-mips / jz4740.h
1 /*
2 * Include file for Ingenic Semiconductor's JZ4740 CPU.
3 */
4 #ifndef __JZ4740_H__
5 #define __JZ4740_H__
6
7 #ifndef __ASSEMBLY__
8 #define UCOS_CSP 0
9
10 #if UCOS_CSP
11 #define __KERNEL__
12 #include <bsp.h>
13 #include <types.h>
14
15 #include <sysdefs.h>
16 #include <cacheops.h>
17 #define KSEG0 KSEG0BASE
18 #else
19 #include <asm/addrspace.h>
20 #include <asm/cacheops.h>
21 #endif
22
23 #define cache_unroll(base,op) \
24 __asm__ __volatile__(" \
25 .set noreorder; \
26 .set mips3; \
27 cache %1, (%0); \
28 .set mips0; \
29 .set reorder" \
30 : \
31 : "r" (base), \
32 "i" (op));
33
34 static inline void jz_flush_dcache(void)
35 {
36 unsigned long start;
37 unsigned long end;
38
39 start = KSEG0;
40 end = start + CONFIG_SYS_DCACHE_SIZE;
41 while (start < end) {
42 cache_unroll(start,Index_Writeback_Inv_D);
43 start += CONFIG_SYS_CACHELINE_SIZE;
44 }
45 }
46
47 static inline void jz_flush_icache(void)
48 {
49 unsigned long start;
50 unsigned long end;
51
52 start = KSEG0;
53 end = start + CONFIG_SYS_ICACHE_SIZE;
54 while(start < end) {
55 cache_unroll(start,Index_Invalidate_I);
56 start += CONFIG_SYS_CACHELINE_SIZE;
57 }
58 }
59
60 /* cpu pipeline flush */
61 static inline void jz_sync(void)
62 {
63 __asm__ volatile ("sync");
64 }
65
66 static inline void jz_writeb(u32 address, u8 value)
67 {
68 *((volatile u8 *)address) = value;
69 }
70
71 static inline void jz_writew(u32 address, u16 value)
72 {
73 *((volatile u16 *)address) = value;
74 }
75
76 static inline void jz_writel(u32 address, u32 value)
77 {
78 *((volatile u32 *)address) = value;
79 }
80
81 static inline u8 jz_readb(u32 address)
82 {
83 return *((volatile u8 *)address);
84 }
85
86 static inline u16 jz_readw(u32 address)
87 {
88 return *((volatile u16 *)address);
89 }
90
91 static inline u32 jz_readl(u32 address)
92 {
93 return *((volatile u32 *)address);
94 }
95
96 #define REG8(addr) *((volatile u8 *)(addr))
97 #define REG16(addr) *((volatile u16 *)(addr))
98 #define REG32(addr) *((volatile u32 *)(addr))
99
100 #else
101
102 #define REG8(addr) (addr)
103 #define REG16(addr) (addr)
104 #define REG32(addr) (addr)
105
106 #endif /* !ASSEMBLY */
107
108 /* Boot ROM Specification */
109 /* NOR Boot config */
110 #define JZ4740_NORBOOT_8BIT 0x00000000 /* 8-bit data bus flash */
111 #define JZ4740_NORBOOT_16BIT 0x10101010 /* 16-bit data bus flash */
112 #define JZ4740_NORBOOT_32BIT 0x20202020 /* 32-bit data bus flash */
113
114 /* NAND Boot config */
115 #define JZ4740_NANDBOOT_B8R3 0xffffffff /* 8-bit bus & 3 row cycles */
116 #define JZ4740_NANDBOOT_B8R2 0xf0f0f0f0 /* 8-bit bus & 2 row cycles */
117 #define JZ4740_NANDBOOT_B16R3 0x0f0f0f0f /* 16-bit bus & 3 row cycles */
118 #define JZ4740_NANDBOOT_B16R2 0x00000000 /* 16-bit bus & 2 row cycles */
119
120
121 /* Register Definitions */
122 #define CPM_BASE 0xB0000000
123 #define INTC_BASE 0xB0001000
124 #define TCU_BASE 0xB0002000
125 #define WDT_BASE 0xB0002000
126 #define RTC_BASE 0xB0003000
127 #define GPIO_BASE 0xB0010000
128 #define AIC_BASE 0xB0020000
129 #define ICDC_BASE 0xB0020000
130 #define MSC_BASE 0xB0021000
131 #define UART0_BASE 0xB0030000
132 #define I2C_BASE 0xB0042000
133 #define SSI_BASE 0xB0043000
134 #define SADC_BASE 0xB0070000
135 #define EMC_BASE 0xB3010000
136 #define DMAC_BASE 0xB3020000
137 #define UHC_BASE 0xB3030000
138 #define UDC_BASE 0xB3040000
139 #define LCD_BASE 0xB3050000
140 #define SLCD_BASE 0xB3050000
141 #define CIM_BASE 0xB3060000
142 #define ETH_BASE 0xB3100000
143
144
145 /*
146 * INTC (Interrupt Controller)
147 */
148 #define INTC_ISR (INTC_BASE + 0x00)
149 #define INTC_IMR (INTC_BASE + 0x04)
150 #define INTC_IMSR (INTC_BASE + 0x08)
151 #define INTC_IMCR (INTC_BASE + 0x0c)
152 #define INTC_IPR (INTC_BASE + 0x10)
153
154 #define REG_INTC_ISR REG32(INTC_ISR)
155 #define REG_INTC_IMR REG32(INTC_IMR)
156 #define REG_INTC_IMSR REG32(INTC_IMSR)
157 #define REG_INTC_IMCR REG32(INTC_IMCR)
158 #define REG_INTC_IPR REG32(INTC_IPR)
159
160 /* 1st-level interrupts */
161 #define IRQ_I2C 1
162 #define IRQ_UHC 3
163 #define IRQ_UART0 9
164 #define IRQ_SADC 12
165 #define IRQ_MSC 14
166 #define IRQ_RTC 15
167 #define IRQ_SSI 16
168 #define IRQ_CIM 17
169 #define IRQ_AIC 18
170 #define IRQ_ETH 19
171 #define IRQ_DMAC 20
172 #define IRQ_TCU2 21
173 #define IRQ_TCU1 22
174 #define IRQ_TCU0 23
175 #define IRQ_UDC 24
176 #define IRQ_GPIO3 25
177 #define IRQ_GPIO2 26
178 #define IRQ_GPIO1 27
179 #define IRQ_GPIO0 28
180 #define IRQ_IPU 29
181 #define IRQ_LCD 30
182
183 /* 2nd-level interrupts */
184 #define IRQ_DMA_0 32 /* 32 to 37 for DMAC channel 0 to 5 */
185 #define IRQ_GPIO_0 48 /* 48 to 175 for GPIO pin 0 to 127 */
186
187
188 /*
189 * RTC
190 */
191 #define RTC_RCR (RTC_BASE + 0x00) /* RTC Control Register */
192 #define RTC_RSR (RTC_BASE + 0x04) /* RTC Second Register */
193 #define RTC_RSAR (RTC_BASE + 0x08) /* RTC Second Alarm Register */
194 #define RTC_RGR (RTC_BASE + 0x0c) /* RTC Regulator Register */
195
196 #define RTC_HCR (RTC_BASE + 0x20) /* Hibernate Control Register */
197 #define RTC_HWFCR (RTC_BASE + 0x24) /* Hibernate Wakeup Filter Counter Reg */
198 #define RTC_HRCR (RTC_BASE + 0x28) /* Hibernate Reset Counter Register */
199 #define RTC_HWCR (RTC_BASE + 0x2c) /* Hibernate Wakeup Control Register */
200 #define RTC_HWRSR (RTC_BASE + 0x30) /* Hibernate Wakeup Status Register */
201 #define RTC_HSPR (RTC_BASE + 0x34) /* Hibernate Scratch Pattern Register */
202
203 #define REG_RTC_RCR REG32(RTC_RCR)
204 #define REG_RTC_RSR REG32(RTC_RSR)
205 #define REG_RTC_RSAR REG32(RTC_RSAR)
206 #define REG_RTC_RGR REG32(RTC_RGR)
207 #define REG_RTC_HCR REG32(RTC_HCR)
208 #define REG_RTC_HWFCR REG32(RTC_HWFCR)
209 #define REG_RTC_HRCR REG32(RTC_HRCR)
210 #define REG_RTC_HWCR REG32(RTC_HWCR)
211 #define REG_RTC_HWRSR REG32(RTC_HWRSR)
212 #define REG_RTC_HSPR REG32(RTC_HSPR)
213
214 /* RTC Control Register */
215 #define RTC_RCR_WRDY (1 << 7) /* Write Ready Flag */
216 #define RTC_RCR_HZ (1 << 6) /* 1Hz Flag */
217 #define RTC_RCR_HZIE (1 << 5) /* 1Hz Interrupt Enable */
218 #define RTC_RCR_AF (1 << 4) /* Alarm Flag */
219 #define RTC_RCR_AIE (1 << 3) /* Alarm Interrupt Enable */
220 #define RTC_RCR_AE (1 << 2) /* Alarm Enable */
221 #define RTC_RCR_RTCE (1 << 0) /* RTC Enable */
222
223 /* RTC Regulator Register */
224 #define RTC_RGR_LOCK (1 << 31) /* Lock Bit */
225 #define RTC_RGR_ADJC_BIT 16
226 #define RTC_RGR_ADJC_MASK (0x3ff << RTC_RGR_ADJC_BIT)
227 #define RTC_RGR_NC1HZ_BIT 0
228 #define RTC_RGR_NC1HZ_MASK (0xffff << RTC_RGR_NC1HZ_BIT)
229
230 /* Hibernate Control Register */
231 #define RTC_HCR_PD (1 << 0) /* Power Down */
232
233 /* Hibernate Wakeup Filter Counter Register */
234 #define RTC_HWFCR_BIT 5
235 #define RTC_HWFCR_MASK (0x7ff << RTC_HWFCR_BIT)
236
237 /* Hibernate Reset Counter Register */
238 #define RTC_HRCR_BIT 5
239 #define RTC_HRCR_MASK (0x7f << RTC_HRCR_BIT)
240
241 /* Hibernate Wakeup Control Register */
242 #define RTC_HWCR_EALM (1 << 0) /* RTC alarm wakeup enable */
243
244 /* Hibernate Wakeup Status Register */
245 #define RTC_HWRSR_HR (1 << 5) /* Hibernate reset */
246 #define RTC_HWRSR_PPR (1 << 4) /* PPR reset */
247 #define RTC_HWRSR_PIN (1 << 1) /* Wakeup pin status bit */
248 #define RTC_HWRSR_ALM (1 << 0) /* RTC alarm status bit */
249
250
251 /*************************************************************************
252 * CPM (Clock reset and Power control Management)
253 *************************************************************************/
254 #define CPM_CPCCR (CPM_BASE+0x00)
255 #define CPM_CPPCR (CPM_BASE+0x10)
256 #define CPM_I2SCDR (CPM_BASE+0x60)
257 #define CPM_LPCDR (CPM_BASE+0x64)
258 #define CPM_MSCCDR (CPM_BASE+0x68)
259 #define CPM_UHCCDR (CPM_BASE+0x6C)
260
261 #define CPM_LCR (CPM_BASE+0x04)
262 #define CPM_CLKGR (CPM_BASE+0x20)
263 #define CPM_SCR (CPM_BASE+0x24)
264
265 #define CPM_HCR (CPM_BASE+0x30)
266 #define CPM_HWFCR (CPM_BASE+0x34)
267 #define CPM_HRCR (CPM_BASE+0x38)
268 #define CPM_HWCR (CPM_BASE+0x3c)
269 #define CPM_HWSR (CPM_BASE+0x40)
270 #define CPM_HSPR (CPM_BASE+0x44)
271
272 #define CPM_RSR (CPM_BASE+0x08)
273
274
275 #define REG_CPM_CPCCR REG32(CPM_CPCCR)
276 #define REG_CPM_CPPCR REG32(CPM_CPPCR)
277 #define REG_CPM_I2SCDR REG32(CPM_I2SCDR)
278 #define REG_CPM_LPCDR REG32(CPM_LPCDR)
279 #define REG_CPM_MSCCDR REG32(CPM_MSCCDR)
280 #define REG_CPM_UHCCDR REG32(CPM_UHCCDR)
281
282 #define REG_CPM_LCR REG32(CPM_LCR)
283 #define REG_CPM_CLKGR REG32(CPM_CLKGR)
284 #define REG_CPM_SCR REG32(CPM_SCR)
285 #define REG_CPM_HCR REG32(CPM_HCR)
286 #define REG_CPM_HWFCR REG32(CPM_HWFCR)
287 #define REG_CPM_HRCR REG32(CPM_HRCR)
288 #define REG_CPM_HWCR REG32(CPM_HWCR)
289 #define REG_CPM_HWSR REG32(CPM_HWSR)
290 #define REG_CPM_HSPR REG32(CPM_HSPR)
291
292 #define REG_CPM_RSR REG32(CPM_RSR)
293
294
295 /* Clock Control Register */
296 #define CPM_CPCCR_I2CS (1 << 31)
297 #define CPM_CPCCR_CLKOEN (1 << 30)
298 #define CPM_CPCCR_UCS (1 << 29)
299 #define CPM_CPCCR_UDIV_BIT 23
300 #define CPM_CPCCR_UDIV_MASK (0x3f << CPM_CPCCR_UDIV_BIT)
301 #define CPM_CPCCR_CE (1 << 22)
302 #define CPM_CPCCR_PCS (1 << 21)
303 #define CPM_CPCCR_LDIV_BIT 16
304 #define CPM_CPCCR_LDIV_MASK (0x1f << CPM_CPCCR_LDIV_BIT)
305 #define CPM_CPCCR_MDIV_BIT 12
306 #define CPM_CPCCR_MDIV_MASK (0x0f << CPM_CPCCR_MDIV_BIT)
307 #define CPM_CPCCR_PDIV_BIT 8
308 #define CPM_CPCCR_PDIV_MASK (0x0f << CPM_CPCCR_PDIV_BIT)
309 #define CPM_CPCCR_HDIV_BIT 4
310 #define CPM_CPCCR_HDIV_MASK (0x0f << CPM_CPCCR_HDIV_BIT)
311 #define CPM_CPCCR_CDIV_BIT 0
312 #define CPM_CPCCR_CDIV_MASK (0x0f << CPM_CPCCR_CDIV_BIT)
313
314 /* I2S Clock Divider Register */
315 #define CPM_I2SCDR_I2SDIV_BIT 0
316 #define CPM_I2SCDR_I2SDIV_MASK (0x1ff << CPM_I2SCDR_I2SDIV_BIT)
317
318 /* LCD Pixel Clock Divider Register */
319 #define CPM_LPCDR_PIXDIV_BIT 0
320 #define CPM_LPCDR_PIXDIV_MASK (0x1ff << CPM_LPCDR_PIXDIV_BIT)
321
322 /* MSC Clock Divider Register */
323 #define CPM_MSCCDR_MSCDIV_BIT 0
324 #define CPM_MSCCDR_MSCDIV_MASK (0x1f << CPM_MSCCDR_MSCDIV_BIT)
325
326 /* PLL Control Register */
327 #define CPM_CPPCR_PLLM_BIT 23
328 #define CPM_CPPCR_PLLM_MASK (0x1ff << CPM_CPPCR_PLLM_BIT)
329 #define CPM_CPPCR_PLLN_BIT 18
330 #define CPM_CPPCR_PLLN_MASK (0x1f << CPM_CPPCR_PLLN_BIT)
331 #define CPM_CPPCR_PLLOD_BIT 16
332 #define CPM_CPPCR_PLLOD_MASK (0x03 << CPM_CPPCR_PLLOD_BIT)
333 #define CPM_CPPCR_PLLS (1 << 10)
334 #define CPM_CPPCR_PLLBP (1 << 9)
335 #define CPM_CPPCR_PLLEN (1 << 8)
336 #define CPM_CPPCR_PLLST_BIT 0
337 #define CPM_CPPCR_PLLST_MASK (0xff << CPM_CPPCR_PLLST_BIT)
338
339 /* Low Power Control Register */
340 #define CPM_LCR_DOZE_DUTY_BIT 3
341 #define CPM_LCR_DOZE_DUTY_MASK (0x1f << CPM_LCR_DOZE_DUTY_BIT)
342 #define CPM_LCR_DOZE_ON (1 << 2)
343 #define CPM_LCR_LPM_BIT 0
344 #define CPM_LCR_LPM_MASK (0x3 << CPM_LCR_LPM_BIT)
345 #define CPM_LCR_LPM_IDLE (0x0 << CPM_LCR_LPM_BIT)
346 #define CPM_LCR_LPM_SLEEP (0x1 << CPM_LCR_LPM_BIT)
347
348 /* Clock Gate Register */
349 #define CPM_CLKGR_UART1 (1 << 15)
350 #define CPM_CLKGR_UHC (1 << 14)
351 #define CPM_CLKGR_IPU (1 << 13)
352 #define CPM_CLKGR_DMAC (1 << 12)
353 #define CPM_CLKGR_UDC (1 << 11)
354 #define CPM_CLKGR_LCD (1 << 10)
355 #define CPM_CLKGR_CIM (1 << 9)
356 #define CPM_CLKGR_SADC (1 << 8)
357 #define CPM_CLKGR_MSC (1 << 7)
358 #define CPM_CLKGR_AIC1 (1 << 6)
359 #define CPM_CLKGR_AIC2 (1 << 5)
360 #define CPM_CLKGR_SSI (1 << 4)
361 #define CPM_CLKGR_I2C (1 << 3)
362 #define CPM_CLKGR_RTC (1 << 2)
363 #define CPM_CLKGR_TCU (1 << 1)
364 #define CPM_CLKGR_UART0 (1 << 0)
365
366 /* Sleep Control Register */
367 #define CPM_SCR_O1ST_BIT 8
368 #define CPM_SCR_O1ST_MASK (0xff << CPM_SCR_O1ST_BIT)
369 #define CPM_SCR_UDCPHY_ENABLE (1 << 6)
370 #define CPM_SCR_USBPHY_DISABLE (1 << 7)
371 #define CPM_SCR_OSC_ENABLE (1 << 4)
372
373 /* Hibernate Control Register */
374 #define CPM_HCR_PD (1 << 0)
375
376 /* Wakeup Filter Counter Register in Hibernate Mode */
377 #define CPM_HWFCR_TIME_BIT 0
378 #define CPM_HWFCR_TIME_MASK (0x3ff << CPM_HWFCR_TIME_BIT)
379
380 /* Reset Counter Register in Hibernate Mode */
381 #define CPM_HRCR_TIME_BIT 0
382 #define CPM_HRCR_TIME_MASK (0x7f << CPM_HRCR_TIME_BIT)
383
384 /* Wakeup Control Register in Hibernate Mode */
385 #define CPM_HWCR_WLE_LOW (0 << 2)
386 #define CPM_HWCR_WLE_HIGH (1 << 2)
387 #define CPM_HWCR_PIN_WAKEUP (1 << 1)
388 #define CPM_HWCR_RTC_WAKEUP (1 << 0)
389
390 /* Wakeup Status Register in Hibernate Mode */
391 #define CPM_HWSR_WSR_PIN (1 << 1)
392 #define CPM_HWSR_WSR_RTC (1 << 0)
393
394 /* Reset Status Register */
395 #define CPM_RSR_HR (1 << 2)
396 #define CPM_RSR_WR (1 << 1)
397 #define CPM_RSR_PR (1 << 0)
398
399
400 /*************************************************************************
401 * TCU (Timer Counter Unit)
402 *************************************************************************/
403 #define TCU_TSR (TCU_BASE + 0x1C) /* Timer Stop Register */
404 #define TCU_TSSR (TCU_BASE + 0x2C) /* Timer Stop Set Register */
405 #define TCU_TSCR (TCU_BASE + 0x3C) /* Timer Stop Clear Register */
406 #define TCU_TER (TCU_BASE + 0x10) /* Timer Counter Enable Register */
407 #define TCU_TESR (TCU_BASE + 0x14) /* Timer Counter Enable Set Register */
408 #define TCU_TECR (TCU_BASE + 0x18) /* Timer Counter Enable Clear Register */
409 #define TCU_TFR (TCU_BASE + 0x20) /* Timer Flag Register */
410 #define TCU_TFSR (TCU_BASE + 0x24) /* Timer Flag Set Register */
411 #define TCU_TFCR (TCU_BASE + 0x28) /* Timer Flag Clear Register */
412 #define TCU_TMR (TCU_BASE + 0x30) /* Timer Mask Register */
413 #define TCU_TMSR (TCU_BASE + 0x34) /* Timer Mask Set Register */
414 #define TCU_TMCR (TCU_BASE + 0x38) /* Timer Mask Clear Register */
415 #define TCU_TDFR0 (TCU_BASE + 0x40) /* Timer Data Full Register */
416 #define TCU_TDHR0 (TCU_BASE + 0x44) /* Timer Data Half Register */
417 #define TCU_TCNT0 (TCU_BASE + 0x48) /* Timer Counter Register */
418 #define TCU_TCSR0 (TCU_BASE + 0x4C) /* Timer Control Register */
419 #define TCU_TDFR1 (TCU_BASE + 0x50)
420 #define TCU_TDHR1 (TCU_BASE + 0x54)
421 #define TCU_TCNT1 (TCU_BASE + 0x58)
422 #define TCU_TCSR1 (TCU_BASE + 0x5C)
423 #define TCU_TDFR2 (TCU_BASE + 0x60)
424 #define TCU_TDHR2 (TCU_BASE + 0x64)
425 #define TCU_TCNT2 (TCU_BASE + 0x68)
426 #define TCU_TCSR2 (TCU_BASE + 0x6C)
427 #define TCU_TDFR3 (TCU_BASE + 0x70)
428 #define TCU_TDHR3 (TCU_BASE + 0x74)
429 #define TCU_TCNT3 (TCU_BASE + 0x78)
430 #define TCU_TCSR3 (TCU_BASE + 0x7C)
431 #define TCU_TDFR4 (TCU_BASE + 0x80)
432 #define TCU_TDHR4 (TCU_BASE + 0x84)
433 #define TCU_TCNT4 (TCU_BASE + 0x88)
434 #define TCU_TCSR4 (TCU_BASE + 0x8C)
435 #define TCU_TDFR5 (TCU_BASE + 0x90)
436 #define TCU_TDHR5 (TCU_BASE + 0x94)
437 #define TCU_TCNT5 (TCU_BASE + 0x98)
438 #define TCU_TCSR5 (TCU_BASE + 0x9C)
439
440 #define REG_TCU_TSR REG32(TCU_TSR)
441 #define REG_TCU_TSSR REG32(TCU_TSSR)
442 #define REG_TCU_TSCR REG32(TCU_TSCR)
443 #define REG_TCU_TER REG8(TCU_TER)
444 #define REG_TCU_TESR REG8(TCU_TESR)
445 #define REG_TCU_TECR REG8(TCU_TECR)
446 #define REG_TCU_TFR REG32(TCU_TFR)
447 #define REG_TCU_TFSR REG32(TCU_TFSR)
448 #define REG_TCU_TFCR REG32(TCU_TFCR)
449 #define REG_TCU_TMR REG32(TCU_TMR)
450 #define REG_TCU_TMSR REG32(TCU_TMSR)
451 #define REG_TCU_TMCR REG32(TCU_TMCR)
452 #define REG_TCU_TDFR0 REG16(TCU_TDFR0)
453 #define REG_TCU_TDHR0 REG16(TCU_TDHR0)
454 #define REG_TCU_TCNT0 REG16(TCU_TCNT0)
455 #define REG_TCU_TCSR0 REG16(TCU_TCSR0)
456 #define REG_TCU_TDFR1 REG16(TCU_TDFR1)
457 #define REG_TCU_TDHR1 REG16(TCU_TDHR1)
458 #define REG_TCU_TCNT1 REG16(TCU_TCNT1)
459 #define REG_TCU_TCSR1 REG16(TCU_TCSR1)
460 #define REG_TCU_TDFR2 REG16(TCU_TDFR2)
461 #define REG_TCU_TDHR2 REG16(TCU_TDHR2)
462 #define REG_TCU_TCNT2 REG16(TCU_TCNT2)
463 #define REG_TCU_TCSR2 REG16(TCU_TCSR2)
464 #define REG_TCU_TDFR3 REG16(TCU_TDFR3)
465 #define REG_TCU_TDHR3 REG16(TCU_TDHR3)
466 #define REG_TCU_TCNT3 REG16(TCU_TCNT3)
467 #define REG_TCU_TCSR3 REG16(TCU_TCSR3)
468 #define REG_TCU_TDFR4 REG16(TCU_TDFR4)
469 #define REG_TCU_TDHR4 REG16(TCU_TDHR4)
470 #define REG_TCU_TCNT4 REG16(TCU_TCNT4)
471 #define REG_TCU_TCSR4 REG16(TCU_TCSR4)
472
473 /* n = 0,1,2,3,4,5 */
474 #define TCU_TDFR(n) (TCU_BASE + (0x40 + (n)*0x10)) /* Timer Data Full Reg */
475 #define TCU_TDHR(n) (TCU_BASE + (0x44 + (n)*0x10)) /* Timer Data Half Reg */
476 #define TCU_TCNT(n) (TCU_BASE + (0x48 + (n)*0x10)) /* Timer Counter Reg */
477 #define TCU_TCSR(n) (TCU_BASE + (0x4C + (n)*0x10)) /* Timer Control Reg */
478
479 #define REG_TCU_TDFR(n) REG16(TCU_TDFR((n)))
480 #define REG_TCU_TDHR(n) REG16(TCU_TDHR((n)))
481 #define REG_TCU_TCNT(n) REG16(TCU_TCNT((n)))
482 #define REG_TCU_TCSR(n) REG16(TCU_TCSR((n)))
483
484 /* Register definitions */
485 #define TCU_TCSR_PWM_SD (1 << 9)
486 #define TCU_TCSR_PWM_INITL_HIGH (1 << 8)
487 #define TCU_TCSR_PWM_EN (1 << 7)
488 #define TCU_TCSR_PRESCALE_BIT 3
489 #define TCU_TCSR_PRESCALE_MASK (0x7 << TCU_TCSR_PRESCALE_BIT)
490 #define TCU_TCSR_PRESCALE1 (0x0 << TCU_TCSR_PRESCALE_BIT)
491 #define TCU_TCSR_PRESCALE4 (0x1 << TCU_TCSR_PRESCALE_BIT)
492 #define TCU_TCSR_PRESCALE16 (0x2 << TCU_TCSR_PRESCALE_BIT)
493 #define TCU_TCSR_PRESCALE64 (0x3 << TCU_TCSR_PRESCALE_BIT)
494 #define TCU_TCSR_PRESCALE256 (0x4 << TCU_TCSR_PRESCALE_BIT)
495 #define TCU_TCSR_PRESCALE1024 (0x5 << TCU_TCSR_PRESCALE_BIT)
496 #define TCU_TCSR_EXT_EN (1 << 2)
497 #define TCU_TCSR_RTC_EN (1 << 1)
498 #define TCU_TCSR_PCK_EN (1 << 0)
499
500 #define TCU_TER_TCEN5 (1 << 5)
501 #define TCU_TER_TCEN4 (1 << 4)
502 #define TCU_TER_TCEN3 (1 << 3)
503 #define TCU_TER_TCEN2 (1 << 2)
504 #define TCU_TER_TCEN1 (1 << 1)
505 #define TCU_TER_TCEN0 (1 << 0)
506
507 #define TCU_TESR_TCST5 (1 << 5)
508 #define TCU_TESR_TCST4 (1 << 4)
509 #define TCU_TESR_TCST3 (1 << 3)
510 #define TCU_TESR_TCST2 (1 << 2)
511 #define TCU_TESR_TCST1 (1 << 1)
512 #define TCU_TESR_TCST0 (1 << 0)
513
514 #define TCU_TECR_TCCL5 (1 << 5)
515 #define TCU_TECR_TCCL4 (1 << 4)
516 #define TCU_TECR_TCCL3 (1 << 3)
517 #define TCU_TECR_TCCL2 (1 << 2)
518 #define TCU_TECR_TCCL1 (1 << 1)
519 #define TCU_TECR_TCCL0 (1 << 0)
520
521 #define TCU_TFR_HFLAG5 (1 << 21)
522 #define TCU_TFR_HFLAG4 (1 << 20)
523 #define TCU_TFR_HFLAG3 (1 << 19)
524 #define TCU_TFR_HFLAG2 (1 << 18)
525 #define TCU_TFR_HFLAG1 (1 << 17)
526 #define TCU_TFR_HFLAG0 (1 << 16)
527 #define TCU_TFR_FFLAG5 (1 << 5)
528 #define TCU_TFR_FFLAG4 (1 << 4)
529 #define TCU_TFR_FFLAG3 (1 << 3)
530 #define TCU_TFR_FFLAG2 (1 << 2)
531 #define TCU_TFR_FFLAG1 (1 << 1)
532 #define TCU_TFR_FFLAG0 (1 << 0)
533
534 #define TCU_TFSR_HFLAG5 (1 << 21)
535 #define TCU_TFSR_HFLAG4 (1 << 20)
536 #define TCU_TFSR_HFLAG3 (1 << 19)
537 #define TCU_TFSR_HFLAG2 (1 << 18)
538 #define TCU_TFSR_HFLAG1 (1 << 17)
539 #define TCU_TFSR_HFLAG0 (1 << 16)
540 #define TCU_TFSR_FFLAG5 (1 << 5)
541 #define TCU_TFSR_FFLAG4 (1 << 4)
542 #define TCU_TFSR_FFLAG3 (1 << 3)
543 #define TCU_TFSR_FFLAG2 (1 << 2)
544 #define TCU_TFSR_FFLAG1 (1 << 1)
545 #define TCU_TFSR_FFLAG0 (1 << 0)
546
547 #define TCU_TFCR_HFLAG5 (1 << 21)
548 #define TCU_TFCR_HFLAG4 (1 << 20)
549 #define TCU_TFCR_HFLAG3 (1 << 19)
550 #define TCU_TFCR_HFLAG2 (1 << 18)
551 #define TCU_TFCR_HFLAG1 (1 << 17)
552 #define TCU_TFCR_HFLAG0 (1 << 16)
553 #define TCU_TFCR_FFLAG5 (1 << 5)
554 #define TCU_TFCR_FFLAG4 (1 << 4)
555 #define TCU_TFCR_FFLAG3 (1 << 3)
556 #define TCU_TFCR_FFLAG2 (1 << 2)
557 #define TCU_TFCR_FFLAG1 (1 << 1)
558 #define TCU_TFCR_FFLAG0 (1 << 0)
559
560 #define TCU_TMR_HMASK5 (1 << 21)
561 #define TCU_TMR_HMASK4 (1 << 20)
562 #define TCU_TMR_HMASK3 (1 << 19)
563 #define TCU_TMR_HMASK2 (1 << 18)
564 #define TCU_TMR_HMASK1 (1 << 17)
565 #define TCU_TMR_HMASK0 (1 << 16)
566 #define TCU_TMR_FMASK5 (1 << 5)
567 #define TCU_TMR_FMASK4 (1 << 4)
568 #define TCU_TMR_FMASK3 (1 << 3)
569 #define TCU_TMR_FMASK2 (1 << 2)
570 #define TCU_TMR_FMASK1 (1 << 1)
571 #define TCU_TMR_FMASK0 (1 << 0)
572
573 #define TCU_TMSR_HMST5 (1 << 21)
574 #define TCU_TMSR_HMST4 (1 << 20)
575 #define TCU_TMSR_HMST3 (1 << 19)
576 #define TCU_TMSR_HMST2 (1 << 18)
577 #define TCU_TMSR_HMST1 (1 << 17)
578 #define TCU_TMSR_HMST0 (1 << 16)
579 #define TCU_TMSR_FMST5 (1 << 5)
580 #define TCU_TMSR_FMST4 (1 << 4)
581 #define TCU_TMSR_FMST3 (1 << 3)
582 #define TCU_TMSR_FMST2 (1 << 2)
583 #define TCU_TMSR_FMST1 (1 << 1)
584 #define TCU_TMSR_FMST0 (1 << 0)
585
586 #define TCU_TMCR_HMCL5 (1 << 21)
587 #define TCU_TMCR_HMCL4 (1 << 20)
588 #define TCU_TMCR_HMCL3 (1 << 19)
589 #define TCU_TMCR_HMCL2 (1 << 18)
590 #define TCU_TMCR_HMCL1 (1 << 17)
591 #define TCU_TMCR_HMCL0 (1 << 16)
592 #define TCU_TMCR_FMCL5 (1 << 5)
593 #define TCU_TMCR_FMCL4 (1 << 4)
594 #define TCU_TMCR_FMCL3 (1 << 3)
595 #define TCU_TMCR_FMCL2 (1 << 2)
596 #define TCU_TMCR_FMCL1 (1 << 1)
597 #define TCU_TMCR_FMCL0 (1 << 0)
598
599 #define TCU_TSR_WDTS (1 << 16)
600 #define TCU_TSR_STOP5 (1 << 5)
601 #define TCU_TSR_STOP4 (1 << 4)
602 #define TCU_TSR_STOP3 (1 << 3)
603 #define TCU_TSR_STOP2 (1 << 2)
604 #define TCU_TSR_STOP1 (1 << 1)
605 #define TCU_TSR_STOP0 (1 << 0)
606
607 #define TCU_TSSR_WDTSS (1 << 16)
608 #define TCU_TSSR_STPS5 (1 << 5)
609 #define TCU_TSSR_STPS4 (1 << 4)
610 #define TCU_TSSR_STPS3 (1 << 3)
611 #define TCU_TSSR_STPS2 (1 << 2)
612 #define TCU_TSSR_STPS1 (1 << 1)
613 #define TCU_TSSR_STPS0 (1 << 0)
614
615 #define TCU_TSSR_WDTSC (1 << 16)
616 #define TCU_TSSR_STPC5 (1 << 5)
617 #define TCU_TSSR_STPC4 (1 << 4)
618 #define TCU_TSSR_STPC3 (1 << 3)
619 #define TCU_TSSR_STPC2 (1 << 2)
620 #define TCU_TSSR_STPC1 (1 << 1)
621 #define TCU_TSSR_STPC0 (1 << 0)
622
623
624 /*
625 * WDT (WatchDog Timer)
626 */
627 #define WDT_TDR (WDT_BASE + 0x00)
628 #define WDT_TCER (WDT_BASE + 0x04)
629 #define WDT_TCNT (WDT_BASE + 0x08)
630 #define WDT_TCSR (WDT_BASE + 0x0C)
631
632 #define REG_WDT_TDR REG16(WDT_TDR)
633 #define REG_WDT_TCER REG8(WDT_TCER)
634 #define REG_WDT_TCNT REG16(WDT_TCNT)
635 #define REG_WDT_TCSR REG16(WDT_TCSR)
636
637 /* Register definition */
638 #define WDT_TCSR_PRESCALE_BIT 3
639 #define WDT_TCSR_PRESCALE_MASK (0x7 << WDT_TCSR_PRESCALE_BIT)
640 #define WDT_TCSR_PRESCALE1 (0x0 << WDT_TCSR_PRESCALE_BIT)
641 #define WDT_TCSR_PRESCALE4 (0x1 << WDT_TCSR_PRESCALE_BIT)
642 #define WDT_TCSR_PRESCALE16 (0x2 << WDT_TCSR_PRESCALE_BIT)
643 #define WDT_TCSR_PRESCALE64 (0x3 << WDT_TCSR_PRESCALE_BIT)
644 #define WDT_TCSR_PRESCALE256 (0x4 << WDT_TCSR_PRESCALE_BIT)
645 #define WDT_TCSR_PRESCALE1024 (0x5 << WDT_TCSR_PRESCALE_BIT)
646 #define WDT_TCSR_EXT_EN (1 << 2)
647 #define WDT_TCSR_RTC_EN (1 << 1)
648 #define WDT_TCSR_PCK_EN (1 << 0)
649
650 #define WDT_TCER_TCEN (1 << 0)
651
652
653 /*
654 * DMAC (DMA Controller)
655 */
656
657 #define MAX_DMA_NUM 6 /* max 6 channels */
658
659 #define DMAC_DSAR(n) (DMAC_BASE + (0x00 + (n) * 0x20)) /* DMA source address */
660 #define DMAC_DTAR(n) (DMAC_BASE + (0x04 + (n) * 0x20)) /* DMA target address */
661 #define DMAC_DTCR(n) (DMAC_BASE + (0x08 + (n) * 0x20)) /* DMA transfer count */
662 #define DMAC_DRSR(n) (DMAC_BASE + (0x0c + (n) * 0x20)) /* DMA request source */
663 #define DMAC_DCCSR(n) (DMAC_BASE + (0x10 + (n) * 0x20)) /* DMA control/status */
664 #define DMAC_DCMD(n) (DMAC_BASE + (0x14 + (n) * 0x20)) /* DMA command */
665 #define DMAC_DDA(n) (DMAC_BASE + (0x18 + (n) * 0x20)) /* DMA descriptor address */
666 #define DMAC_DMACR (DMAC_BASE + 0x0300) /* DMA control register */
667 #define DMAC_DMAIPR (DMAC_BASE + 0x0304) /* DMA interrupt pending */
668 #define DMAC_DMADBR (DMAC_BASE + 0x0308) /* DMA doorbell */
669 #define DMAC_DMADBSR (DMAC_BASE + 0x030C) /* DMA doorbell set */
670
671 /* channel 0 */
672 #define DMAC_DSAR0 DMAC_DSAR(0)
673 #define DMAC_DTAR0 DMAC_DTAR(0)
674 #define DMAC_DTCR0 DMAC_DTCR(0)
675 #define DMAC_DRSR0 DMAC_DRSR(0)
676 #define DMAC_DCCSR0 DMAC_DCCSR(0)
677 #define DMAC_DCMD0 DMAC_DCMD(0)
678 #define DMAC_DDA0 DMAC_DDA(0)
679
680 /* channel 1 */
681 #define DMAC_DSAR1 DMAC_DSAR(1)
682 #define DMAC_DTAR1 DMAC_DTAR(1)
683 #define DMAC_DTCR1 DMAC_DTCR(1)
684 #define DMAC_DRSR1 DMAC_DRSR(1)
685 #define DMAC_DCCSR1 DMAC_DCCSR(1)
686 #define DMAC_DCMD1 DMAC_DCMD(1)
687 #define DMAC_DDA1 DMAC_DDA(1)
688
689 /* channel 2 */
690 #define DMAC_DSAR2 DMAC_DSAR(2)
691 #define DMAC_DTAR2 DMAC_DTAR(2)
692 #define DMAC_DTCR2 DMAC_DTCR(2)
693 #define DMAC_DRSR2 DMAC_DRSR(2)
694 #define DMAC_DCCSR2 DMAC_DCCSR(2)
695 #define DMAC_DCMD2 DMAC_DCMD(2)
696 #define DMAC_DDA2 DMAC_DDA(2)
697
698 /* channel 3 */
699 #define DMAC_DSAR3 DMAC_DSAR(3)
700 #define DMAC_DTAR3 DMAC_DTAR(3)
701 #define DMAC_DTCR3 DMAC_DTCR(3)
702 #define DMAC_DRSR3 DMAC_DRSR(3)
703 #define DMAC_DCCSR3 DMAC_DCCSR(3)
704 #define DMAC_DCMD3 DMAC_DCMD(3)
705 #define DMAC_DDA3 DMAC_DDA(3)
706
707 /* channel 4 */
708 #define DMAC_DSAR4 DMAC_DSAR(4)
709 #define DMAC_DTAR4 DMAC_DTAR(4)
710 #define DMAC_DTCR4 DMAC_DTCR(4)
711 #define DMAC_DRSR4 DMAC_DRSR(4)
712 #define DMAC_DCCSR4 DMAC_DCCSR(4)
713 #define DMAC_DCMD4 DMAC_DCMD(4)
714 #define DMAC_DDA4 DMAC_DDA(4)
715
716 /* channel 5 */
717 #define DMAC_DSAR5 DMAC_DSAR(5)
718 #define DMAC_DTAR5 DMAC_DTAR(5)
719 #define DMAC_DTCR5 DMAC_DTCR(5)
720 #define DMAC_DRSR5 DMAC_DRSR(5)
721 #define DMAC_DCCSR5 DMAC_DCCSR(5)
722 #define DMAC_DCMD5 DMAC_DCMD(5)
723 #define DMAC_DDA5 DMAC_DDA(5)
724
725 #define REG_DMAC_DSAR(n) REG32(DMAC_DSAR((n)))
726 #define REG_DMAC_DTAR(n) REG32(DMAC_DTAR((n)))
727 #define REG_DMAC_DTCR(n) REG32(DMAC_DTCR((n)))
728 #define REG_DMAC_DRSR(n) REG32(DMAC_DRSR((n)))
729 #define REG_DMAC_DCCSR(n) REG32(DMAC_DCCSR((n)))
730 #define REG_DMAC_DCMD(n) REG32(DMAC_DCMD((n)))
731 #define REG_DMAC_DDA(n) REG32(DMAC_DDA((n)))
732 #define REG_DMAC_DMACR REG32(DMAC_DMACR)
733 #define REG_DMAC_DMAIPR REG32(DMAC_DMAIPR)
734 #define REG_DMAC_DMADBR REG32(DMAC_DMADBR)
735 #define REG_DMAC_DMADBSR REG32(DMAC_DMADBSR)
736
737 /* DMA request source register */
738 #define DMAC_DRSR_RS_BIT 0
739 #define DMAC_DRSR_RS_MASK (0x1f << DMAC_DRSR_RS_BIT)
740 #define DMAC_DRSR_RS_AUTO (8 << DMAC_DRSR_RS_BIT)
741 #define DMAC_DRSR_RS_UART0OUT (20 << DMAC_DRSR_RS_BIT)
742 #define DMAC_DRSR_RS_UART0IN (21 << DMAC_DRSR_RS_BIT)
743 #define DMAC_DRSR_RS_SSIOUT (22 << DMAC_DRSR_RS_BIT)
744 #define DMAC_DRSR_RS_SSIIN (23 << DMAC_DRSR_RS_BIT)
745 #define DMAC_DRSR_RS_AICOUT (24 << DMAC_DRSR_RS_BIT)
746 #define DMAC_DRSR_RS_AICIN (25 << DMAC_DRSR_RS_BIT)
747 #define DMAC_DRSR_RS_MSCOUT (26 << DMAC_DRSR_RS_BIT)
748 #define DMAC_DRSR_RS_MSCIN (27 << DMAC_DRSR_RS_BIT)
749 #define DMAC_DRSR_RS_TCU (28 << DMAC_DRSR_RS_BIT)
750 #define DMAC_DRSR_RS_SADC (29 << DMAC_DRSR_RS_BIT)
751 #define DMAC_DRSR_RS_SLCD (30 << DMAC_DRSR_RS_BIT)
752
753 /* DMA channel control/status register */
754 #define DMAC_DCCSR_NDES (1 << 31) /* descriptor (0) or not (1) ? */
755 #define DMAC_DCCSR_CDOA_BIT 16 /* copy of DMA offset address */
756 #define DMAC_DCCSR_CDOA_MASK (0xff << DMAC_DCCSR_CDOA_BIT)
757 #define DMAC_DCCSR_INV (1 << 6) /* descriptor invalid */
758 #define DMAC_DCCSR_AR (1 << 4) /* address error */
759 #define DMAC_DCCSR_TT (1 << 3) /* transfer terminated */
760 #define DMAC_DCCSR_HLT (1 << 2) /* DMA halted */
761 #define DMAC_DCCSR_CT (1 << 1) /* count terminated */
762 #define DMAC_DCCSR_EN (1 << 0) /* channel enable bit */
763
764 /* DMA channel command register */
765 #define DMAC_DCMD_SAI (1 << 23) /* source address increment */
766 #define DMAC_DCMD_DAI (1 << 22) /* dest address increment */
767 #define DMAC_DCMD_RDIL_BIT 16 /* request detection interval length */
768 #define DMAC_DCMD_RDIL_MASK (0x0f << DMAC_DCMD_RDIL_BIT)
769 #define DMAC_DCMD_RDIL_IGN (0 << DMAC_DCMD_RDIL_BIT)
770 #define DMAC_DCMD_RDIL_2 (1 << DMAC_DCMD_RDIL_BIT)
771 #define DMAC_DCMD_RDIL_4 (2 << DMAC_DCMD_RDIL_BIT)
772 #define DMAC_DCMD_RDIL_8 (3 << DMAC_DCMD_RDIL_BIT)
773 #define DMAC_DCMD_RDIL_12 (4 << DMAC_DCMD_RDIL_BIT)
774 #define DMAC_DCMD_RDIL_16 (5 << DMAC_DCMD_RDIL_BIT)
775 #define DMAC_DCMD_RDIL_20 (6 << DMAC_DCMD_RDIL_BIT)
776 #define DMAC_DCMD_RDIL_24 (7 << DMAC_DCMD_RDIL_BIT)
777 #define DMAC_DCMD_RDIL_28 (8 << DMAC_DCMD_RDIL_BIT)
778 #define DMAC_DCMD_RDIL_32 (9 << DMAC_DCMD_RDIL_BIT)
779 #define DMAC_DCMD_RDIL_48 (10 << DMAC_DCMD_RDIL_BIT)
780 #define DMAC_DCMD_RDIL_60 (11 << DMAC_DCMD_RDIL_BIT)
781 #define DMAC_DCMD_RDIL_64 (12 << DMAC_DCMD_RDIL_BIT)
782 #define DMAC_DCMD_RDIL_124 (13 << DMAC_DCMD_RDIL_BIT)
783 #define DMAC_DCMD_RDIL_128 (14 << DMAC_DCMD_RDIL_BIT)
784 #define DMAC_DCMD_RDIL_200 (15 << DMAC_DCMD_RDIL_BIT)
785 #define DMAC_DCMD_SWDH_BIT 14 /* source port width */
786 #define DMAC_DCMD_SWDH_MASK (0x03 << DMAC_DCMD_SWDH_BIT)
787 #define DMAC_DCMD_SWDH_32 (0 << DMAC_DCMD_SWDH_BIT)
788 #define DMAC_DCMD_SWDH_8 (1 << DMAC_DCMD_SWDH_BIT)
789 #define DMAC_DCMD_SWDH_16 (2 << DMAC_DCMD_SWDH_BIT)
790 #define DMAC_DCMD_DWDH_BIT 12 /* dest port width */
791 #define DMAC_DCMD_DWDH_MASK (0x03 << DMAC_DCMD_DWDH_BIT)
792 #define DMAC_DCMD_DWDH_32 (0 << DMAC_DCMD_DWDH_BIT)
793 #define DMAC_DCMD_DWDH_8 (1 << DMAC_DCMD_DWDH_BIT)
794 #define DMAC_DCMD_DWDH_16 (2 << DMAC_DCMD_DWDH_BIT)
795 #define DMAC_DCMD_DS_BIT 8 /* transfer data size of a data unit */
796 #define DMAC_DCMD_DS_MASK (0x07 << DMAC_DCMD_DS_BIT)
797 #define DMAC_DCMD_DS_32BIT (0 << DMAC_DCMD_DS_BIT)
798 #define DMAC_DCMD_DS_8BIT (1 << DMAC_DCMD_DS_BIT)
799 #define DMAC_DCMD_DS_16BIT (2 << DMAC_DCMD_DS_BIT)
800 #define DMAC_DCMD_DS_16BYTE (3 << DMAC_DCMD_DS_BIT)
801 #define DMAC_DCMD_DS_32BYTE (4 << DMAC_DCMD_DS_BIT)
802 #define DMAC_DCMD_TM (1 << 7) /* transfer mode: 0-single 1-block */
803 #define DMAC_DCMD_DES_V (1 << 4) /* descriptor valid flag */
804 #define DMAC_DCMD_DES_VM (1 << 3) /* descriptor valid mask: 1:support V-bit */
805 #define DMAC_DCMD_DES_VIE (1 << 2) /* DMA valid error interrupt enable */
806 #define DMAC_DCMD_TIE (1 << 1) /* DMA transfer interrupt enable */
807 #define DMAC_DCMD_LINK (1 << 0) /* descriptor link enable */
808
809 /* DMA descriptor address register */
810 #define DMAC_DDA_BASE_BIT 12 /* descriptor base address */
811 #define DMAC_DDA_BASE_MASK (0x0fffff << DMAC_DDA_BASE_BIT)
812 #define DMAC_DDA_OFFSET_BIT 4 /* descriptor offset address */
813 #define DMAC_DDA_OFFSET_MASK (0x0ff << DMAC_DDA_OFFSET_BIT)
814
815 /* DMA control register */
816 #define DMAC_DMACR_PR_BIT 8 /* channel priority mode */
817 #define DMAC_DMACR_PR_MASK (0x03 << DMAC_DMACR_PR_BIT)
818 #define DMAC_DMACR_PR_012345 (0 << DMAC_DMACR_PR_BIT)
819 #define DMAC_DMACR_PR_023145 (1 << DMAC_DMACR_PR_BIT)
820 #define DMAC_DMACR_PR_201345 (2 << DMAC_DMACR_PR_BIT)
821 #define DMAC_DMACR_PR_RR (3 << DMAC_DMACR_PR_BIT) /* round robin */
822 #define DMAC_DMACR_HLT (1 << 3) /* DMA halt flag */
823 #define DMAC_DMACR_AR (1 << 2) /* address error flag */
824 #define DMAC_DMACR_DMAE (1 << 0) /* DMA enable bit */
825
826 /* DMA doorbell register */
827 #define DMAC_DMADBR_DB5 (1 << 5) /* doorbell for channel 5 */
828 #define DMAC_DMADBR_DB4 (1 << 5) /* doorbell for channel 4 */
829 #define DMAC_DMADBR_DB3 (1 << 5) /* doorbell for channel 3 */
830 #define DMAC_DMADBR_DB2 (1 << 5) /* doorbell for channel 2 */
831 #define DMAC_DMADBR_DB1 (1 << 5) /* doorbell for channel 1 */
832 #define DMAC_DMADBR_DB0 (1 << 5) /* doorbell for channel 0 */
833
834 /* DMA doorbell set register */
835 #define DMAC_DMADBSR_DBS5 (1 << 5) /* enable doorbell for channel 5 */
836 #define DMAC_DMADBSR_DBS4 (1 << 5) /* enable doorbell for channel 4 */
837 #define DMAC_DMADBSR_DBS3 (1 << 5) /* enable doorbell for channel 3 */
838 #define DMAC_DMADBSR_DBS2 (1 << 5) /* enable doorbell for channel 2 */
839 #define DMAC_DMADBSR_DBS1 (1 << 5) /* enable doorbell for channel 1 */
840 #define DMAC_DMADBSR_DBS0 (1 << 5) /* enable doorbell for channel 0 */
841
842 /* DMA interrupt pending register */
843 #define DMAC_DMAIPR_CIRQ5 (1 << 5) /* irq pending status for channel 5 */
844 #define DMAC_DMAIPR_CIRQ4 (1 << 4) /* irq pending status for channel 4 */
845 #define DMAC_DMAIPR_CIRQ3 (1 << 3) /* irq pending status for channel 3 */
846 #define DMAC_DMAIPR_CIRQ2 (1 << 2) /* irq pending status for channel 2 */
847 #define DMAC_DMAIPR_CIRQ1 (1 << 1) /* irq pending status for channel 1 */
848 #define DMAC_DMAIPR_CIRQ0 (1 << 0) /* irq pending status for channel 0 */
849
850
851 /*************************************************************************
852 * GPIO (General-Purpose I/O Ports)
853 *************************************************************************/
854 #define MAX_GPIO_NUM 128
855
856 /* = 0,1,2,3 */
857 #define GPIO_PXPIN(n) (GPIO_BASE + (0x00 + (n)*0x100)) /* PIN Level Register */
858 #define GPIO_PXDAT(n) (GPIO_BASE + (0x10 + (n)*0x100)) /* Port Data Register */
859 #define GPIO_PXDATS(n) (GPIO_BASE + (0x14 + (n)*0x100)) /* Port Data Set Register */
860 #define GPIO_PXDATC(n) (GPIO_BASE + (0x18 + (n)*0x100)) /* Port Data Clear Register */
861 #define GPIO_PXIM(n) (GPIO_BASE + (0x20 + (n)*0x100)) /* Interrupt Mask Register */
862 #define GPIO_PXIMS(n) (GPIO_BASE + (0x24 + (n)*0x100)) /* Interrupt Mask Set Reg */
863 #define GPIO_PXIMC(n) (GPIO_BASE + (0x28 + (n)*0x100)) /* Interrupt Mask Clear Reg */
864 #define GPIO_PXPE(n) (GPIO_BASE + (0x30 + (n)*0x100)) /* Pull Enable Register */
865 #define GPIO_PXPES(n) (GPIO_BASE + (0x34 + (n)*0x100)) /* Pull Enable Set Reg. */
866 #define GPIO_PXPEC(n) (GPIO_BASE + (0x38 + (n)*0x100)) /* Pull Enable Clear Reg. */
867 #define GPIO_PXFUN(n) (GPIO_BASE + (0x40 + (n)*0x100)) /* Function Register */
868 #define GPIO_PXFUNS(n) (GPIO_BASE + (0x44 + (n)*0x100)) /* Function Set Register */
869 #define GPIO_PXFUNC(n) (GPIO_BASE + (0x48 + (n)*0x100)) /* Function Clear Register */
870 #define GPIO_PXSEL(n) (GPIO_BASE + (0x50 + (n)*0x100)) /* Select Register */
871 #define GPIO_PXSELS(n) (GPIO_BASE + (0x54 + (n)*0x100)) /* Select Set Register */
872 #define GPIO_PXSELC(n) (GPIO_BASE + (0x58 + (n)*0x100)) /* Select Clear Register */
873 #define GPIO_PXDIR(n) (GPIO_BASE + (0x60 + (n)*0x100)) /* Direction Register */
874 #define GPIO_PXDIRS(n) (GPIO_BASE + (0x64 + (n)*0x100)) /* Direction Set Register */
875 #define GPIO_PXDIRC(n) (GPIO_BASE + (0x68 + (n)*0x100)) /* Direction Clear Register */
876 #define GPIO_PXTRG(n) (GPIO_BASE + (0x70 + (n)*0x100)) /* Trigger Register */
877 #define GPIO_PXTRGS(n) (GPIO_BASE + (0x74 + (n)*0x100)) /* Trigger Set Register */
878 #define GPIO_PXTRGC(n) (GPIO_BASE + (0x78 + (n)*0x100)) /* Trigger Set Register */
879 #define GPIO_PXFLG(n) (GPIO_BASE + (0x80 + (n)*0x100)) /* Port Flag Register */
880 #define GPIO_PXFLGC(n) (GPIO_BASE + (0x14 + (n)*0x100)) /* Port Flag clear Register */
881
882 #define REG_GPIO_PXPIN(n) REG32(GPIO_PXPIN((n))) /* PIN level */
883 #define REG_GPIO_PXDAT(n) REG32(GPIO_PXDAT((n))) /* 1: interrupt pending */
884 #define REG_GPIO_PXDATS(n) REG32(GPIO_PXDATS((n)))
885 #define REG_GPIO_PXDATC(n) REG32(GPIO_PXDATC((n)))
886 #define REG_GPIO_PXIM(n) REG32(GPIO_PXIM((n))) /* 1: mask pin interrupt */
887 #define REG_GPIO_PXIMS(n) REG32(GPIO_PXIMS((n)))
888 #define REG_GPIO_PXIMC(n) REG32(GPIO_PXIMC((n)))
889 #define REG_GPIO_PXPE(n) REG32(GPIO_PXPE((n))) /* 1: disable pull up/down */
890 #define REG_GPIO_PXPES(n) REG32(GPIO_PXPES((n)))
891 #define REG_GPIO_PXPEC(n) REG32(GPIO_PXPEC((n)))
892 #define REG_GPIO_PXFUN(n) REG32(GPIO_PXFUN((n))) /* 0:GPIO or intr, 1:FUNC */
893 #define REG_GPIO_PXFUNS(n) REG32(GPIO_PXFUNS((n)))
894 #define REG_GPIO_PXFUNC(n) REG32(GPIO_PXFUNC((n)))
895 #define REG_GPIO_PXSEL(n) REG32(GPIO_PXSEL((n))) /* 0:GPIO/Fun0,1:intr/fun1*/
896 #define REG_GPIO_PXSELS(n) REG32(GPIO_PXSELS((n)))
897 #define REG_GPIO_PXSELC(n) REG32(GPIO_PXSELC((n)))
898 #define REG_GPIO_PXDIR(n) REG32(GPIO_PXDIR((n))) /* 0:input/low-level-trig/falling-edge-trig, 1:output/high-level-trig/rising-edge-trig */
899 #define REG_GPIO_PXDIRS(n) REG32(GPIO_PXDIRS((n)))
900 #define REG_GPIO_PXDIRC(n) REG32(GPIO_PXDIRC((n)))
901 #define REG_GPIO_PXTRG(n) REG32(GPIO_PXTRG((n))) /* 0:level-trigger, 1:edge-trigger */
902 #define REG_GPIO_PXTRGS(n) REG32(GPIO_PXTRGS((n)))
903 #define REG_GPIO_PXTRGC(n) REG32(GPIO_PXTRGC((n)))
904 #define REG_GPIO_PXFLG(n) REG32(GPIO_PXFLG((n))) /* interrupt flag */
905 #define REG_GPIO_PXFLGC(n) REG32(GPIO_PXFLGC((n))) /* interrupt flag */
906
907
908 /*************************************************************************
909 * UART
910 *************************************************************************/
911
912 #define IRDA_BASE UART0_BASE
913 #define UART_BASE UART0_BASE
914 #define UART_OFF 0x1000
915
916 /* Register Offset */
917 #define OFF_RDR (0x00) /* R 8b H'xx */
918 #define OFF_TDR (0x00) /* W 8b H'xx */
919 #define OFF_DLLR (0x00) /* RW 8b H'00 */
920 #define OFF_DLHR (0x04) /* RW 8b H'00 */
921 #define OFF_IER (0x04) /* RW 8b H'00 */
922 #define OFF_ISR (0x08) /* R 8b H'01 */
923 #define OFF_FCR (0x08) /* W 8b H'00 */
924 #define OFF_LCR (0x0C) /* RW 8b H'00 */
925 #define OFF_MCR (0x10) /* RW 8b H'00 */
926 #define OFF_LSR (0x14) /* R 8b H'00 */
927 #define OFF_MSR (0x18) /* R 8b H'00 */
928 #define OFF_SPR (0x1C) /* RW 8b H'00 */
929 #define OFF_SIRCR (0x20) /* RW 8b H'00, UART0 */
930 #define OFF_UMR (0x24) /* RW 8b H'00, UART M Register */
931 #define OFF_UACR (0x28) /* RW 8b H'00, UART Add Cycle Register */
932
933 /* Register Address */
934 #define UART0_RDR (UART0_BASE + OFF_RDR)
935 #define UART0_TDR (UART0_BASE + OFF_TDR)
936 #define UART0_DLLR (UART0_BASE + OFF_DLLR)
937 #define UART0_DLHR (UART0_BASE + OFF_DLHR)
938 #define UART0_IER (UART0_BASE + OFF_IER)
939 #define UART0_ISR (UART0_BASE + OFF_ISR)
940 #define UART0_FCR (UART0_BASE + OFF_FCR)
941 #define UART0_LCR (UART0_BASE + OFF_LCR)
942 #define UART0_MCR (UART0_BASE + OFF_MCR)
943 #define UART0_LSR (UART0_BASE + OFF_LSR)
944 #define UART0_MSR (UART0_BASE + OFF_MSR)
945 #define UART0_SPR (UART0_BASE + OFF_SPR)
946 #define UART0_SIRCR (UART0_BASE + OFF_SIRCR)
947 #define UART0_UMR (UART0_BASE + OFF_UMR)
948 #define UART0_UACR (UART0_BASE + OFF_UACR)
949
950 /*
951 * Define macros for UART_IER
952 * UART Interrupt Enable Register
953 */
954 #define UART_IER_RIE (1 << 0) /* 0: receive fifo "full" interrupt disable */
955 #define UART_IER_TIE (1 << 1) /* 0: transmit fifo "empty" interrupt disable */
956 #define UART_IER_RLIE (1 << 2) /* 0: receive line status interrupt disable */
957 #define UART_IER_MIE (1 << 3) /* 0: modem status interrupt disable */
958 #define UART_IER_RTIE (1 << 4) /* 0: receive timeout interrupt disable */
959
960 /*
961 * Define macros for UART_ISR
962 * UART Interrupt Status Register
963 */
964 #define UART_ISR_IP (1 << 0) /* 0: interrupt is pending 1: no interrupt */
965 #define UART_ISR_IID (7 << 1) /* Source of Interrupt */
966 #define UART_ISR_IID_MSI (0 << 1) /* Modem status interrupt */
967 #define UART_ISR_IID_THRI (1 << 1) /* Transmitter holding register empty */
968 #define UART_ISR_IID_RDI (2 << 1) /* Receiver data interrupt */
969 #define UART_ISR_IID_RLSI (3 << 1) /* Receiver line status interrupt */
970 #define UART_ISR_FFMS (3 << 6) /* FIFO mode select, set when UART_FCR.FE is set to 1 */
971 #define UART_ISR_FFMS_NO_FIFO (0 << 6)
972 #define UART_ISR_FFMS_FIFO_MODE (3 << 6)
973
974 /*
975 * Define macros for UART_FCR
976 * UART FIFO Control Register
977 */
978 #define UART_FCR_FE (1 << 0) /* 0: non-FIFO mode 1: FIFO mode */
979 #define UART_FCR_RFLS (1 << 1) /* write 1 to flush receive FIFO */
980 #define UART_FCR_TFLS (1 << 2) /* write 1 to flush transmit FIFO */
981 #define UART_FCR_DMS (1 << 3) /* 0: disable DMA mode */
982 #define UART_FCR_UUE (1 << 4) /* 0: disable UART */
983 #define UART_FCR_RTRG (3 << 6) /* Receive FIFO Data Trigger */
984 #define UART_FCR_RTRG_1 (0 << 6)
985 #define UART_FCR_RTRG_4 (1 << 6)
986 #define UART_FCR_RTRG_8 (2 << 6)
987 #define UART_FCR_RTRG_15 (3 << 6)
988
989 /*
990 * Define macros for UART_LCR
991 * UART Line Control Register
992 */
993 #define UART_LCR_WLEN (3 << 0) /* word length */
994 #define UART_LCR_WLEN_5 (0 << 0)
995 #define UART_LCR_WLEN_6 (1 << 0)
996 #define UART_LCR_WLEN_7 (2 << 0)
997 #define UART_LCR_WLEN_8 (3 << 0)
998 #define UART_LCR_STOP (1 << 2) /* 0: 1 stop bit when word length is 5,6,7,8
999 1: 1.5 stop bits when 5; 2 stop bits when 6,7,8 */
1000 #define UART_LCR_STOP_1 (0 << 2) /* 0: 1 stop bit when word length is 5,6,7,8
1001 1: 1.5 stop bits when 5; 2 stop bits when 6,7,8 */
1002 #define UART_LCR_STOP_2 (1 << 2) /* 0: 1 stop bit when word length is 5,6,7,8
1003 1: 1.5 stop bits when 5; 2 stop bits when 6,7,8 */
1004
1005 #define UART_LCR_PE (1 << 3) /* 0: parity disable */
1006 #define UART_LCR_PROE (1 << 4) /* 0: even parity 1: odd parity */
1007 #define UART_LCR_SPAR (1 << 5) /* 0: sticky parity disable */
1008 #define UART_LCR_SBRK (1 << 6) /* write 0 normal, write 1 send break */
1009 #define UART_LCR_DLAB (1 << 7) /* 0: access UART_RDR/TDR/IER 1: access UART_DLLR/DLHR */
1010
1011 /*
1012 * Define macros for UART_LSR
1013 * UART Line Status Register
1014 */
1015 #define UART_LSR_DR (1 << 0) /* 0: receive FIFO is empty 1: receive data is ready */
1016 #define UART_LSR_ORER (1 << 1) /* 0: no overrun error */
1017 #define UART_LSR_PER (1 << 2) /* 0: no parity error */
1018 #define UART_LSR_FER (1 << 3) /* 0; no framing error */
1019 #define UART_LSR_BRK (1 << 4) /* 0: no break detected 1: receive a break signal */
1020 #define UART_LSR_TDRQ (1 << 5) /* 1: transmit FIFO half "empty" */
1021 #define UART_LSR_TEMT (1 << 6) /* 1: transmit FIFO and shift registers empty */
1022 #define UART_LSR_RFER (1 << 7) /* 0: no receive error 1: receive error in FIFO mode */
1023
1024 /*
1025 * Define macros for UART_MCR
1026 * UART Modem Control Register
1027 */
1028 #define UART_MCR_DTR (1 << 0) /* 0: DTR_ ouput high */
1029 #define UART_MCR_RTS (1 << 1) /* 0: RTS_ output high */
1030 #define UART_MCR_OUT1 (1 << 2) /* 0: UART_MSR.RI is set to 0 and RI_ input high */
1031 #define UART_MCR_OUT2 (1 << 3) /* 0: UART_MSR.DCD is set to 0 and DCD_ input high */
1032 #define UART_MCR_LOOP (1 << 4) /* 0: normal 1: loopback mode */
1033 #define UART_MCR_MCE (1 << 7) /* 0: modem function is disable */
1034
1035 /*
1036 * Define macros for UART_MSR
1037 * UART Modem Status Register
1038 */
1039 #define UART_MSR_DCTS (1 << 0) /* 0: no change on CTS_ pin since last read of UART_MSR */
1040 #define UART_MSR_DDSR (1 << 1) /* 0: no change on DSR_ pin since last read of UART_MSR */
1041 #define UART_MSR_DRI (1 << 2) /* 0: no change on RI_ pin since last read of UART_MSR */
1042 #define UART_MSR_DDCD (1 << 3) /* 0: no change on DCD_ pin since last read of UART_MSR */
1043 #define UART_MSR_CTS (1 << 4) /* 0: CTS_ pin is high */
1044 #define UART_MSR_DSR (1 << 5) /* 0: DSR_ pin is high */
1045 #define UART_MSR_RI (1 << 6) /* 0: RI_ pin is high */
1046 #define UART_MSR_DCD (1 << 7) /* 0: DCD_ pin is high */
1047
1048 /*
1049 * Define macros for SIRCR
1050 * Slow IrDA Control Register
1051 */
1052 #define SIRCR_TSIRE (1 << 0) /* 0: transmitter is in UART mode 1: IrDA mode */
1053 #define SIRCR_RSIRE (1 << 1) /* 0: receiver is in UART mode 1: IrDA mode */
1054 #define SIRCR_TPWS (1 << 2) /* 0: transmit 0 pulse width is 3/16 of bit length
1055 1: 0 pulse width is 1.6us for 115.2Kbps */
1056 #define SIRCR_TXPL (1 << 3) /* 0: encoder generates a positive pulse for 0 */
1057 #define SIRCR_RXPL (1 << 4) /* 0: decoder interprets positive pulse as 0 */
1058
1059
1060 /*************************************************************************
1061 * AIC (AC97/I2S Controller)
1062 *************************************************************************/
1063 #define AIC_FR (AIC_BASE + 0x000)
1064 #define AIC_CR (AIC_BASE + 0x004)
1065 #define AIC_ACCR1 (AIC_BASE + 0x008)
1066 #define AIC_ACCR2 (AIC_BASE + 0x00C)
1067 #define AIC_I2SCR (AIC_BASE + 0x010)
1068 #define AIC_SR (AIC_BASE + 0x014)
1069 #define AIC_ACSR (AIC_BASE + 0x018)
1070 #define AIC_I2SSR (AIC_BASE + 0x01C)
1071 #define AIC_ACCAR (AIC_BASE + 0x020)
1072 #define AIC_ACCDR (AIC_BASE + 0x024)
1073 #define AIC_ACSAR (AIC_BASE + 0x028)
1074 #define AIC_ACSDR (AIC_BASE + 0x02C)
1075 #define AIC_I2SDIV (AIC_BASE + 0x030)
1076 #define AIC_DR (AIC_BASE + 0x034)
1077
1078 #define REG_AIC_FR REG32(AIC_FR)
1079 #define REG_AIC_CR REG32(AIC_CR)
1080 #define REG_AIC_ACCR1 REG32(AIC_ACCR1)
1081 #define REG_AIC_ACCR2 REG32(AIC_ACCR2)
1082 #define REG_AIC_I2SCR REG32(AIC_I2SCR)
1083 #define REG_AIC_SR REG32(AIC_SR)
1084 #define REG_AIC_ACSR REG32(AIC_ACSR)
1085 #define REG_AIC_I2SSR REG32(AIC_I2SSR)
1086 #define REG_AIC_ACCAR REG32(AIC_ACCAR)
1087 #define REG_AIC_ACCDR REG32(AIC_ACCDR)
1088 #define REG_AIC_ACSAR REG32(AIC_ACSAR)
1089 #define REG_AIC_ACSDR REG32(AIC_ACSDR)
1090 #define REG_AIC_I2SDIV REG32(AIC_I2SDIV)
1091 #define REG_AIC_DR REG32(AIC_DR)
1092
1093 /* AIC Controller Configuration Register (AIC_FR) */
1094
1095 #define AIC_FR_RFTH_BIT 12 /* Receive FIFO Threshold */
1096 #define AIC_FR_RFTH_MASK (0xf << AIC_FR_RFTH_BIT)
1097 #define AIC_FR_TFTH_BIT 8 /* Transmit FIFO Threshold */
1098 #define AIC_FR_TFTH_MASK (0xf << AIC_FR_TFTH_BIT)
1099 #define AIC_FR_ICDC (1 << 5) /* External(0) or Internal CODEC(1) */
1100 #define AIC_FR_AUSEL (1 << 4) /* AC97(0) or I2S/MSB-justified(1) */
1101 #define AIC_FR_RST (1 << 3) /* AIC registers reset */
1102 #define AIC_FR_BCKD (1 << 2) /* I2S BIT_CLK direction, 0:input,1:output */
1103 #define AIC_FR_SYNCD (1 << 1) /* I2S SYNC direction, 0:input,1:output */
1104 #define AIC_FR_ENB (1 << 0) /* AIC enable bit */
1105
1106 /* AIC Controller Common Control Register (AIC_CR) */
1107
1108 #define AIC_CR_OSS_BIT 19 /* Output Sample Size from memory (AIC V2 only) */
1109 #define AIC_CR_OSS_MASK (0x7 << AIC_CR_OSS_BIT)
1110 #define AIC_CR_OSS_8BIT (0x0 << AIC_CR_OSS_BIT)
1111 #define AIC_CR_OSS_16BIT (0x1 << AIC_CR_OSS_BIT)
1112 #define AIC_CR_OSS_18BIT (0x2 << AIC_CR_OSS_BIT)
1113 #define AIC_CR_OSS_20BIT (0x3 << AIC_CR_OSS_BIT)
1114 #define AIC_CR_OSS_24BIT (0x4 << AIC_CR_OSS_BIT)
1115 #define AIC_CR_ISS_BIT 16 /* Input Sample Size from memory (AIC V2 only) */
1116 #define AIC_CR_ISS_MASK (0x7 << AIC_CR_ISS_BIT)
1117 #define AIC_CR_ISS_8BIT (0x0 << AIC_CR_ISS_BIT)
1118 #define AIC_CR_ISS_16BIT (0x1 << AIC_CR_ISS_BIT)
1119 #define AIC_CR_ISS_18BIT (0x2 << AIC_CR_ISS_BIT)
1120 #define AIC_CR_ISS_20BIT (0x3 << AIC_CR_ISS_BIT)
1121 #define AIC_CR_ISS_24BIT (0x4 << AIC_CR_ISS_BIT)
1122 #define AIC_CR_RDMS (1 << 15) /* Receive DMA enable */
1123 #define AIC_CR_TDMS (1 << 14) /* Transmit DMA enable */
1124 #define AIC_CR_M2S (1 << 11) /* Mono to Stereo enable */
1125 #define AIC_CR_ENDSW (1 << 10) /* Endian switch enable */
1126 #define AIC_CR_AVSTSU (1 << 9) /* Signed <-> Unsigned toggle enable */
1127 #define AIC_CR_FLUSH (1 << 8) /* Flush FIFO */
1128 #define AIC_CR_EROR (1 << 6) /* Enable ROR interrupt */
1129 #define AIC_CR_ETUR (1 << 5) /* Enable TUR interrupt */
1130 #define AIC_CR_ERFS (1 << 4) /* Enable RFS interrupt */
1131 #define AIC_CR_ETFS (1 << 3) /* Enable TFS interrupt */
1132 #define AIC_CR_ENLBF (1 << 2) /* Enable Loopback Function */
1133 #define AIC_CR_ERPL (1 << 1) /* Enable Playback Function */
1134 #define AIC_CR_EREC (1 << 0) /* Enable Record Function */
1135
1136 /* AIC Controller AC-link Control Register 1 (AIC_ACCR1) */
1137
1138 #define AIC_ACCR1_RS_BIT 16 /* Receive Valid Slots */
1139 #define AIC_ACCR1_RS_MASK (0x3ff << AIC_ACCR1_RS_BIT)
1140 #define AIC_ACCR1_RS_SLOT12 (1 << 25) /* Slot 12 valid bit */
1141 #define AIC_ACCR1_RS_SLOT11 (1 << 24) /* Slot 11 valid bit */
1142 #define AIC_ACCR1_RS_SLOT10 (1 << 23) /* Slot 10 valid bit */
1143 #define AIC_ACCR1_RS_SLOT9 (1 << 22) /* Slot 9 valid bit, LFE */
1144 #define AIC_ACCR1_RS_SLOT8 (1 << 21) /* Slot 8 valid bit, Surround Right */
1145 #define AIC_ACCR1_RS_SLOT7 (1 << 20) /* Slot 7 valid bit, Surround Left */
1146 #define AIC_ACCR1_RS_SLOT6 (1 << 19) /* Slot 6 valid bit, PCM Center */
1147 #define AIC_ACCR1_RS_SLOT5 (1 << 18) /* Slot 5 valid bit */
1148 #define AIC_ACCR1_RS_SLOT4 (1 << 17) /* Slot 4 valid bit, PCM Right */
1149 #define AIC_ACCR1_RS_SLOT3 (1 << 16) /* Slot 3 valid bit, PCM Left */
1150 #define AIC_ACCR1_XS_BIT 0 /* Transmit Valid Slots */
1151 #define AIC_ACCR1_XS_MASK (0x3ff << AIC_ACCR1_XS_BIT)
1152 #define AIC_ACCR1_XS_SLOT12 (1 << 9) /* Slot 12 valid bit */
1153 #define AIC_ACCR1_XS_SLOT11 (1 << 8) /* Slot 11 valid bit */
1154 #define AIC_ACCR1_XS_SLOT10 (1 << 7) /* Slot 10 valid bit */
1155 #define AIC_ACCR1_XS_SLOT9 (1 << 6) /* Slot 9 valid bit, LFE */
1156 #define AIC_ACCR1_XS_SLOT8 (1 << 5) /* Slot 8 valid bit, Surround Right */
1157 #define AIC_ACCR1_XS_SLOT7 (1 << 4) /* Slot 7 valid bit, Surround Left */
1158 #define AIC_ACCR1_XS_SLOT6 (1 << 3) /* Slot 6 valid bit, PCM Center */
1159 #define AIC_ACCR1_XS_SLOT5 (1 << 2) /* Slot 5 valid bit */
1160 #define AIC_ACCR1_XS_SLOT4 (1 << 1) /* Slot 4 valid bit, PCM Right */
1161 #define AIC_ACCR1_XS_SLOT3 (1 << 0) /* Slot 3 valid bit, PCM Left */
1162
1163 /* AIC Controller AC-link Control Register 2 (AIC_ACCR2) */
1164
1165 #define AIC_ACCR2_ERSTO (1 << 18) /* Enable RSTO interrupt */
1166 #define AIC_ACCR2_ESADR (1 << 17) /* Enable SADR interrupt */
1167 #define AIC_ACCR2_ECADT (1 << 16) /* Enable CADT interrupt */
1168 #define AIC_ACCR2_OASS_BIT 8 /* Output Sample Size for AC-link */
1169 #define AIC_ACCR2_OASS_MASK (0x3 << AIC_ACCR2_OASS_BIT)
1170 #define AIC_ACCR2_OASS_20BIT (0 << AIC_ACCR2_OASS_BIT) /* Output Audio Sample Size is 20-bit */
1171 #define AIC_ACCR2_OASS_18BIT (1 << AIC_ACCR2_OASS_BIT) /* Output Audio Sample Size is 18-bit */
1172 #define AIC_ACCR2_OASS_16BIT (2 << AIC_ACCR2_OASS_BIT) /* Output Audio Sample Size is 16-bit */
1173 #define AIC_ACCR2_OASS_8BIT (3 << AIC_ACCR2_OASS_BIT) /* Output Audio Sample Size is 8-bit */
1174 #define AIC_ACCR2_IASS_BIT 6 /* Output Sample Size for AC-link */
1175 #define AIC_ACCR2_IASS_MASK (0x3 << AIC_ACCR2_IASS_BIT)
1176 #define AIC_ACCR2_IASS_20BIT (0 << AIC_ACCR2_IASS_BIT) /* Input Audio Sample Size is 20-bit */
1177 #define AIC_ACCR2_IASS_18BIT (1 << AIC_ACCR2_IASS_BIT) /* Input Audio Sample Size is 18-bit */
1178 #define AIC_ACCR2_IASS_16BIT (2 << AIC_ACCR2_IASS_BIT) /* Input Audio Sample Size is 16-bit */
1179 #define AIC_ACCR2_IASS_8BIT (3 << AIC_ACCR2_IASS_BIT) /* Input Audio Sample Size is 8-bit */
1180 #define AIC_ACCR2_SO (1 << 3) /* SDATA_OUT output value */
1181 #define AIC_ACCR2_SR (1 << 2) /* RESET# pin level */
1182 #define AIC_ACCR2_SS (1 << 1) /* SYNC pin level */
1183 #define AIC_ACCR2_SA (1 << 0) /* SYNC and SDATA_OUT alternation */
1184
1185 /* AIC Controller I2S/MSB-justified Control Register (AIC_I2SCR) */
1186
1187 #define AIC_I2SCR_STPBK (1 << 12) /* Stop BIT_CLK for I2S/MSB-justified */
1188 #define AIC_I2SCR_WL_BIT 1 /* Input/Output Sample Size for I2S/MSB-justified */
1189 #define AIC_I2SCR_WL_MASK (0x7 << AIC_I2SCR_WL_BIT)
1190 #define AIC_I2SCR_WL_24BIT (0 << AIC_I2SCR_WL_BIT) /* Word Length is 24 bit */
1191 #define AIC_I2SCR_WL_20BIT (1 << AIC_I2SCR_WL_BIT) /* Word Length is 20 bit */
1192 #define AIC_I2SCR_WL_18BIT (2 << AIC_I2SCR_WL_BIT) /* Word Length is 18 bit */
1193 #define AIC_I2SCR_WL_16BIT (3 << AIC_I2SCR_WL_BIT) /* Word Length is 16 bit */
1194 #define AIC_I2SCR_WL_8BIT (4 << AIC_I2SCR_WL_BIT) /* Word Length is 8 bit */
1195 #define AIC_I2SCR_AMSL (1 << 0) /* 0:I2S, 1:MSB-justified */
1196
1197 /* AIC Controller FIFO Status Register (AIC_SR) */
1198
1199 #define AIC_SR_RFL_BIT 24 /* Receive FIFO Level */
1200 #define AIC_SR_RFL_MASK (0x3f << AIC_SR_RFL_BIT)
1201 #define AIC_SR_TFL_BIT 8 /* Transmit FIFO level */
1202 #define AIC_SR_TFL_MASK (0x3f << AIC_SR_TFL_BIT)
1203 #define AIC_SR_ROR (1 << 6) /* Receive FIFO Overrun */
1204 #define AIC_SR_TUR (1 << 5) /* Transmit FIFO Underrun */
1205 #define AIC_SR_RFS (1 << 4) /* Receive FIFO Service Request */
1206 #define AIC_SR_TFS (1 << 3) /* Transmit FIFO Service Request */
1207
1208 /* AIC Controller AC-link Status Register (AIC_ACSR) */
1209
1210 #define AIC_ACSR_SLTERR (1 << 21) /* Slot Error Flag */
1211 #define AIC_ACSR_CRDY (1 << 20) /* External CODEC Ready Flag */
1212 #define AIC_ACSR_CLPM (1 << 19) /* External CODEC low power mode flag */
1213 #define AIC_ACSR_RSTO (1 << 18) /* External CODEC regs read status timeout */
1214 #define AIC_ACSR_SADR (1 << 17) /* External CODEC regs status addr and data received */
1215 #define AIC_ACSR_CADT (1 << 16) /* Command Address and Data Transmitted */
1216
1217 /* AIC Controller I2S/MSB-justified Status Register (AIC_I2SSR) */
1218
1219 #define AIC_I2SSR_BSY (1 << 2) /* AIC Busy in I2S/MSB-justified format */
1220
1221 /* AIC Controller AC97 codec Command Address Register (AIC_ACCAR) */
1222
1223 #define AIC_ACCAR_CAR_BIT 0
1224 #define AIC_ACCAR_CAR_MASK (0xfffff << AIC_ACCAR_CAR_BIT)
1225
1226 /* AIC Controller AC97 codec Command Data Register (AIC_ACCDR) */
1227
1228 #define AIC_ACCDR_CDR_BIT 0
1229 #define AIC_ACCDR_CDR_MASK (0xfffff << AIC_ACCDR_CDR_BIT)
1230
1231 /* AIC Controller AC97 codec Status Address Register (AIC_ACSAR) */
1232
1233 #define AIC_ACSAR_SAR_BIT 0
1234 #define AIC_ACSAR_SAR_MASK (0xfffff << AIC_ACSAR_SAR_BIT)
1235
1236 /* AIC Controller AC97 codec Status Data Register (AIC_ACSDR) */
1237
1238 #define AIC_ACSDR_SDR_BIT 0
1239 #define AIC_ACSDR_SDR_MASK (0xfffff << AIC_ACSDR_SDR_BIT)
1240
1241 /* AIC Controller I2S/MSB-justified Clock Divider Register (AIC_I2SDIV) */
1242
1243 #define AIC_I2SDIV_DIV_BIT 0
1244 #define AIC_I2SDIV_DIV_MASK (0x7f << AIC_I2SDIV_DIV_BIT)
1245 #define AIC_I2SDIV_BITCLK_3072KHZ (0x0C << AIC_I2SDIV_DIV_BIT) /* BIT_CLK of 3.072MHz */
1246 #define AIC_I2SDIV_BITCLK_2836KHZ (0x0D << AIC_I2SDIV_DIV_BIT) /* BIT_CLK of 2.836MHz */
1247 #define AIC_I2SDIV_BITCLK_1418KHZ (0x1A << AIC_I2SDIV_DIV_BIT) /* BIT_CLK of 1.418MHz */
1248 #define AIC_I2SDIV_BITCLK_1024KHZ (0x24 << AIC_I2SDIV_DIV_BIT) /* BIT_CLK of 1.024MHz */
1249 #define AIC_I2SDIV_BITCLK_7089KHZ (0x34 << AIC_I2SDIV_DIV_BIT) /* BIT_CLK of 708.92KHz */
1250 #define AIC_I2SDIV_BITCLK_512KHZ (0x48 << AIC_I2SDIV_DIV_BIT) /* BIT_CLK of 512.00KHz */
1251
1252
1253 /*************************************************************************
1254 * ICDC (Internal CODEC)
1255 *************************************************************************/
1256 #define ICDC_CR (ICDC_BASE + 0x0400) /* ICDC Control Register */
1257 #define ICDC_APWAIT (ICDC_BASE + 0x0404) /* Anti-Pop WAIT Stage Timing Control Register */
1258 #define ICDC_APPRE (ICDC_BASE + 0x0408) /* Anti-Pop HPEN-PRE Stage Timing Control Register */
1259 #define ICDC_APHPEN (ICDC_BASE + 0x040C) /* Anti-Pop HPEN Stage Timing Control Register */
1260 #define ICDC_APSR (ICDC_BASE + 0x0410) /* Anti-Pop Status Register */
1261 #define ICDC_CDCCR1 (ICDC_BASE + 0x0080)
1262 #define ICDC_CDCCR2 (ICDC_BASE + 0x0084)
1263
1264 #define REG_ICDC_CR REG32(ICDC_CR)
1265 #define REG_ICDC_APWAIT REG32(ICDC_APWAIT)
1266 #define REG_ICDC_APPRE REG32(ICDC_APPRE)
1267 #define REG_ICDC_APHPEN REG32(ICDC_APHPEN)
1268 #define REG_ICDC_APSR REG32(ICDC_APSR)
1269 #define REG_ICDC_CDCCR1 REG32(ICDC_CDCCR1)
1270 #define REG_ICDC_CDCCR2 REG32(ICDC_CDCCR2)
1271
1272 /* ICDC Control Register */
1273 #define ICDC_CR_LINVOL_BIT 24 /* LINE Input Volume Gain: GAIN=LINVOL*1.5-34.5 */
1274 #define ICDC_CR_LINVOL_MASK (0x1f << ICDC_CR_LINVOL_BIT)
1275 #define ICDC_CR_ASRATE_BIT 20 /* Audio Sample Rate */
1276 #define ICDC_CR_ASRATE_MASK (0x0f << ICDC_CR_ASRATE_BIT)
1277 #define ICDC_CR_ASRATE_8000 (0x0 << ICDC_CR_ASRATE_BIT)
1278 #define ICDC_CR_ASRATE_11025 (0x1 << ICDC_CR_ASRATE_BIT)
1279 #define ICDC_CR_ASRATE_12000 (0x2 << ICDC_CR_ASRATE_BIT)
1280 #define ICDC_CR_ASRATE_16000 (0x3 << ICDC_CR_ASRATE_BIT)
1281 #define ICDC_CR_ASRATE_22050 (0x4 << ICDC_CR_ASRATE_BIT)
1282 #define ICDC_CR_ASRATE_24000 (0x5 << ICDC_CR_ASRATE_BIT)
1283 #define ICDC_CR_ASRATE_32000 (0x6 << ICDC_CR_ASRATE_BIT)
1284 #define ICDC_CR_ASRATE_44100 (0x7 << ICDC_CR_ASRATE_BIT)
1285 #define ICDC_CR_ASRATE_48000 (0x8 << ICDC_CR_ASRATE_BIT)
1286 #define ICDC_CR_MICBG_BIT 18 /* MIC Boost Gain */
1287 #define ICDC_CR_MICBG_MASK (0x3 << ICDC_CR_MICBG_BIT)
1288 #define ICDC_CR_MICBG_0DB (0x0 << ICDC_CR_MICBG_BIT)
1289 #define ICDC_CR_MICBG_6DB (0x1 << ICDC_CR_MICBG_BIT)
1290 #define ICDC_CR_MICBG_12DB (0x2 << ICDC_CR_MICBG_BIT)
1291 #define ICDC_CR_MICBG_20DB (0x3 << ICDC_CR_MICBG_BIT)
1292 #define ICDC_CR_HPVOL_BIT 16 /* Headphone Volume Gain */
1293 #define ICDC_CR_HPVOL_MASK (0x3 << ICDC_CR_HPVOL_BIT)
1294 #define ICDC_CR_HPVOL_0DB (0x0 << ICDC_CR_HPVOL_BIT)
1295 #define ICDC_CR_HPVOL_2DB (0x1 << ICDC_CR_HPVOL_BIT)
1296 #define ICDC_CR_HPVOL_4DB (0x2 << ICDC_CR_HPVOL_BIT)
1297 #define ICDC_CR_HPVOL_6DB (0x3 << ICDC_CR_HPVOL_BIT)
1298 #define ICDC_CR_ELINEIN (1 << 13) /* Enable LINE Input */
1299 #define ICDC_CR_EMIC (1 << 12) /* Enable MIC Input */
1300 #define ICDC_CR_SW1ON (1 << 11) /* Switch 1 in CODEC is on */
1301 #define ICDC_CR_EADC (1 << 10) /* Enable ADC */
1302 #define ICDC_CR_SW2ON (1 << 9) /* Switch 2 in CODEC is on */
1303 #define ICDC_CR_EDAC (1 << 8) /* Enable DAC */
1304 #define ICDC_CR_HPMUTE (1 << 5) /* Headphone Mute */
1305 #define ICDC_CR_HPTON (1 << 4) /* Headphone Amplifier Trun On */
1306 #define ICDC_CR_HPTOFF (1 << 3) /* Headphone Amplifier Trun Off */
1307 #define ICDC_CR_TAAP (1 << 2) /* Turn Around of the Anti-Pop Procedure */
1308 #define ICDC_CR_EAP (1 << 1) /* Enable Anti-Pop Procedure */
1309 #define ICDC_CR_SUSPD (1 << 0) /* CODEC Suspend */
1310
1311 /* Anti-Pop WAIT Stage Timing Control Register */
1312 #define ICDC_APWAIT_WAITSN_BIT 0
1313 #define ICDC_APWAIT_WAITSN_MASK (0x7ff << ICDC_APWAIT_WAITSN_BIT)
1314
1315 /* Anti-Pop HPEN-PRE Stage Timing Control Register */
1316 #define ICDC_APPRE_PRESN_BIT 0
1317 #define ICDC_APPRE_PRESN_MASK (0x1ff << ICDC_APPRE_PRESN_BIT)
1318
1319 /* Anti-Pop HPEN Stage Timing Control Register */
1320 #define ICDC_APHPEN_HPENSN_BIT 0
1321 #define ICDC_APHPEN_HPENSN_MASK (0x3fff << ICDC_APHPEN_HPENSN_BIT)
1322
1323 /* Anti-Pop Status Register */
1324 #define ICDC_SR_HPST_BIT 14 /* Headphone Amplifier State */
1325 #define ICDC_SR_HPST_MASK (0x7 << ICDC_SR_HPST_BIT)
1326 #define ICDC_SR_HPST_HP_OFF (0x0 << ICDC_SR_HPST_BIT) /* HP amplifier is off */
1327 #define ICDC_SR_HPST_TON_WAIT (0x1 << ICDC_SR_HPST_BIT) /* wait state in turn-on */
1328 #define ICDC_SR_HPST_TON_PRE (0x2 << ICDC_SR_HPST_BIT) /* pre-enable state in turn-on */
1329 #define ICDC_SR_HPST_TON_HPEN (0x3 << ICDC_SR_HPST_BIT) /* HP enable state in turn-on */
1330 #define ICDC_SR_HPST_TOFF_HPEN (0x4 << ICDC_SR_HPST_BIT) /* HP enable state in turn-off */
1331 #define ICDC_SR_HPST_TOFF_PRE (0x5 << ICDC_SR_HPST_BIT) /* pre-enable state in turn-off */
1332 #define ICDC_SR_HPST_TOFF_WAIT (0x6 << ICDC_SR_HPST_BIT) /* wait state in turn-off */
1333 #define ICDC_SR_HPST_HP_ON (0x7 << ICDC_SR_HPST_BIT) /* HP amplifier is on */
1334 #define ICDC_SR_SNCNT_BIT 0 /* Sample Number Counter */
1335 #define ICDC_SR_SNCNT_MASK (0x3fff << ICDC_SR_SNCNT_BIT)
1336
1337
1338 /*************************************************************************
1339 * I2C
1340 *************************************************************************/
1341 #define I2C_DR (I2C_BASE + 0x000)
1342 #define I2C_CR (I2C_BASE + 0x004)
1343 #define I2C_SR (I2C_BASE + 0x008)
1344 #define I2C_GR (I2C_BASE + 0x00C)
1345
1346 #define REG_I2C_DR REG8(I2C_DR)
1347 #define REG_I2C_CR REG8(I2C_CR)
1348 #define REG_I2C_SR REG8(I2C_SR)
1349 #define REG_I2C_GR REG16(I2C_GR)
1350
1351 /* I2C Control Register (I2C_CR) */
1352
1353 #define I2C_CR_IEN (1 << 4)
1354 #define I2C_CR_STA (1 << 3)
1355 #define I2C_CR_STO (1 << 2)
1356 #define I2C_CR_AC (1 << 1)
1357 #define I2C_CR_I2CE (1 << 0)
1358
1359 /* I2C Status Register (I2C_SR) */
1360
1361 #define I2C_SR_STX (1 << 4)
1362 #define I2C_SR_BUSY (1 << 3)
1363 #define I2C_SR_TEND (1 << 2)
1364 #define I2C_SR_DRF (1 << 1)
1365 #define I2C_SR_ACKF (1 << 0)
1366
1367
1368 /*************************************************************************
1369 * SSI
1370 *************************************************************************/
1371 #define SSI_DR (SSI_BASE + 0x000)
1372 #define SSI_CR0 (SSI_BASE + 0x004)
1373 #define SSI_CR1 (SSI_BASE + 0x008)
1374 #define SSI_SR (SSI_BASE + 0x00C)
1375 #define SSI_ITR (SSI_BASE + 0x010)
1376 #define SSI_ICR (SSI_BASE + 0x014)
1377 #define SSI_GR (SSI_BASE + 0x018)
1378
1379 #define REG_SSI_DR REG32(SSI_DR)
1380 #define REG_SSI_CR0 REG16(SSI_CR0)
1381 #define REG_SSI_CR1 REG32(SSI_CR1)
1382 #define REG_SSI_SR REG32(SSI_SR)
1383 #define REG_SSI_ITR REG16(SSI_ITR)
1384 #define REG_SSI_ICR REG8(SSI_ICR)
1385 #define REG_SSI_GR REG16(SSI_GR)
1386
1387 /* SSI Data Register (SSI_DR) */
1388
1389 #define SSI_DR_GPC_BIT 0
1390 #define SSI_DR_GPC_MASK (0x1ff << SSI_DR_GPC_BIT)
1391
1392 /* SSI Control Register 0 (SSI_CR0) */
1393
1394 #define SSI_CR0_SSIE (1 << 15)
1395 #define SSI_CR0_TIE (1 << 14)
1396 #define SSI_CR0_RIE (1 << 13)
1397 #define SSI_CR0_TEIE (1 << 12)
1398 #define SSI_CR0_REIE (1 << 11)
1399 #define SSI_CR0_LOOP (1 << 10)
1400 #define SSI_CR0_RFINE (1 << 9)
1401 #define SSI_CR0_RFINC (1 << 8)
1402 #define SSI_CR0_FSEL (1 << 6)
1403 #define SSI_CR0_TFLUSH (1 << 2)
1404 #define SSI_CR0_RFLUSH (1 << 1)
1405 #define SSI_CR0_DISREV (1 << 0)
1406
1407 /* SSI Control Register 1 (SSI_CR1) */
1408
1409 #define SSI_CR1_FRMHL_BIT 30
1410 #define SSI_CR1_FRMHL_MASK (0x3 << SSI_CR1_FRMHL_BIT)
1411 #define SSI_CR1_FRMHL_CELOW_CE2LOW (0 << SSI_CR1_FRMHL_BIT) /* SSI_CE_ is low valid and SSI_CE2_ is low valid */
1412 #define SSI_CR1_FRMHL_CEHIGH_CE2LOW (1 << SSI_CR1_FRMHL_BIT) /* SSI_CE_ is high valid and SSI_CE2_ is low valid */
1413 #define SSI_CR1_FRMHL_CELOW_CE2HIGH (2 << SSI_CR1_FRMHL_BIT) /* SSI_CE_ is low valid and SSI_CE2_ is high valid */
1414 #define SSI_CR1_FRMHL_CEHIGH_CE2HIGH (3 << SSI_CR1_FRMHL_BIT) /* SSI_CE_ is high valid and SSI_CE2_ is high valid */
1415 #define SSI_CR1_TFVCK_BIT 28
1416 #define SSI_CR1_TFVCK_MASK (0x3 << SSI_CR1_TFVCK_BIT)
1417 #define SSI_CR1_TFVCK_0 (0 << SSI_CR1_TFVCK_BIT)
1418 #define SSI_CR1_TFVCK_1 (1 << SSI_CR1_TFVCK_BIT)
1419 #define SSI_CR1_TFVCK_2 (2 << SSI_CR1_TFVCK_BIT)
1420 #define SSI_CR1_TFVCK_3 (3 << SSI_CR1_TFVCK_BIT)
1421 #define SSI_CR1_TCKFI_BIT 26
1422 #define SSI_CR1_TCKFI_MASK (0x3 << SSI_CR1_TCKFI_BIT)
1423 #define SSI_CR1_TCKFI_0 (0 << SSI_CR1_TCKFI_BIT)
1424 #define SSI_CR1_TCKFI_1 (1 << SSI_CR1_TCKFI_BIT)
1425 #define SSI_CR1_TCKFI_2 (2 << SSI_CR1_TCKFI_BIT)
1426 #define SSI_CR1_TCKFI_3 (3 << SSI_CR1_TCKFI_BIT)
1427 #define SSI_CR1_LFST (1 << 25)
1428 #define SSI_CR1_ITFRM (1 << 24)
1429 #define SSI_CR1_UNFIN (1 << 23)
1430 #define SSI_CR1_MULTS (1 << 22)
1431 #define SSI_CR1_FMAT_BIT 20
1432 #define SSI_CR1_FMAT_MASK (0x3 << SSI_CR1_FMAT_BIT)
1433 #define SSI_CR1_FMAT_SPI (0 << SSI_CR1_FMAT_BIT) /* Motorola¡¯s SPI format */
1434 #define SSI_CR1_FMAT_SSP (1 << SSI_CR1_FMAT_BIT) /* TI's SSP format */
1435 #define SSI_CR1_FMAT_MW1 (2 << SSI_CR1_FMAT_BIT) /* National Microwire 1 format */
1436 #define SSI_CR1_FMAT_MW2 (3 << SSI_CR1_FMAT_BIT) /* National Microwire 2 format */
1437 #define SSI_CR1_TTRG_BIT 16
1438 #define SSI_CR1_TTRG_MASK (0xf << SSI_CR1_TTRG_BIT)
1439 #define SSI_CR1_TTRG_1 (0 << SSI_CR1_TTRG_BIT)
1440 #define SSI_CR1_TTRG_8 (1 << SSI_CR1_TTRG_BIT)
1441 #define SSI_CR1_TTRG_16 (2 << SSI_CR1_TTRG_BIT)
1442 #define SSI_CR1_TTRG_24 (3 << SSI_CR1_TTRG_BIT)
1443 #define SSI_CR1_TTRG_32 (4 << SSI_CR1_TTRG_BIT)
1444 #define SSI_CR1_TTRG_40 (5 << SSI_CR1_TTRG_BIT)
1445 #define SSI_CR1_TTRG_48 (6 << SSI_CR1_TTRG_BIT)
1446 #define SSI_CR1_TTRG_56 (7 << SSI_CR1_TTRG_BIT)
1447 #define SSI_CR1_TTRG_64 (8 << SSI_CR1_TTRG_BIT)
1448 #define SSI_CR1_TTRG_72 (9 << SSI_CR1_TTRG_BIT)
1449 #define SSI_CR1_TTRG_80 (10<< SSI_CR1_TTRG_BIT)
1450 #define SSI_CR1_TTRG_88 (11<< SSI_CR1_TTRG_BIT)
1451 #define SSI_CR1_TTRG_96 (12<< SSI_CR1_TTRG_BIT)
1452 #define SSI_CR1_TTRG_104 (13<< SSI_CR1_TTRG_BIT)
1453 #define SSI_CR1_TTRG_112 (14<< SSI_CR1_TTRG_BIT)
1454 #define SSI_CR1_TTRG_120 (15<< SSI_CR1_TTRG_BIT)
1455 #define SSI_CR1_MCOM_BIT 12
1456 #define SSI_CR1_MCOM_MASK (0xf << SSI_CR1_MCOM_BIT)
1457 #define SSI_CR1_MCOM_1BIT (0x0 << SSI_CR1_MCOM_BIT) /* 1-bit command selected */
1458 #define SSI_CR1_MCOM_2BIT (0x1 << SSI_CR1_MCOM_BIT) /* 2-bit command selected */
1459 #define SSI_CR1_MCOM_3BIT (0x2 << SSI_CR1_MCOM_BIT) /* 3-bit command selected */
1460 #define SSI_CR1_MCOM_4BIT (0x3 << SSI_CR1_MCOM_BIT) /* 4-bit command selected */
1461 #define SSI_CR1_MCOM_5BIT (0x4 << SSI_CR1_MCOM_BIT) /* 5-bit command selected */
1462 #define SSI_CR1_MCOM_6BIT (0x5 << SSI_CR1_MCOM_BIT) /* 6-bit command selected */
1463 #define SSI_CR1_MCOM_7BIT (0x6 << SSI_CR1_MCOM_BIT) /* 7-bit command selected */
1464 #define SSI_CR1_MCOM_8BIT (0x7 << SSI_CR1_MCOM_BIT) /* 8-bit command selected */
1465 #define SSI_CR1_MCOM_9BIT (0x8 << SSI_CR1_MCOM_BIT) /* 9-bit command selected */
1466 #define SSI_CR1_MCOM_10BIT (0x9 << SSI_CR1_MCOM_BIT) /* 10-bit command selected */
1467 #define SSI_CR1_MCOM_11BIT (0xA << SSI_CR1_MCOM_BIT) /* 11-bit command selected */
1468 #define SSI_CR1_MCOM_12BIT (0xB << SSI_CR1_MCOM_BIT) /* 12-bit command selected */
1469 #define SSI_CR1_MCOM_13BIT (0xC << SSI_CR1_MCOM_BIT) /* 13-bit command selected */
1470 #define SSI_CR1_MCOM_14BIT (0xD << SSI_CR1_MCOM_BIT) /* 14-bit command selected */
1471 #define SSI_CR1_MCOM_15BIT (0xE << SSI_CR1_MCOM_BIT) /* 15-bit command selected */
1472 #define SSI_CR1_MCOM_16BIT (0xF << SSI_CR1_MCOM_BIT) /* 16-bit command selected */
1473 #define SSI_CR1_RTRG_BIT 8
1474 #define SSI_CR1_RTRG_MASK (0xf << SSI_CR1_RTRG_BIT)
1475 #define SSI_CR1_RTRG_1 (0 << SSI_CR1_RTRG_BIT)
1476 #define SSI_CR1_RTRG_8 (1 << SSI_CR1_RTRG_BIT)
1477 #define SSI_CR1_RTRG_16 (2 << SSI_CR1_RTRG_BIT)
1478 #define SSI_CR1_RTRG_24 (3 << SSI_CR1_RTRG_BIT)
1479 #define SSI_CR1_RTRG_32 (4 << SSI_CR1_RTRG_BIT)
1480 #define SSI_CR1_RTRG_40 (5 << SSI_CR1_RTRG_BIT)
1481 #define SSI_CR1_RTRG_48 (6 << SSI_CR1_RTRG_BIT)
1482 #define SSI_CR1_RTRG_56 (7 << SSI_CR1_RTRG_BIT)
1483 #define SSI_CR1_RTRG_64 (8 << SSI_CR1_RTRG_BIT)
1484 #define SSI_CR1_RTRG_72 (9 << SSI_CR1_RTRG_BIT)
1485 #define SSI_CR1_RTRG_80 (10<< SSI_CR1_RTRG_BIT)
1486 #define SSI_CR1_RTRG_88 (11<< SSI_CR1_RTRG_BIT)
1487 #define SSI_CR1_RTRG_96 (12<< SSI_CR1_RTRG_BIT)
1488 #define SSI_CR1_RTRG_104 (13<< SSI_CR1_RTRG_BIT)
1489 #define SSI_CR1_RTRG_112 (14<< SSI_CR1_RTRG_BIT)
1490 #define SSI_CR1_RTRG_120 (15<< SSI_CR1_RTRG_BIT)
1491 #define SSI_CR1_FLEN_BIT 4
1492 #define SSI_CR1_FLEN_MASK (0xf << SSI_CR1_FLEN_BIT)
1493 #define SSI_CR1_FLEN_2BIT (0x0 << SSI_CR1_FLEN_BIT)
1494 #define SSI_CR1_FLEN_3BIT (0x1 << SSI_CR1_FLEN_BIT)
1495 #define SSI_CR1_FLEN_4BIT (0x2 << SSI_CR1_FLEN_BIT)
1496 #define SSI_CR1_FLEN_5BIT (0x3 << SSI_CR1_FLEN_BIT)
1497 #define SSI_CR1_FLEN_6BIT (0x4 << SSI_CR1_FLEN_BIT)
1498 #define SSI_CR1_FLEN_7BIT (0x5 << SSI_CR1_FLEN_BIT)
1499 #define SSI_CR1_FLEN_8BIT (0x6 << SSI_CR1_FLEN_BIT)
1500 #define SSI_CR1_FLEN_9BIT (0x7 << SSI_CR1_FLEN_BIT)
1501 #define SSI_CR1_FLEN_10BIT (0x8 << SSI_CR1_FLEN_BIT)
1502 #define SSI_CR1_FLEN_11BIT (0x9 << SSI_CR1_FLEN_BIT)
1503 #define SSI_CR1_FLEN_12BIT (0xA << SSI_CR1_FLEN_BIT)
1504 #define SSI_CR1_FLEN_13BIT (0xB << SSI_CR1_FLEN_BIT)
1505 #define SSI_CR1_FLEN_14BIT (0xC << SSI_CR1_FLEN_BIT)
1506 #define SSI_CR1_FLEN_15BIT (0xD << SSI_CR1_FLEN_BIT)
1507 #define SSI_CR1_FLEN_16BIT (0xE << SSI_CR1_FLEN_BIT)
1508 #define SSI_CR1_FLEN_17BIT (0xF << SSI_CR1_FLEN_BIT)
1509 #define SSI_CR1_PHA (1 << 1)
1510 #define SSI_CR1_POL (1 << 0)
1511
1512 /* SSI Status Register (SSI_SR) */
1513
1514 #define SSI_SR_TFIFONUM_BIT 16
1515 #define SSI_SR_TFIFONUM_MASK (0xff << SSI_SR_TFIFONUM_BIT)
1516 #define SSI_SR_RFIFONUM_BIT 8
1517 #define SSI_SR_RFIFONUM_MASK (0xff << SSI_SR_RFIFONUM_BIT)
1518 #define SSI_SR_END (1 << 7)
1519 #define SSI_SR_BUSY (1 << 6)
1520 #define SSI_SR_TFF (1 << 5)
1521 #define SSI_SR_RFE (1 << 4)
1522 #define SSI_SR_TFHE (1 << 3)
1523 #define SSI_SR_RFHF (1 << 2)
1524 #define SSI_SR_UNDR (1 << 1)
1525 #define SSI_SR_OVER (1 << 0)
1526
1527 /* SSI Interval Time Control Register (SSI_ITR) */
1528
1529 #define SSI_ITR_CNTCLK (1 << 15)
1530 #define SSI_ITR_IVLTM_BIT 0
1531 #define SSI_ITR_IVLTM_MASK (0x7fff << SSI_ITR_IVLTM_BIT)
1532
1533
1534 /*************************************************************************
1535 * MSC
1536 *************************************************************************/
1537 #define MSC_STRPCL (MSC_BASE + 0x000)
1538 #define MSC_STAT (MSC_BASE + 0x004)
1539 #define MSC_CLKRT (MSC_BASE + 0x008)
1540 #define MSC_CMDAT (MSC_BASE + 0x00C)
1541 #define MSC_RESTO (MSC_BASE + 0x010)
1542 #define MSC_RDTO (MSC_BASE + 0x014)
1543 #define MSC_BLKLEN (MSC_BASE + 0x018)
1544 #define MSC_NOB (MSC_BASE + 0x01C)
1545 #define MSC_SNOB (MSC_BASE + 0x020)
1546 #define MSC_IMASK (MSC_BASE + 0x024)
1547 #define MSC_IREG (MSC_BASE + 0x028)
1548 #define MSC_CMD (MSC_BASE + 0x02C)
1549 #define MSC_ARG (MSC_BASE + 0x030)
1550 #define MSC_RES (MSC_BASE + 0x034)
1551 #define MSC_RXFIFO (MSC_BASE + 0x038)
1552 #define MSC_TXFIFO (MSC_BASE + 0x03C)
1553
1554 #define REG_MSC_STRPCL REG16(MSC_STRPCL)
1555 #define REG_MSC_STAT REG32(MSC_STAT)
1556 #define REG_MSC_CLKRT REG16(MSC_CLKRT)
1557 #define REG_MSC_CMDAT REG32(MSC_CMDAT)
1558 #define REG_MSC_RESTO REG16(MSC_RESTO)
1559 #define REG_MSC_RDTO REG16(MSC_RDTO)
1560 #define REG_MSC_BLKLEN REG16(MSC_BLKLEN)
1561 #define REG_MSC_NOB REG16(MSC_NOB)
1562 #define REG_MSC_SNOB REG16(MSC_SNOB)
1563 #define REG_MSC_IMASK REG16(MSC_IMASK)
1564 #define REG_MSC_IREG REG16(MSC_IREG)
1565 #define REG_MSC_CMD REG8(MSC_CMD)
1566 #define REG_MSC_ARG REG32(MSC_ARG)
1567 #define REG_MSC_RES REG16(MSC_RES)
1568 #define REG_MSC_RXFIFO REG32(MSC_RXFIFO)
1569 #define REG_MSC_TXFIFO REG32(MSC_TXFIFO)
1570
1571 /* MSC Clock and Control Register (MSC_STRPCL) */
1572
1573 #define MSC_STRPCL_EXIT_MULTIPLE (1 << 7)
1574 #define MSC_STRPCL_EXIT_TRANSFER (1 << 6)
1575 #define MSC_STRPCL_START_READWAIT (1 << 5)
1576 #define MSC_STRPCL_STOP_READWAIT (1 << 4)
1577 #define MSC_STRPCL_RESET (1 << 3)
1578 #define MSC_STRPCL_START_OP (1 << 2)
1579 #define MSC_STRPCL_CLOCK_CONTROL_BIT 0
1580 #define MSC_STRPCL_CLOCK_CONTROL_MASK (0x3 << MSC_STRPCL_CLOCK_CONTROL_BIT)
1581 #define MSC_STRPCL_CLOCK_CONTROL_STOP (0x1 << MSC_STRPCL_CLOCK_CONTROL_BIT) /* Stop MMC/SD clock */
1582 #define MSC_STRPCL_CLOCK_CONTROL_START (0x2 << MSC_STRPCL_CLOCK_CONTROL_BIT) /* Start MMC/SD clock */
1583
1584 /* MSC Status Register (MSC_STAT) */
1585
1586 #define MSC_STAT_IS_RESETTING (1 << 15)
1587 #define MSC_STAT_SDIO_INT_ACTIVE (1 << 14)
1588 #define MSC_STAT_PRG_DONE (1 << 13)
1589 #define MSC_STAT_DATA_TRAN_DONE (1 << 12)
1590 #define MSC_STAT_END_CMD_RES (1 << 11)
1591 #define MSC_STAT_DATA_FIFO_AFULL (1 << 10)
1592 #define MSC_STAT_IS_READWAIT (1 << 9)
1593 #define MSC_STAT_CLK_EN (1 << 8)
1594 #define MSC_STAT_DATA_FIFO_FULL (1 << 7)
1595 #define MSC_STAT_DATA_FIFO_EMPTY (1 << 6)
1596 #define MSC_STAT_CRC_RES_ERR (1 << 5)
1597 #define MSC_STAT_CRC_READ_ERROR (1 << 4)
1598 #define MSC_STAT_CRC_WRITE_ERROR_BIT 2
1599 #define MSC_STAT_CRC_WRITE_ERROR_MASK (0x3 << MSC_STAT_CRC_WRITE_ERROR_BIT)
1600 #define MSC_STAT_CRC_WRITE_ERROR_NO (0 << MSC_STAT_CRC_WRITE_ERROR_BIT) /* No error on transmission of data */
1601 #define MSC_STAT_CRC_WRITE_ERROR (1 << MSC_STAT_CRC_WRITE_ERROR_BIT) /* Card observed erroneous transmission of data */
1602 #define MSC_STAT_CRC_WRITE_ERROR_NOSTS (2 << MSC_STAT_CRC_WRITE_ERROR_BIT) /* No CRC status is sent back */
1603 #define MSC_STAT_TIME_OUT_RES (1 << 1)
1604 #define MSC_STAT_TIME_OUT_READ (1 << 0)
1605
1606 /* MSC Bus Clock Control Register (MSC_CLKRT) */
1607
1608 #define MSC_CLKRT_CLK_RATE_BIT 0
1609 #define MSC_CLKRT_CLK_RATE_MASK (0x7 << MSC_CLKRT_CLK_RATE_BIT)
1610 #define MSC_CLKRT_CLK_RATE_DIV_1 (0x0 << MSC_CLKRT_CLK_RATE_BIT) /* CLK_SRC */
1611 #define MSC_CLKRT_CLK_RATE_DIV_2 (0x1 << MSC_CLKRT_CLK_RATE_BIT) /* 1/2 of CLK_SRC */
1612 #define MSC_CLKRT_CLK_RATE_DIV_4 (0x2 << MSC_CLKRT_CLK_RATE_BIT) /* 1/4 of CLK_SRC */
1613 #define MSC_CLKRT_CLK_RATE_DIV_8 (0x3 << MSC_CLKRT_CLK_RATE_BIT) /* 1/8 of CLK_SRC */
1614 #define MSC_CLKRT_CLK_RATE_DIV_16 (0x4 << MSC_CLKRT_CLK_RATE_BIT) /* 1/16 of CLK_SRC */
1615 #define MSC_CLKRT_CLK_RATE_DIV_32 (0x5 << MSC_CLKRT_CLK_RATE_BIT) /* 1/32 of CLK_SRC */
1616 #define MSC_CLKRT_CLK_RATE_DIV_64 (0x6 << MSC_CLKRT_CLK_RATE_BIT) /* 1/64 of CLK_SRC */
1617 #define MSC_CLKRT_CLK_RATE_DIV_128 (0x7 << MSC_CLKRT_CLK_RATE_BIT) /* 1/128 of CLK_SRC */
1618
1619 /* MSC Command Sequence Control Register (MSC_CMDAT) */
1620
1621 #define MSC_CMDAT_IO_ABORT (1 << 11)
1622 #define MSC_CMDAT_BUS_WIDTH_BIT 9
1623 #define MSC_CMDAT_BUS_WIDTH_MASK (0x3 << MSC_CMDAT_BUS_WIDTH_BIT)
1624 #define MSC_CMDAT_BUS_WIDTH_1BIT (0x0 << MSC_CMDAT_BUS_WIDTH_BIT) /* 1-bit data bus */
1625 #define MSC_CMDAT_BUS_WIDTH_4BIT (0x2 << MSC_CMDAT_BUS_WIDTH_BIT) /* 4-bit data bus */
1626 #define CMDAT_BUS_WIDTH1 (0x0 << MSC_CMDAT_BUS_WIDTH_BIT)
1627 #define CMDAT_BUS_WIDTH4 (0x2 << MSC_CMDAT_BUS_WIDTH_BIT)
1628 #define MSC_CMDAT_DMA_EN (1 << 8)
1629 #define MSC_CMDAT_INIT (1 << 7)
1630 #define MSC_CMDAT_BUSY (1 << 6)
1631 #define MSC_CMDAT_STREAM_BLOCK (1 << 5)
1632 #define MSC_CMDAT_WRITE (1 << 4)
1633 #define MSC_CMDAT_READ (0 << 4)
1634 #define MSC_CMDAT_DATA_EN (1 << 3)
1635 #define MSC_CMDAT_RESPONSE_BIT 0
1636 #define MSC_CMDAT_RESPONSE_MASK (0x7 << MSC_CMDAT_RESPONSE_BIT)
1637 #define MSC_CMDAT_RESPONSE_NONE (0x0 << MSC_CMDAT_RESPONSE_BIT) /* No response */
1638 #define MSC_CMDAT_RESPONSE_R1 (0x1 << MSC_CMDAT_RESPONSE_BIT) /* Format R1 and R1b */
1639 #define MSC_CMDAT_RESPONSE_R2 (0x2 << MSC_CMDAT_RESPONSE_BIT) /* Format R2 */
1640 #define MSC_CMDAT_RESPONSE_R3 (0x3 << MSC_CMDAT_RESPONSE_BIT) /* Format R3 */
1641 #define MSC_CMDAT_RESPONSE_R4 (0x4 << MSC_CMDAT_RESPONSE_BIT) /* Format R4 */
1642 #define MSC_CMDAT_RESPONSE_R5 (0x5 << MSC_CMDAT_RESPONSE_BIT) /* Format R5 */
1643 #define MSC_CMDAT_RESPONSE_R6 (0x6 << MSC_CMDAT_RESPONSE_BIT) /* Format R6 */
1644
1645 #define CMDAT_DMA_EN (1 << 8)
1646 #define CMDAT_INIT (1 << 7)
1647 #define CMDAT_BUSY (1 << 6)
1648 #define CMDAT_STREAM (1 << 5)
1649 #define CMDAT_WRITE (1 << 4)
1650 #define CMDAT_DATA_EN (1 << 3)
1651
1652 /* MSC Interrupts Mask Register (MSC_IMASK) */
1653
1654 #define MSC_IMASK_SDIO (1 << 7)
1655 #define MSC_IMASK_TXFIFO_WR_REQ (1 << 6)
1656 #define MSC_IMASK_RXFIFO_RD_REQ (1 << 5)
1657 #define MSC_IMASK_END_CMD_RES (1 << 2)
1658 #define MSC_IMASK_PRG_DONE (1 << 1)
1659 #define MSC_IMASK_DATA_TRAN_DONE (1 << 0)
1660
1661
1662 /* MSC Interrupts Status Register (MSC_IREG) */
1663
1664 #define MSC_IREG_SDIO (1 << 7)
1665 #define MSC_IREG_TXFIFO_WR_REQ (1 << 6)
1666 #define MSC_IREG_RXFIFO_RD_REQ (1 << 5)
1667 #define MSC_IREG_END_CMD_RES (1 << 2)
1668 #define MSC_IREG_PRG_DONE (1 << 1)
1669 #define MSC_IREG_DATA_TRAN_DONE (1 << 0)
1670
1671
1672 /*************************************************************************
1673 * EMC (External Memory Controller)
1674 *************************************************************************/
1675 #define EMC_BCR (EMC_BASE + 0x0) /* BCR */
1676
1677 #define EMC_SMCR0 (EMC_BASE + 0x10) /* Static Memory Control Register 0 */
1678 #define EMC_SMCR1 (EMC_BASE + 0x14) /* Static Memory Control Register 1 */
1679 #define EMC_SMCR2 (EMC_BASE + 0x18) /* Static Memory Control Register 2 */
1680 #define EMC_SMCR3 (EMC_BASE + 0x1c) /* Static Memory Control Register 3 */
1681 #define EMC_SMCR4 (EMC_BASE + 0x20) /* Static Memory Control Register 4 */
1682 #define EMC_SACR0 (EMC_BASE + 0x30) /* Static Memory Bank 0 Addr Config Reg */
1683 #define EMC_SACR1 (EMC_BASE + 0x34) /* Static Memory Bank 1 Addr Config Reg */
1684 #define EMC_SACR2 (EMC_BASE + 0x38) /* Static Memory Bank 2 Addr Config Reg */
1685 #define EMC_SACR3 (EMC_BASE + 0x3c) /* Static Memory Bank 3 Addr Config Reg */
1686 #define EMC_SACR4 (EMC_BASE + 0x40) /* Static Memory Bank 4 Addr Config Reg */
1687
1688 #define EMC_NFCSR (EMC_BASE + 0x050) /* NAND Flash Control/Status Register */
1689 #define EMC_NFECR (EMC_BASE + 0x100) /* NAND Flash ECC Control Register */
1690 #define EMC_NFECC (EMC_BASE + 0x104) /* NAND Flash ECC Data Register */
1691 #define EMC_NFPAR0 (EMC_BASE + 0x108) /* NAND Flash RS Parity 0 Register */
1692 #define EMC_NFPAR1 (EMC_BASE + 0x10c) /* NAND Flash RS Parity 1 Register */
1693 #define EMC_NFPAR2 (EMC_BASE + 0x110) /* NAND Flash RS Parity 2 Register */
1694 #define EMC_NFINTS (EMC_BASE + 0x114) /* NAND Flash Interrupt Status Register */
1695 #define EMC_NFINTE (EMC_BASE + 0x118) /* NAND Flash Interrupt Enable Register */
1696 #define EMC_NFERR0 (EMC_BASE + 0x11c) /* NAND Flash RS Error Report 0 Register */
1697 #define EMC_NFERR1 (EMC_BASE + 0x120) /* NAND Flash RS Error Report 1 Register */
1698 #define EMC_NFERR2 (EMC_BASE + 0x124) /* NAND Flash RS Error Report 2 Register */
1699 #define EMC_NFERR3 (EMC_BASE + 0x128) /* NAND Flash RS Error Report 3 Register */
1700
1701 #define EMC_DMCR (EMC_BASE + 0x80) /* DRAM Control Register */
1702 #define EMC_RTCSR (EMC_BASE + 0x84) /* Refresh Time Control/Status Register */
1703 #define EMC_RTCNT (EMC_BASE + 0x88) /* Refresh Timer Counter */
1704 #define EMC_RTCOR (EMC_BASE + 0x8c) /* Refresh Time Constant Register */
1705 #define EMC_DMAR0 (EMC_BASE + 0x90) /* SDRAM Bank 0 Addr Config Register */
1706 #define EMC_SDMR0 (EMC_BASE + 0xa000) /* Mode Register of SDRAM bank 0 */
1707
1708 #define REG_EMC_BCR REG32(EMC_BCR)
1709
1710 #define REG_EMC_SMCR0 REG32(EMC_SMCR0)
1711 #define REG_EMC_SMCR1 REG32(EMC_SMCR1)
1712 #define REG_EMC_SMCR2 REG32(EMC_SMCR2)
1713 #define REG_EMC_SMCR3 REG32(EMC_SMCR3)
1714 #define REG_EMC_SMCR4 REG32(EMC_SMCR4)
1715 #define REG_EMC_SACR0 REG32(EMC_SACR0)
1716 #define REG_EMC_SACR1 REG32(EMC_SACR1)
1717 #define REG_EMC_SACR2 REG32(EMC_SACR2)
1718 #define REG_EMC_SACR3 REG32(EMC_SACR3)
1719 #define REG_EMC_SACR4 REG32(EMC_SACR4)
1720
1721 #define REG_EMC_NFCSR REG32(EMC_NFCSR)
1722 #define REG_EMC_NFECR REG32(EMC_NFECR)
1723 #define REG_EMC_NFECC REG32(EMC_NFECC)
1724 #define REG_EMC_NFPAR0 REG32(EMC_NFPAR0)
1725 #define REG_EMC_NFPAR1 REG32(EMC_NFPAR1)
1726 #define REG_EMC_NFPAR2 REG32(EMC_NFPAR2)
1727 #define REG_EMC_NFINTS REG32(EMC_NFINTS)
1728 #define REG_EMC_NFINTE REG32(EMC_NFINTE)
1729 #define REG_EMC_NFERR0 REG32(EMC_NFERR0)
1730 #define REG_EMC_NFERR1 REG32(EMC_NFERR1)
1731 #define REG_EMC_NFERR2 REG32(EMC_NFERR2)
1732 #define REG_EMC_NFERR3 REG32(EMC_NFERR3)
1733
1734 #define REG_EMC_DMCR REG32(EMC_DMCR)
1735 #define REG_EMC_RTCSR REG16(EMC_RTCSR)
1736 #define REG_EMC_RTCNT REG16(EMC_RTCNT)
1737 #define REG_EMC_RTCOR REG16(EMC_RTCOR)
1738 #define REG_EMC_DMAR0 REG32(EMC_DMAR0)
1739
1740 /* Static Memory Control Register */
1741 #define EMC_SMCR_STRV_BIT 24
1742 #define EMC_SMCR_STRV_MASK (0x0f << EMC_SMCR_STRV_BIT)
1743 #define EMC_SMCR_TAW_BIT 20
1744 #define EMC_SMCR_TAW_MASK (0x0f << EMC_SMCR_TAW_BIT)
1745 #define EMC_SMCR_TBP_BIT 16
1746 #define EMC_SMCR_TBP_MASK (0x0f << EMC_SMCR_TBP_BIT)
1747 #define EMC_SMCR_TAH_BIT 12
1748 #define EMC_SMCR_TAH_MASK (0x07 << EMC_SMCR_TAH_BIT)
1749 #define EMC_SMCR_TAS_BIT 8
1750 #define EMC_SMCR_TAS_MASK (0x07 << EMC_SMCR_TAS_BIT)
1751 #define EMC_SMCR_BW_BIT 6
1752 #define EMC_SMCR_BW_MASK (0x03 << EMC_SMCR_BW_BIT)
1753 #define EMC_SMCR_BW_8BIT (0 << EMC_SMCR_BW_BIT)
1754 #define EMC_SMCR_BW_16BIT (1 << EMC_SMCR_BW_BIT)
1755 #define EMC_SMCR_BW_32BIT (2 << EMC_SMCR_BW_BIT)
1756 #define EMC_SMCR_BCM (1 << 3)
1757 #define EMC_SMCR_BL_BIT 1
1758 #define EMC_SMCR_BL_MASK (0x03 << EMC_SMCR_BL_BIT)
1759 #define EMC_SMCR_BL_4 (0 << EMC_SMCR_BL_BIT)
1760 #define EMC_SMCR_BL_8 (1 << EMC_SMCR_BL_BIT)
1761 #define EMC_SMCR_BL_16 (2 << EMC_SMCR_BL_BIT)
1762 #define EMC_SMCR_BL_32 (3 << EMC_SMCR_BL_BIT)
1763 #define EMC_SMCR_SMT (1 << 0)
1764
1765 /* Static Memory Bank Addr Config Reg */
1766 #define EMC_SACR_BASE_BIT 8
1767 #define EMC_SACR_BASE_MASK (0xff << EMC_SACR_BASE_BIT)
1768 #define EMC_SACR_MASK_BIT 0
1769 #define EMC_SACR_MASK_MASK (0xff << EMC_SACR_MASK_BIT)
1770
1771 /* NAND Flash Control/Status Register */
1772 #define EMC_NFCSR_NFCE4 (1 << 7) /* NAND Flash Enable */
1773 #define EMC_NFCSR_NFE4 (1 << 6) /* NAND Flash FCE# Assertion Enable */
1774 #define EMC_NFCSR_NFCE3 (1 << 5)
1775 #define EMC_NFCSR_NFE3 (1 << 4)
1776 #define EMC_NFCSR_NFCE2 (1 << 3)
1777 #define EMC_NFCSR_NFE2 (1 << 2)
1778 #define EMC_NFCSR_NFCE1 (1 << 1)
1779 #define EMC_NFCSR_NFE1 (1 << 0)
1780
1781 /* NAND Flash ECC Control Register */
1782 #define EMC_NFECR_PRDY (1 << 4) /* Parity Ready */
1783 #define EMC_NFECR_RS_DECODING (0 << 3) /* RS is in decoding phase */
1784 #define EMC_NFECR_RS_ENCODING (1 << 3) /* RS is in encoding phase */
1785 #define EMC_NFECR_HAMMING (0 << 2) /* Select HAMMING Correction Algorithm */
1786 #define EMC_NFECR_RS (1 << 2) /* Select RS Correction Algorithm */
1787 #define EMC_NFECR_ERST (1 << 1) /* ECC Reset */
1788 #define EMC_NFECR_ECCE (1 << 0) /* ECC Enable */
1789
1790 /* NAND Flash ECC Data Register */
1791 #define EMC_NFECC_ECC2_BIT 16
1792 #define EMC_NFECC_ECC2_MASK (0xff << EMC_NFECC_ECC2_BIT)
1793 #define EMC_NFECC_ECC1_BIT 8
1794 #define EMC_NFECC_ECC1_MASK (0xff << EMC_NFECC_ECC1_BIT)
1795 #define EMC_NFECC_ECC0_BIT 0
1796 #define EMC_NFECC_ECC0_MASK (0xff << EMC_NFECC_ECC0_BIT)
1797
1798 /* NAND Flash Interrupt Status Register */
1799 #define EMC_NFINTS_ERRCNT_BIT 29 /* Error Count */
1800 #define EMC_NFINTS_ERRCNT_MASK (0x7 << EMC_NFINTS_ERRCNT_BIT)
1801 #define EMC_NFINTS_PADF (1 << 4) /* Padding Finished */
1802 #define EMC_NFINTS_DECF (1 << 3) /* Decoding Finished */
1803 #define EMC_NFINTS_ENCF (1 << 2) /* Encoding Finished */
1804 #define EMC_NFINTS_UNCOR (1 << 1) /* Uncorrectable Error Occurred */
1805 #define EMC_NFINTS_ERR (1 << 0) /* Error Occurred */
1806
1807 /* NAND Flash Interrupt Enable Register */
1808 #define EMC_NFINTE_PADFE (1 << 4) /* Padding Finished Interrupt Enable */
1809 #define EMC_NFINTE_DECFE (1 << 3) /* Decoding Finished Interrupt Enable */
1810 #define EMC_NFINTE_ENCFE (1 << 2) /* Encoding Finished Interrupt Enable */
1811 #define EMC_NFINTE_UNCORE (1 << 1) /* Uncorrectable Error Occurred Intr Enable */
1812 #define EMC_NFINTE_ERRE (1 << 0) /* Error Occurred Interrupt */
1813
1814 /* NAND Flash RS Error Report Register */
1815 #define EMC_NFERR_INDEX_BIT 16 /* Error Symbol Index */
1816 #define EMC_NFERR_INDEX_MASK (0x1ff << EMC_NFERR_INDEX_BIT)
1817 #define EMC_NFERR_MASK_BIT 0 /* Error Symbol Value */
1818 #define EMC_NFERR_MASK_MASK (0x1ff << EMC_NFERR_MASK_BIT)
1819
1820
1821 /* DRAM Control Register */
1822 #define EMC_DMCR_BW_BIT 31
1823 #define EMC_DMCR_BW (1 << EMC_DMCR_BW_BIT)
1824 #define EMC_DMCR_CA_BIT 26
1825 #define EMC_DMCR_CA_MASK (0x07 << EMC_DMCR_CA_BIT)
1826 #define EMC_DMCR_CA_8 (0 << EMC_DMCR_CA_BIT)
1827 #define EMC_DMCR_CA_9 (1 << EMC_DMCR_CA_BIT)
1828 #define EMC_DMCR_CA_10 (2 << EMC_DMCR_CA_BIT)
1829 #define EMC_DMCR_CA_11 (3 << EMC_DMCR_CA_BIT)
1830 #define EMC_DMCR_CA_12 (4 << EMC_DMCR_CA_BIT)
1831 #define EMC_DMCR_RMODE (1 << 25)
1832 #define EMC_DMCR_RFSH (1 << 24)
1833 #define EMC_DMCR_MRSET (1 << 23)
1834 #define EMC_DMCR_RA_BIT 20
1835 #define EMC_DMCR_RA_MASK (0x03 << EMC_DMCR_RA_BIT)
1836 #define EMC_DMCR_RA_11 (0 << EMC_DMCR_RA_BIT)
1837 #define EMC_DMCR_RA_12 (1 << EMC_DMCR_RA_BIT)
1838 #define EMC_DMCR_RA_13 (2 << EMC_DMCR_RA_BIT)
1839 #define EMC_DMCR_BA_BIT 19
1840 #define EMC_DMCR_BA (1 << EMC_DMCR_BA_BIT)
1841 #define EMC_DMCR_PDM (1 << 18)
1842 #define EMC_DMCR_EPIN (1 << 17)
1843 #define EMC_DMCR_TRAS_BIT 13
1844 #define EMC_DMCR_TRAS_MASK (0x07 << EMC_DMCR_TRAS_BIT)
1845 #define EMC_DMCR_RCD_BIT 11
1846 #define EMC_DMCR_RCD_MASK (0x03 << EMC_DMCR_RCD_BIT)
1847 #define EMC_DMCR_TPC_BIT 8
1848 #define EMC_DMCR_TPC_MASK (0x07 << EMC_DMCR_TPC_BIT)
1849 #define EMC_DMCR_TRWL_BIT 5
1850 #define EMC_DMCR_TRWL_MASK (0x03 << EMC_DMCR_TRWL_BIT)
1851 #define EMC_DMCR_TRC_BIT 2
1852 #define EMC_DMCR_TRC_MASK (0x07 << EMC_DMCR_TRC_BIT)
1853 #define EMC_DMCR_TCL_BIT 0
1854 #define EMC_DMCR_TCL_MASK (0x03 << EMC_DMCR_TCL_BIT)
1855
1856 /* Refresh Time Control/Status Register */
1857 #define EMC_RTCSR_CMF (1 << 7)
1858 #define EMC_RTCSR_CKS_BIT 0
1859 #define EMC_RTCSR_CKS_MASK (0x07 << EMC_RTCSR_CKS_BIT)
1860 #define EMC_RTCSR_CKS_DISABLE (0 << EMC_RTCSR_CKS_BIT)
1861 #define EMC_RTCSR_CKS_4 (1 << EMC_RTCSR_CKS_BIT)
1862 #define EMC_RTCSR_CKS_16 (2 << EMC_RTCSR_CKS_BIT)
1863 #define EMC_RTCSR_CKS_64 (3 << EMC_RTCSR_CKS_BIT)
1864 #define EMC_RTCSR_CKS_256 (4 << EMC_RTCSR_CKS_BIT)
1865 #define EMC_RTCSR_CKS_1024 (5 << EMC_RTCSR_CKS_BIT)
1866 #define EMC_RTCSR_CKS_2048 (6 << EMC_RTCSR_CKS_BIT)
1867 #define EMC_RTCSR_CKS_4096 (7 << EMC_RTCSR_CKS_BIT)
1868
1869 /* SDRAM Bank Address Configuration Register */
1870 #define EMC_DMAR_BASE_BIT 8
1871 #define EMC_DMAR_BASE_MASK (0xff << EMC_DMAR_BASE_BIT)
1872 #define EMC_DMAR_MASK_BIT 0
1873 #define EMC_DMAR_MASK_MASK (0xff << EMC_DMAR_MASK_BIT)
1874
1875 /* Mode Register of SDRAM bank 0 */
1876 #define EMC_SDMR_BM (1 << 9) /* Write Burst Mode */
1877 #define EMC_SDMR_OM_BIT 7 /* Operating Mode */
1878 #define EMC_SDMR_OM_MASK (3 << EMC_SDMR_OM_BIT)
1879 #define EMC_SDMR_OM_NORMAL (0 << EMC_SDMR_OM_BIT)
1880 #define EMC_SDMR_CAS_BIT 4 /* CAS Latency */
1881 #define EMC_SDMR_CAS_MASK (7 << EMC_SDMR_CAS_BIT)
1882 #define EMC_SDMR_CAS_1 (1 << EMC_SDMR_CAS_BIT)
1883 #define EMC_SDMR_CAS_2 (2 << EMC_SDMR_CAS_BIT)
1884 #define EMC_SDMR_CAS_3 (3 << EMC_SDMR_CAS_BIT)
1885 #define EMC_SDMR_BT_BIT 3 /* Burst Type */
1886 #define EMC_SDMR_BT_MASK (1 << EMC_SDMR_BT_BIT)
1887 #define EMC_SDMR_BT_SEQ (0 << EMC_SDMR_BT_BIT) /* Sequential */
1888 #define EMC_SDMR_BT_INT (1 << EMC_SDMR_BT_BIT) /* Interleave */
1889 #define EMC_SDMR_BL_BIT 0 /* Burst Length */
1890 #define EMC_SDMR_BL_MASK (7 << EMC_SDMR_BL_BIT)
1891 #define EMC_SDMR_BL_1 (0 << EMC_SDMR_BL_BIT)
1892 #define EMC_SDMR_BL_2 (1 << EMC_SDMR_BL_BIT)
1893 #define EMC_SDMR_BL_4 (2 << EMC_SDMR_BL_BIT)
1894 #define EMC_SDMR_BL_8 (3 << EMC_SDMR_BL_BIT)
1895
1896 #define EMC_SDMR_CAS2_16BIT \
1897 (EMC_SDMR_CAS_2 | EMC_SDMR_BT_SEQ | EMC_SDMR_BL_2)
1898 #define EMC_SDMR_CAS2_32BIT \
1899 (EMC_SDMR_CAS_2 | EMC_SDMR_BT_SEQ | EMC_SDMR_BL_4)
1900 #define EMC_SDMR_CAS3_16BIT \
1901 (EMC_SDMR_CAS_3 | EMC_SDMR_BT_SEQ | EMC_SDMR_BL_2)
1902 #define EMC_SDMR_CAS3_32BIT \
1903 (EMC_SDMR_CAS_3 | EMC_SDMR_BT_SEQ | EMC_SDMR_BL_4)
1904
1905 /*************************************************************************
1906 * CIM
1907 *************************************************************************/
1908 #define CIM_CFG (CIM_BASE + 0x0000)
1909 #define CIM_CTRL (CIM_BASE + 0x0004)
1910 #define CIM_STATE (CIM_BASE + 0x0008)
1911 #define CIM_IID (CIM_BASE + 0x000C)
1912 #define CIM_RXFIFO (CIM_BASE + 0x0010)
1913 #define CIM_DA (CIM_BASE + 0x0020)
1914 #define CIM_FA (CIM_BASE + 0x0024)
1915 #define CIM_FID (CIM_BASE + 0x0028)
1916 #define CIM_CMD (CIM_BASE + 0x002C)
1917
1918 #define REG_CIM_CFG REG32(CIM_CFG)
1919 #define REG_CIM_CTRL REG32(CIM_CTRL)
1920 #define REG_CIM_STATE REG32(CIM_STATE)
1921 #define REG_CIM_IID REG32(CIM_IID)
1922 #define REG_CIM_RXFIFO REG32(CIM_RXFIFO)
1923 #define REG_CIM_DA REG32(CIM_DA)
1924 #define REG_CIM_FA REG32(CIM_FA)
1925 #define REG_CIM_FID REG32(CIM_FID)
1926 #define REG_CIM_CMD REG32(CIM_CMD)
1927
1928 /* CIM Configuration Register (CIM_CFG) */
1929
1930 #define CIM_CFG_INV_DAT (1 << 15)
1931 #define CIM_CFG_VSP (1 << 14)
1932 #define CIM_CFG_HSP (1 << 13)
1933 #define CIM_CFG_PCP (1 << 12)
1934 #define CIM_CFG_DUMMY_ZERO (1 << 9)
1935 #define CIM_CFG_EXT_VSYNC (1 << 8)
1936 #define CIM_CFG_PACK_BIT 4
1937 #define CIM_CFG_PACK_MASK (0x7 << CIM_CFG_PACK_BIT)
1938 #define CIM_CFG_PACK_0 (0 << CIM_CFG_PACK_BIT)
1939 #define CIM_CFG_PACK_1 (1 << CIM_CFG_PACK_BIT)
1940 #define CIM_CFG_PACK_2 (2 << CIM_CFG_PACK_BIT)
1941 #define CIM_CFG_PACK_3 (3 << CIM_CFG_PACK_BIT)
1942 #define CIM_CFG_PACK_4 (4 << CIM_CFG_PACK_BIT)
1943 #define CIM_CFG_PACK_5 (5 << CIM_CFG_PACK_BIT)
1944 #define CIM_CFG_PACK_6 (6 << CIM_CFG_PACK_BIT)
1945 #define CIM_CFG_PACK_7 (7 << CIM_CFG_PACK_BIT)
1946 #define CIM_CFG_DSM_BIT 0
1947 #define CIM_CFG_DSM_MASK (0x3 << CIM_CFG_DSM_BIT)
1948 #define CIM_CFG_DSM_CPM (0 << CIM_CFG_DSM_BIT) /* CCIR656 Progressive Mode */
1949 #define CIM_CFG_DSM_CIM (1 << CIM_CFG_DSM_BIT) /* CCIR656 Interlace Mode */
1950 #define CIM_CFG_DSM_GCM (2 << CIM_CFG_DSM_BIT) /* Gated Clock Mode */
1951 #define CIM_CFG_DSM_NGCM (3 << CIM_CFG_DSM_BIT) /* Non-Gated Clock Mode */
1952
1953 /* CIM Control Register (CIM_CTRL) */
1954
1955 #define CIM_CTRL_MCLKDIV_BIT 24
1956 #define CIM_CTRL_MCLKDIV_MASK (0xff << CIM_CTRL_MCLKDIV_BIT)
1957 #define CIM_CTRL_FRC_BIT 16
1958 #define CIM_CTRL_FRC_MASK (0xf << CIM_CTRL_FRC_BIT)
1959 #define CIM_CTRL_FRC_1 (0x0 << CIM_CTRL_FRC_BIT) /* Sample every frame */
1960 #define CIM_CTRL_FRC_2 (0x1 << CIM_CTRL_FRC_BIT) /* Sample 1/2 frame */
1961 #define CIM_CTRL_FRC_3 (0x2 << CIM_CTRL_FRC_BIT) /* Sample 1/3 frame */
1962 #define CIM_CTRL_FRC_4 (0x3 << CIM_CTRL_FRC_BIT) /* Sample 1/4 frame */
1963 #define CIM_CTRL_FRC_5 (0x4 << CIM_CTRL_FRC_BIT) /* Sample 1/5 frame */
1964 #define CIM_CTRL_FRC_6 (0x5 << CIM_CTRL_FRC_BIT) /* Sample 1/6 frame */
1965 #define CIM_CTRL_FRC_7 (0x6 << CIM_CTRL_FRC_BIT) /* Sample 1/7 frame */
1966 #define CIM_CTRL_FRC_8 (0x7 << CIM_CTRL_FRC_BIT) /* Sample 1/8 frame */
1967 #define CIM_CTRL_FRC_9 (0x8 << CIM_CTRL_FRC_BIT) /* Sample 1/9 frame */
1968 #define CIM_CTRL_FRC_10 (0x9 << CIM_CTRL_FRC_BIT) /* Sample 1/10 frame */
1969 #define CIM_CTRL_FRC_11 (0xA << CIM_CTRL_FRC_BIT) /* Sample 1/11 frame */
1970 #define CIM_CTRL_FRC_12 (0xB << CIM_CTRL_FRC_BIT) /* Sample 1/12 frame */
1971 #define CIM_CTRL_FRC_13 (0xC << CIM_CTRL_FRC_BIT) /* Sample 1/13 frame */
1972 #define CIM_CTRL_FRC_14 (0xD << CIM_CTRL_FRC_BIT) /* Sample 1/14 frame */
1973 #define CIM_CTRL_FRC_15 (0xE << CIM_CTRL_FRC_BIT) /* Sample 1/15 frame */
1974 #define CIM_CTRL_FRC_16 (0xF << CIM_CTRL_FRC_BIT) /* Sample 1/16 frame */
1975 #define CIM_CTRL_VDDM (1 << 13)
1976 #define CIM_CTRL_DMA_SOFM (1 << 12)
1977 #define CIM_CTRL_DMA_EOFM (1 << 11)
1978 #define CIM_CTRL_DMA_STOPM (1 << 10)
1979 #define CIM_CTRL_RXF_TRIGM (1 << 9)
1980 #define CIM_CTRL_RXF_OFM (1 << 8)
1981 #define CIM_CTRL_RXF_TRIG_BIT 4
1982 #define CIM_CTRL_RXF_TRIG_MASK (0x7 << CIM_CTRL_RXF_TRIG_BIT)
1983 #define CIM_CTRL_RXF_TRIG_4 (0 << CIM_CTRL_RXF_TRIG_BIT) /* RXFIFO Trigger Value is 4 */
1984 #define CIM_CTRL_RXF_TRIG_8 (1 << CIM_CTRL_RXF_TRIG_BIT) /* RXFIFO Trigger Value is 8 */
1985 #define CIM_CTRL_RXF_TRIG_12 (2 << CIM_CTRL_RXF_TRIG_BIT) /* RXFIFO Trigger Value is 12 */
1986 #define CIM_CTRL_RXF_TRIG_16 (3 << CIM_CTRL_RXF_TRIG_BIT) /* RXFIFO Trigger Value is 16 */
1987 #define CIM_CTRL_RXF_TRIG_20 (4 << CIM_CTRL_RXF_TRIG_BIT) /* RXFIFO Trigger Value is 20 */
1988 #define CIM_CTRL_RXF_TRIG_24 (5 << CIM_CTRL_RXF_TRIG_BIT) /* RXFIFO Trigger Value is 24 */
1989 #define CIM_CTRL_RXF_TRIG_28 (6 << CIM_CTRL_RXF_TRIG_BIT) /* RXFIFO Trigger Value is 28 */
1990 #define CIM_CTRL_RXF_TRIG_32 (7 << CIM_CTRL_RXF_TRIG_BIT) /* RXFIFO Trigger Value is 32 */
1991 #define CIM_CTRL_DMA_EN (1 << 2)
1992 #define CIM_CTRL_RXF_RST (1 << 1)
1993 #define CIM_CTRL_ENA (1 << 0)
1994
1995 /* CIM State Register (CIM_STATE) */
1996
1997 #define CIM_STATE_DMA_SOF (1 << 6)
1998 #define CIM_STATE_DMA_EOF (1 << 5)
1999 #define CIM_STATE_DMA_STOP (1 << 4)
2000 #define CIM_STATE_RXF_OF (1 << 3)
2001 #define CIM_STATE_RXF_TRIG (1 << 2)
2002 #define CIM_STATE_RXF_EMPTY (1 << 1)
2003 #define CIM_STATE_VDD (1 << 0)
2004
2005 /* CIM DMA Command Register (CIM_CMD) */
2006
2007 #define CIM_CMD_SOFINT (1 << 31)
2008 #define CIM_CMD_EOFINT (1 << 30)
2009 #define CIM_CMD_STOP (1 << 28)
2010 #define CIM_CMD_LEN_BIT 0
2011 #define CIM_CMD_LEN_MASK (0xffffff << CIM_CMD_LEN_BIT)
2012
2013
2014 /*************************************************************************
2015 * SADC (Smart A/D Controller)
2016 *************************************************************************/
2017
2018 #define SADC_ENA (SADC_BASE + 0x00) /* ADC Enable Register */
2019 #define SADC_CFG (SADC_BASE + 0x04) /* ADC Configure Register */
2020 #define SADC_CTRL (SADC_BASE + 0x08) /* ADC Control Register */
2021 #define SADC_STATE (SADC_BASE + 0x0C) /* ADC Status Register*/
2022 #define SADC_SAMETIME (SADC_BASE + 0x10) /* ADC Same Point Time Register */
2023 #define SADC_WAITTIME (SADC_BASE + 0x14) /* ADC Wait Time Register */
2024 #define SADC_TSDAT (SADC_BASE + 0x18) /* ADC Touch Screen Data Register */
2025 #define SADC_BATDAT (SADC_BASE + 0x1C) /* ADC PBAT Data Register */
2026 #define SADC_SADDAT (SADC_BASE + 0x20) /* ADC SADCIN Data Register */
2027
2028 #define REG_SADC_ENA REG8(SADC_ENA)
2029 #define REG_SADC_CFG REG32(SADC_CFG)
2030 #define REG_SADC_CTRL REG8(SADC_CTRL)
2031 #define REG_SADC_STATE REG8(SADC_STATE)
2032 #define REG_SADC_SAMETIME REG16(SADC_SAMETIME)
2033 #define REG_SADC_WAITTIME REG16(SADC_WAITTIME)
2034 #define REG_SADC_TSDAT REG32(SADC_TSDAT)
2035 #define REG_SADC_BATDAT REG16(SADC_BATDAT)
2036 #define REG_SADC_SADDAT REG16(SADC_SADDAT)
2037
2038 /* ADC Enable Register */
2039 #define SADC_ENA_ADEN (1 << 7) /* Touch Screen Enable */
2040 #define SADC_ENA_TSEN (1 << 2) /* Touch Screen Enable */
2041 #define SADC_ENA_PBATEN (1 << 1) /* PBAT Enable */
2042 #define SADC_ENA_SADCINEN (1 << 0) /* SADCIN Enable */
2043
2044 /* ADC Configure Register */
2045 #define SADC_CFG_CLKOUT_NUM_BIT 16
2046 #define SADC_CFG_CLKOUT_NUM_MASK (0x7 << SADC_CFG_CLKOUT_NUM_BIT)
2047 #define SADC_CFG_TS_DMA (1 << 15) /* Touch Screen DMA Enable */
2048 #define SADC_CFG_XYZ_BIT 13 /* XYZ selection */
2049 #define SADC_CFG_XYZ_MASK (0x3 << SADC_CFG_XYZ_BIT)
2050 #define SADC_CFG_XY (0 << SADC_CFG_XYZ_BIT)
2051 #define SADC_CFG_XYZ (1 << SADC_CFG_XYZ_BIT)
2052 #define SADC_CFG_XYZ1Z2 (2 << SADC_CFG_XYZ_BIT)
2053 #define SADC_CFG_SNUM_BIT 10 /* Sample Number */
2054 #define SADC_CFG_SNUM_MASK (0x7 << SADC_CFG_SNUM_BIT)
2055 #define SADC_CFG_SNUM_1 (0x0 << SADC_CFG_SNUM_BIT)
2056 #define SADC_CFG_SNUM_2 (0x1 << SADC_CFG_SNUM_BIT)
2057 #define SADC_CFG_SNUM_3 (0x2 << SADC_CFG_SNUM_BIT)
2058 #define SADC_CFG_SNUM_4 (0x3 << SADC_CFG_SNUM_BIT)
2059 #define SADC_CFG_SNUM_5 (0x4 << SADC_CFG_SNUM_BIT)
2060 #define SADC_CFG_SNUM_6 (0x5 << SADC_CFG_SNUM_BIT)
2061 #define SADC_CFG_SNUM_8 (0x6 << SADC_CFG_SNUM_BIT)
2062 #define SADC_CFG_SNUM_9 (0x7 << SADC_CFG_SNUM_BIT)
2063 #define SADC_CFG_CLKDIV_BIT 5 /* AD Converter frequency clock divider */
2064 #define SADC_CFG_CLKDIV_MASK (0x1f << SADC_CFG_CLKDIV_BIT)
2065 #define SADC_CFG_PBAT_HIGH (0 << 4) /* PBAT >= 2.5V */
2066 #define SADC_CFG_PBAT_LOW (1 << 4) /* PBAT < 2.5V */
2067 #define SADC_CFG_CMD_BIT 0 /* ADC Command */
2068 #define SADC_CFG_CMD_MASK (0xf << SADC_CFG_CMD_BIT)
2069 #define SADC_CFG_CMD_X_SE (0x0 << SADC_CFG_CMD_BIT) /* X Single-End */
2070 #define SADC_CFG_CMD_Y_SE (0x1 << SADC_CFG_CMD_BIT) /* Y Single-End */
2071 #define SADC_CFG_CMD_X_DIFF (0x2 << SADC_CFG_CMD_BIT) /* X Differential */
2072 #define SADC_CFG_CMD_Y_DIFF (0x3 << SADC_CFG_CMD_BIT) /* Y Differential */
2073 #define SADC_CFG_CMD_Z1_DIFF (0x4 << SADC_CFG_CMD_BIT) /* Z1 Differential */
2074 #define SADC_CFG_CMD_Z2_DIFF (0x5 << SADC_CFG_CMD_BIT) /* Z2 Differential */
2075 #define SADC_CFG_CMD_Z3_DIFF (0x6 << SADC_CFG_CMD_BIT) /* Z3 Differential */
2076 #define SADC_CFG_CMD_Z4_DIFF (0x7 << SADC_CFG_CMD_BIT) /* Z4 Differential */
2077 #define SADC_CFG_CMD_TP_SE (0x8 << SADC_CFG_CMD_BIT) /* Touch Pressure */
2078 #define SADC_CFG_CMD_PBATH_SE (0x9 << SADC_CFG_CMD_BIT) /* PBAT >= 2.5V */
2079 #define SADC_CFG_CMD_PBATL_SE (0xa << SADC_CFG_CMD_BIT) /* PBAT < 2.5V */
2080 #define SADC_CFG_CMD_SADCIN_SE (0xb << SADC_CFG_CMD_BIT) /* Measure SADCIN */
2081 #define SADC_CFG_CMD_INT_PEN (0xc << SADC_CFG_CMD_BIT) /* INT_PEN Enable */
2082
2083 /* ADC Control Register */
2084 #define SADC_CTRL_PENDM (1 << 4) /* Pen Down Interrupt Mask */
2085 #define SADC_CTRL_PENUM (1 << 3) /* Pen Up Interrupt Mask */
2086 #define SADC_CTRL_TSRDYM (1 << 2) /* Touch Screen Data Ready Interrupt Mask */
2087 #define SADC_CTRL_PBATRDYM (1 << 1) /* PBAT Data Ready Interrupt Mask */
2088 #define SADC_CTRL_SRDYM (1 << 0) /* SADCIN Data Ready Interrupt Mask */
2089
2090 /* ADC Status Register */
2091 #define SADC_STATE_TSBUSY (1 << 7) /* TS A/D is working */
2092 #define SADC_STATE_PBATBUSY (1 << 6) /* PBAT A/D is working */
2093 #define SADC_STATE_SBUSY (1 << 5) /* SADCIN A/D is working */
2094 #define SADC_STATE_PEND (1 << 4) /* Pen Down Interrupt Flag */
2095 #define SADC_STATE_PENU (1 << 3) /* Pen Up Interrupt Flag */
2096 #define SADC_STATE_TSRDY (1 << 2) /* Touch Screen Data Ready Interrupt Flag */
2097 #define SADC_STATE_PBATRDY (1 << 1) /* PBAT Data Ready Interrupt Flag */
2098 #define SADC_STATE_SRDY (1 << 0) /* SADCIN Data Ready Interrupt Flag */
2099
2100 /* ADC Touch Screen Data Register */
2101 #define SADC_TSDAT_DATA0_BIT 0
2102 #define SADC_TSDAT_DATA0_MASK (0xfff << SADC_TSDAT_DATA0_BIT)
2103 #define SADC_TSDAT_TYPE0 (1 << 15)
2104 #define SADC_TSDAT_DATA1_BIT 16
2105 #define SADC_TSDAT_DATA1_MASK (0xfff << SADC_TSDAT_DATA1_BIT)
2106 #define SADC_TSDAT_TYPE1 (1 << 31)
2107
2108
2109 /*************************************************************************
2110 * SLCD (Smart LCD Controller)
2111 *************************************************************************/
2112
2113 #define SLCD_CFG (SLCD_BASE + 0xA0) /* SLCD Configure Register */
2114 #define SLCD_CTRL (SLCD_BASE + 0xA4) /* SLCD Control Register */
2115 #define SLCD_STATE (SLCD_BASE + 0xA8) /* SLCD Status Register */
2116 #define SLCD_DATA (SLCD_BASE + 0xAC) /* SLCD Data Register */
2117 #define SLCD_FIFO (SLCD_BASE + 0xB0) /* SLCD FIFO Register */
2118
2119 #define REG_SLCD_CFG REG32(SLCD_CFG)
2120 #define REG_SLCD_CTRL REG8(SLCD_CTRL)
2121 #define REG_SLCD_STATE REG8(SLCD_STATE)
2122 #define REG_SLCD_DATA REG32(SLCD_DATA)
2123 #define REG_SLCD_FIFO REG32(SLCD_FIFO)
2124
2125 /* SLCD Configure Register */
2126 #define SLCD_CFG_BURST_BIT 14
2127 #define SLCD_CFG_BURST_MASK (0x3 << SLCD_CFG_BURST_BIT)
2128 #define SLCD_CFG_BURST_4_WORD (0 << SLCD_CFG_BURST_BIT)
2129 #define SLCD_CFG_BURST_8_WORD (1 << SLCD_CFG_BURST_BIT)
2130 #define SLCD_CFG_DWIDTH_BIT 10
2131 #define SLCD_CFG_DWIDTH_MASK (0x7 << SLCD_CFG_DWIDTH_BIT)
2132 #define SLCD_CFG_DWIDTH_18 (0 << SLCD_CFG_DWIDTH_BIT)
2133 #define SLCD_CFG_DWIDTH_16 (1 << SLCD_CFG_DWIDTH_BIT)
2134 #define SLCD_CFG_DWIDTH_8_x3 (2 << SLCD_CFG_DWIDTH_BIT)
2135 #define SLCD_CFG_DWIDTH_8_x2 (3 << SLCD_CFG_DWIDTH_BIT)
2136 #define SLCD_CFG_DWIDTH_8_x1 (4 << SLCD_CFG_DWIDTH_BIT)
2137 #define SLCD_CFG_DWIDTH_9_x2 (4 << SLCD_CFG_DWIDTH_BIT)
2138 #define SLCD_CFG_CWIDTH_16BIT (0 << 8)
2139 #define SLCD_CFG_CWIDTH_8BIT (1 << 8)
2140 #define SLCD_CFG_CWIDTH_18BIT (2 << 8)
2141 #define SLCD_CFG_CS_ACTIVE_LOW (0 << 4)
2142 #define SLCD_CFG_CS_ACTIVE_HIGH (1 << 4)
2143 #define SLCD_CFG_RS_CMD_LOW (0 << 3)
2144 #define SLCD_CFG_RS_CMD_HIGH (1 << 3)
2145 #define SLCD_CFG_CLK_ACTIVE_FALLING (0 << 1)
2146 #define SLCD_CFG_CLK_ACTIVE_RISING (1 << 1)
2147 #define SLCD_CFG_TYPE_PARALLEL (0 << 0)
2148 #define SLCD_CFG_TYPE_SERIAL (1 << 0)
2149
2150 /* SLCD Control Register */
2151 #define SLCD_CTRL_DMA_EN (1 << 0)
2152
2153 /* SLCD Status Register */
2154 #define SLCD_STATE_BUSY (1 << 0)
2155
2156 /* SLCD Data Register */
2157 #define SLCD_DATA_RS_DATA (0 << 31)
2158 #define SLCD_DATA_RS_COMMAND (1 << 31)
2159
2160 /* SLCD FIFO Register */
2161 #define SLCD_FIFO_RS_DATA (0 << 31)
2162 #define SLCD_FIFO_RS_COMMAND (1 << 31)
2163
2164
2165 /*************************************************************************
2166 * LCD (LCD Controller)
2167 *************************************************************************/
2168 #define LCD_CFG (LCD_BASE + 0x00) /* LCD Configure Register */
2169 #define LCD_VSYNC (LCD_BASE + 0x04) /* Vertical Synchronize Register */
2170 #define LCD_HSYNC (LCD_BASE + 0x08) /* Horizontal Synchronize Register */
2171 #define LCD_VAT (LCD_BASE + 0x0c) /* Virtual Area Setting Register */
2172 #define LCD_DAH (LCD_BASE + 0x10) /* Display Area Horizontal Start/End Point */
2173 #define LCD_DAV (LCD_BASE + 0x14) /* Display Area Vertical Start/End Point */
2174 #define LCD_PS (LCD_BASE + 0x18) /* PS Signal Setting */
2175 #define LCD_CLS (LCD_BASE + 0x1c) /* CLS Signal Setting */
2176 #define LCD_SPL (LCD_BASE + 0x20) /* SPL Signal Setting */
2177 #define LCD_REV (LCD_BASE + 0x24) /* REV Signal Setting */
2178 #define LCD_CTRL (LCD_BASE + 0x30) /* LCD Control Register */
2179 #define LCD_STATE (LCD_BASE + 0x34) /* LCD Status Register */
2180 #define LCD_IID (LCD_BASE + 0x38) /* Interrupt ID Register */
2181 #define LCD_DA0 (LCD_BASE + 0x40) /* Descriptor Address Register 0 */
2182 #define LCD_SA0 (LCD_BASE + 0x44) /* Source Address Register 0 */
2183 #define LCD_FID0 (LCD_BASE + 0x48) /* Frame ID Register 0 */
2184 #define LCD_CMD0 (LCD_BASE + 0x4c) /* DMA Command Register 0 */
2185 #define LCD_DA1 (LCD_BASE + 0x50) /* Descriptor Address Register 1 */
2186 #define LCD_SA1 (LCD_BASE + 0x54) /* Source Address Register 1 */
2187 #define LCD_FID1 (LCD_BASE + 0x58) /* Frame ID Register 1 */
2188 #define LCD_CMD1 (LCD_BASE + 0x5c) /* DMA Command Register 1 */
2189
2190 #define REG_LCD_CFG REG32(LCD_CFG)
2191 #define REG_LCD_VSYNC REG32(LCD_VSYNC)
2192 #define REG_LCD_HSYNC REG32(LCD_HSYNC)
2193 #define REG_LCD_VAT REG32(LCD_VAT)
2194 #define REG_LCD_DAH REG32(LCD_DAH)
2195 #define REG_LCD_DAV REG32(LCD_DAV)
2196 #define REG_LCD_PS REG32(LCD_PS)
2197 #define REG_LCD_CLS REG32(LCD_CLS)
2198 #define REG_LCD_SPL REG32(LCD_SPL)
2199 #define REG_LCD_REV REG32(LCD_REV)
2200 #define REG_LCD_CTRL REG32(LCD_CTRL)
2201 #define REG_LCD_STATE REG32(LCD_STATE)
2202 #define REG_LCD_IID REG32(LCD_IID)
2203 #define REG_LCD_DA0 REG32(LCD_DA0)
2204 #define REG_LCD_SA0 REG32(LCD_SA0)
2205 #define REG_LCD_FID0 REG32(LCD_FID0)
2206 #define REG_LCD_CMD0 REG32(LCD_CMD0)
2207 #define REG_LCD_DA1 REG32(LCD_DA1)
2208 #define REG_LCD_SA1 REG32(LCD_SA1)
2209 #define REG_LCD_FID1 REG32(LCD_FID1)
2210 #define REG_LCD_CMD1 REG32(LCD_CMD1)
2211
2212 /* LCD Configure Register */
2213 #define LCD_CFG_LCDPIN_BIT 31 /* LCD pins selection */
2214 #define LCD_CFG_LCDPIN_MASK (0x1 << LCD_CFG_LCDPIN_BIT)
2215 #define LCD_CFG_LCDPIN_LCD (0x0 << LCD_CFG_LCDPIN_BIT)
2216 #define LCD_CFG_LCDPIN_SLCD (0x1 << LCD_CFG_LCDPIN_BIT)
2217 #define LCD_CFG_PSM (1 << 23) /* PS signal mode */
2218 #define LCD_CFG_CLSM (1 << 22) /* CLS signal mode */
2219 #define LCD_CFG_SPLM (1 << 21) /* SPL signal mode */
2220 #define LCD_CFG_REVM (1 << 20) /* REV signal mode */
2221 #define LCD_CFG_HSYNM (1 << 19) /* HSYNC signal mode */
2222 #define LCD_CFG_PCLKM (1 << 18) /* PCLK signal mode */
2223 #define LCD_CFG_INVDAT (1 << 17) /* Inverse output data */
2224 #define LCD_CFG_SYNDIR_IN (1 << 16) /* VSYNC&HSYNC direction */
2225 #define LCD_CFG_PSP (1 << 15) /* PS pin reset state */
2226 #define LCD_CFG_CLSP (1 << 14) /* CLS pin reset state */
2227 #define LCD_CFG_SPLP (1 << 13) /* SPL pin reset state */
2228 #define LCD_CFG_REVP (1 << 12) /* REV pin reset state */
2229 #define LCD_CFG_HSP (1 << 11) /* HSYNC pority:0-active high,1-active low */
2230 #define LCD_CFG_PCP (1 << 10) /* PCLK pority:0-rising,1-falling */
2231 #define LCD_CFG_DEP (1 << 9) /* DE pority:0-active high,1-active low */
2232 #define LCD_CFG_VSP (1 << 8) /* VSYNC pority:0-rising,1-falling */
2233 #define LCD_CFG_PDW_BIT 4 /* STN pins utilization */
2234 #define LCD_CFG_PDW_MASK (0x3 << LCD_DEV_PDW_BIT)
2235 #define LCD_CFG_PDW_1 (0 << LCD_CFG_PDW_BIT) /* LCD_D[0] */
2236 #define LCD_CFG_PDW_2 (1 << LCD_CFG_PDW_BIT) /* LCD_D[0:1] */
2237 #define LCD_CFG_PDW_4 (2 << LCD_CFG_PDW_BIT) /* LCD_D[0:3]/LCD_D[8:11] */
2238 #define LCD_CFG_PDW_8 (3 << LCD_CFG_PDW_BIT) /* LCD_D[0:7]/LCD_D[8:15] */
2239 #define LCD_CFG_MODE_BIT 0 /* Display Device Mode Select */
2240 #define LCD_CFG_MODE_MASK (0x0f << LCD_CFG_MODE_BIT)
2241 #define LCD_CFG_MODE_GENERIC_TFT (0 << LCD_CFG_MODE_BIT) /* 16,18 bit TFT */
2242 #define LCD_CFG_MODE_SPECIAL_TFT_1 (1 << LCD_CFG_MODE_BIT)
2243 #define LCD_CFG_MODE_SPECIAL_TFT_2 (2 << LCD_CFG_MODE_BIT)
2244 #define LCD_CFG_MODE_SPECIAL_TFT_3 (3 << LCD_CFG_MODE_BIT)
2245 #define LCD_CFG_MODE_NONINTER_CCIR656 (4 << LCD_CFG_MODE_BIT)
2246 #define LCD_CFG_MODE_INTER_CCIR656 (5 << LCD_CFG_MODE_BIT)
2247 #define LCD_CFG_MODE_SINGLE_CSTN (8 << LCD_CFG_MODE_BIT)
2248 #define LCD_CFG_MODE_SINGLE_MSTN (9 << LCD_CFG_MODE_BIT)
2249 #define LCD_CFG_MODE_DUAL_CSTN (10 << LCD_CFG_MODE_BIT)
2250 #define LCD_CFG_MODE_DUAL_MSTN (11 << LCD_CFG_MODE_BIT)
2251 #define LCD_CFG_MODE_SERIAL_TFT (12 << LCD_CFG_MODE_BIT)
2252 #define LCD_CFG_MODE_GENERIC_18BIT_TFT (13 << LCD_CFG_MODE_BIT)
2253 /* JZ47XX defines */
2254 #define LCD_CFG_MODE_SHARP_HR (1 << LCD_CFG_MODE_BIT)
2255 #define LCD_CFG_MODE_CASIO_TFT (2 << LCD_CFG_MODE_BIT)
2256 #define LCD_CFG_MODE_SAMSUNG_ALPHA (3 << LCD_CFG_MODE_BIT)
2257
2258
2259
2260 /* Vertical Synchronize Register */
2261 #define LCD_VSYNC_VPS_BIT 16 /* VSYNC pulse start in line clock, fixed to 0 */
2262 #define LCD_VSYNC_VPS_MASK (0xffff << LCD_VSYNC_VPS_BIT)
2263 #define LCD_VSYNC_VPE_BIT 0 /* VSYNC pulse end in line clock */
2264 #define LCD_VSYNC_VPE_MASK (0xffff << LCD_VSYNC_VPS_BIT)
2265
2266 /* Horizontal Synchronize Register */
2267 #define LCD_HSYNC_HPS_BIT 16 /* HSYNC pulse start position in dot clock */
2268 #define LCD_HSYNC_HPS_MASK (0xffff << LCD_HSYNC_HPS_BIT)
2269 #define LCD_HSYNC_HPE_BIT 0 /* HSYNC pulse end position in dot clock */
2270 #define LCD_HSYNC_HPE_MASK (0xffff << LCD_HSYNC_HPE_BIT)
2271
2272 /* Virtual Area Setting Register */
2273 #define LCD_VAT_HT_BIT 16 /* Horizontal Total size in dot clock */
2274 #define LCD_VAT_HT_MASK (0xffff << LCD_VAT_HT_BIT)
2275 #define LCD_VAT_VT_BIT 0 /* Vertical Total size in dot clock */
2276 #define LCD_VAT_VT_MASK (0xffff << LCD_VAT_VT_BIT)
2277
2278 /* Display Area Horizontal Start/End Point Register */
2279 #define LCD_DAH_HDS_BIT 16 /* Horizontal display area start in dot clock */
2280 #define LCD_DAH_HDS_MASK (0xffff << LCD_DAH_HDS_BIT)
2281 #define LCD_DAH_HDE_BIT 0 /* Horizontal display area end in dot clock */
2282 #define LCD_DAH_HDE_MASK (0xffff << LCD_DAH_HDE_BIT)
2283
2284 /* Display Area Vertical Start/End Point Register */
2285 #define LCD_DAV_VDS_BIT 16 /* Vertical display area start in line clock */
2286 #define LCD_DAV_VDS_MASK (0xffff << LCD_DAV_VDS_BIT)
2287 #define LCD_DAV_VDE_BIT 0 /* Vertical display area end in line clock */
2288 #define LCD_DAV_VDE_MASK (0xffff << LCD_DAV_VDE_BIT)
2289
2290 /* PS Signal Setting */
2291 #define LCD_PS_PSS_BIT 16 /* PS signal start position in dot clock */
2292 #define LCD_PS_PSS_MASK (0xffff << LCD_PS_PSS_BIT)
2293 #define LCD_PS_PSE_BIT 0 /* PS signal end position in dot clock */
2294 #define LCD_PS_PSE_MASK (0xffff << LCD_PS_PSE_BIT)
2295
2296 /* CLS Signal Setting */
2297 #define LCD_CLS_CLSS_BIT 16 /* CLS signal start position in dot clock */
2298 #define LCD_CLS_CLSS_MASK (0xffff << LCD_CLS_CLSS_BIT)
2299 #define LCD_CLS_CLSE_BIT 0 /* CLS signal end position in dot clock */
2300 #define LCD_CLS_CLSE_MASK (0xffff << LCD_CLS_CLSE_BIT)
2301
2302 /* SPL Signal Setting */
2303 #define LCD_SPL_SPLS_BIT 16 /* SPL signal start position in dot clock */
2304 #define LCD_SPL_SPLS_MASK (0xffff << LCD_SPL_SPLS_BIT)
2305 #define LCD_SPL_SPLE_BIT 0 /* SPL signal end position in dot clock */
2306 #define LCD_SPL_SPLE_MASK (0xffff << LCD_SPL_SPLE_BIT)
2307
2308 /* REV Signal Setting */
2309 #define LCD_REV_REVS_BIT 16 /* REV signal start position in dot clock */
2310 #define LCD_REV_REVS_MASK (0xffff << LCD_REV_REVS_BIT)
2311
2312 /* LCD Control Register */
2313 #define LCD_CTRL_BST_BIT 28 /* Burst Length Selection */
2314 #define LCD_CTRL_BST_MASK (0x03 << LCD_CTRL_BST_BIT)
2315 #define LCD_CTRL_BST_4 (0 << LCD_CTRL_BST_BIT) /* 4-word */
2316 #define LCD_CTRL_BST_8 (1 << LCD_CTRL_BST_BIT) /* 8-word */
2317 #define LCD_CTRL_BST_16 (2 << LCD_CTRL_BST_BIT) /* 16-word */
2318 #define LCD_CTRL_RGB565 (0 << 27) /* RGB565 mode */
2319 #define LCD_CTRL_RGB555 (1 << 27) /* RGB555 mode */
2320 #define LCD_CTRL_OFUP (1 << 26) /* Output FIFO underrun protection enable */
2321 #define LCD_CTRL_FRC_BIT 24 /* STN FRC Algorithm Selection */
2322 #define LCD_CTRL_FRC_MASK (0x03 << LCD_CTRL_FRC_BIT)
2323 #define LCD_CTRL_FRC_16 (0 << LCD_CTRL_FRC_BIT) /* 16 grayscale */
2324 #define LCD_CTRL_FRC_4 (1 << LCD_CTRL_FRC_BIT) /* 4 grayscale */
2325 #define LCD_CTRL_FRC_2 (2 << LCD_CTRL_FRC_BIT) /* 2 grayscale */
2326 #define LCD_CTRL_PDD_BIT 16 /* Load Palette Delay Counter */
2327 #define LCD_CTRL_PDD_MASK (0xff << LCD_CTRL_PDD_BIT)
2328 #define LCD_CTRL_EOFM (1 << 13) /* EOF interrupt mask */
2329 #define LCD_CTRL_SOFM (1 << 12) /* SOF interrupt mask */
2330 #define LCD_CTRL_OFUM (1 << 11) /* Output FIFO underrun interrupt mask */
2331 #define LCD_CTRL_IFUM0 (1 << 10) /* Input FIFO 0 underrun interrupt mask */
2332 #define LCD_CTRL_IFUM1 (1 << 9) /* Input FIFO 1 underrun interrupt mask */
2333 #define LCD_CTRL_LDDM (1 << 8) /* LCD disable done interrupt mask */
2334 #define LCD_CTRL_QDM (1 << 7) /* LCD quick disable done interrupt mask */
2335 #define LCD_CTRL_BEDN (1 << 6) /* Endian selection */
2336 #define LCD_CTRL_PEDN (1 << 5) /* Endian in byte:0-msb first, 1-lsb first */
2337 #define LCD_CTRL_DIS (1 << 4) /* Disable indicate bit */
2338 #define LCD_CTRL_ENA (1 << 3) /* LCD enable bit */
2339 #define LCD_CTRL_BPP_BIT 0 /* Bits Per Pixel */
2340 #define LCD_CTRL_BPP_MASK (0x07 << LCD_CTRL_BPP_BIT)
2341 #define LCD_CTRL_BPP_1 (0 << LCD_CTRL_BPP_BIT) /* 1 bpp */
2342 #define LCD_CTRL_BPP_2 (1 << LCD_CTRL_BPP_BIT) /* 2 bpp */
2343 #define LCD_CTRL_BPP_4 (2 << LCD_CTRL_BPP_BIT) /* 4 bpp */
2344 #define LCD_CTRL_BPP_8 (3 << LCD_CTRL_BPP_BIT) /* 8 bpp */
2345 #define LCD_CTRL_BPP_16 (4 << LCD_CTRL_BPP_BIT) /* 15/16 bpp */
2346 #define LCD_CTRL_BPP_18_24 (5 << LCD_CTRL_BPP_BIT) /* 18/24/32 bpp */
2347
2348 /* LCD Status Register */
2349 #define LCD_STATE_QD (1 << 7) /* Quick Disable Done */
2350 #define LCD_STATE_EOF (1 << 5) /* EOF Flag */
2351 #define LCD_STATE_SOF (1 << 4) /* SOF Flag */
2352 #define LCD_STATE_OFU (1 << 3) /* Output FIFO Underrun */
2353 #define LCD_STATE_IFU0 (1 << 2) /* Input FIFO 0 Underrun */
2354 #define LCD_STATE_IFU1 (1 << 1) /* Input FIFO 1 Underrun */
2355 #define LCD_STATE_LDD (1 << 0) /* LCD Disabled */
2356
2357 /* DMA Command Register */
2358 #define LCD_CMD_SOFINT (1 << 31)
2359 #define LCD_CMD_EOFINT (1 << 30)
2360 #define LCD_CMD_PAL (1 << 28)
2361 #define LCD_CMD_LEN_BIT 0
2362 #define LCD_CMD_LEN_MASK (0xffffff << LCD_CMD_LEN_BIT)
2363
2364
2365 /*************************************************************************
2366 * USB Device
2367 *************************************************************************/
2368 #define USB_BASE UDC_BASE
2369
2370 #define USB_REG_FADDR (USB_BASE + 0x00) /* Function Address 8-bit */
2371 #define USB_REG_POWER (USB_BASE + 0x01) /* Power Managemetn 8-bit */
2372 #define USB_REG_INTRIN (USB_BASE + 0x02) /* Interrupt IN 16-bit */
2373 #define USB_REG_INTROUT (USB_BASE + 0x04) /* Interrupt OUT 16-bit */
2374 #define USB_REG_INTRINE (USB_BASE + 0x06) /* Intr IN enable 16-bit */
2375 #define USB_REG_INTROUTE (USB_BASE + 0x08) /* Intr OUT enable 16-bit */
2376 #define USB_REG_INTRUSB (USB_BASE + 0x0a) /* Interrupt USB 8-bit */
2377 #define USB_REG_INTRUSBE (USB_BASE + 0x0b) /* Interrupt USB Enable 8-bit */
2378 #define USB_REG_FRAME (USB_BASE + 0x0c) /* Frame number 16-bit */
2379 #define USB_REG_INDEX (USB_BASE + 0x0e) /* Index register 8-bit */
2380 #define USB_REG_TESTMODE (USB_BASE + 0x0f) /* USB test mode 8-bit */
2381
2382 #define USB_REG_CSR0 (USB_BASE + 0x12) /* EP0 CSR 8-bit */
2383 #define USB_REG_INMAXP (USB_BASE + 0x10) /* EP1-2 IN Max Pkt Size 16-bit */
2384 #define USB_REG_INCSR (USB_BASE + 0x12) /* EP1-2 IN CSR LSB 8/16bit */
2385 #define USB_REG_INCSRH (USB_BASE + 0x13) /* EP1-2 IN CSR MSB 8-bit */
2386 #define USB_REG_OUTMAXP (USB_BASE + 0x14) /* EP1 OUT Max Pkt Size 16-bit */
2387 #define USB_REG_OUTCSR (USB_BASE + 0x16) /* EP1 OUT CSR LSB 8/16bit */
2388 #define USB_REG_OUTCSRH (USB_BASE + 0x17) /* EP1 OUT CSR MSB 8-bit */
2389 #define USB_REG_OUTCOUNT (USB_BASE + 0x18) /* bytes in EP0/1 OUT FIFO 16-bit */
2390
2391 #define USB_FIFO_EP0 (USB_BASE + 0x20)
2392 #define USB_FIFO_EP1 (USB_BASE + 0x24)
2393 #define USB_FIFO_EP2 (USB_BASE + 0x28)
2394
2395 #define USB_REG_EPINFO (USB_BASE + 0x78) /* Endpoint information */
2396 #define USB_REG_RAMINFO (USB_BASE + 0x79) /* RAM information */
2397
2398 #define USB_REG_INTR (USB_BASE + 0x200) /* DMA pending interrupts */
2399 #define USB_REG_CNTL1 (USB_BASE + 0x204) /* DMA channel 1 control */
2400 #define USB_REG_ADDR1 (USB_BASE + 0x208) /* DMA channel 1 AHB memory addr */
2401 #define USB_REG_COUNT1 (USB_BASE + 0x20c) /* DMA channel 1 byte count */
2402 #define USB_REG_CNTL2 (USB_BASE + 0x214) /* DMA channel 2 control */
2403 #define USB_REG_ADDR2 (USB_BASE + 0x218) /* DMA channel 2 AHB memory addr */
2404 #define USB_REG_COUNT2 (USB_BASE + 0x21c) /* DMA channel 2 byte count */
2405
2406
2407 /* Power register bit masks */
2408 #define USB_POWER_SUSPENDM 0x01
2409 #define USB_POWER_RESUME 0x04
2410 #define USB_POWER_HSMODE 0x10
2411 #define USB_POWER_HSENAB 0x20
2412 #define USB_POWER_SOFTCONN 0x40
2413
2414 /* Interrupt register bit masks */
2415 #define USB_INTR_SUSPEND 0x01
2416 #define USB_INTR_RESUME 0x02
2417 #define USB_INTR_RESET 0x04
2418
2419 #define USB_INTR_EP0 0x0001
2420 #define USB_INTR_INEP1 0x0002
2421 #define USB_INTR_INEP2 0x0004
2422 #define USB_INTR_OUTEP1 0x0002
2423
2424 /* CSR0 bit masks */
2425 #define USB_CSR0_OUTPKTRDY 0x01
2426 #define USB_CSR0_INPKTRDY 0x02
2427 #define USB_CSR0_SENTSTALL 0x04
2428 #define USB_CSR0_DATAEND 0x08
2429 #define USB_CSR0_SETUPEND 0x10
2430 #define USB_CSR0_SENDSTALL 0x20
2431 #define USB_CSR0_SVDOUTPKTRDY 0x40
2432 #define USB_CSR0_SVDSETUPEND 0x80
2433
2434 /* Endpoint CSR register bits */
2435 #define USB_INCSRH_AUTOSET 0x80
2436 #define USB_INCSRH_ISO 0x40
2437 #define USB_INCSRH_MODE 0x20
2438 #define USB_INCSRH_DMAREQENAB 0x10
2439 #define USB_INCSRH_DMAREQMODE 0x04
2440 #define USB_INCSR_CDT 0x40
2441 #define USB_INCSR_SENTSTALL 0x20
2442 #define USB_INCSR_SENDSTALL 0x10
2443 #define USB_INCSR_FF 0x08
2444 #define USB_INCSR_UNDERRUN 0x04
2445 #define USB_INCSR_FFNOTEMPT 0x02
2446 #define USB_INCSR_INPKTRDY 0x01
2447 #define USB_OUTCSRH_AUTOCLR 0x80
2448 #define USB_OUTCSRH_ISO 0x40
2449 #define USB_OUTCSRH_DMAREQENAB 0x20
2450 #define USB_OUTCSRH_DNYT 0x10
2451 #define USB_OUTCSRH_DMAREQMODE 0x08
2452 #define USB_OUTCSR_CDT 0x80
2453 #define USB_OUTCSR_SENTSTALL 0x40
2454 #define USB_OUTCSR_SENDSTALL 0x20
2455 #define USB_OUTCSR_FF 0x10
2456 #define USB_OUTCSR_DATAERR 0x08
2457 #define USB_OUTCSR_OVERRUN 0x04
2458 #define USB_OUTCSR_FFFULL 0x02
2459 #define USB_OUTCSR_OUTPKTRDY 0x01
2460
2461 /* Testmode register bits */
2462 #define USB_TEST_SE0NAK 0x01
2463 #define USB_TEST_J 0x02
2464 #define USB_TEST_K 0x04
2465 #define USB_TEST_PACKET 0x08
2466
2467 /* DMA control bits */
2468 #define USB_CNTL_ENA 0x01
2469 #define USB_CNTL_DIR_IN 0x02
2470 #define USB_CNTL_MODE_1 0x04
2471 #define USB_CNTL_INTR_EN 0x08
2472 #define USB_CNTL_EP(n) ((n) << 4)
2473 #define USB_CNTL_BURST_0 (0 << 9)
2474 #define USB_CNTL_BURST_4 (1 << 9)
2475 #define USB_CNTL_BURST_8 (2 << 9)
2476 #define USB_CNTL_BURST_16 (3 << 9)
2477
2478
2479
2480 /* Module Operation Definitions */
2481 #ifndef __ASSEMBLY__
2482
2483
2484 /* GPIO Pins Description */
2485 /* PORT 0: */
2486 /* PIN/BIT N FUNC0 FUNC1 */
2487 /* 0 D0 - */
2488 /* 1 D1 - */
2489 /* 2 D2 - */
2490 /* 3 D3 - */
2491 /* 4 D4 - */
2492 /* 5 D5 - */
2493 /* 6 D6 - */
2494 /* 7 D7 - */
2495 /* 8 D8 - */
2496 /* 9 D9 - */
2497 /* 10 D10 - */
2498 /* 11 D11 - */
2499 /* 12 D12 - */
2500 /* 13 D13 - */
2501 /* 14 D14 - */
2502 /* 15 D15 - */
2503 /* 16 D16 - */
2504 /* 17 D17 - */
2505 /* 18 D18 - */
2506 /* 19 D19 - */
2507 /* 20 D20 - */
2508 /* 21 D21 - */
2509 /* 22 D22 - */
2510 /* 23 D23 - */
2511 /* 24 D24 - */
2512 /* 25 D25 - */
2513 /* 26 D26 - */
2514 /* 27 D27 - */
2515 /* 28 D28 - */
2516 /* 29 D29 - */
2517 /* 30 D30 - */
2518 /* 31 D31 - */
2519 /*------------------------------------------------------ */
2520 /* PORT 1: */
2521 /* */
2522 /* PIN/BIT N FUNC0 FUNC1 */
2523 /* 0 A0 - */
2524 /* 1 A1 - */
2525 /* 2 A2 - */
2526 /* 3 A3 - */
2527 /* 4 A4 - */
2528 /* 5 A5 - */
2529 /* 6 A6 - */
2530 /* 7 A7 - */
2531 /* 8 A8 - */
2532 /* 9 A9 - */
2533 /* 10 A10 - */
2534 /* 11 A11 - */
2535 /* 12 A12 - */
2536 /* 13 A13 - */
2537 /* 14 A14 - */
2538 /* 15 A15/CL - */
2539 /* 16 A16/AL - */
2540 /* 17 LCD_CLS A21 */
2541 /* 18 LCD_SPL A22 */
2542 /* 19 DCS# - */
2543 /* 20 RAS# - */
2544 /* 21 CAS# - */
2545 /* 22 RDWE#/BUFD# - */
2546 /* 23 CKE - */
2547 /* 24 CKO - */
2548 /* 25 CS1# - */
2549 /* 26 CS2# - */
2550 /* 27 CS3# - */
2551 /* 28 CS4# - */
2552 /* 29 RD# - */
2553 /* 30 WR# - */
2554 /* 31 WE0# - */
2555 /* Note: PIN15&16 are CL&AL when connecting to NAND flash. */
2556 /*------------------------------------------------------ */
2557 /* PORT 2: */
2558 /* */
2559 /* PIN/BIT N FUNC0 FUNC1 */
2560 /* 0 LCD_D0 - */
2561 /* 1 LCD_D1 - */
2562 /* 2 LCD_D2 - */
2563 /* 3 LCD_D3 - */
2564 /* 4 LCD_D4 - */
2565 /* 5 LCD_D5 - */
2566 /* 6 LCD_D6 - */
2567 /* 7 LCD_D7 - */
2568 /* 8 LCD_D8 - */
2569 /* 9 LCD_D9 - */
2570 /* 10 LCD_D10 - */
2571 /* 11 LCD_D11 - */
2572 /* 12 LCD_D12 - */
2573 /* 13 LCD_D13 - */
2574 /* 14 LCD_D14 - */
2575 /* 15 LCD_D15 - */
2576 /* 16 LCD_D16 - */
2577 /* 17 LCD_D17 - */
2578 /* 18 LCD_PCLK - */
2579 /* 19 LCD_HSYNC - */
2580 /* 20 LCD_VSYNC - */
2581 /* 21 LCD_DE - */
2582 /* 22 LCD_PS A19 */
2583 /* 23 LCD_REV A20 */
2584 /* 24 WE1# - */
2585 /* 25 WE2# - */
2586 /* 26 WE3# - */
2587 /* 27 WAIT# - */
2588 /* 28 FRE# - */
2589 /* 29 FWE# - */
2590 /* 30(NOTE:FRB#) - - */
2591 /* 31 - - */
2592 /* NOTE(1): PIN30 is used for FRB# when connecting to NAND flash. */
2593 /*------------------------------------------------------ */
2594 /* PORT 3: */
2595 /* */
2596 /* PIN/BIT N FUNC0 FUNC1 */
2597 /* 0 CIM_D0 - */
2598 /* 1 CIM_D1 - */
2599 /* 2 CIM_D2 - */
2600 /* 3 CIM_D3 - */
2601 /* 4 CIM_D4 - */
2602 /* 5 CIM_D5 - */
2603 /* 6 CIM_D6 - */
2604 /* 7 CIM_D7 - */
2605 /* 8 MSC_CMD - */
2606 /* 9 MSC_CLK - */
2607 /* 10 MSC_D0 - */
2608 /* 11 MSC_D1 - */
2609 /* 12 MSC_D2 - */
2610 /* 13 MSC_D3 - */
2611 /* 14 CIM_MCLK - */
2612 /* 15 CIM_PCLK - */
2613 /* 16 CIM_VSYNC - */
2614 /* 17 CIM_HSYNC - */
2615 /* 18 SSI_CLK SCLK_RSTN */
2616 /* 19 SSI_CE0# BIT_CLK(AIC) */
2617 /* 20 SSI_DT SDATA_OUT(AIC) */
2618 /* 21 SSI_DR SDATA_IN(AIC) */
2619 /* 22 SSI_CE1#&GPC SYNC(AIC) */
2620 /* 23 PWM0 I2C_SDA */
2621 /* 24 PWM1 I2C_SCK */
2622 /* 25 PWM2 UART0_TxD */
2623 /* 26 PWM3 UART0_RxD */
2624 /* 27 PWM4 A17 */
2625 /* 28 PWM5 A18 */
2626 /* 29 - - */
2627 /* 30 PWM6 UART0_CTS/UART1_RxD */
2628 /* 31 PWM7 UART0_RTS/UART1_TxD */
2629 /*
2630 * p is the port number (0,1,2,3)
2631 * o is the pin offset (0-31) inside the port
2632 * n is the absolute number of a pin (0-127), regardless of the port
2633 */
2634
2635 /* Function Pins Mode */
2636
2637 #define __gpio_as_func0(n) \
2638 do { \
2639 unsigned int p, o; \
2640 p = (n) / 32; \
2641 o = (n) % 32; \
2642 REG_GPIO_PXFUNS(p) = (1 << o); \
2643 REG_GPIO_PXSELC(p) = (1 << o); \
2644 } while (0)
2645
2646 #define __gpio_as_func1(n) \
2647 do { \
2648 unsigned int p, o; \
2649 p = (n) / 32; \
2650 o = (n) % 32; \
2651 REG_GPIO_PXFUNS(p) = (1 << o); \
2652 REG_GPIO_PXSELS(p) = (1 << o); \
2653 } while (0)
2654
2655 /*
2656 * D0 ~ D31, A0 ~ A16, DCS#, RAS#, CAS#, CKE#,
2657 * RDWE#, CKO#, WE0#, WE1#, WE2#, WE3#
2658 */
2659 #define __gpio_as_sdram_32bit() \
2660 do { \
2661 REG_GPIO_PXFUNS(0) = 0xffffffff; \
2662 REG_GPIO_PXSELC(0) = 0xffffffff; \
2663 REG_GPIO_PXPES(0) = 0xffffffff; \
2664 REG_GPIO_PXFUNS(1) = 0x81f9ffff; \
2665 REG_GPIO_PXSELC(1) = 0x81f9ffff; \
2666 REG_GPIO_PXPES(1) = 0x81f9ffff; \
2667 REG_GPIO_PXFUNS(2) = 0x07000000; \
2668 REG_GPIO_PXSELC(2) = 0x07000000; \
2669 REG_GPIO_PXPES(2) = 0x07000000; \
2670 } while (0)
2671
2672 /*
2673 * D0 ~ D15, A0 ~ A16, DCS#, RAS#, CAS#, CKE#,
2674 * RDWE#, CKO#, WE0#, WE1#
2675 */
2676 #define __gpio_as_sdram_16bit_4720() \
2677 do { \
2678 REG_GPIO_PXFUNS(0) = 0x5442bfaa; \
2679 REG_GPIO_PXSELC(0) = 0x5442bfaa; \
2680 REG_GPIO_PXPES(0) = 0x5442bfaa; \
2681 REG_GPIO_PXFUNS(1) = 0x81f9ffff; \
2682 REG_GPIO_PXSELC(1) = 0x81f9ffff; \
2683 REG_GPIO_PXPES(1) = 0x81f9ffff; \
2684 REG_GPIO_PXFUNS(2) = 0x01000000; \
2685 REG_GPIO_PXSELC(2) = 0x01000000; \
2686 REG_GPIO_PXPES(2) = 0x01000000; \
2687 } while (0)
2688
2689 /*
2690 * D0 ~ D15, A0 ~ A16, DCS#, RAS#, CAS#, CKE#,
2691 * RDWE#, CKO#, WE0#, WE1#
2692 */
2693 #define __gpio_as_sdram_16bit_4725() \
2694 do { \
2695 REG_GPIO_PXFUNS(0) = 0x0000ffff; \
2696 REG_GPIO_PXSELC(0) = 0x0000ffff; \
2697 REG_GPIO_PXPES(0) = 0x0000ffff; \
2698 REG_GPIO_PXFUNS(1) = 0x81f9ffff; \
2699 REG_GPIO_PXSELC(1) = 0x81f9ffff; \
2700 REG_GPIO_PXPES(1) = 0x81f9ffff; \
2701 REG_GPIO_PXFUNS(2) = 0x01000000; \
2702 REG_GPIO_PXSELC(2) = 0x01000000; \
2703 REG_GPIO_PXPES(2) = 0x01000000; \
2704 } while (0)
2705
2706
2707 /*
2708 * CS1#, CLE, ALE, FRE#, FWE#, FRB#, RDWE#/BUFD#
2709 */
2710 #define __gpio_as_nand() \
2711 do { \
2712 REG_GPIO_PXFUNS(1) = 0x02018000; \
2713 REG_GPIO_PXSELC(1) = 0x02018000; \
2714 REG_GPIO_PXPES(1) = 0x02018000; \
2715 REG_GPIO_PXFUNS(2) = 0x30000000; \
2716 REG_GPIO_PXSELC(2) = 0x30000000; \
2717 REG_GPIO_PXPES(2) = 0x30000000; \
2718 REG_GPIO_PXFUNC(2) = 0x40000000; \
2719 REG_GPIO_PXSELC(2) = 0x40000000; \
2720 REG_GPIO_PXDIRC(2) = 0x40000000; \
2721 REG_GPIO_PXPES(2) = 0x40000000; \
2722 REG_GPIO_PXFUNS(1) = 0x00400000; \
2723 REG_GPIO_PXSELC(1) = 0x00400000; \
2724 } while (0)
2725
2726 /*
2727 * CS4#, RD#, WR#, WAIT#, A0 ~ A22, D0 ~ D7
2728 */
2729 #define __gpio_as_nor_8bit() \
2730 do { \
2731 REG_GPIO_PXFUNS(0) = 0x000000ff; \
2732 REG_GPIO_PXSELC(0) = 0x000000ff; \
2733 REG_GPIO_PXPES(0) = 0x000000ff; \
2734 REG_GPIO_PXFUNS(1) = 0x7041ffff; \
2735 REG_GPIO_PXSELC(1) = 0x7041ffff; \
2736 REG_GPIO_PXPES(1) = 0x7041ffff; \
2737 REG_GPIO_PXFUNS(1) = 0x00060000; \
2738 REG_GPIO_PXSELS(1) = 0x00060000; \
2739 REG_GPIO_PXPES(1) = 0x00060000; \
2740 REG_GPIO_PXFUNS(2) = 0x08000000; \
2741 REG_GPIO_PXSELC(2) = 0x08000000; \
2742 REG_GPIO_PXPES(2) = 0x08000000; \
2743 REG_GPIO_PXFUNS(2) = 0x00c00000; \
2744 REG_GPIO_PXSELS(2) = 0x00c00000; \
2745 REG_GPIO_PXPES(2) = 0x00c00000; \
2746 REG_GPIO_PXFUNS(3) = 0x18000000; \
2747 REG_GPIO_PXSELS(3) = 0x18000000; \
2748 REG_GPIO_PXPES(3) = 0x18000000; \
2749 } while (0)
2750
2751 /*
2752 * CS4#, RD#, WR#, WAIT#, A0 ~ A22, D0 ~ D15
2753 */
2754 #define __gpio_as_nor_16bit() \
2755 do { \
2756 REG_GPIO_PXFUNS(0) = 0x0000ffff; \
2757 REG_GPIO_PXSELC(0) = 0x0000ffff; \
2758 REG_GPIO_PXPES(0) = 0x0000ffff; \
2759 REG_GPIO_PXFUNS(1) = 0x7041ffff; \
2760 REG_GPIO_PXSELC(1) = 0x7041ffff; \
2761 REG_GPIO_PXPES(1) = 0x7041ffff; \
2762 REG_GPIO_PXFUNS(1) = 0x00060000; \
2763 REG_GPIO_PXSELS(1) = 0x00060000; \
2764 REG_GPIO_PXPES(1) = 0x00060000; \
2765 REG_GPIO_PXFUNS(2) = 0x08000000; \
2766 REG_GPIO_PXSELC(2) = 0x08000000; \
2767 REG_GPIO_PXPES(2) = 0x08000000; \
2768 REG_GPIO_PXFUNS(2) = 0x00c00000; \
2769 REG_GPIO_PXSELS(2) = 0x00c00000; \
2770 REG_GPIO_PXPES(2) = 0x00c00000; \
2771 REG_GPIO_PXFUNS(3) = 0x18000000; \
2772 REG_GPIO_PXSELS(3) = 0x18000000; \
2773 REG_GPIO_PXPES(3) = 0x18000000; \
2774 } while (0)
2775
2776 /*
2777 * UART0_TxD, UART_RxD0
2778 */
2779 #define __gpio_as_uart0() \
2780 do { \
2781 REG_GPIO_PXFUNS(3) = 0x06000000; \
2782 REG_GPIO_PXSELS(3) = 0x06000000; \
2783 REG_GPIO_PXPES(3) = 0x06000000; \
2784 } while (0)
2785
2786 #define __gpio_jtag_to_uart0() \
2787 do { \
2788 REG_GPIO_PXSELS(2) = 0x80000000; \
2789 } while (0)
2790
2791 /*
2792 * UART0_CTS, UART0_RTS
2793 */
2794 #define __gpio_as_ctsrts() \
2795 do { \
2796 REG_GPIO_PXFUNS(3) = 0xc0000000; \
2797 REG_GPIO_PXSELS(3) = 0xc0000000; \
2798 REG_GPIO_PXTRGC(3) = 0xc0000000; \
2799 REG_GPIO_PXPES(3) = 0xc0000000; \
2800 } while (0)
2801
2802 /*
2803 * UART1_TxD, UART1_RxD1
2804 */
2805 #define __gpio_as_uart1() \
2806 do { \
2807 REG_GPIO_PXFUNS(3) = 0xc0000000; \
2808 REG_GPIO_PXSELC(3) = 0xc0000000; \
2809 REG_GPIO_PXTRGS(3) = 0xc0000000; \
2810 REG_GPIO_PXPES(3) = 0xc0000000; \
2811 } while (0)
2812
2813 /*
2814 * LCD_D0~LCD_D7, LCD_PCLK, LCD_HSYNC, LCD_VSYNC, LCD_DE
2815 */
2816 #define __gpio_as_lcd_8bit() \
2817 do { \
2818 REG_GPIO_PXFUNS(2) = 0x003c00ff; \
2819 REG_GPIO_PXSELC(2) = 0x003c00ff; \
2820 REG_GPIO_PXPES(2) = 0x003c00ff; \
2821 } while (0)
2822
2823 /*
2824 * LCD_D0~LCD_D15, LCD_PCLK, LCD_HSYNC, LCD_VSYNC, LCD_DE
2825 */
2826 #define __gpio_as_lcd_16bit() \
2827 do { \
2828 REG_GPIO_PXFUNS(2) = 0x003cffff; \
2829 REG_GPIO_PXSELC(2) = 0x003cffff; \
2830 REG_GPIO_PXPES(2) = 0x003cffff; \
2831 } while (0)
2832
2833 /*
2834 * LCD_D0~LCD_D17, LCD_PCLK, LCD_HSYNC, LCD_VSYNC, LCD_DE
2835 */
2836 #define __gpio_as_lcd_18bit() \
2837 do { \
2838 REG_GPIO_PXFUNS(2) = 0x003fffff; \
2839 REG_GPIO_PXSELC(2) = 0x003fffff; \
2840 REG_GPIO_PXPES(2) = 0x003fffff; \
2841 } while (0)
2842
2843
2844 /* LCD_D0~LCD_D7, SLCD_RS, SLCD_CS */
2845 #define __gpio_as_slcd_8bit() \
2846 do { \
2847 REG_GPIO_PXFUNS(2) = 0x001800ff; \
2848 REG_GPIO_PXSELC(2) = 0x001800ff; \
2849 } while (0)
2850
2851 /* LCD_D0~LCD_D7, SLCD_RS, SLCD_CS */
2852 #define __gpio_as_slcd_9bit() \
2853 do { \
2854 REG_GPIO_PXFUNS(2) = 0x001801ff; \
2855 REG_GPIO_PXSELC(2) = 0x001801ff; \
2856 } while (0)
2857
2858 /* LCD_D0~LCD_D15, SLCD_RS, SLCD_CS */
2859 #define __gpio_as_slcd_16bit() \
2860 do { \
2861 REG_GPIO_PXFUNS(2) = 0x0018ffff; \
2862 REG_GPIO_PXSELC(2) = 0x0018ffff; \
2863 } while (0)
2864
2865 /* LCD_D0~LCD_D17, SLCD_RS, SLCD_CS */
2866 #define __gpio_as_slcd_18bit() \
2867 do { \
2868 REG_GPIO_PXFUNS(2) = 0x001bffff; \
2869 REG_GPIO_PXSELC(2) = 0x001bffff; \
2870 } while (0)
2871 /*
2872 * CIM_D0~CIM_D7, CIM_MCLK, CIM_PCLK, CIM_VSYNC, CIM_HSYNC
2873 */
2874 #define __gpio_as_cim() \
2875 do { \
2876 REG_GPIO_PXFUNS(3) = 0x0003c0ff; \
2877 REG_GPIO_PXSELC(3) = 0x0003c0ff; \
2878 REG_GPIO_PXPES(3) = 0x0003c0ff; \
2879 } while (0)
2880
2881 /*
2882 * SDATA_OUT, SDATA_IN, BIT_CLK, SYNC, SCLK_RESET
2883 */
2884 #define __gpio_as_aic() \
2885 do { \
2886 REG_GPIO_PXFUNS(3) = 0x007c0000; \
2887 REG_GPIO_PXSELS(3) = 0x007c0000; \
2888 REG_GPIO_PXPES(3) = 0x007c0000; \
2889 } while (0)
2890
2891 /*
2892 * MSC_CMD, MSC_CLK, MSC_D0 ~ MSC_D3
2893 */
2894 #define __gpio_as_msc() \
2895 do { \
2896 REG_GPIO_PXFUNS(3) = 0x00003f00; \
2897 REG_GPIO_PXSELC(3) = 0x00003f00; \
2898 REG_GPIO_PXPES(3) = 0x00003f00; \
2899 } while (0)
2900
2901 /*
2902 * SSI_CS0, SSI_CLK, SSI_DT, SSI_DR
2903 */
2904 #define __gpio_as_ssi() \
2905 do { \
2906 REG_GPIO_PXFUNS(3) = 0x003c0000; \
2907 REG_GPIO_PXSELC(3) = 0x003c0000; \
2908 REG_GPIO_PXPES(3) = 0x003c0000; \
2909 } while (0)
2910
2911 /*
2912 * I2C_SCK, I2C_SDA
2913 */
2914 #define __gpio_as_i2c() \
2915 do { \
2916 REG_GPIO_PXFUNS(3) = 0x01800000; \
2917 REG_GPIO_PXSELS(3) = 0x01800000; \
2918 REG_GPIO_PXPES(3) = 0x01800000; \
2919 } while (0)
2920
2921 /*
2922 * PWM0
2923 */
2924 #define __gpio_as_pwm0() \
2925 do { \
2926 REG_GPIO_PXFUNS(3) = 0x00800000; \
2927 REG_GPIO_PXSELC(3) = 0x00800000; \
2928 REG_GPIO_PXPES(3) = 0x00800000; \
2929 } while (0)
2930
2931 /*
2932 * PWM1
2933 */
2934 #define __gpio_as_pwm1() \
2935 do { \
2936 REG_GPIO_PXFUNS(3) = 0x01000000; \
2937 REG_GPIO_PXSELC(3) = 0x01000000; \
2938 REG_GPIO_PXPES(3) = 0x01000000; \
2939 } while (0)
2940
2941 /*
2942 * PWM2
2943 */
2944 #define __gpio_as_pwm2() \
2945 do { \
2946 REG_GPIO_PXFUNS(3) = 0x02000000; \
2947 REG_GPIO_PXSELC(3) = 0x02000000; \
2948 REG_GPIO_PXPES(3) = 0x02000000; \
2949 } while (0)
2950
2951 /*
2952 * PWM3
2953 */
2954 #define __gpio_as_pwm3() \
2955 do { \
2956 REG_GPIO_PXFUNS(3) = 0x04000000; \
2957 REG_GPIO_PXSELC(3) = 0x04000000; \
2958 REG_GPIO_PXPES(3) = 0x04000000; \
2959 } while (0)
2960
2961 /*
2962 * PWM4
2963 */
2964 #define __gpio_as_pwm4() \
2965 do { \
2966 REG_GPIO_PXFUNS(3) = 0x08000000; \
2967 REG_GPIO_PXSELC(3) = 0x08000000; \
2968 REG_GPIO_PXPES(3) = 0x08000000; \
2969 } while (0)
2970
2971 /*
2972 * PWM5
2973 */
2974 #define __gpio_as_pwm5() \
2975 do { \
2976 REG_GPIO_PXFUNS(3) = 0x10000000; \
2977 REG_GPIO_PXSELC(3) = 0x10000000; \
2978 REG_GPIO_PXPES(3) = 0x10000000; \
2979 } while (0)
2980
2981 /*
2982 * PWM6
2983 */
2984 #define __gpio_as_pwm6() \
2985 do { \
2986 REG_GPIO_PXFUNS(3) = 0x40000000; \
2987 REG_GPIO_PXSELC(3) = 0x40000000; \
2988 REG_GPIO_PXPES(3) = 0x40000000; \
2989 } while (0)
2990
2991 /*
2992 * PWM7
2993 */
2994 #define __gpio_as_pwm7() \
2995 do { \
2996 REG_GPIO_PXFUNS(3) = 0x80000000; \
2997 REG_GPIO_PXSELC(3) = 0x80000000; \
2998 REG_GPIO_PXPES(3) = 0x80000000; \
2999 } while (0)
3000
3001 /*
3002 * n = 0 ~ 7
3003 */
3004 #define __gpio_as_pwm(n) __gpio_as_pwm##n()
3005
3006 /* GPIO or Interrupt Mode */
3007
3008 #define __gpio_get_port(p) (REG_GPIO_PXPIN(p))
3009
3010 #define __gpio_port_as_output(p, o) \
3011 do { \
3012 REG_GPIO_PXFUNC(p) = (1 << (o)); \
3013 REG_GPIO_PXSELC(p) = (1 << (o)); \
3014 REG_GPIO_PXDIRS(p) = (1 << (o)); \
3015 } while (0)
3016
3017 #define __gpio_port_as_input(p, o) \
3018 do { \
3019 REG_GPIO_PXFUNC(p) = (1 << (o)); \
3020 REG_GPIO_PXSELC(p) = (1 << (o)); \
3021 REG_GPIO_PXDIRC(p) = (1 << (o)); \
3022 } while (0)
3023
3024 #define __gpio_as_output(n) \
3025 do { \
3026 unsigned int p, o; \
3027 p = (n) / 32; \
3028 o = (n) % 32; \
3029 __gpio_port_as_output(p, o); \
3030 } while (0)
3031
3032 #define __gpio_as_input(n) \
3033 do { \
3034 unsigned int p, o; \
3035 p = (n) / 32; \
3036 o = (n) % 32; \
3037 __gpio_port_as_input(p, o); \
3038 } while (0)
3039
3040 #define __gpio_set_pin(n) \
3041 do { \
3042 unsigned int p, o; \
3043 p = (n) / 32; \
3044 o = (n) % 32; \
3045 REG_GPIO_PXDATS(p) = (1 << o); \
3046 } while (0)
3047
3048 #define __gpio_clear_pin(n) \
3049 do { \
3050 unsigned int p, o; \
3051 p = (n) / 32; \
3052 o = (n) % 32; \
3053 REG_GPIO_PXDATC(p) = (1 << o); \
3054 } while (0)
3055
3056 #define __gpio_get_pin(n) \
3057 ({ \
3058 unsigned int p, o, v; \
3059 p = (n) / 32; \
3060 o = (n) % 32; \
3061 if (__gpio_get_port(p) & (1 << o)) \
3062 v = 1; \
3063 else \
3064 v = 0; \
3065 v; \
3066 })
3067
3068 #define __gpio_as_irq_high_level(n) \
3069 do { \
3070 unsigned int p, o; \
3071 p = (n) / 32; \
3072 o = (n) % 32; \
3073 REG_GPIO_PXIMS(p) = (1 << o); \
3074 REG_GPIO_PXTRGC(p) = (1 << o); \
3075 REG_GPIO_PXFUNC(p) = (1 << o); \
3076 REG_GPIO_PXSELS(p) = (1 << o); \
3077 REG_GPIO_PXDIRS(p) = (1 << o); \
3078 REG_GPIO_PXFLGC(p) = (1 << o); \
3079 REG_GPIO_PXIMC(p) = (1 << o); \
3080 } while (0)
3081
3082 #define __gpio_as_irq_low_level(n) \
3083 do { \
3084 unsigned int p, o; \
3085 p = (n) / 32; \
3086 o = (n) % 32; \
3087 REG_GPIO_PXIMS(p) = (1 << o); \
3088 REG_GPIO_PXTRGC(p) = (1 << o); \
3089 REG_GPIO_PXFUNC(p) = (1 << o); \
3090 REG_GPIO_PXSELS(p) = (1 << o); \
3091 REG_GPIO_PXDIRC(p) = (1 << o); \
3092 REG_GPIO_PXFLGC(p) = (1 << o); \
3093 REG_GPIO_PXIMC(p) = (1 << o); \
3094 } while (0)
3095
3096 #define __gpio_as_irq_rise_edge(n) \
3097 do { \
3098 unsigned int p, o; \
3099 p = (n) / 32; \
3100 o = (n) % 32; \
3101 REG_GPIO_PXIMS(p) = (1 << o); \
3102 REG_GPIO_PXTRGS(p) = (1 << o); \
3103 REG_GPIO_PXFUNC(p) = (1 << o); \
3104 REG_GPIO_PXSELS(p) = (1 << o); \
3105 REG_GPIO_PXDIRS(p) = (1 << o); \
3106 REG_GPIO_PXFLGC(p) = (1 << o); \
3107 REG_GPIO_PXIMC(p) = (1 << o); \
3108 } while (0)
3109
3110 #define __gpio_as_irq_fall_edge(n) \
3111 do { \
3112 unsigned int p, o; \
3113 p = (n) / 32; \
3114 o = (n) % 32; \
3115 REG_GPIO_PXIMS(p) = (1 << o); \
3116 REG_GPIO_PXTRGS(p) = (1 << o); \
3117 REG_GPIO_PXFUNC(p) = (1 << o); \
3118 REG_GPIO_PXSELS(p) = (1 << o); \
3119 REG_GPIO_PXDIRC(p) = (1 << o); \
3120 REG_GPIO_PXFLGC(p) = (1 << o); \
3121 REG_GPIO_PXIMC(p) = (1 << o); \
3122 } while (0)
3123
3124 #define __gpio_mask_irq(n) \
3125 do { \
3126 unsigned int p, o; \
3127 p = (n) / 32; \
3128 o = (n) % 32; \
3129 REG_GPIO_PXIMS(p) = (1 << o); \
3130 } while (0)
3131
3132 #define __gpio_unmask_irq(n) \
3133 do { \
3134 unsigned int p, o; \
3135 p = (n) / 32; \
3136 o = (n) % 32; \
3137 REG_GPIO_PXIMC(p) = (1 << o); \
3138 } while (0)
3139
3140 #define __gpio_ack_irq(n) \
3141 do { \
3142 unsigned int p, o; \
3143 p = (n) / 32; \
3144 o = (n) % 32; \
3145 REG_GPIO_PXFLGC(p) = (1 << o); \
3146 } while (0)
3147
3148 #define __gpio_get_irq() \
3149 ({ \
3150 unsigned int p, i, tmp, v = 0; \
3151 for (p = 3; p >= 0; p--) { \
3152 tmp = REG_GPIO_PXFLG(p); \
3153 for (i = 0; i < 32; i++) \
3154 if (tmp & (1 << i)) \
3155 v = (32*p + i); \
3156 } \
3157 v; \
3158 })
3159
3160 #define __gpio_group_irq(n) \
3161 ({ \
3162 register int tmp, i; \
3163 tmp = REG_GPIO_PXFLG((n)); \
3164 for (i=31;i>=0;i--) \
3165 if (tmp & (1 << i)) \
3166 break; \
3167 i; \
3168 })
3169
3170 #define __gpio_enable_pull(n) \
3171 do { \
3172 unsigned int p, o; \
3173 p = (n) / 32; \
3174 o = (n) % 32; \
3175 REG_GPIO_PXPEC(p) = (1 << o); \
3176 } while (0)
3177
3178 #define __gpio_disable_pull(n) \
3179 do { \
3180 unsigned int p, o; \
3181 p = (n) / 32; \
3182 o = (n) % 32; \
3183 REG_GPIO_PXPES(p) = (1 << o); \
3184 } while (0)
3185
3186
3187 /***************************************************************************
3188 * CPM
3189 ***************************************************************************/
3190 #define __cpm_get_pllm() \
3191 ((REG_CPM_CPPCR & CPM_CPPCR_PLLM_MASK) >> CPM_CPPCR_PLLM_BIT)
3192 #define __cpm_get_plln() \
3193 ((REG_CPM_CPPCR & CPM_CPPCR_PLLN_MASK) >> CPM_CPPCR_PLLN_BIT)
3194 #define __cpm_get_pllod() \
3195 ((REG_CPM_CPPCR & CPM_CPPCR_PLLOD_MASK) >> CPM_CPPCR_PLLOD_BIT)
3196
3197 #define __cpm_get_cdiv() \
3198 ((REG_CPM_CPCCR & CPM_CPCCR_CDIV_MASK) >> CPM_CPCCR_CDIV_BIT)
3199 #define __cpm_get_hdiv() \
3200 ((REG_CPM_CPCCR & CPM_CPCCR_HDIV_MASK) >> CPM_CPCCR_HDIV_BIT)
3201 #define __cpm_get_pdiv() \
3202 ((REG_CPM_CPCCR & CPM_CPCCR_PDIV_MASK) >> CPM_CPCCR_PDIV_BIT)
3203 #define __cpm_get_mdiv() \
3204 ((REG_CPM_CPCCR & CPM_CPCCR_MDIV_MASK) >> CPM_CPCCR_MDIV_BIT)
3205 #define __cpm_get_ldiv() \
3206 ((REG_CPM_CPCCR & CPM_CPCCR_LDIV_MASK) >> CPM_CPCCR_LDIV_BIT)
3207 #define __cpm_get_udiv() \
3208 ((REG_CPM_CPCCR & CPM_CPCCR_UDIV_MASK) >> CPM_CPCCR_UDIV_BIT)
3209 #define __cpm_get_i2sdiv() \
3210 ((REG_CPM_I2SCDR & CPM_I2SCDR_I2SDIV_MASK) >> CPM_I2SCDR_I2SDIV_BIT)
3211 #define __cpm_get_pixdiv() \
3212 ((REG_CPM_LPCDR & CPM_LPCDR_PIXDIV_MASK) >> CPM_LPCDR_PIXDIV_BIT)
3213 #define __cpm_get_mscdiv() \
3214 ((REG_CPM_MSCCDR & CPM_MSCCDR_MSCDIV_MASK) >> CPM_MSCCDR_MSCDIV_BIT)
3215
3216 #define __cpm_set_cdiv(v) \
3217 (REG_CPM_CPCCR = (REG_CPM_CPCCR & ~CPM_CPCCR_CDIV_MASK) | ((v) << (CPM_CPCCR_CDIV_BIT)))
3218 #define __cpm_set_hdiv(v) \
3219 (REG_CPM_CPCCR = (REG_CPM_CPCCR & ~CPM_CPCCR_HDIV_MASK) | ((v) << (CPM_CPCCR_HDIV_BIT)))
3220 #define __cpm_set_pdiv(v) \
3221 (REG_CPM_CPCCR = (REG_CPM_CPCCR & ~CPM_CPCCR_PDIV_MASK) | ((v) << (CPM_CPCCR_PDIV_BIT)))
3222 #define __cpm_set_mdiv(v) \
3223 (REG_CPM_CPCCR = (REG_CPM_CPCCR & ~CPM_CPCCR_MDIV_MASK) | ((v) << (CPM_CPCCR_MDIV_BIT)))
3224 #define __cpm_set_ldiv(v) \
3225 (REG_CPM_CPCCR = (REG_CPM_CPCCR & ~CPM_CPCCR_LDIV_MASK) | ((v) << (CPM_CPCCR_LDIV_BIT)))
3226 #define __cpm_set_udiv(v) \
3227 (REG_CPM_CPCCR = (REG_CPM_CPCCR & ~CPM_CPCCR_UDIV_MASK) | ((v) << (CPM_CPCCR_UDIV_BIT)))
3228 #define __cpm_set_i2sdiv(v) \
3229 (REG_CPM_I2SCDR = (REG_CPM_I2SCDR & ~CPM_I2SCDR_I2SDIV_MASK) | ((v) << (CPM_I2SCDR_I2SDIV_BIT)))
3230 #define __cpm_set_pixdiv(v) \
3231 (REG_CPM_LPCDR = (REG_CPM_LPCDR & ~CPM_LPCDR_PIXDIV_MASK) | ((v) << (CPM_LPCDR_PIXDIV_BIT)))
3232 #define __cpm_set_mscdiv(v) \
3233 (REG_CPM_MSCCDR = (REG_CPM_MSCCDR & ~CPM_MSCCDR_MSCDIV_MASK) | ((v) << (CPM_MSCCDR_MSCDIV_BIT)))
3234
3235 #define __cpm_select_i2sclk_exclk() (REG_CPM_CPCCR &= ~CPM_CPCCR_I2CS)
3236 #define __cpm_select_i2sclk_pll() (REG_CPM_CPCCR |= CPM_CPCCR_I2CS)
3237 #define __cpm_enable_cko() (REG_CPM_CPCCR |= CPM_CPCCR_CLKOEN)
3238 #define __cpm_select_usbclk_exclk() (REG_CPM_CPCCR &= ~CPM_CPCCR_UCS)
3239 #define __cpm_select_usbclk_pll() (REG_CPM_CPCCR |= CPM_CPCCR_UCS)
3240 #define __cpm_enable_pll_change() (REG_CPM_CPCCR |= CPM_CPCCR_CE)
3241 #define __cpm_pllout_direct() (REG_CPM_CPCCR |= CPM_CPCCR_PCS)
3242 #define __cpm_pllout_div2() (REG_CPM_CPCCR &= ~CPM_CPCCR_PCS)
3243
3244 #define __cpm_pll_is_on() (REG_CPM_CPPCR & CPM_CPPCR_PLLS)
3245 #define __cpm_pll_bypass() (REG_CPM_CPPCR |= CPM_CPPCR_PLLBP)
3246 #define __cpm_pll_enable() (REG_CPM_CPPCR |= CPM_CPPCR_PLLEN)
3247
3248 #define __cpm_get_cclk_doze_duty() \
3249 ((REG_CPM_LCR & CPM_LCR_DOZE_DUTY_MASK) >> CPM_LCR_DOZE_DUTY_BIT)
3250 #define __cpm_set_cclk_doze_duty(v) \
3251 (REG_CPM_LCR = (REG_CPM_LCR & ~CPM_LCR_DOZE_DUTY_MASK) | ((v) << (CPM_LCR_DOZE_DUTY_BIT)))
3252
3253 #define __cpm_doze_mode() (REG_CPM_LCR |= CPM_LCR_DOZE_ON)
3254 #define __cpm_idle_mode() \
3255 (REG_CPM_LCR = (REG_CPM_LCR & ~CPM_LCR_LPM_MASK) | CPM_LCR_LPM_IDLE)
3256 #define __cpm_sleep_mode() \
3257 (REG_CPM_LCR = (REG_CPM_LCR & ~CPM_LCR_LPM_MASK) | CPM_LCR_LPM_SLEEP)
3258
3259 #define __cpm_stop_all() (REG_CPM_CLKGR = 0x7fff)
3260 #define __cpm_stop_uart1() (REG_CPM_CLKGR |= CPM_CLKGR_UART1)
3261 #define __cpm_stop_uhc() (REG_CPM_CLKGR |= CPM_CLKGR_UHC)
3262 #define __cpm_stop_ipu() (REG_CPM_CLKGR |= CPM_CLKGR_IPU)
3263 #define __cpm_stop_dmac() (REG_CPM_CLKGR |= CPM_CLKGR_DMAC)
3264 #define __cpm_stop_udc() (REG_CPM_CLKGR |= CPM_CLKGR_UDC)
3265 #define __cpm_stop_lcd() (REG_CPM_CLKGR |= CPM_CLKGR_LCD)
3266 #define __cpm_stop_cim() (REG_CPM_CLKGR |= CPM_CLKGR_CIM)
3267 #define __cpm_stop_sadc() (REG_CPM_CLKGR |= CPM_CLKGR_SADC)
3268 #define __cpm_stop_msc() (REG_CPM_CLKGR |= CPM_CLKGR_MSC)
3269 #define __cpm_stop_aic1() (REG_CPM_CLKGR |= CPM_CLKGR_AIC1)
3270 #define __cpm_stop_aic2() (REG_CPM_CLKGR |= CPM_CLKGR_AIC2)
3271 #define __cpm_stop_ssi() (REG_CPM_CLKGR |= CPM_CLKGR_SSI)
3272 #define __cpm_stop_i2c() (REG_CPM_CLKGR |= CPM_CLKGR_I2C)
3273 #define __cpm_stop_rtc() (REG_CPM_CLKGR |= CPM_CLKGR_RTC)
3274 #define __cpm_stop_tcu() (REG_CPM_CLKGR |= CPM_CLKGR_TCU)
3275 #define __cpm_stop_uart0() (REG_CPM_CLKGR |= CPM_CLKGR_UART0)
3276
3277 #define __cpm_start_all() (REG_CPM_CLKGR = 0x0)
3278 #define __cpm_start_uart1() (REG_CPM_CLKGR &= ~CPM_CLKGR_UART1)
3279 #define __cpm_start_uhc() (REG_CPM_CLKGR &= ~CPM_CLKGR_UHC)
3280 #define __cpm_start_ipu() (REG_CPM_CLKGR &= ~CPM_CLKGR_IPU)
3281 #define __cpm_start_dmac() (REG_CPM_CLKGR &= ~CPM_CLKGR_DMAC)
3282 #define __cpm_start_udc() (REG_CPM_CLKGR &= ~CPM_CLKGR_UDC)
3283 #define __cpm_start_lcd() (REG_CPM_CLKGR &= ~CPM_CLKGR_LCD)
3284 #define __cpm_start_cim() (REG_CPM_CLKGR &= ~CPM_CLKGR_CIM)
3285 #define __cpm_start_sadc() (REG_CPM_CLKGR &= ~CPM_CLKGR_SADC)
3286 #define __cpm_start_msc() (REG_CPM_CLKGR &= ~CPM_CLKGR_MSC)
3287 #define __cpm_start_aic1() (REG_CPM_CLKGR &= ~CPM_CLKGR_AIC1)
3288 #define __cpm_start_aic2() (REG_CPM_CLKGR &= ~CPM_CLKGR_AIC2)
3289 #define __cpm_start_ssi() (REG_CPM_CLKGR &= ~CPM_CLKGR_SSI)
3290 #define __cpm_start_i2c() (REG_CPM_CLKGR &= ~CPM_CLKGR_I2C)
3291 #define __cpm_start_rtc() (REG_CPM_CLKGR &= ~CPM_CLKGR_RTC)
3292 #define __cpm_start_tcu() (REG_CPM_CLKGR &= ~CPM_CLKGR_TCU)
3293 #define __cpm_start_uart0() (REG_CPM_CLKGR &= ~CPM_CLKGR_UART0)
3294
3295 #define __cpm_get_o1st() \
3296 ((REG_CPM_SCR & CPM_SCR_O1ST_MASK) >> CPM_SCR_O1ST_BIT)
3297 #define __cpm_set_o1st(v) \
3298 (REG_CPM_SCR = (REG_CPM_SCR & ~CPM_SCR_O1ST_MASK) | ((v) << (CPM_SCR_O1ST_BIT)))
3299 #define __cpm_suspend_udcphy() (REG_CPM_SCR &= ~CPM_SCR_UDCPHY_ENABLE)
3300 #define __cpm_suspend_usbphy() (REG_CPM_SCR |= CPM_SCR_USBPHY_DISABLE)
3301 #define __cpm_enable_osc_in_sleep() (REG_CPM_SCR |= CPM_SCR_OSC_ENABLE)
3302
3303
3304 #ifdef CONFIG_SYS_EXTAL
3305 #define JZ_EXTAL CONFIG_SYS_EXTAL
3306 #else
3307 #define JZ_EXTAL 3686400
3308 #endif
3309 #define JZ_EXTAL2 32768 /* RTC clock */
3310
3311 /* PLL output frequency */
3312 static __inline__ unsigned int __cpm_get_pllout(void)
3313 {
3314 unsigned long m, n, no, pllout;
3315 unsigned long cppcr = REG_CPM_CPPCR;
3316 unsigned long od[4] = {1, 2, 2, 4};
3317 if ((cppcr & CPM_CPPCR_PLLEN) && !(cppcr & CPM_CPPCR_PLLBP)) {
3318 m = __cpm_get_pllm() + 2;
3319 n = __cpm_get_plln() + 2;
3320 no = od[__cpm_get_pllod()];
3321 pllout = ((JZ_EXTAL) / (n * no)) * m;
3322 } else
3323 pllout = JZ_EXTAL;
3324 return pllout;
3325 }
3326
3327 /* PLL output frequency for MSC/I2S/LCD/USB */
3328 static __inline__ unsigned int __cpm_get_pllout2(void)
3329 {
3330 if (REG_CPM_CPCCR & CPM_CPCCR_PCS)
3331 return __cpm_get_pllout();
3332 else
3333 return __cpm_get_pllout()/2;
3334 }
3335
3336 /* CPU core clock */
3337 static __inline__ unsigned int __cpm_get_cclk(void)
3338 {
3339 int div[] = {1, 2, 3, 4, 6, 8, 12, 16, 24, 32};
3340
3341 return __cpm_get_pllout() / div[__cpm_get_cdiv()];
3342 }
3343
3344 /* AHB system bus clock */
3345 static __inline__ unsigned int __cpm_get_hclk(void)
3346 {
3347 int div[] = {1, 2, 3, 4, 6, 8, 12, 16, 24, 32};
3348
3349 return __cpm_get_pllout() / div[__cpm_get_hdiv()];
3350 }
3351
3352 /* Memory bus clock */
3353 static __inline__ unsigned int __cpm_get_mclk(void)
3354 {
3355 int div[] = {1, 2, 3, 4, 6, 8, 12, 16, 24, 32};
3356
3357 return __cpm_get_pllout() / div[__cpm_get_mdiv()];
3358 }
3359
3360 /* APB peripheral bus clock */
3361 static __inline__ unsigned int __cpm_get_pclk(void)
3362 {
3363 int div[] = {1, 2, 3, 4, 6, 8, 12, 16, 24, 32};
3364
3365 return __cpm_get_pllout() / div[__cpm_get_pdiv()];
3366 }
3367
3368 /* LCDC module clock */
3369 static __inline__ unsigned int __cpm_get_lcdclk(void)
3370 {
3371 return __cpm_get_pllout2() / (__cpm_get_ldiv() + 1);
3372 }
3373
3374 /* LCD pixel clock */
3375 static __inline__ unsigned int __cpm_get_pixclk(void)
3376 {
3377 return __cpm_get_pllout2() / (__cpm_get_pixdiv() + 1);
3378 }
3379
3380 /* I2S clock */
3381 static __inline__ unsigned int __cpm_get_i2sclk(void)
3382 {
3383 if (REG_CPM_CPCCR & CPM_CPCCR_I2CS) {
3384 return __cpm_get_pllout2() / (__cpm_get_i2sdiv() + 1);
3385 }
3386 else {
3387 return JZ_EXTAL;
3388 }
3389 }
3390
3391 /* USB clock */
3392 static __inline__ unsigned int __cpm_get_usbclk(void)
3393 {
3394 if (REG_CPM_CPCCR & CPM_CPCCR_UCS) {
3395 return __cpm_get_pllout2() / (__cpm_get_udiv() + 1);
3396 }
3397 else {
3398 return JZ_EXTAL;
3399 }
3400 }
3401
3402 /* MSC clock */
3403 static __inline__ unsigned int __cpm_get_mscclk(void)
3404 {
3405 return __cpm_get_pllout2() / (__cpm_get_mscdiv() + 1);
3406 }
3407
3408 /* EXTAL clock for UART,I2C,SSI,TCU,USB-PHY */
3409 static __inline__ unsigned int __cpm_get_extalclk(void)
3410 {
3411 return JZ_EXTAL;
3412 }
3413
3414 /* RTC clock for CPM,INTC,RTC,TCU,WDT */
3415 static __inline__ unsigned int __cpm_get_rtcclk(void)
3416 {
3417 return JZ_EXTAL2;
3418 }
3419
3420 /*
3421 * Output 24MHz for SD and 16MHz for MMC.
3422 */
3423 static inline void __cpm_select_msc_clk(int sd)
3424 {
3425 unsigned int pllout2 = __cpm_get_pllout2();
3426 unsigned int div = 0;
3427
3428 if (sd) {
3429 div = pllout2 / 24000000;
3430 }
3431 else {
3432 div = pllout2 / 16000000;
3433 }
3434
3435 REG_CPM_MSCCDR = div - 1;
3436 }
3437
3438 /*
3439 * TCU
3440 */
3441 /* where 'n' is the TCU channel */
3442 #define __tcu_select_extalclk(n) \
3443 (REG_TCU_TCSR((n)) = (REG_TCU_TCSR((n)) & ~(TCU_TCSR_EXT_EN | TCU_TCSR_RTC_EN | TCU_TCSR_PCK_EN)) | TCU_TCSR_EXT_EN)
3444 #define __tcu_select_rtcclk(n) \
3445 (REG_TCU_TCSR((n)) = (REG_TCU_TCSR((n)) & ~(TCU_TCSR_EXT_EN | TCU_TCSR_RTC_EN | TCU_TCSR_PCK_EN)) | TCU_TCSR_RTC_EN)
3446 #define __tcu_select_pclk(n) \
3447 (REG_TCU_TCSR((n)) = (REG_TCU_TCSR((n)) & ~(TCU_TCSR_EXT_EN | TCU_TCSR_RTC_EN | TCU_TCSR_PCK_EN)) | TCU_TCSR_PCK_EN)
3448
3449 #define __tcu_select_clk_div1(n) \
3450 (REG_TCU_TCSR((n)) = (REG_TCU_TCSR((n)) & ~TCU_TCSR_PRESCALE_MASK) | TCU_TCSR_PRESCALE1)
3451 #define __tcu_select_clk_div4(n) \
3452 (REG_TCU_TCSR((n)) = (REG_TCU_TCSR((n)) & ~TCU_TCSR_PRESCALE_MASK) | TCU_TCSR_PRESCALE4)
3453 #define __tcu_select_clk_div16(n) \
3454 (REG_TCU_TCSR((n)) = (REG_TCU_TCSR((n)) & ~TCU_TCSR_PRESCALE_MASK) | TCU_TCSR_PRESCALE16)
3455 #define __tcu_select_clk_div64(n) \
3456 (REG_TCU_TCSR((n)) = (REG_TCU_TCSR((n)) & ~TCU_TCSR_PRESCALE_MASK) | TCU_TCSR_PRESCALE64)
3457 #define __tcu_select_clk_div256(n) \
3458 (REG_TCU_TCSR((n)) = (REG_TCU_TCSR((n)) & ~TCU_TCSR_PRESCALE_MASK) | TCU_TCSR_PRESCALE256)
3459 #define __tcu_select_clk_div1024(n) \
3460 (REG_TCU_TCSR((n)) = (REG_TCU_TCSR((n)) & ~TCU_TCSR_PRESCALE_MASK) | TCU_TCSR_PRESCALE1024)
3461
3462 #define __tcu_enable_pwm_output(n) ( REG_TCU_TCSR((n)) |= TCU_TCSR_PWM_EN )
3463 #define __tcu_disable_pwm_output(n) ( REG_TCU_TCSR((n)) &= ~TCU_TCSR_PWM_EN )
3464
3465 #define __tcu_init_pwm_output_high(n) ( REG_TCU_TCSR((n)) |= TCU_TCSR_PWM_INITL_HIGH )
3466 #define __tcu_init_pwm_output_low(n) ( REG_TCU_TCSR((n)) &= ~TCU_TCSR_PWM_INITL_HIGH )
3467
3468 #define __tcu_set_pwm_output_shutdown_graceful(n) ( REG_TCU_TCSR((n)) &= ~TCU_TCSR_PWM_SD )
3469 #define __tcu_set_pwm_output_shutdown_abrupt(n) ( REG_TCU_TCSR((n)) |= TCU_TCSR_PWM_SD )
3470
3471 #define __tcu_start_counter(n) ( REG_TCU_TESR |= (1 << (n)) )
3472 #define __tcu_stop_counter(n) ( REG_TCU_TECR |= (1 << (n)) )
3473
3474 #define __tcu_half_match_flag(n) ( REG_TCU_TFR & (1 << ((n) + 16)) )
3475 #define __tcu_full_match_flag(n) ( REG_TCU_TFR & (1 << (n)) )
3476 #define __tcu_set_half_match_flag(n) ( REG_TCU_TFSR = (1 << ((n) + 16)) )
3477 #define __tcu_set_full_match_flag(n) ( REG_TCU_TFSR = (1 << (n)) )
3478 #define __tcu_clear_half_match_flag(n) ( REG_TCU_TFCR = (1 << ((n) + 16)) )
3479 #define __tcu_clear_full_match_flag(n) ( REG_TCU_TFCR = (1 << (n)) )
3480 #define __tcu_mask_half_match_irq(n) ( REG_TCU_TMSR = (1 << ((n) + 16)) )
3481 #define __tcu_mask_full_match_irq(n) ( REG_TCU_TMSR = (1 << (n)) )
3482 #define __tcu_unmask_half_match_irq(n) ( REG_TCU_TMCR = (1 << ((n) + 16)) )
3483 #define __tcu_unmask_full_match_irq(n) ( REG_TCU_TMCR = (1 << (n)) )
3484
3485 #define __tcu_wdt_clock_stopped() ( REG_TCU_TSR & TCU_TSSR_WDTSC )
3486 #define __tcu_timer_clock_stopped(n) ( REG_TCU_TSR & (1 << (n)) )
3487
3488 #define __tcu_start_wdt_clock() ( REG_TCU_TSCR = TCU_TSSR_WDTSC )
3489 #define __tcu_start_timer_clock(n) ( REG_TCU_TSCR = (1 << (n)) )
3490
3491 #define __tcu_stop_wdt_clock() ( REG_TCU_TSSR = TCU_TSSR_WDTSC )
3492 #define __tcu_stop_timer_clock(n) ( REG_TCU_TSSR = (1 << (n)) )
3493
3494 #define __tcu_get_count(n) ( REG_TCU_TCNT((n)) )
3495 #define __tcu_set_count(n,v) ( REG_TCU_TCNT((n)) = (v) )
3496 #define __tcu_set_full_data(n,v) ( REG_TCU_TDFR((n)) = (v) )
3497 #define __tcu_set_half_data(n,v) ( REG_TCU_TDHR((n)) = (v) )
3498
3499
3500 /***************************************************************************
3501 * WDT
3502 ***************************************************************************/
3503 #define __wdt_start() ( REG_WDT_TCER |= WDT_TCER_TCEN )
3504 #define __wdt_stop() ( REG_WDT_TCER &= ~WDT_TCER_TCEN )
3505 #define __wdt_set_count(v) ( REG_WDT_TCNT = (v) )
3506 #define __wdt_set_data(v) ( REG_WDT_TDR = (v) )
3507
3508 #define __wdt_select_extalclk() \
3509 (REG_WDT_TCSR = (REG_WDT_TCSR & ~(WDT_TCSR_EXT_EN | WDT_TCSR_RTC_EN | WDT_TCSR_PCK_EN)) | WDT_TCSR_EXT_EN)
3510 #define __wdt_select_rtcclk() \
3511 (REG_WDT_TCSR = (REG_WDT_TCSR & ~(WDT_TCSR_EXT_EN | WDT_TCSR_RTC_EN | WDT_TCSR_PCK_EN)) | WDT_TCSR_RTC_EN)
3512 #define __wdt_select_pclk() \
3513 (REG_WDT_TCSR = (REG_WDT_TCSR & ~(WDT_TCSR_EXT_EN | WDT_TCSR_RTC_EN | WDT_TCSR_PCK_EN)) | WDT_TCSR_PCK_EN)
3514
3515 #define __wdt_select_clk_div1() \
3516 (REG_WDT_TCSR = (REG_WDT_TCSR & ~WDT_TCSR_PRESCALE_MASK) | WDT_TCSR_PRESCALE1)
3517 #define __wdt_select_clk_div4() \
3518 (REG_WDT_TCSR = (REG_WDT_TCSR & ~WDT_TCSR_PRESCALE_MASK) | WDT_TCSR_PRESCALE4)
3519 #define __wdt_select_clk_div16() \
3520 (REG_WDT_TCSR = (REG_WDT_TCSR & ~WDT_TCSR_PRESCALE_MASK) | WDT_TCSR_PRESCALE16)
3521 #define __wdt_select_clk_div64() \
3522 (REG_WDT_TCSR = (REG_WDT_TCSR & ~WDT_TCSR_PRESCALE_MASK) | WDT_TCSR_PRESCALE64)
3523 #define __wdt_select_clk_div256() \
3524 (REG_WDT_TCSR = (REG_WDT_TCSR & ~WDT_TCSR_PRESCALE_MASK) | WDT_TCSR_PRESCALE256)
3525 #define __wdt_select_clk_div1024() \
3526 (REG_WDT_TCSR = (REG_WDT_TCSR & ~WDT_TCSR_PRESCALE_MASK) | WDT_TCSR_PRESCALE1024)
3527
3528
3529 /***************************************************************************
3530 * UART
3531 ***************************************************************************/
3532
3533 #define __uart_enable() ( REG8(UART0_FCR) |= UARTFCR_UUE | UARTFCR_FE )
3534 #define __uart_disable() ( REG8(UART0_FCR) = ~UARTFCR_UUE )
3535
3536 #define __uart_enable_transmit_irq() ( REG8(UART0_IER) |= UARTIER_TIE )
3537 #define __uart_disable_transmit_irq() ( REG8(UART0_IER) &= ~UARTIER_TIE )
3538
3539 #define __uart_enable_receive_irq() \
3540 ( REG8(UART0_IER) |= UARTIER_RIE | UARTIER_RLIE | UARTIER_RTIE )
3541 #define __uart_disable_receive_irq() \
3542 ( REG8(UART0_IER) &= ~(UARTIER_RIE | UARTIER_RLIE | UARTIER_RTIE) )
3543
3544 #define __uart_enable_loopback() ( REG8(UART0_MCR) |= UARTMCR_LOOP )
3545 #define __uart_disable_loopback() ( REG8(UART0_MCR) &= ~UARTMCR_LOOP )
3546
3547 #define __uart_set_8n1() ( REG8(UART0_LCR) = UARTLCR_WLEN_8 )
3548
3549 #define __uart_set_baud(devclk, baud) \
3550 do { \
3551 REG8(UART0_LCR) |= UARTLCR_DLAB; \
3552 REG8(UART0_DLLR) = (devclk / 16 / baud) & 0xff; \
3553 REG8(UART0_DLHR) = ((devclk / 16 / baud) >> 8) & 0xff; \
3554 REG8(UART0_LCR) &= ~UARTLCR_DLAB; \
3555 } while (0)
3556
3557 #define __uart_parity_error() ( (REG8(UART0_LSR) & UARTLSR_PER) != 0 )
3558 #define __uart_clear_errors() \
3559 ( REG8(UART0_LSR) &= ~(UARTLSR_ORER | UARTLSR_BRK | UARTLSR_FER | UARTLSR_PER | UARTLSR_RFER) )
3560
3561 #define __uart_transmit_fifo_empty() ( (REG8(UART0_LSR) & UARTLSR_TDRQ) != 0 )
3562 #define __uart_transmit_end() ( (REG8(UART0_LSR) & UARTLSR_TEMT) != 0 )
3563 #define __uart_transmit_char(ch) ( REG8(UART0_TDR) = (ch) )
3564 #define __uart_receive_fifo_full() ( (REG8(UART0_LSR) & UARTLSR_DR) != 0 )
3565 #define __uart_receive_ready() ( (REG8(UART0_LSR) & UARTLSR_DR) != 0 )
3566 #define __uart_receive_char() REG8(UART0_RDR)
3567 #define __uart_disable_irda() ( REG8(UART0_SIRCR) &= ~(SIRCR_TSIRE | SIRCR_RSIRE) )
3568 #define __uart_enable_irda() \
3569 /* Tx high pulse as 0, Rx low pulse as 0 */ \
3570 ( REG8(UART0_SIRCR) = SIRCR_TSIRE | SIRCR_RSIRE | SIRCR_RXPL | SIRCR_TPWS )
3571
3572
3573 /***************************************************************************
3574 * DMAC
3575 ***************************************************************************/
3576
3577 /* n is the DMA channel (0 - 5) */
3578
3579 #define __dmac_enable_module() \
3580 ( REG_DMAC_DMACR |= DMAC_DMACR_DMAE | DMAC_DMACR_PR_RR )
3581 #define __dmac_disable_module() \
3582 ( REG_DMAC_DMACR &= ~DMAC_DMACR_DMAE )
3583
3584 /* p=0,1,2,3 */
3585 #define __dmac_set_priority(p) \
3586 do { \
3587 REG_DMAC_DMACR &= ~DMAC_DMACR_PR_MASK; \
3588 REG_DMAC_DMACR |= ((p) << DMAC_DMACR_PR_BIT); \
3589 } while (0)
3590
3591 #define __dmac_test_halt_error() ( REG_DMAC_DMACR & DMAC_DMACR_HLT )
3592 #define __dmac_test_addr_error() ( REG_DMAC_DMACR & DMAC_DMACR_AR )
3593
3594 #define __dmac_enable_descriptor(n) \
3595 ( REG_DMAC_DCCSR((n)) &= ~DMAC_DCCSR_NDES )
3596 #define __dmac_disable_descriptor(n) \
3597 ( REG_DMAC_DCCSR((n)) |= DMAC_DCCSR_NDES )
3598
3599 #define __dmac_enable_channel(n) \
3600 ( REG_DMAC_DCCSR((n)) |= DMAC_DCCSR_EN )
3601 #define __dmac_disable_channel(n) \
3602 ( REG_DMAC_DCCSR((n)) &= ~DMAC_DCCSR_EN )
3603 #define __dmac_channel_enabled(n) \
3604 ( REG_DMAC_DCCSR((n)) & DMAC_DCCSR_EN )
3605
3606 #define __dmac_channel_enable_irq(n) \
3607 ( REG_DMAC_DCMD((n)) |= DMAC_DCMD_TIE )
3608 #define __dmac_channel_disable_irq(n) \
3609 ( REG_DMAC_DCMD((n)) &= ~DMAC_DCMD_TIE )
3610
3611 #define __dmac_channel_transmit_halt_detected(n) \
3612 ( REG_DMAC_DCCSR((n)) & DMAC_DCCSR_HLT )
3613 #define __dmac_channel_transmit_end_detected(n) \
3614 ( REG_DMAC_DCCSR((n)) & DMAC_DCCSR_TT )
3615 #define __dmac_channel_address_error_detected(n) \
3616 ( REG_DMAC_DCCSR((n)) & DMAC_DCCSR_AR )
3617 #define __dmac_channel_count_terminated_detected(n) \
3618 ( REG_DMAC_DCCSR((n)) & DMAC_DCCSR_CT )
3619 #define __dmac_channel_descriptor_invalid_detected(n) \
3620 ( REG_DMAC_DCCSR((n)) & DMAC_DCCSR_INV )
3621
3622 #define __dmac_channel_clear_transmit_halt(n) \
3623 ( REG_DMAC_DCCSR(n) &= ~DMAC_DCCSR_HLT )
3624 #define __dmac_channel_clear_transmit_end(n) \
3625 ( REG_DMAC_DCCSR(n) &= ~DMAC_DCCSR_TT )
3626 #define __dmac_channel_clear_address_error(n) \
3627 ( REG_DMAC_DCCSR(n) &= ~DMAC_DCCSR_AR )
3628 #define __dmac_channel_clear_count_terminated(n) \
3629 ( REG_DMAC_DCCSR((n)) &= ~DMAC_DCCSR_CT )
3630 #define __dmac_channel_clear_descriptor_invalid(n) \
3631 ( REG_DMAC_DCCSR((n)) &= ~DMAC_DCCSR_INV )
3632
3633 #define __dmac_channel_set_single_mode(n) \
3634 ( REG_DMAC_DCMD((n)) &= ~DMAC_DCMD_TM )
3635 #define __dmac_channel_set_block_mode(n) \
3636 ( REG_DMAC_DCMD((n)) |= DMAC_DCMD_TM )
3637
3638 #define __dmac_channel_set_transfer_unit_32bit(n) \
3639 do { \
3640 REG_DMAC_DCMD((n)) &= ~DMAC_DCMD_DS_MASK; \
3641 REG_DMAC_DCMD((n)) |= DMAC_DCMD_DS_32BIT; \
3642 } while (0)
3643
3644 #define __dmac_channel_set_transfer_unit_16bit(n) \
3645 do { \
3646 REG_DMAC_DCMD((n)) &= ~DMAC_DCMD_DS_MASK; \
3647 REG_DMAC_DCMD((n)) |= DMAC_DCMD_DS_16BIT; \
3648 } while (0)
3649
3650 #define __dmac_channel_set_transfer_unit_8bit(n) \
3651 do { \
3652 REG_DMAC_DCMD((n)) &= ~DMAC_DCMD_DS_MASK; \
3653 REG_DMAC_DCMD((n)) |= DMAC_DCMD_DS_8BIT; \
3654 } while (0)
3655
3656 #define __dmac_channel_set_transfer_unit_16byte(n) \
3657 do { \
3658 REG_DMAC_DCMD((n)) &= ~DMAC_DCMD_DS_MASK; \
3659 REG_DMAC_DCMD((n)) |= DMAC_DCMD_DS_16BYTE; \
3660 } while (0)
3661
3662 #define __dmac_channel_set_transfer_unit_32byte(n) \
3663 do { \
3664 REG_DMAC_DCMD((n)) &= ~DMAC_DCMD_DS_MASK; \
3665 REG_DMAC_DCMD((n)) |= DMAC_DCMD_DS_32BYTE; \
3666 } while (0)
3667
3668 /* w=8,16,32 */
3669 #define __dmac_channel_set_dest_port_width(n,w) \
3670 do { \
3671 REG_DMAC_DCMD((n)) &= ~DMAC_DCMD_DWDH_MASK; \
3672 REG_DMAC_DCMD((n)) |= DMAC_DCMD_DWDH_##w; \
3673 } while (0)
3674
3675 /* w=8,16,32 */
3676 #define __dmac_channel_set_src_port_width(n,w) \
3677 do { \
3678 REG_DMAC_DCMD((n)) &= ~DMAC_DCMD_SWDH_MASK; \
3679 REG_DMAC_DCMD((n)) |= DMAC_DCMD_SWDH_##w; \
3680 } while (0)
3681
3682 /* v=0-15 */
3683 #define __dmac_channel_set_rdil(n,v) \
3684 do { \
3685 REG_DMAC_DCMD((n)) &= ~DMAC_DCMD_RDIL_MASK; \
3686 REG_DMAC_DCMD((n) |= ((v) << DMAC_DCMD_RDIL_BIT); \
3687 } while (0)
3688
3689 #define __dmac_channel_dest_addr_fixed(n) \
3690 ( REG_DMAC_DCMD((n)) &= ~DMAC_DCMD_DAI )
3691 #define __dmac_channel_dest_addr_increment(n) \
3692 ( REG_DMAC_DCMD((n)) |= DMAC_DCMD_DAI )
3693
3694 #define __dmac_channel_src_addr_fixed(n) \
3695 ( REG_DMAC_DCMD((n)) &= ~DMAC_DCMD_SAI )
3696 #define __dmac_channel_src_addr_increment(n) \
3697 ( REG_DMAC_DCMD((n)) |= DMAC_DCMD_SAI )
3698
3699 #define __dmac_channel_set_doorbell(n) \
3700 ( REG_DMAC_DMADBSR = (1 << (n)) )
3701
3702 #define __dmac_channel_irq_detected(n) ( REG_DMAC_DMAIPR & (1 << (n)) )
3703 #define __dmac_channel_ack_irq(n) ( REG_DMAC_DMAIPR &= ~(1 << (n)) )
3704
3705 static __inline__ int __dmac_get_irq(void)
3706 {
3707 int i;
3708 for (i = 0; i < MAX_DMA_NUM; i++)
3709 if (__dmac_channel_irq_detected(i))
3710 return i;
3711 return -1;
3712 }
3713
3714
3715 /***************************************************************************
3716 * AIC (AC'97 & I2S Controller)
3717 ***************************************************************************/
3718
3719 #define __aic_enable() ( REG_AIC_FR |= AIC_FR_ENB )
3720 #define __aic_disable() ( REG_AIC_FR &= ~AIC_FR_ENB )
3721
3722 #define __aic_select_ac97() ( REG_AIC_FR &= ~AIC_FR_AUSEL )
3723 #define __aic_select_i2s() ( REG_AIC_FR |= AIC_FR_AUSEL )
3724
3725 #define __i2s_as_master() ( REG_AIC_FR |= AIC_FR_BCKD | AIC_FR_SYNCD )
3726 #define __i2s_as_slave() ( REG_AIC_FR &= ~(AIC_FR_BCKD | AIC_FR_SYNCD) )
3727 #define __aic_reset_status() ( REG_AIC_FR & AIC_FR_RST )
3728
3729 #define __aic_reset() \
3730 do { \
3731 REG_AIC_FR |= AIC_FR_RST; \
3732 } while(0)
3733
3734
3735 #define __aic_set_transmit_trigger(n) \
3736 do { \
3737 REG_AIC_FR &= ~AIC_FR_TFTH_MASK; \
3738 REG_AIC_FR |= ((n) << AIC_FR_TFTH_BIT); \
3739 } while(0)
3740
3741 #define __aic_set_receive_trigger(n) \
3742 do { \
3743 REG_AIC_FR &= ~AIC_FR_RFTH_MASK; \
3744 REG_AIC_FR |= ((n) << AIC_FR_RFTH_BIT); \
3745 } while(0)
3746
3747 #define __aic_enable_record() ( REG_AIC_CR |= AIC_CR_EREC )
3748 #define __aic_disable_record() ( REG_AIC_CR &= ~AIC_CR_EREC )
3749 #define __aic_enable_replay() ( REG_AIC_CR |= AIC_CR_ERPL )
3750 #define __aic_disable_replay() ( REG_AIC_CR &= ~AIC_CR_ERPL )
3751 #define __aic_enable_loopback() ( REG_AIC_CR |= AIC_CR_ENLBF )
3752 #define __aic_disable_loopback() ( REG_AIC_CR &= ~AIC_CR_ENLBF )
3753
3754 #define __aic_flush_fifo() ( REG_AIC_CR |= AIC_CR_FLUSH )
3755 #define __aic_unflush_fifo() ( REG_AIC_CR &= ~AIC_CR_FLUSH )
3756
3757 #define __aic_enable_transmit_intr() \
3758 ( REG_AIC_CR |= (AIC_CR_ETFS | AIC_CR_ETUR) )
3759 #define __aic_disable_transmit_intr() \
3760 ( REG_AIC_CR &= ~(AIC_CR_ETFS | AIC_CR_ETUR) )
3761 #define __aic_enable_receive_intr() \
3762 ( REG_AIC_CR |= (AIC_CR_ERFS | AIC_CR_EROR) )
3763 #define __aic_disable_receive_intr() \
3764 ( REG_AIC_CR &= ~(AIC_CR_ERFS | AIC_CR_EROR) )
3765
3766 #define __aic_enable_transmit_dma() ( REG_AIC_CR |= AIC_CR_TDMS )
3767 #define __aic_disable_transmit_dma() ( REG_AIC_CR &= ~AIC_CR_TDMS )
3768 #define __aic_enable_receive_dma() ( REG_AIC_CR |= AIC_CR_RDMS )
3769 #define __aic_disable_receive_dma() ( REG_AIC_CR &= ~AIC_CR_RDMS )
3770
3771 #define __aic_enable_mono2stereo() ( REG_AIC_CR |= AIC_CR_M2S )
3772 #define __aic_disable_mono2stereo() ( REG_AIC_CR &= ~AIC_CR_M2S )
3773 #define __aic_enable_byteswap() ( REG_AIC_CR |= AIC_CR_ENDSW )
3774 #define __aic_disable_byteswap() ( REG_AIC_CR &= ~AIC_CR_ENDSW )
3775 #define __aic_enable_unsignadj() ( REG_AIC_CR |= AIC_CR_AVSTSU )
3776 #define __aic_disable_unsignadj() ( REG_AIC_CR &= ~AIC_CR_AVSTSU )
3777
3778 #define AC97_PCM_XS_L_FRONT AIC_ACCR1_XS_SLOT3
3779 #define AC97_PCM_XS_R_FRONT AIC_ACCR1_XS_SLOT4
3780 #define AC97_PCM_XS_CENTER AIC_ACCR1_XS_SLOT6
3781 #define AC97_PCM_XS_L_SURR AIC_ACCR1_XS_SLOT7
3782 #define AC97_PCM_XS_R_SURR AIC_ACCR1_XS_SLOT8
3783 #define AC97_PCM_XS_LFE AIC_ACCR1_XS_SLOT9
3784
3785 #define AC97_PCM_RS_L_FRONT AIC_ACCR1_RS_SLOT3
3786 #define AC97_PCM_RS_R_FRONT AIC_ACCR1_RS_SLOT4
3787 #define AC97_PCM_RS_CENTER AIC_ACCR1_RS_SLOT6
3788 #define AC97_PCM_RS_L_SURR AIC_ACCR1_RS_SLOT7
3789 #define AC97_PCM_RS_R_SURR AIC_ACCR1_RS_SLOT8
3790 #define AC97_PCM_RS_LFE AIC_ACCR1_RS_SLOT9
3791
3792 #define __ac97_set_xs_none() ( REG_AIC_ACCR1 &= ~AIC_ACCR1_XS_MASK )
3793 #define __ac97_set_xs_mono() \
3794 do { \
3795 REG_AIC_ACCR1 &= ~AIC_ACCR1_XS_MASK; \
3796 REG_AIC_ACCR1 |= AC97_PCM_XS_R_FRONT; \
3797 } while(0)
3798 #define __ac97_set_xs_stereo() \
3799 do { \
3800 REG_AIC_ACCR1 &= ~AIC_ACCR1_XS_MASK; \
3801 REG_AIC_ACCR1 |= AC97_PCM_XS_L_FRONT | AC97_PCM_XS_R_FRONT; \
3802 } while(0)
3803
3804 /* In fact, only stereo is support now. */
3805 #define __ac97_set_rs_none() ( REG_AIC_ACCR1 &= ~AIC_ACCR1_RS_MASK )
3806 #define __ac97_set_rs_mono() \
3807 do { \
3808 REG_AIC_ACCR1 &= ~AIC_ACCR1_RS_MASK; \
3809 REG_AIC_ACCR1 |= AC97_PCM_RS_R_FRONT; \
3810 } while(0)
3811 #define __ac97_set_rs_stereo() \
3812 do { \
3813 REG_AIC_ACCR1 &= ~AIC_ACCR1_RS_MASK; \
3814 REG_AIC_ACCR1 |= AC97_PCM_RS_L_FRONT | AC97_PCM_RS_R_FRONT; \
3815 } while(0)
3816
3817 #define __ac97_warm_reset_codec() \
3818 do { \
3819 REG_AIC_ACCR2 |= AIC_ACCR2_SA; \
3820 REG_AIC_ACCR2 |= AIC_ACCR2_SS; \
3821 udelay(2); \
3822 REG_AIC_ACCR2 &= ~AIC_ACCR2_SS; \
3823 REG_AIC_ACCR2 &= ~AIC_ACCR2_SA; \
3824 } while (0)
3825
3826 #define __ac97_cold_reset_codec() \
3827 do { \
3828 REG_AIC_ACCR2 |= AIC_ACCR2_SR; \
3829 udelay(2); \
3830 REG_AIC_ACCR2 &= ~AIC_ACCR2_SR; \
3831 } while (0)
3832
3833 /* n=8,16,18,20 */
3834 #define __ac97_set_iass(n) \
3835 ( REG_AIC_ACCR2 = (REG_AIC_ACCR2 & ~AIC_ACCR2_IASS_MASK) | AIC_ACCR2_IASS_##n##BIT )
3836 #define __ac97_set_oass(n) \
3837 ( REG_AIC_ACCR2 = (REG_AIC_ACCR2 & ~AIC_ACCR2_OASS_MASK) | AIC_ACCR2_OASS_##n##BIT )
3838
3839 #define __i2s_select_i2s() ( REG_AIC_I2SCR &= ~AIC_I2SCR_AMSL )
3840 #define __i2s_select_msbjustified() ( REG_AIC_I2SCR |= AIC_I2SCR_AMSL )
3841
3842 /* n=8,16,18,20,24 */
3843 /*#define __i2s_set_sample_size(n) \
3844 ( REG_AIC_I2SCR |= (REG_AIC_I2SCR & ~AIC_I2SCR_WL_MASK) | AIC_I2SCR_WL_##n##BIT )*/
3845
3846 #define __i2s_set_oss_sample_size(n) \
3847 ( REG_AIC_CR = (REG_AIC_CR & ~AIC_CR_OSS_MASK) | AIC_CR_OSS_##n##BIT )
3848 #define __i2s_set_iss_sample_size(n) \
3849 ( REG_AIC_CR = (REG_AIC_CR & ~AIC_CR_ISS_MASK) | AIC_CR_ISS_##n##BIT )
3850
3851 #define __i2s_stop_bitclk() ( REG_AIC_I2SCR |= AIC_I2SCR_STPBK )
3852 #define __i2s_start_bitclk() ( REG_AIC_I2SCR &= ~AIC_I2SCR_STPBK )
3853
3854 #define __aic_transmit_request() ( REG_AIC_SR & AIC_SR_TFS )
3855 #define __aic_receive_request() ( REG_AIC_SR & AIC_SR_RFS )
3856 #define __aic_transmit_underrun() ( REG_AIC_SR & AIC_SR_TUR )
3857 #define __aic_receive_overrun() ( REG_AIC_SR & AIC_SR_ROR )
3858
3859 #define __aic_clear_errors() ( REG_AIC_SR &= ~(AIC_SR_TUR | AIC_SR_ROR) )
3860
3861 #define __aic_get_transmit_resident() \
3862 ( (REG_AIC_SR & AIC_SR_TFL_MASK) >> AIC_SR_TFL_BIT )
3863 #define __aic_get_receive_count() \
3864 ( (REG_AIC_SR & AIC_SR_RFL_MASK) >> AIC_SR_RFL_BIT )
3865
3866 #define __ac97_command_transmitted() ( REG_AIC_ACSR & AIC_ACSR_CADT )
3867 #define __ac97_status_received() ( REG_AIC_ACSR & AIC_ACSR_SADR )
3868 #define __ac97_status_receive_timeout() ( REG_AIC_ACSR & AIC_ACSR_RSTO )
3869 #define __ac97_codec_is_low_power_mode() ( REG_AIC_ACSR & AIC_ACSR_CLPM )
3870 #define __ac97_codec_is_ready() ( REG_AIC_ACSR & AIC_ACSR_CRDY )
3871 #define __ac97_slot_error_detected() ( REG_AIC_ACSR & AIC_ACSR_SLTERR )
3872 #define __ac97_clear_slot_error() ( REG_AIC_ACSR &= ~AIC_ACSR_SLTERR )
3873
3874 #define __i2s_is_busy() ( REG_AIC_I2SSR & AIC_I2SSR_BSY )
3875
3876 #define CODEC_READ_CMD (1 << 19)
3877 #define CODEC_WRITE_CMD (0 << 19)
3878 #define CODEC_REG_INDEX_BIT 12
3879 #define CODEC_REG_INDEX_MASK (0x7f << CODEC_REG_INDEX_BIT) /* 18:12 */
3880 #define CODEC_REG_DATA_BIT 4
3881 #define CODEC_REG_DATA_MASK (0x0ffff << 4) /* 19:4 */
3882
3883 #define __ac97_out_rcmd_addr(reg) \
3884 do { \
3885 REG_AIC_ACCAR = CODEC_READ_CMD | ((reg) << CODEC_REG_INDEX_BIT); \
3886 } while (0)
3887
3888 #define __ac97_out_wcmd_addr(reg) \
3889 do { \
3890 REG_AIC_ACCAR = CODEC_WRITE_CMD | ((reg) << CODEC_REG_INDEX_BIT); \
3891 } while (0)
3892
3893 #define __ac97_out_data(value) \
3894 do { \
3895 REG_AIC_ACCDR = ((value) << CODEC_REG_DATA_BIT); \
3896 } while (0)
3897
3898 #define __ac97_in_data() \
3899 ( (REG_AIC_ACSDR & CODEC_REG_DATA_MASK) >> CODEC_REG_DATA_BIT )
3900
3901 #define __ac97_in_status_addr() \
3902 ( (REG_AIC_ACSAR & CODEC_REG_INDEX_MASK) >> CODEC_REG_INDEX_BIT )
3903
3904 #define __i2s_set_sample_rate(i2sclk, sync) \
3905 ( REG_AIC_I2SDIV = ((i2sclk) / (4*64)) / (sync) )
3906
3907 #define __aic_write_tfifo(v) ( REG_AIC_DR = (v) )
3908 #define __aic_read_rfifo() ( REG_AIC_DR )
3909
3910 #define __aic_internal_codec() ( REG_AIC_FR |= AIC_FR_ICDC )
3911 #define __aic_external_codec() ( REG_AIC_FR &= ~AIC_FR_ICDC )
3912
3913 /* Define next ops for AC97 compatible */
3914
3915 #define AC97_ACSR AIC_ACSR
3916
3917 #define __ac97_enable() __aic_enable(); __aic_select_ac97()
3918 #define __ac97_disable() __aic_disable()
3919 #define __ac97_reset() __aic_reset()
3920
3921 #define __ac97_set_transmit_trigger(n) __aic_set_transmit_trigger(n)
3922 #define __ac97_set_receive_trigger(n) __aic_set_receive_trigger(n)
3923
3924 #define __ac97_enable_record() __aic_enable_record()
3925 #define __ac97_disable_record() __aic_disable_record()
3926 #define __ac97_enable_replay() __aic_enable_replay()
3927 #define __ac97_disable_replay() __aic_disable_replay()
3928 #define __ac97_enable_loopback() __aic_enable_loopback()
3929 #define __ac97_disable_loopback() __aic_disable_loopback()
3930
3931 #define __ac97_enable_transmit_dma() __aic_enable_transmit_dma()
3932 #define __ac97_disable_transmit_dma() __aic_disable_transmit_dma()
3933 #define __ac97_enable_receive_dma() __aic_enable_receive_dma()
3934 #define __ac97_disable_receive_dma() __aic_disable_receive_dma()
3935
3936 #define __ac97_transmit_request() __aic_transmit_request()
3937 #define __ac97_receive_request() __aic_receive_request()
3938 #define __ac97_transmit_underrun() __aic_transmit_underrun()
3939 #define __ac97_receive_overrun() __aic_receive_overrun()
3940
3941 #define __ac97_clear_errors() __aic_clear_errors()
3942
3943 #define __ac97_get_transmit_resident() __aic_get_transmit_resident()
3944 #define __ac97_get_receive_count() __aic_get_receive_count()
3945
3946 #define __ac97_enable_transmit_intr() __aic_enable_transmit_intr()
3947 #define __ac97_disable_transmit_intr() __aic_disable_transmit_intr()
3948 #define __ac97_enable_receive_intr() __aic_enable_receive_intr()
3949 #define __ac97_disable_receive_intr() __aic_disable_receive_intr()
3950
3951 #define __ac97_write_tfifo(v) __aic_write_tfifo(v)
3952 #define __ac97_read_rfifo() __aic_read_rfifo()
3953
3954 /* Define next ops for I2S compatible */
3955
3956 #define I2S_ACSR AIC_I2SSR
3957
3958 #define __i2s_enable() __aic_enable(); __aic_select_i2s()
3959 #define __i2s_disable() __aic_disable()
3960 #define __i2s_reset() __aic_reset()
3961
3962 #define __i2s_set_transmit_trigger(n) __aic_set_transmit_trigger(n)
3963 #define __i2s_set_receive_trigger(n) __aic_set_receive_trigger(n)
3964
3965 #define __i2s_enable_record() __aic_enable_record()
3966 #define __i2s_disable_record() __aic_disable_record()
3967 #define __i2s_enable_replay() __aic_enable_replay()
3968 #define __i2s_disable_replay() __aic_disable_replay()
3969 #define __i2s_enable_loopback() __aic_enable_loopback()
3970 #define __i2s_disable_loopback() __aic_disable_loopback()
3971
3972 #define __i2s_enable_transmit_dma() __aic_enable_transmit_dma()
3973 #define __i2s_disable_transmit_dma() __aic_disable_transmit_dma()
3974 #define __i2s_enable_receive_dma() __aic_enable_receive_dma()
3975 #define __i2s_disable_receive_dma() __aic_disable_receive_dma()
3976
3977 #define __i2s_transmit_request() __aic_transmit_request()
3978 #define __i2s_receive_request() __aic_receive_request()
3979 #define __i2s_transmit_underrun() __aic_transmit_underrun()
3980 #define __i2s_receive_overrun() __aic_receive_overrun()
3981
3982 #define __i2s_clear_errors() __aic_clear_errors()
3983
3984 #define __i2s_get_transmit_resident() __aic_get_transmit_resident()
3985 #define __i2s_get_receive_count() __aic_get_receive_count()
3986
3987 #define __i2s_enable_transmit_intr() __aic_enable_transmit_intr()
3988 #define __i2s_disable_transmit_intr() __aic_disable_transmit_intr()
3989 #define __i2s_enable_receive_intr() __aic_enable_receive_intr()
3990 #define __i2s_disable_receive_intr() __aic_disable_receive_intr()
3991
3992 #define __i2s_write_tfifo(v) __aic_write_tfifo(v)
3993 #define __i2s_read_rfifo() __aic_read_rfifo()
3994
3995 #define __i2s_reset_codec() \
3996 do { \
3997 } while (0)
3998
3999
4000 /***************************************************************************
4001 * ICDC
4002 ***************************************************************************/
4003 #define __i2s_internal_codec() __aic_internal_codec()
4004 #define __i2s_external_codec() __aic_external_codec()
4005
4006 /***************************************************************************
4007 * INTC
4008 ***************************************************************************/
4009 #define __intc_unmask_irq(n) ( REG_INTC_IMCR = (1 << (n)) )
4010 #define __intc_mask_irq(n) ( REG_INTC_IMSR = (1 << (n)) )
4011 #define __intc_ack_irq(n) ( REG_INTC_IPR = (1 << (n)) )
4012
4013
4014 /***************************************************************************
4015 * I2C
4016 ***************************************************************************/
4017
4018 #define __i2c_enable() ( REG_I2C_CR |= I2C_CR_I2CE )
4019 #define __i2c_disable() ( REG_I2C_CR &= ~I2C_CR_I2CE )
4020
4021 #define __i2c_send_start() ( REG_I2C_CR |= I2C_CR_STA )
4022 #define __i2c_send_stop() ( REG_I2C_CR |= I2C_CR_STO )
4023 #define __i2c_send_ack() ( REG_I2C_CR &= ~I2C_CR_AC )
4024 #define __i2c_send_nack() ( REG_I2C_CR |= I2C_CR_AC )
4025
4026 #define __i2c_set_drf() ( REG_I2C_SR |= I2C_SR_DRF )
4027 #define __i2c_clear_drf() ( REG_I2C_SR &= ~I2C_SR_DRF )
4028 #define __i2c_check_drf() ( REG_I2C_SR & I2C_SR_DRF )
4029
4030 #define __i2c_received_ack() ( !(REG_I2C_SR & I2C_SR_ACKF) )
4031 #define __i2c_is_busy() ( REG_I2C_SR & I2C_SR_BUSY )
4032 #define __i2c_transmit_ended() ( REG_I2C_SR & I2C_SR_TEND )
4033
4034 #define __i2c_set_clk(dev_clk, i2c_clk) \
4035 ( REG_I2C_GR = (dev_clk) / (16*(i2c_clk)) - 1 )
4036
4037 #define __i2c_read() ( REG_I2C_DR )
4038 #define __i2c_write(val) ( REG_I2C_DR = (val) )
4039
4040
4041 /***************************************************************************
4042 * MSC
4043 ***************************************************************************/
4044
4045 #define __msc_start_op() \
4046 ( REG_MSC_STRPCL = MSC_STRPCL_START_OP | MSC_STRPCL_CLOCK_CONTROL_START )
4047
4048 #define __msc_set_resto(to) ( REG_MSC_RESTO = to )
4049 #define __msc_set_rdto(to) ( REG_MSC_RDTO = to )
4050 #define __msc_set_cmd(cmd) ( REG_MSC_CMD = cmd )
4051 #define __msc_set_arg(arg) ( REG_MSC_ARG = arg )
4052 #define __msc_set_nob(nob) ( REG_MSC_NOB = nob )
4053 #define __msc_get_nob() ( REG_MSC_NOB )
4054 #define __msc_set_blklen(len) ( REG_MSC_BLKLEN = len )
4055 #define __msc_set_cmdat(cmdat) ( REG_MSC_CMDAT = cmdat )
4056 #define __msc_set_cmdat_ioabort() ( REG_MSC_CMDAT |= MSC_CMDAT_IO_ABORT )
4057 #define __msc_clear_cmdat_ioabort() ( REG_MSC_CMDAT &= ~MSC_CMDAT_IO_ABORT )
4058
4059 #define __msc_set_cmdat_bus_width1() \
4060 do { \
4061 REG_MSC_CMDAT &= ~MSC_CMDAT_BUS_WIDTH_MASK; \
4062 REG_MSC_CMDAT |= MSC_CMDAT_BUS_WIDTH_1BIT; \
4063 } while(0)
4064
4065 #define __msc_set_cmdat_bus_width4() \
4066 do { \
4067 REG_MSC_CMDAT &= ~MSC_CMDAT_BUS_WIDTH_MASK; \
4068 REG_MSC_CMDAT |= MSC_CMDAT_BUS_WIDTH_4BIT; \
4069 } while(0)
4070
4071 #define __msc_set_cmdat_dma_en() ( REG_MSC_CMDAT |= MSC_CMDAT_DMA_EN )
4072 #define __msc_set_cmdat_init() ( REG_MSC_CMDAT |= MSC_CMDAT_INIT )
4073 #define __msc_set_cmdat_busy() ( REG_MSC_CMDAT |= MSC_CMDAT_BUSY )
4074 #define __msc_set_cmdat_stream() ( REG_MSC_CMDAT |= MSC_CMDAT_STREAM_BLOCK )
4075 #define __msc_set_cmdat_block() ( REG_MSC_CMDAT &= ~MSC_CMDAT_STREAM_BLOCK )
4076 #define __msc_set_cmdat_read() ( REG_MSC_CMDAT &= ~MSC_CMDAT_WRITE_READ )
4077 #define __msc_set_cmdat_write() ( REG_MSC_CMDAT |= MSC_CMDAT_WRITE_READ )
4078 #define __msc_set_cmdat_data_en() ( REG_MSC_CMDAT |= MSC_CMDAT_DATA_EN )
4079
4080 /* r is MSC_CMDAT_RESPONSE_FORMAT_Rx or MSC_CMDAT_RESPONSE_FORMAT_NONE */
4081 #define __msc_set_cmdat_res_format(r) \
4082 do { \
4083 REG_MSC_CMDAT &= ~MSC_CMDAT_RESPONSE_FORMAT_MASK; \
4084 REG_MSC_CMDAT |= (r); \
4085 } while(0)
4086
4087 #define __msc_clear_cmdat() \
4088 REG_MSC_CMDAT &= ~( MSC_CMDAT_IO_ABORT | MSC_CMDAT_DMA_EN | MSC_CMDAT_INIT| \
4089 MSC_CMDAT_BUSY | MSC_CMDAT_STREAM_BLOCK | MSC_CMDAT_WRITE_READ | \
4090 MSC_CMDAT_DATA_EN | MSC_CMDAT_RESPONSE_FORMAT_MASK )
4091
4092 #define __msc_get_imask() ( REG_MSC_IMASK )
4093 #define __msc_mask_all_intrs() ( REG_MSC_IMASK = 0xff )
4094 #define __msc_unmask_all_intrs() ( REG_MSC_IMASK = 0x00 )
4095 #define __msc_mask_rd() ( REG_MSC_IMASK |= MSC_IMASK_RXFIFO_RD_REQ )
4096 #define __msc_unmask_rd() ( REG_MSC_IMASK &= ~MSC_IMASK_RXFIFO_RD_REQ )
4097 #define __msc_mask_wr() ( REG_MSC_IMASK |= MSC_IMASK_TXFIFO_WR_REQ )
4098 #define __msc_unmask_wr() ( REG_MSC_IMASK &= ~MSC_IMASK_TXFIFO_WR_REQ )
4099 #define __msc_mask_endcmdres() ( REG_MSC_IMASK |= MSC_IMASK_END_CMD_RES )
4100 #define __msc_unmask_endcmdres() ( REG_MSC_IMASK &= ~MSC_IMASK_END_CMD_RES )
4101 #define __msc_mask_datatrandone() ( REG_MSC_IMASK |= MSC_IMASK_DATA_TRAN_DONE )
4102 #define __msc_unmask_datatrandone() ( REG_MSC_IMASK &= ~MSC_IMASK_DATA_TRAN_DONE )
4103 #define __msc_mask_prgdone() ( REG_MSC_IMASK |= MSC_IMASK_PRG_DONE )
4104 #define __msc_unmask_prgdone() ( REG_MSC_IMASK &= ~MSC_IMASK_PRG_DONE )
4105
4106 /* n=0,1,2,3,4,5,6,7 */
4107 #define __msc_set_clkrt(n) \
4108 do { \
4109 REG_MSC_CLKRT = n; \
4110 } while(0)
4111
4112 #define __msc_get_ireg() ( REG_MSC_IREG )
4113 #define __msc_ireg_rd() ( REG_MSC_IREG & MSC_IREG_RXFIFO_RD_REQ )
4114 #define __msc_ireg_wr() ( REG_MSC_IREG & MSC_IREG_TXFIFO_WR_REQ )
4115 #define __msc_ireg_end_cmd_res() ( REG_MSC_IREG & MSC_IREG_END_CMD_RES )
4116 #define __msc_ireg_data_tran_done() ( REG_MSC_IREG & MSC_IREG_DATA_TRAN_DONE )
4117 #define __msc_ireg_prg_done() ( REG_MSC_IREG & MSC_IREG_PRG_DONE )
4118 #define __msc_ireg_clear_end_cmd_res() ( REG_MSC_IREG = MSC_IREG_END_CMD_RES )
4119 #define __msc_ireg_clear_data_tran_done() ( REG_MSC_IREG = MSC_IREG_DATA_TRAN_DONE )
4120 #define __msc_ireg_clear_prg_done() ( REG_MSC_IREG = MSC_IREG_PRG_DONE )
4121
4122 #define __msc_get_stat() ( REG_MSC_STAT )
4123 #define __msc_stat_not_end_cmd_res() ( (REG_MSC_STAT & MSC_STAT_END_CMD_RES) == 0)
4124 #define __msc_stat_crc_err() \
4125 ( REG_MSC_STAT & (MSC_STAT_CRC_RES_ERR | MSC_STAT_CRC_READ_ERROR | MSC_STAT_CRC_WRITE_ERROR_YES) )
4126 #define __msc_stat_res_crc_err() ( REG_MSC_STAT & MSC_STAT_CRC_RES_ERR )
4127 #define __msc_stat_rd_crc_err() ( REG_MSC_STAT & MSC_STAT_CRC_READ_ERROR )
4128 #define __msc_stat_wr_crc_err() ( REG_MSC_STAT & MSC_STAT_CRC_WRITE_ERROR_YES )
4129 #define __msc_stat_resto_err() ( REG_MSC_STAT & MSC_STAT_TIME_OUT_RES )
4130 #define __msc_stat_rdto_err() ( REG_MSC_STAT & MSC_STAT_TIME_OUT_READ )
4131
4132 #define __msc_rd_resfifo() ( REG_MSC_RES )
4133 #define __msc_rd_rxfifo() ( REG_MSC_RXFIFO )
4134 #define __msc_wr_txfifo(v) ( REG_MSC_TXFIFO = v )
4135
4136 #define __msc_reset() \
4137 do { \
4138 REG_MSC_STRPCL = MSC_STRPCL_RESET; \
4139 while (REG_MSC_STAT & MSC_STAT_IS_RESETTING); \
4140 } while (0)
4141
4142 #define __msc_start_clk() \
4143 do { \
4144 REG_MSC_STRPCL = MSC_STRPCL_CLOCK_CONTROL_START; \
4145 } while (0)
4146
4147 #define __msc_stop_clk() \
4148 do { \
4149 REG_MSC_STRPCL = MSC_STRPCL_CLOCK_CONTROL_STOP; \
4150 } while (0)
4151
4152 #define MMC_CLK 19169200
4153 #define SD_CLK 24576000
4154
4155 /* msc_clk should little than pclk and little than clk retrieve from card */
4156 #define __msc_calc_clk_divisor(type,dev_clk,msc_clk,lv) \
4157 do { \
4158 unsigned int rate, pclk, i; \
4159 pclk = dev_clk; \
4160 rate = type?SD_CLK:MMC_CLK; \
4161 if (msc_clk && msc_clk < pclk) \
4162 pclk = msc_clk; \
4163 i = 0; \
4164 while (pclk < rate) \
4165 { \
4166 i ++; \
4167 rate >>= 1; \
4168 } \
4169 lv = i; \
4170 } while(0)
4171
4172 /* divide rate to little than or equal to 400kHz */
4173 #define __msc_calc_slow_clk_divisor(type, lv) \
4174 do { \
4175 unsigned int rate, i; \
4176 rate = (type?SD_CLK:MMC_CLK)/1000/400; \
4177 i = 0; \
4178 while (rate > 0) \
4179 { \
4180 rate >>= 1; \
4181 i ++; \
4182 } \
4183 lv = i; \
4184 } while(0)
4185
4186
4187 /***************************************************************************
4188 * SSI
4189 ***************************************************************************/
4190
4191 #define __ssi_enable() ( REG_SSI_CR0 |= SSI_CR0_SSIE )
4192 #define __ssi_disable() ( REG_SSI_CR0 &= ~SSI_CR0_SSIE )
4193 #define __ssi_select_ce() ( REG_SSI_CR0 &= ~SSI_CR0_FSEL )
4194
4195 #define __ssi_normal_mode() ( REG_SSI_ITR &= ~SSI_ITR_IVLTM_MASK )
4196
4197 #define __ssi_select_ce2() \
4198 do { \
4199 REG_SSI_CR0 |= SSI_CR0_FSEL; \
4200 REG_SSI_CR1 &= ~SSI_CR1_MULTS; \
4201 } while (0)
4202
4203 #define __ssi_select_gpc() \
4204 do { \
4205 REG_SSI_CR0 &= ~SSI_CR0_FSEL; \
4206 REG_SSI_CR1 |= SSI_CR1_MULTS; \
4207 } while (0)
4208
4209 #define __ssi_enable_tx_intr() \
4210 ( REG_SSI_CR0 |= SSI_CR0_TIE | SSI_CR0_TEIE )
4211
4212 #define __ssi_disable_tx_intr() \
4213 ( REG_SSI_CR0 &= ~(SSI_CR0_TIE | SSI_CR0_TEIE) )
4214
4215 #define __ssi_enable_rx_intr() \
4216 ( REG_SSI_CR0 |= SSI_CR0_RIE | SSI_CR0_REIE )
4217
4218 #define __ssi_disable_rx_intr() \
4219 ( REG_SSI_CR0 &= ~(SSI_CR0_RIE | SSI_CR0_REIE) )
4220
4221 #define __ssi_enable_loopback() ( REG_SSI_CR0 |= SSI_CR0_LOOP )
4222 #define __ssi_disable_loopback() ( REG_SSI_CR0 &= ~SSI_CR0_LOOP )
4223
4224 #define __ssi_enable_receive() ( REG_SSI_CR0 &= ~SSI_CR0_DISREV )
4225 #define __ssi_disable_receive() ( REG_SSI_CR0 |= SSI_CR0_DISREV )
4226
4227 #define __ssi_finish_receive() \
4228 ( REG_SSI_CR0 |= (SSI_CR0_RFINE | SSI_CR0_RFINC) )
4229
4230 #define __ssi_disable_recvfinish() \
4231 ( REG_SSI_CR0 &= ~(SSI_CR0_RFINE | SSI_CR0_RFINC) )
4232
4233 #define __ssi_flush_txfifo() ( REG_SSI_CR0 |= SSI_CR0_TFLUSH )
4234 #define __ssi_flush_rxfifo() ( REG_SSI_CR0 |= SSI_CR0_RFLUSH )
4235
4236 #define __ssi_flush_fifo() \
4237 ( REG_SSI_CR0 |= SSI_CR0_TFLUSH | SSI_CR0_RFLUSH )
4238
4239 #define __ssi_finish_transmit() ( REG_SSI_CR1 &= ~SSI_CR1_UNFIN )
4240
4241 #define __ssi_spi_format() \
4242 do { \
4243 REG_SSI_CR1 &= ~SSI_CR1_FMAT_MASK; \
4244 REG_SSI_CR1 |= SSI_CR1_FMAT_SPI; \
4245 REG_SSI_CR1 &= ~(SSI_CR1_TFVCK_MASK|SSI_CR1_TCKFI_MASK);\
4246 REG_SSI_CR1 |= (SSI_CR1_TFVCK_1 | SSI_CR1_TCKFI_1); \
4247 } while (0)
4248
4249 /* TI's SSP format, must clear SSI_CR1.UNFIN */
4250 #define __ssi_ssp_format() \
4251 do { \
4252 REG_SSI_CR1 &= ~(SSI_CR1_FMAT_MASK | SSI_CR1_UNFIN); \
4253 REG_SSI_CR1 |= SSI_CR1_FMAT_SSP; \
4254 } while (0)
4255
4256 /* National's Microwire format, must clear SSI_CR0.RFINE, and set max delay */
4257 #define __ssi_microwire_format() \
4258 do { \
4259 REG_SSI_CR1 &= ~SSI_CR1_FMAT_MASK; \
4260 REG_SSI_CR1 |= SSI_CR1_FMAT_MW1; \
4261 REG_SSI_CR1 &= ~(SSI_CR1_TFVCK_MASK|SSI_CR1_TCKFI_MASK);\
4262 REG_SSI_CR1 |= (SSI_CR1_TFVCK_3 | SSI_CR1_TCKFI_3); \
4263 REG_SSI_CR0 &= ~SSI_CR0_RFINE; \
4264 } while (0)
4265
4266 /* CE# level (FRMHL), CE# in interval time (ITFRM),
4267 clock phase and polarity (PHA POL),
4268 interval time (SSIITR), interval characters/frame (SSIICR) */
4269
4270 /* frmhl,endian,mcom,flen,pha,pol MASK */
4271 #define SSICR1_MISC_MASK \
4272 ( SSI_CR1_FRMHL_MASK | SSI_CR1_LFST | SSI_CR1_MCOM_MASK \
4273 | SSI_CR1_FLEN_MASK | SSI_CR1_PHA | SSI_CR1_POL ) \
4274
4275 #define __ssi_spi_set_misc(frmhl,endian,flen,mcom,pha,pol) \
4276 do { \
4277 REG_SSI_CR1 &= ~SSICR1_MISC_MASK; \
4278 REG_SSI_CR1 |= ((frmhl) << 30) | ((endian) << 25) | \
4279 (((mcom) - 1) << 12) | (((flen) - 2) << 4) | \
4280 ((pha) << 1) | (pol); \
4281 } while(0)
4282
4283 /* Transfer with MSB or LSB first */
4284 #define __ssi_set_msb() ( REG_SSI_CR1 &= ~SSI_CR1_LFST )
4285 #define __ssi_set_lsb() ( REG_SSI_CR1 |= SSI_CR1_LFST )
4286
4287 #define __ssi_set_frame_length(n) \
4288 REG_SSI_CR1 = (REG_SSI_CR1 & ~SSI_CR1_FLEN_MASK) | (((n) - 2) << 4)
4289
4290 /* n = 1 - 16 */
4291 #define __ssi_set_microwire_command_length(n) \
4292 ( REG_SSI_CR1 = ((REG_SSI_CR1 & ~SSI_CR1_MCOM_MASK) | SSI_CR1_MCOM_##n##BIT) )
4293
4294 /* Set the clock phase for SPI */
4295 #define __ssi_set_spi_clock_phase(n) \
4296 ( REG_SSI_CR1 = ((REG_SSI_CR1 & ~SSI_CR1_PHA) | (n&0x1)) )
4297
4298 /* Set the clock polarity for SPI */
4299 #define __ssi_set_spi_clock_polarity(n) \
4300 ( REG_SSI_CR1 = ((REG_SSI_CR1 & ~SSI_CR1_POL) | (n&0x1)) )
4301
4302 /* n = ix8 */
4303 #define __ssi_set_tx_trigger(n) \
4304 do { \
4305 REG_SSI_CR1 &= ~SSI_CR1_TTRG_MASK; \
4306 REG_SSI_CR1 |= SSI_CR1_TTRG_##n; \
4307 } while (0)
4308
4309 /* n = ix8 */
4310 #define __ssi_set_rx_trigger(n) \
4311 do { \
4312 REG_SSI_CR1 &= ~SSI_CR1_RTRG_MASK; \
4313 REG_SSI_CR1 |= SSI_CR1_RTRG_##n; \
4314 } while (0)
4315
4316 #define __ssi_get_txfifo_count() \
4317 ( (REG_SSI_SR & SSI_SR_TFIFONUM_MASK) >> SSI_SR_TFIFONUM_BIT )
4318
4319 #define __ssi_get_rxfifo_count() \
4320 ( (REG_SSI_SR & SSI_SR_RFIFONUM_MASK) >> SSI_SR_RFIFONUM_BIT )
4321
4322 #define __ssi_clear_errors() \
4323 ( REG_SSI_SR &= ~(SSI_SR_UNDR | SSI_SR_OVER) )
4324
4325 #define __ssi_transfer_end() ( REG_SSI_SR & SSI_SR_END )
4326 #define __ssi_is_busy() ( REG_SSI_SR & SSI_SR_BUSY )
4327
4328 #define __ssi_txfifo_full() ( REG_SSI_SR & SSI_SR_TFF )
4329 #define __ssi_rxfifo_empty() ( REG_SSI_SR & SSI_SR_RFE )
4330 #define __ssi_rxfifo_noempty() ( REG_SSI_SR & SSI_SR_RFHF )
4331
4332 #define __ssi_set_clk(dev_clk, ssi_clk) \
4333 ( REG_SSI_GR = (dev_clk) / (2*(ssi_clk)) - 1 )
4334
4335 #define __ssi_receive_data() REG_SSI_DR
4336 #define __ssi_transmit_data(v) ( REG_SSI_DR = (v) )
4337
4338
4339 /***************************************************************************
4340 * CIM
4341 ***************************************************************************/
4342
4343 #define __cim_enable() ( REG_CIM_CTRL |= CIM_CTRL_ENA )
4344 #define __cim_disable() ( REG_CIM_CTRL &= ~CIM_CTRL_ENA )
4345
4346 #define __cim_input_data_inverse() ( REG_CIM_CFG |= CIM_CFG_INV_DAT )
4347 #define __cim_input_data_normal() ( REG_CIM_CFG &= ~CIM_CFG_INV_DAT )
4348
4349 #define __cim_vsync_active_low() ( REG_CIM_CFG |= CIM_CFG_VSP )
4350 #define __cim_vsync_active_high() ( REG_CIM_CFG &= ~CIM_CFG_VSP )
4351
4352 #define __cim_hsync_active_low() ( REG_CIM_CFG |= CIM_CFG_HSP )
4353 #define __cim_hsync_active_high() ( REG_CIM_CFG &= ~CIM_CFG_HSP )
4354
4355 #define __cim_sample_data_at_pclk_falling_edge() \
4356 ( REG_CIM_CFG |= CIM_CFG_PCP )
4357 #define __cim_sample_data_at_pclk_rising_edge() \
4358 ( REG_CIM_CFG &= ~CIM_CFG_PCP )
4359
4360 #define __cim_enable_dummy_zero() ( REG_CIM_CFG |= CIM_CFG_DUMMY_ZERO )
4361 #define __cim_disable_dummy_zero() ( REG_CIM_CFG &= ~CIM_CFG_DUMMY_ZERO )
4362
4363 #define __cim_select_external_vsync() ( REG_CIM_CFG |= CIM_CFG_EXT_VSYNC )
4364 #define __cim_select_internal_vsync() ( REG_CIM_CFG &= ~CIM_CFG_EXT_VSYNC )
4365
4366 /* n=0-7 */
4367 #define __cim_set_data_packing_mode(n) \
4368 do { \
4369 REG_CIM_CFG &= ~CIM_CFG_PACK_MASK; \
4370 REG_CIM_CFG |= (CIM_CFG_PACK_##n); \
4371 } while (0)
4372
4373 #define __cim_enable_ccir656_progressive_mode() \
4374 do { \
4375 REG_CIM_CFG &= ~CIM_CFG_DSM_MASK; \
4376 REG_CIM_CFG |= CIM_CFG_DSM_CPM; \
4377 } while (0)
4378
4379 #define __cim_enable_ccir656_interlace_mode() \
4380 do { \
4381 REG_CIM_CFG &= ~CIM_CFG_DSM_MASK; \
4382 REG_CIM_CFG |= CIM_CFG_DSM_CIM; \
4383 } while (0)
4384
4385 #define __cim_enable_gated_clock_mode() \
4386 do { \
4387 REG_CIM_CFG &= ~CIM_CFG_DSM_MASK; \
4388 REG_CIM_CFG |= CIM_CFG_DSM_GCM; \
4389 } while (0)
4390
4391 #define __cim_enable_nongated_clock_mode() \
4392 do { \
4393 REG_CIM_CFG &= ~CIM_CFG_DSM_MASK; \
4394 REG_CIM_CFG |= CIM_CFG_DSM_NGCM; \
4395 } while (0)
4396
4397 /* sclk:system bus clock
4398 * mclk: CIM master clock
4399 */
4400 #define __cim_set_master_clk(sclk, mclk) \
4401 do { \
4402 REG_CIM_CTRL &= ~CIM_CTRL_MCLKDIV_MASK; \
4403 REG_CIM_CTRL |= (((sclk)/(mclk) - 1) << CIM_CTRL_MCLKDIV_BIT); \
4404 } while (0)
4405
4406 #define __cim_enable_sof_intr() \
4407 ( REG_CIM_CTRL |= CIM_CTRL_DMA_SOFM )
4408 #define __cim_disable_sof_intr() \
4409 ( REG_CIM_CTRL &= ~CIM_CTRL_DMA_SOFM )
4410
4411 #define __cim_enable_eof_intr() \
4412 ( REG_CIM_CTRL |= CIM_CTRL_DMA_EOFM )
4413 #define __cim_disable_eof_intr() \
4414 ( REG_CIM_CTRL &= ~CIM_CTRL_DMA_EOFM )
4415
4416 #define __cim_enable_stop_intr() \
4417 ( REG_CIM_CTRL |= CIM_CTRL_DMA_STOPM )
4418 #define __cim_disable_stop_intr() \
4419 ( REG_CIM_CTRL &= ~CIM_CTRL_DMA_STOPM )
4420
4421 #define __cim_enable_trig_intr() \
4422 ( REG_CIM_CTRL |= CIM_CTRL_RXF_TRIGM )
4423 #define __cim_disable_trig_intr() \
4424 ( REG_CIM_CTRL &= ~CIM_CTRL_RXF_TRIGM )
4425
4426 #define __cim_enable_rxfifo_overflow_intr() \
4427 ( REG_CIM_CTRL |= CIM_CTRL_RXF_OFM )
4428 #define __cim_disable_rxfifo_overflow_intr() \
4429 ( REG_CIM_CTRL &= ~CIM_CTRL_RXF_OFM )
4430
4431 /* n=1-16 */
4432 #define __cim_set_frame_rate(n) \
4433 do { \
4434 REG_CIM_CTRL &= ~CIM_CTRL_FRC_MASK; \
4435 REG_CIM_CTRL |= CIM_CTRL_FRC_##n; \
4436 } while (0)
4437
4438 #define __cim_enable_dma() ( REG_CIM_CTRL |= CIM_CTRL_DMA_EN )
4439 #define __cim_disable_dma() ( REG_CIM_CTRL &= ~CIM_CTRL_DMA_EN )
4440
4441 #define __cim_reset_rxfifo() ( REG_CIM_CTRL |= CIM_CTRL_RXF_RST )
4442 #define __cim_unreset_rxfifo() ( REG_CIM_CTRL &= ~CIM_CTRL_RXF_RST )
4443
4444 /* n=4,8,12,16,20,24,28,32 */
4445 #define __cim_set_rxfifo_trigger(n) \
4446 do { \
4447 REG_CIM_CTRL &= ~CIM_CTRL_RXF_TRIG_MASK; \
4448 REG_CIM_CTRL |= CIM_CTRL_RXF_TRIG_##n; \
4449 } while (0)
4450
4451 #define __cim_clear_state() ( REG_CIM_STATE = 0 )
4452
4453 #define __cim_disable_done() ( REG_CIM_STATE & CIM_STATE_VDD )
4454 #define __cim_rxfifo_empty() ( REG_CIM_STATE & CIM_STATE_RXF_EMPTY )
4455 #define __cim_rxfifo_reach_trigger() ( REG_CIM_STATE & CIM_STATE_RXF_TRIG )
4456 #define __cim_rxfifo_overflow() ( REG_CIM_STATE & CIM_STATE_RXF_OF )
4457 #define __cim_clear_rxfifo_overflow() ( REG_CIM_STATE &= ~CIM_STATE_RXF_OF )
4458 #define __cim_dma_stop() ( REG_CIM_STATE & CIM_STATE_DMA_STOP )
4459 #define __cim_dma_eof() ( REG_CIM_STATE & CIM_STATE_DMA_EOF )
4460 #define __cim_dma_sof() ( REG_CIM_STATE & CIM_STATE_DMA_SOF )
4461
4462 #define __cim_get_iid() ( REG_CIM_IID )
4463 #define __cim_get_image_data() ( REG_CIM_RXFIFO )
4464 #define __cim_get_dam_cmd() ( REG_CIM_CMD )
4465
4466 #define __cim_set_da(a) ( REG_CIM_DA = (a) )
4467
4468 /***************************************************************************
4469 * LCD
4470 ***************************************************************************/
4471 #define __lcd_as_smart_lcd() ( REG_LCD_CFG |= (1<<LCD_CFG_LCDPIN_BIT) )
4472 #define __lcd_as_general_lcd() ( REG_LCD_CFG &= ~(1<<LCD_CFG_LCDPIN_BIT) )
4473
4474 #define __lcd_set_dis() ( REG_LCD_CTRL |= LCD_CTRL_DIS )
4475 #define __lcd_clr_dis() ( REG_LCD_CTRL &= ~LCD_CTRL_DIS )
4476
4477 #define __lcd_set_ena() ( REG_LCD_CTRL |= LCD_CTRL_ENA )
4478 #define __lcd_clr_ena() ( REG_LCD_CTRL &= ~LCD_CTRL_ENA )
4479
4480 /* n=1,2,4,8,16 */
4481 #define __lcd_set_bpp(n) \
4482 ( REG_LCD_CTRL = (REG_LCD_CTRL & ~LCD_CTRL_BPP_MASK) | LCD_CTRL_BPP_##n )
4483
4484 /* n=4,8,16 */
4485 #define __lcd_set_burst_length(n) \
4486 do { \
4487 REG_LCD_CTRL &= ~LCD_CTRL_BST_MASK; \
4488 REG_LCD_CTRL |= LCD_CTRL_BST_n##; \
4489 } while (0)
4490
4491 #define __lcd_select_rgb565() ( REG_LCD_CTRL &= ~LCD_CTRL_RGB555 )
4492 #define __lcd_select_rgb555() ( REG_LCD_CTRL |= LCD_CTRL_RGB555 )
4493
4494 #define __lcd_set_ofup() ( REG_LCD_CTRL |= LCD_CTRL_OFUP )
4495 #define __lcd_clr_ofup() ( REG_LCD_CTRL &= ~LCD_CTRL_OFUP )
4496
4497 /* n=2,4,16 */
4498 #define __lcd_set_stn_frc(n) \
4499 do { \
4500 REG_LCD_CTRL &= ~LCD_CTRL_FRC_MASK; \
4501 REG_LCD_CTRL |= LCD_CTRL_FRC_n##; \
4502 } while (0)
4503
4504
4505 #define __lcd_pixel_endian_little() ( REG_LCD_CTRL |= LCD_CTRL_PEDN )
4506 #define __lcd_pixel_endian_big() ( REG_LCD_CTRL &= ~LCD_CTRL_PEDN )
4507
4508 #define __lcd_reverse_byte_endian() ( REG_LCD_CTRL |= LCD_CTRL_BEDN )
4509 #define __lcd_normal_byte_endian() ( REG_LCD_CTRL &= ~LCD_CTRL_BEDN )
4510
4511 #define __lcd_enable_eof_intr() ( REG_LCD_CTRL |= LCD_CTRL_EOFM )
4512 #define __lcd_disable_eof_intr() ( REG_LCD_CTRL &= ~LCD_CTRL_EOFM )
4513
4514 #define __lcd_enable_sof_intr() ( REG_LCD_CTRL |= LCD_CTRL_SOFM )
4515 #define __lcd_disable_sof_intr() ( REG_LCD_CTRL &= ~LCD_CTRL_SOFM )
4516
4517 #define __lcd_enable_ofu_intr() ( REG_LCD_CTRL |= LCD_CTRL_OFUM )
4518 #define __lcd_disable_ofu_intr() ( REG_LCD_CTRL &= ~LCD_CTRL_OFUM )
4519
4520 #define __lcd_enable_ifu0_intr() ( REG_LCD_CTRL |= LCD_CTRL_IFUM0 )
4521 #define __lcd_disable_ifu0_intr() ( REG_LCD_CTRL &= ~LCD_CTRL_IFUM0 )
4522
4523 #define __lcd_enable_ifu1_intr() ( REG_LCD_CTRL |= LCD_CTRL_IFUM1 )
4524 #define __lcd_disable_ifu1_intr() ( REG_LCD_CTRL &= ~LCD_CTRL_IFUM1 )
4525
4526 #define __lcd_enable_ldd_intr() ( REG_LCD_CTRL |= LCD_CTRL_LDDM )
4527 #define __lcd_disable_ldd_intr() ( REG_LCD_CTRL &= ~LCD_CTRL_LDDM )
4528
4529 #define __lcd_enable_qd_intr() ( REG_LCD_CTRL |= LCD_CTRL_QDM )
4530 #define __lcd_disable_qd_intr() ( REG_LCD_CTRL &= ~LCD_CTRL_QDM )
4531
4532
4533 /* LCD status register indication */
4534
4535 #define __lcd_quick_disable_done() ( REG_LCD_STATE & LCD_STATE_QD )
4536 #define __lcd_disable_done() ( REG_LCD_STATE & LCD_STATE_LDD )
4537 #define __lcd_infifo0_underrun() ( REG_LCD_STATE & LCD_STATE_IFU0 )
4538 #define __lcd_infifo1_underrun() ( REG_LCD_STATE & LCD_STATE_IFU1 )
4539 #define __lcd_outfifo_underrun() ( REG_LCD_STATE & LCD_STATE_OFU )
4540 #define __lcd_start_of_frame() ( REG_LCD_STATE & LCD_STATE_SOF )
4541 #define __lcd_end_of_frame() ( REG_LCD_STATE & LCD_STATE_EOF )
4542
4543 #define __lcd_clr_outfifounderrun() ( REG_LCD_STATE &= ~LCD_STATE_OFU )
4544 #define __lcd_clr_sof() ( REG_LCD_STATE &= ~LCD_STATE_SOF )
4545 #define __lcd_clr_eof() ( REG_LCD_STATE &= ~LCD_STATE_EOF )
4546
4547 #define __lcd_panel_white() ( REG_LCD_CFG |= LCD_CFG_WHITE )
4548 #define __lcd_panel_black() ( REG_LCD_CFG &= ~LCD_CFG_WHITE )
4549
4550 /* n=1,2,4,8 for single mono-STN
4551 * n=4,8 for dual mono-STN
4552 */
4553 #define __lcd_set_panel_datawidth(n) \
4554 do { \
4555 REG_LCD_CFG &= ~LCD_CFG_PDW_MASK; \
4556 REG_LCD_CFG |= LCD_CFG_PDW_n##; \
4557 } while (0)
4558
4559 /* m=LCD_CFG_MODE_GENERUIC_TFT_xxx */
4560 #define __lcd_set_panel_mode(m) \
4561 do { \
4562 REG_LCD_CFG &= ~LCD_CFG_MODE_MASK; \
4563 REG_LCD_CFG |= (m); \
4564 } while(0)
4565
4566 /* n = 0-255 */
4567 #define __lcd_disable_ac_bias() ( REG_LCD_IO = 0xff )
4568 #define __lcd_set_ac_bias(n) \
4569 do { \
4570 REG_LCD_IO &= ~LCD_IO_ACB_MASK; \
4571 REG_LCD_IO |= ((n) << LCD_IO_ACB_BIT); \
4572 } while(0)
4573
4574 #define __lcd_io_set_dir() ( REG_LCD_IO |= LCD_IO_DIR )
4575 #define __lcd_io_clr_dir() ( REG_LCD_IO &= ~LCD_IO_DIR )
4576
4577 #define __lcd_io_set_dep() ( REG_LCD_IO |= LCD_IO_DEP )
4578 #define __lcd_io_clr_dep() ( REG_LCD_IO &= ~LCD_IO_DEP )
4579
4580 #define __lcd_io_set_vsp() ( REG_LCD_IO |= LCD_IO_VSP )
4581 #define __lcd_io_clr_vsp() ( REG_LCD_IO &= ~LCD_IO_VSP )
4582
4583 #define __lcd_io_set_hsp() ( REG_LCD_IO |= LCD_IO_HSP )
4584 #define __lcd_io_clr_hsp() ( REG_LCD_IO &= ~LCD_IO_HSP )
4585
4586 #define __lcd_io_set_pcp() ( REG_LCD_IO |= LCD_IO_PCP )
4587 #define __lcd_io_clr_pcp() ( REG_LCD_IO &= ~LCD_IO_PCP )
4588
4589 #define __lcd_vsync_get_vps() \
4590 ( (REG_LCD_VSYNC & LCD_VSYNC_VPS_MASK) >> LCD_VSYNC_VPS_BIT )
4591
4592 #define __lcd_vsync_get_vpe() \
4593 ( (REG_LCD_VSYNC & LCD_VSYNC_VPE_MASK) >> LCD_VSYNC_VPE_BIT )
4594 #define __lcd_vsync_set_vpe(n) \
4595 do { \
4596 REG_LCD_VSYNC &= ~LCD_VSYNC_VPE_MASK; \
4597 REG_LCD_VSYNC |= (n) << LCD_VSYNC_VPE_BIT; \
4598 } while (0)
4599
4600 #define __lcd_hsync_get_hps() \
4601 ( (REG_LCD_HSYNC & LCD_HSYNC_HPS_MASK) >> LCD_HSYNC_HPS_BIT )
4602 #define __lcd_hsync_set_hps(n) \
4603 do { \
4604 REG_LCD_HSYNC &= ~LCD_HSYNC_HPS_MASK; \
4605 REG_LCD_HSYNC |= (n) << LCD_HSYNC_HPS_BIT; \
4606 } while (0)
4607
4608 #define __lcd_hsync_get_hpe() \
4609 ( (REG_LCD_HSYNC & LCD_HSYNC_HPE_MASK) >> LCD_VSYNC_HPE_BIT )
4610 #define __lcd_hsync_set_hpe(n) \
4611 do { \
4612 REG_LCD_HSYNC &= ~LCD_HSYNC_HPE_MASK; \
4613 REG_LCD_HSYNC |= (n) << LCD_HSYNC_HPE_BIT; \
4614 } while (0)
4615
4616 #define __lcd_vat_get_ht() \
4617 ( (REG_LCD_VAT & LCD_VAT_HT_MASK) >> LCD_VAT_HT_BIT )
4618 #define __lcd_vat_set_ht(n) \
4619 do { \
4620 REG_LCD_VAT &= ~LCD_VAT_HT_MASK; \
4621 REG_LCD_VAT |= (n) << LCD_VAT_HT_BIT; \
4622 } while (0)
4623
4624 #define __lcd_vat_get_vt() \
4625 ( (REG_LCD_VAT & LCD_VAT_VT_MASK) >> LCD_VAT_VT_BIT )
4626 #define __lcd_vat_set_vt(n) \
4627 do { \
4628 REG_LCD_VAT &= ~LCD_VAT_VT_MASK; \
4629 REG_LCD_VAT |= (n) << LCD_VAT_VT_BIT; \
4630 } while (0)
4631
4632 #define __lcd_dah_get_hds() \
4633 ( (REG_LCD_DAH & LCD_DAH_HDS_MASK) >> LCD_DAH_HDS_BIT )
4634 #define __lcd_dah_set_hds(n) \
4635 do { \
4636 REG_LCD_DAH &= ~LCD_DAH_HDS_MASK; \
4637 REG_LCD_DAH |= (n) << LCD_DAH_HDS_BIT; \
4638 } while (0)
4639
4640 #define __lcd_dah_get_hde() \
4641 ( (REG_LCD_DAH & LCD_DAH_HDE_MASK) >> LCD_DAH_HDE_BIT )
4642 #define __lcd_dah_set_hde(n) \
4643 do { \
4644 REG_LCD_DAH &= ~LCD_DAH_HDE_MASK; \
4645 REG_LCD_DAH |= (n) << LCD_DAH_HDE_BIT; \
4646 } while (0)
4647
4648 #define __lcd_dav_get_vds() \
4649 ( (REG_LCD_DAV & LCD_DAV_VDS_MASK) >> LCD_DAV_VDS_BIT )
4650 #define __lcd_dav_set_vds(n) \
4651 do { \
4652 REG_LCD_DAV &= ~LCD_DAV_VDS_MASK; \
4653 REG_LCD_DAV |= (n) << LCD_DAV_VDS_BIT; \
4654 } while (0)
4655
4656 #define __lcd_dav_get_vde() \
4657 ( (REG_LCD_DAV & LCD_DAV_VDE_MASK) >> LCD_DAV_VDE_BIT )
4658 #define __lcd_dav_set_vde(n) \
4659 do { \
4660 REG_LCD_DAV &= ~LCD_DAV_VDE_MASK; \
4661 REG_LCD_DAV |= (n) << LCD_DAV_VDE_BIT; \
4662 } while (0)
4663
4664 #define __lcd_cmd0_set_sofint() ( REG_LCD_CMD0 |= LCD_CMD_SOFINT )
4665 #define __lcd_cmd0_clr_sofint() ( REG_LCD_CMD0 &= ~LCD_CMD_SOFINT )
4666 #define __lcd_cmd1_set_sofint() ( REG_LCD_CMD1 |= LCD_CMD_SOFINT )
4667 #define __lcd_cmd1_clr_sofint() ( REG_LCD_CMD1 &= ~LCD_CMD_SOFINT )
4668
4669 #define __lcd_cmd0_set_eofint() ( REG_LCD_CMD0 |= LCD_CMD_EOFINT )
4670 #define __lcd_cmd0_clr_eofint() ( REG_LCD_CMD0 &= ~LCD_CMD_EOFINT )
4671 #define __lcd_cmd1_set_eofint() ( REG_LCD_CMD1 |= LCD_CMD_EOFINT )
4672 #define __lcd_cmd1_clr_eofint() ( REG_LCD_CMD1 &= ~LCD_CMD_EOFINT )
4673
4674 #define __lcd_cmd0_set_pal() ( REG_LCD_CMD0 |= LCD_CMD_PAL )
4675 #define __lcd_cmd0_clr_pal() ( REG_LCD_CMD0 &= ~LCD_CMD_PAL )
4676
4677 #define __lcd_cmd0_get_len() \
4678 ( (REG_LCD_CMD0 & LCD_CMD_LEN_MASK) >> LCD_CMD_LEN_BIT )
4679 #define __lcd_cmd1_get_len() \
4680 ( (REG_LCD_CMD1 & LCD_CMD_LEN_MASK) >> LCD_CMD_LEN_BIT )
4681
4682 /***************************************************************************
4683 * RTC ops
4684 ***************************************************************************/
4685
4686 #define __rtc_write_ready() ( REG_RTC_RCR & RTC_RCR_WRDY )
4687 #define __rtc_enabled() \
4688 do{ \
4689 while(!__rtc_write_ready()); \
4690 REG_RTC_RCR |= RTC_RCR_RTCE ; \
4691 }while(0) \
4692
4693 #define __rtc_disabled() \
4694 do{ \
4695 while(!__rtc_write_ready()); \
4696 REG_RTC_RCR &= ~RTC_RCR_RTCE; \
4697 }while(0)
4698 #define __rtc_enable_alarm() \
4699 do{ \
4700 while(!__rtc_write_ready()); \
4701 REG_RTC_RCR |= RTC_RCR_AE; \
4702 }while(0)
4703
4704 #define __rtc_disable_alarm() \
4705 do{ \
4706 while(!__rtc_write_ready()); \
4707 REG_RTC_RCR &= ~RTC_RCR_AE; \
4708 }while(0)
4709
4710 #define __rtc_enable_alarm_irq() \
4711 do{ \
4712 while(!__rtc_write_ready()); \
4713 REG_RTC_RCR |= RTC_RCR_AIE; \
4714 }while(0)
4715
4716 #define __rtc_disable_alarm_irq() \
4717 do{ \
4718 while(!__rtc_write_ready()); \
4719 REG_RTC_RCR &= ~RTC_RCR_AIE; \
4720 }while(0)
4721 #define __rtc_enable_Hz_irq() \
4722 do{ \
4723 while(!__rtc_write_ready()); \
4724 REG_RTC_RCR |= RTC_RCR_HZIE; \
4725 }while(0)
4726
4727 #define __rtc_disable_Hz_irq() \
4728 do{ \
4729 while(!__rtc_write_ready()); \
4730 REG_RTC_RCR &= ~RTC_RCR_HZIE; \
4731 }while(0)
4732 #define __rtc_get_1Hz_flag() \
4733 do{ \
4734 while(!__rtc_write_ready()); \
4735 ((REG_RTC_RCR >> RTC_RCR_HZ) & 0x1); \
4736 }while(0)
4737 #define __rtc_clear_1Hz_flag() \
4738 do{ \
4739 while(!__rtc_write_ready()); \
4740 REG_RTC_RCR &= ~RTC_RCR_HZ; \
4741 }while(0)
4742 #define __rtc_get_alarm_flag() \
4743 do{ \
4744 while(!__rtc_write_ready()); \
4745 ((REG_RTC_RCR >> RTC_RCR_AF) & 0x1) \
4746 while(0)
4747 #define __rtc_clear_alarm_flag() \
4748 do{ \
4749 while(!__rtc_write_ready()); \
4750 REG_RTC_RCR &= ~RTC_RCR_AF; \
4751 }while(0)
4752 #define __rtc_get_second() \
4753 do{ \
4754 while(!__rtc_write_ready());\
4755 REG_RTC_RSR; \
4756 }while(0)
4757
4758 #define __rtc_set_second(v) \
4759 do{ \
4760 while(!__rtc_write_ready()); \
4761 REG_RTC_RSR = v; \
4762 }while(0)
4763
4764 #define __rtc_get_alarm_second() \
4765 do{ \
4766 while(!__rtc_write_ready()); \
4767 REG_RTC_RSAR; \
4768 }while(0)
4769
4770
4771 #define __rtc_set_alarm_second(v) \
4772 do{ \
4773 while(!__rtc_write_ready()); \
4774 REG_RTC_RSAR = v; \
4775 }while(0)
4776
4777 #define __rtc_RGR_is_locked() \
4778 do{ \
4779 while(!__rtc_write_ready()); \
4780 REG_RTC_RGR >> RTC_RGR_LOCK; \
4781 }while(0)
4782 #define __rtc_lock_RGR() \
4783 do{ \
4784 while(!__rtc_write_ready()); \
4785 REG_RTC_RGR |= RTC_RGR_LOCK; \
4786 }while(0)
4787
4788 #define __rtc_unlock_RGR() \
4789 do{ \
4790 while(!__rtc_write_ready()); \
4791 REG_RTC_RGR &= ~RTC_RGR_LOCK; \
4792 }while(0)
4793
4794 #define __rtc_get_adjc_val() \
4795 do{ \
4796 while(!__rtc_write_ready()); \
4797 ( (REG_RTC_RGR & RTC_RGR_ADJC_MASK) >> RTC_RGR_ADJC_BIT ); \
4798 }while(0)
4799 #define __rtc_set_adjc_val(v) \
4800 do{ \
4801 while(!__rtc_write_ready()); \
4802 ( REG_RTC_RGR = ( (REG_RTC_RGR & ~RTC_RGR_ADJC_MASK) | (v << RTC_RGR_ADJC_BIT) )) \
4803 }while(0)
4804
4805 #define __rtc_get_nc1Hz_val() \
4806 while(!__rtc_write_ready()); \
4807 ( (REG_RTC_RGR & RTC_RGR_NC1HZ_MASK) >> RTC_RGR_NC1HZ_BIT )
4808
4809 #define __rtc_set_nc1Hz_val(v) \
4810 do{ \
4811 while(!__rtc_write_ready()); \
4812 ( REG_RTC_RGR = ( (REG_RTC_RGR & ~RTC_RGR_NC1HZ_MASK) | (v << RTC_RGR_NC1HZ_BIT) )) \
4813 }while(0)
4814 #define __rtc_power_down() \
4815 do{ \
4816 while(!__rtc_write_ready()); \
4817 REG_RTC_HCR |= RTC_HCR_PD; \
4818 }while(0)
4819
4820 #define __rtc_get_hwfcr_val() \
4821 do{ \
4822 while(!__rtc_write_ready()); \
4823 REG_RTC_HWFCR & RTC_HWFCR_MASK; \
4824 }while(0)
4825 #define __rtc_set_hwfcr_val(v) \
4826 do{ \
4827 while(!__rtc_write_ready()); \
4828 REG_RTC_HWFCR = (v) & RTC_HWFCR_MASK; \
4829 }while(0)
4830
4831 #define __rtc_get_hrcr_val() \
4832 do{ \
4833 while(!__rtc_write_ready()); \
4834 ( REG_RTC_HRCR & RTC_HRCR_MASK ); \
4835 }while(0)
4836 #define __rtc_set_hrcr_val(v) \
4837 do{ \
4838 while(!__rtc_write_ready()); \
4839 ( REG_RTC_HRCR = (v) & RTC_HRCR_MASK ); \
4840 }while(0)
4841
4842 #define __rtc_enable_alarm_wakeup() \
4843 do{ \
4844 while(!__rtc_write_ready()); \
4845 ( REG_RTC_HWCR |= RTC_HWCR_EALM ); \
4846 }while(0)
4847
4848 #define __rtc_disable_alarm_wakeup() \
4849 do{ \
4850 while(!__rtc_write_ready()); \
4851 ( REG_RTC_HWCR &= ~RTC_HWCR_EALM ); \
4852 }while(0)
4853
4854 #define __rtc_status_hib_reset_occur() \
4855 do{ \
4856 while(!__rtc_write_ready()); \
4857 ( (REG_RTC_HWRSR >> RTC_HWRSR_HR) & 0x1 ); \
4858 }while(0)
4859 #define __rtc_status_ppr_reset_occur() \
4860 do{ \
4861 while(!__rtc_write_ready()); \
4862 ( (REG_RTC_HWRSR >> RTC_HWRSR_PPR) & 0x1 ); \
4863 }while(0)
4864 #define __rtc_status_wakeup_pin_waken_up() \
4865 do{ \
4866 while(!__rtc_write_ready()); \
4867 ( (REG_RTC_HWRSR >> RTC_HWRSR_PIN) & 0x1 ); \
4868 }while(0)
4869 #define __rtc_status_alarm_waken_up() \
4870 do{ \
4871 while(!__rtc_write_ready()); \
4872 ( (REG_RTC_HWRSR >> RTC_HWRSR_ALM) & 0x1 ); \
4873 }while(0)
4874 #define __rtc_clear_hib_stat_all() \
4875 do{ \
4876 while(!__rtc_write_ready()); \
4877 ( REG_RTC_HWRSR = 0 ); \
4878 }while(0)
4879
4880 #define __rtc_get_scratch_pattern() \
4881 while(!__rtc_write_ready()); \
4882 (REG_RTC_HSPR)
4883 #define __rtc_set_scratch_pattern(n) \
4884 do{ \
4885 while(!__rtc_write_ready()); \
4886 (REG_RTC_HSPR = n ); \
4887 }while(0)
4888
4889
4890 #endif /* !__ASSEMBLY__ */
4891
4892 #endif /* __JZ4740_H__ */
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