target/linux/brcm47xx/patches-2.6.28/250-ohci-ssb-usb2.patch

   1 diff --git a/drivers/usb/host/ohci-ssb.c b/drivers/usb/host/ohci-ssb.c
   2 --- a/drivers/usb/host/ohci-ssb.c
   3 +++ b/drivers/usb/host/ohci-ssb.c
   4 @@ -106,10 +106,59 @@ static int ssb_ohci_attach(struct ssb_device *dev)
   5         int err = -ENOMEM;
   6         u32 tmp, flags = 0;
   7
   8 -       if (dev->id.coreid == SSB_DEV_USB11_HOSTDEV)
   9 +       /*
  10 +        * THE FOLLOWING COMMENTS PRESERVED FROM GPL SOURCE RELEASE
  11 +        *
  12 +        * The USB core requires a special bit to be set during core
  13 +        * reset to enable host (OHCI) mode. Resetting the SB core in
  14 +        * pcibios_enable_device() is a hack for compatibility with
  15 +        * vanilla usb-ohci so that it does not have to know about
  16 +        * SB. A driver that wants to use the USB core in device mode
  17 +        * should know about SB and should reset the bit back to 0
  18 +        * after calling pcibios_enable_device().
  19 +        */
  20 +
  21 +       if (dev->id.coreid == SSB_DEV_USB11_HOSTDEV) {
  22                 flags |= SSB_OHCI_TMSLOW_HOSTMODE;
  23 +               ssb_device_enable(dev, flags);
  24 +       }
  25 +
  26 +       /*
  27 +        * USB 2.0 special considerations:
  28 +        *
  29 +        * 1. Since the core supports both OHCI and EHCI functions, it must
  30 +        *    only be reset once.
  31 +        *
  32 +        * 2. In addition to the standard SB reset sequence, the Host Control
  33 +        *    Register must be programmed to bring the USB core and various
  34 +        *    phy components out of reset.
  35 +        */
  36 +
  37 +       else if (dev->id.coreid == SSB_DEV_USB20_HOST) {
  38 +#warning FIX ME need test for core being up & exit
  39 +               ssb_device_enable(dev, 0);
  40 +               ssb_write32(dev, 0x200, 0x7ff);
  41 +               udelay(1);
  42 +               if (dev->id.revision == 1) { // bug in rev 1
  43 +
  44 +                       /* Change Flush control reg */
  45 +                       tmp = ssb_read32(dev, 0x400);
  46 +                       tmp &= ~8;
  47 +                       ssb_write32(dev, 0x400, tmp);
  48 +                       tmp = ssb_read32(dev, 0x400);
  49 +                       printk("USB20H fcr: 0x%0x\n", tmp);
  50 +
  51 +                       /* Change Shim control reg */
  52 +                       tmp = ssb_read32(dev, 0x304);
  53 +                       tmp &= ~0x100;
  54 +                       ssb_write32(dev, 0x304, tmp);
  55 +                       tmp = ssb_read32(dev, 0x304);
  56 +                       printk("USB20H shim: 0x%0x\n", tmp);
  57 +               }
  58 +       }
  59 +       else
  60 +               ssb_device_enable(dev, 0);
  61
  62 -       ssb_device_enable(dev, flags);
  63
  64         hcd = usb_create_hcd(&ssb_ohci_hc_driver, dev->dev,
  65                         dev_name(dev->dev));
  66 @@ -200,6 +249,7 @@ static int ssb_ohci_resume(struct ssb_device *dev)
  67  static const struct ssb_device_id ssb_ohci_table[] = {
  68         SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_USB11_HOSTDEV, SSB_ANY_REV),
  69         SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_USB11_HOST, SSB_ANY_REV),
  70 +       SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_USB20_HOST, SSB_ANY_REV),
  71         SSB_DEVTABLE_END
  72  };
  73  MODULE_DEVICE_TABLE(ssb, ssb_ohci_table);