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ramips: register gpio buttons on the DIR-300 revB board
[openwrt.git] / target / linux / xburst / patches-2.6.32 / 001-core.patch
1 From 42789dfb077bb7b640ee19d0e3f7808dc5318adf Mon Sep 17 00:00:00 2001
2 From: Lars-Peter Clausen <lars@metafoo.de>
3 Date: Mon, 11 Jan 2010 04:29:35 +0100
4 Subject: [PATCH] /opt/Projects/openwrt/target/linux/xburst/patches-2.6.31/001-core.patch
5
6 ---
7 arch/mips/Kconfig | 29 ++++
8 arch/mips/Makefile | 18 +++
9 arch/mips/boot/Makefile | 23 +++-
10 arch/mips/include/asm/bootinfo.h | 6 +
11 arch/mips/include/asm/cpu.h | 13 ++-
12 arch/mips/include/asm/mach-generic/irq.h | 2 +-
13 arch/mips/include/asm/r4kcache.h | 231 ++++++++++++++++++++++++++++++
14 arch/mips/include/asm/suspend.h | 3 +
15 arch/mips/kernel/cpu-probe.c | 21 +++
16 arch/mips/mm/c-r4k.c | 30 ++++
17 arch/mips/mm/cache.c | 2 +
18 arch/mips/mm/tlbex.c | 5 +
19 12 files changed, 379 insertions(+), 4 deletions(-)
20
21 --- a/arch/mips/Kconfig
22 +++ b/arch/mips/Kconfig
23 @@ -174,6 +174,9 @@ config MACH_JAZZ
24 Members include the Acer PICA, MIPS Magnum 4000, MIPS Millennium and
25 Olivetti M700-10 workstations.
26
27 +config MACH_JZ
28 + bool "Ingenic JZ4720/JZ4740 based machines"
29 +
30 config LASAT
31 bool "LASAT Networks platforms"
32 select CEVT_R4K
33 @@ -677,6 +680,7 @@ source "arch/mips/alchemy/Kconfig"
34 source "arch/mips/basler/excite/Kconfig"
35 source "arch/mips/bcm63xx/Kconfig"
36 source "arch/mips/jazz/Kconfig"
37 +source "arch/mips/jz4740/Kconfig"
38 source "arch/mips/lasat/Kconfig"
39 source "arch/mips/pmc-sierra/Kconfig"
40 source "arch/mips/sgi-ip27/Kconfig"
41 @@ -1913,6 +1917,14 @@ config NR_CPUS
42
43 source "kernel/time/Kconfig"
44
45 +# the value of (max order + 1)
46 +config FORCE_MAX_ZONEORDER
47 + prompt "MAX_ZONEORDER"
48 + int
49 + default "12"
50 + help
51 + The max memory that can be allocated = 4KB * 2^(CONFIG_FORCE_MAX_ZONEORDER - 1)
52 +
53 #
54 # Timer Interrupt Frequency Configuration
55 #
56 --- a/arch/mips/Makefile
57 +++ b/arch/mips/Makefile
58 @@ -184,6 +184,14 @@ cflags-$(CONFIG_AR7) += -I$(srctree)/ar
59 load-$(CONFIG_AR7) += 0xffffffff94100000
60
61 #
62 +# Commond Ingenic JZ4740 series
63 +#
64 +
65 +core-$(CONFIG_SOC_JZ4740) += arch/mips/jz4740/
66 +cflags-$(CONFIG_SOC_JZ4740) += -I$(srctree)/arch/mips/include/asm/mach-jz4740
67 +load-$(CONFIG_SOC_JZ4740) += 0xffffffff80010000
68 +
69 +#
70 # Acer PICA 61, Mips Magnum 4000 and Olivetti M700.
71 #
72 core-$(CONFIG_MACH_JAZZ) += arch/mips/jazz/
73 @@ -705,6 +713,12 @@ makeboot =$(Q)$(MAKE) $(build)=arch/mips
74
75 all: $(all-y)
76
77 +uImage: $(vmlinux-32)
78 + +@$(call makeboot,$@)
79 +
80 +zImage: $(vmlinux-32)
81 + +@$(call makeboot,$@)
82 +
83 vmlinux.bin: $(vmlinux-32)
84 +@$(call makeboot,$@)
85
86 @@ -734,6 +748,7 @@ install:
87
88 archclean:
89 @$(MAKE) $(clean)=arch/mips/boot
90 + @$(MAKE) $(clean)=arch/mips/boot/compressed
91 @$(MAKE) $(clean)=arch/mips/lasat
92
93 define archhelp
94 @@ -741,6 +756,9 @@ define archhelp
95 echo ' vmlinux.ecoff - ECOFF boot image'
96 echo ' vmlinux.bin - Raw binary boot image'
97 echo ' vmlinux.srec - SREC boot image'
98 + echo ' uImage - u-boot format image (arch/$(ARCH)/boot/uImage)'
99 + echo ' zImage - Compressed binary image (arch/$(ARCH)/boot/compressed/zImage)'
100 + echo ' vmlinux.bin - Uncompressed binary image (arch/$(ARCH)/boot/vmlinux.bin)'
101 echo
102 echo ' These will be default as apropriate for a configured platform.'
103 endef
104 --- a/arch/mips/boot/Makefile
105 +++ b/arch/mips/boot/Makefile
106 @@ -7,6 +7,9 @@
107 # Copyright (C) 2004 Maciej W. Rozycki
108 #
109
110 +# This one must match the LOADADDR in arch/mips/Makefile!
111 +LOADADDR=0x80010000
112 +
113 #
114 # Some DECstations need all possible sections of an ECOFF executable
115 #
116 @@ -25,7 +28,7 @@ strip-flags = $(addprefix --remove-secti
117
118 VMLINUX = vmlinux
119
120 -all: vmlinux.ecoff vmlinux.srec addinitrd
121 +all: vmlinux.ecoff vmlinux.srec addinitrd uImage zImage
122
123 vmlinux.ecoff: $(obj)/elf2ecoff $(VMLINUX)
124 $(obj)/elf2ecoff $(VMLINUX) vmlinux.ecoff $(E2EFLAGS)
125 @@ -42,8 +45,24 @@ vmlinux.srec: $(VMLINUX)
126 $(obj)/addinitrd: $(obj)/addinitrd.c
127 $(HOSTCC) -o $@ $^
128
129 +uImage: $(VMLINUX) vmlinux.bin
130 + rm -f $(obj)/vmlinux.bin.gz
131 + gzip -9 $(obj)/vmlinux.bin
132 + mkimage -A mips -O linux -T kernel -C gzip \
133 + -a $(LOADADDR) -e $(shell sh ./$(obj)/tools/entry $(NM) $(VMLINUX) ) \
134 + -n 'Linux-$(KERNELRELEASE)' \
135 + -d $(obj)/vmlinux.bin.gz $(obj)/uImage
136 + @echo ' Kernel: arch/mips/boot/$@ is ready'
137 +
138 +zImage:
139 + $(Q)$(MAKE) $(build)=$(obj)/compressed loadaddr=$(LOADADDR) $@
140 + @echo ' Kernel: arch/mips/boot/compressed/$@ is ready'
141 +
142 clean-files += addinitrd \
143 elf2ecoff \
144 vmlinux.bin \
145 vmlinux.ecoff \
146 - vmlinux.srec
147 + vmlinux.srec \
148 + vmlinux.bin.gz \
149 + uImage \
150 + zImage
151 --- a/arch/mips/include/asm/bootinfo.h
152 +++ b/arch/mips/include/asm/bootinfo.h
153 @@ -69,6 +69,12 @@
154 #define MACH_DEXXON_GDIUM2F10 5
155 #define MACH_LOONGSON_END 6
156
157 +/*
158 + * Valid machtype for group INGENIC
159 + */
160 +#define MACH_INGENIC_JZ4720 0 /* JZ4730 SOC */
161 +#define MACH_INGENIC_JZ4740 1 /* JZ4740 SOC */
162 +
163 #define CL_SIZE COMMAND_LINE_SIZE
164
165 extern char *system_type;
166 --- a/arch/mips/include/asm/cpu.h
167 +++ b/arch/mips/include/asm/cpu.h
168 @@ -34,7 +34,7 @@
169 #define PRID_COMP_LSI 0x080000
170 #define PRID_COMP_LEXRA 0x0b0000
171 #define PRID_COMP_CAVIUM 0x0d0000
172 -
173 +#define PRID_COMP_INGENIC 0xd00000
174
175 /*
176 * Assigned values for the product ID register. In order to detect a
177 @@ -133,6 +133,12 @@
178 #define PRID_IMP_CAVIUM_CN52XX 0x0700
179
180 /*
181 + * These are the PRID's for when 23:16 == PRID_COMP_INGENIC
182 + */
183 +
184 +#define PRID_IMP_JZRISC 0x0200
185 +
186 +/*
187 * Definitions for 7:0 on legacy processors
188 */
189
190 @@ -224,6 +230,11 @@ enum cpu_type_enum {
191 CPU_5KC, CPU_20KC, CPU_25KF, CPU_SB1, CPU_SB1A, CPU_LOONGSON2,
192 CPU_CAVIUM_OCTEON,
193
194 + /*
195 + * Ingenic class processors
196 + */
197 + CPU_JZRISC, CPU_XBURST,
198 +
199 CPU_LAST
200 };
201
202 --- a/arch/mips/include/asm/mach-generic/irq.h
203 +++ b/arch/mips/include/asm/mach-generic/irq.h
204 @@ -9,7 +9,7 @@
205 #define __ASM_MACH_GENERIC_IRQ_H
206
207 #ifndef NR_IRQS
208 -#define NR_IRQS 128
209 +#define NR_IRQS 256
210 #endif
211
212 #ifdef CONFIG_I8259
213 --- a/arch/mips/include/asm/r4kcache.h
214 +++ b/arch/mips/include/asm/r4kcache.h
215 @@ -17,6 +17,58 @@
216 #include <asm/cpu-features.h>
217 #include <asm/mipsmtregs.h>
218
219 +#ifdef CONFIG_JZRISC
220 +
221 +#define K0_TO_K1() \
222 +do { \
223 + unsigned long __k0_addr; \
224 + \
225 + __asm__ __volatile__( \
226 + "la %0, 1f\n\t" \
227 + "or %0, %0, %1\n\t" \
228 + "jr %0\n\t" \
229 + "nop\n\t" \
230 + "1: nop\n" \
231 + : "=&r"(__k0_addr) \
232 + : "r" (0x20000000) ); \
233 +} while(0)
234 +
235 +#define K1_TO_K0() \
236 +do { \
237 + unsigned long __k0_addr; \
238 + __asm__ __volatile__( \
239 + "nop;nop;nop;nop;nop;nop;nop\n\t" \
240 + "la %0, 1f\n\t" \
241 + "jr %0\n\t" \
242 + "nop\n\t" \
243 + "1: nop\n" \
244 + : "=&r" (__k0_addr)); \
245 +} while (0)
246 +
247 +#define INVALIDATE_BTB() \
248 +do { \
249 + unsigned long tmp; \
250 + __asm__ __volatile__( \
251 + ".set mips32\n\t" \
252 + "mfc0 %0, $16, 7\n\t" \
253 + "nop\n\t" \
254 + "ori %0, 2\n\t" \
255 + "mtc0 %0, $16, 7\n\t" \
256 + "nop\n\t" \
257 + : "=&r" (tmp)); \
258 +} while (0)
259 +
260 +#define SYNC_WB() __asm__ __volatile__ ("sync")
261 +
262 +#else /* CONFIG_JZRISC */
263 +
264 +#define K0_TO_K1() do { } while (0)
265 +#define K1_TO_K0() do { } while (0)
266 +#define INVALIDATE_BTB() do { } while (0)
267 +#define SYNC_WB() do { } while (0)
268 +
269 +#endif /* CONFIG_JZRISC */
270 +
271 /*
272 * This macro return a properly sign-extended address suitable as base address
273 * for indexed cache operations. Two issues here:
274 @@ -144,6 +196,7 @@ static inline void flush_icache_line_ind
275 {
276 __iflush_prologue
277 cache_op(Index_Invalidate_I, addr);
278 + INVALIDATE_BTB();
279 __iflush_epilogue
280 }
281
282 @@ -151,6 +204,7 @@ static inline void flush_dcache_line_ind
283 {
284 __dflush_prologue
285 cache_op(Index_Writeback_Inv_D, addr);
286 + SYNC_WB();
287 __dflush_epilogue
288 }
289
290 @@ -163,6 +217,7 @@ static inline void flush_icache_line(uns
291 {
292 __iflush_prologue
293 cache_op(Hit_Invalidate_I, addr);
294 + INVALIDATE_BTB();
295 __iflush_epilogue
296 }
297
298 @@ -170,6 +225,7 @@ static inline void flush_dcache_line(uns
299 {
300 __dflush_prologue
301 cache_op(Hit_Writeback_Inv_D, addr);
302 + SYNC_WB();
303 __dflush_epilogue
304 }
305
306 @@ -177,6 +233,7 @@ static inline void invalidate_dcache_lin
307 {
308 __dflush_prologue
309 cache_op(Hit_Invalidate_D, addr);
310 + SYNC_WB();
311 __dflush_epilogue
312 }
313
314 @@ -209,6 +266,7 @@ static inline void flush_scache_line(uns
315 static inline void protected_flush_icache_line(unsigned long addr)
316 {
317 protected_cache_op(Hit_Invalidate_I, addr);
318 + INVALIDATE_BTB();
319 }
320
321 /*
322 @@ -220,6 +278,7 @@ static inline void protected_flush_icach
323 static inline void protected_writeback_dcache_line(unsigned long addr)
324 {
325 protected_cache_op(Hit_Writeback_Inv_D, addr);
326 + SYNC_WB();
327 }
328
329 static inline void protected_writeback_scache_line(unsigned long addr)
330 @@ -396,8 +455,10 @@ static inline void blast_##pfx##cache##l
331 __BUILD_BLAST_CACHE(d, dcache, Index_Writeback_Inv_D, Hit_Writeback_Inv_D, 16)
332 __BUILD_BLAST_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 16)
333 __BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 16)
334 +#ifndef CONFIG_JZRISC
335 __BUILD_BLAST_CACHE(d, dcache, Index_Writeback_Inv_D, Hit_Writeback_Inv_D, 32)
336 __BUILD_BLAST_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 32)
337 +#endif
338 __BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 32)
339 __BUILD_BLAST_CACHE(d, dcache, Index_Writeback_Inv_D, Hit_Writeback_Inv_D, 64)
340 __BUILD_BLAST_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 64)
341 @@ -405,12 +466,122 @@ __BUILD_BLAST_CACHE(s, scache, Index_Wri
342 __BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 128)
343
344 __BUILD_BLAST_CACHE(inv_d, dcache, Index_Writeback_Inv_D, Hit_Invalidate_D, 16)
345 +#ifndef CONFIG_JZRISC
346 __BUILD_BLAST_CACHE(inv_d, dcache, Index_Writeback_Inv_D, Hit_Invalidate_D, 32)
347 +#endif
348 __BUILD_BLAST_CACHE(inv_s, scache, Index_Writeback_Inv_SD, Hit_Invalidate_SD, 16)
349 __BUILD_BLAST_CACHE(inv_s, scache, Index_Writeback_Inv_SD, Hit_Invalidate_SD, 32)
350 __BUILD_BLAST_CACHE(inv_s, scache, Index_Writeback_Inv_SD, Hit_Invalidate_SD, 64)
351 __BUILD_BLAST_CACHE(inv_s, scache, Index_Writeback_Inv_SD, Hit_Invalidate_SD, 128)
352
353 +#ifdef CONFIG_JZRISC
354 +
355 +static inline void blast_dcache32(void)
356 +{
357 + unsigned long start = INDEX_BASE;
358 + unsigned long end = start + current_cpu_data.dcache.waysize;
359 + unsigned long ws_inc = 1UL << current_cpu_data.dcache.waybit;
360 + unsigned long ws_end = current_cpu_data.dcache.ways <<
361 + current_cpu_data.dcache.waybit;
362 + unsigned long ws, addr;
363 +
364 + for (ws = 0; ws < ws_end; ws += ws_inc)
365 + for (addr = start; addr < end; addr += 0x400)
366 + cache32_unroll32(addr|ws,Index_Writeback_Inv_D);
367 +
368 + SYNC_WB();
369 +}
370 +
371 +static inline void blast_dcache32_page(unsigned long page)
372 +{
373 + unsigned long start = page;
374 + unsigned long end = page + PAGE_SIZE;
375 +
376 + do {
377 + cache32_unroll32(start,Hit_Writeback_Inv_D);
378 + start += 0x400;
379 + } while (start < end);
380 +
381 + SYNC_WB();
382 +}
383 +
384 +static inline void blast_dcache32_page_indexed(unsigned long page)
385 +{
386 + unsigned long indexmask = current_cpu_data.dcache.waysize - 1;
387 + unsigned long start = INDEX_BASE + (page & indexmask);
388 + unsigned long end = start + PAGE_SIZE;
389 + unsigned long ws_inc = 1UL << current_cpu_data.dcache.waybit;
390 + unsigned long ws_end = current_cpu_data.dcache.ways <<
391 + current_cpu_data.dcache.waybit;
392 + unsigned long ws, addr;
393 +
394 + for (ws = 0; ws < ws_end; ws += ws_inc)
395 + for (addr = start; addr < end; addr += 0x400)
396 + cache32_unroll32(addr|ws,Index_Writeback_Inv_D);
397 +
398 + SYNC_WB();
399 +}
400 +
401 +static inline void blast_icache32(void)
402 +{
403 + unsigned long start = INDEX_BASE;
404 + unsigned long end = start + current_cpu_data.icache.waysize;
405 + unsigned long ws_inc = 1UL << current_cpu_data.icache.waybit;
406 + unsigned long ws_end = current_cpu_data.icache.ways <<
407 + current_cpu_data.icache.waybit;
408 + unsigned long ws, addr;
409 +
410 + K0_TO_K1();
411 +
412 + for (ws = 0; ws < ws_end; ws += ws_inc)
413 + for (addr = start; addr < end; addr += 0x400)
414 + cache32_unroll32(addr|ws,Index_Invalidate_I);
415 +
416 + INVALIDATE_BTB();
417 +
418 + K1_TO_K0();
419 +}
420 +
421 +static inline void blast_icache32_page(unsigned long page)
422 +{
423 + unsigned long start = page;
424 + unsigned long end = page + PAGE_SIZE;
425 +
426 + K0_TO_K1();
427 +
428 + do {
429 + cache32_unroll32(start,Hit_Invalidate_I);
430 + start += 0x400;
431 + } while (start < end);
432 +
433 + INVALIDATE_BTB();
434 +
435 + K1_TO_K0();
436 +}
437 +
438 +static inline void blast_icache32_page_indexed(unsigned long page)
439 +{
440 + unsigned long indexmask = current_cpu_data.icache.waysize - 1;
441 + unsigned long start = INDEX_BASE + (page & indexmask);
442 + unsigned long end = start + PAGE_SIZE;
443 + unsigned long ws_inc = 1UL << current_cpu_data.icache.waybit;
444 + unsigned long ws_end = current_cpu_data.icache.ways <<
445 + current_cpu_data.icache.waybit;
446 + unsigned long ws, addr;
447 +
448 + K0_TO_K1();
449 +
450 + for (ws = 0; ws < ws_end; ws += ws_inc)
451 + for (addr = start; addr < end; addr += 0x400)
452 + cache32_unroll32(addr|ws,Index_Invalidate_I);
453 +
454 + INVALIDATE_BTB();
455 +
456 + K1_TO_K0();
457 +}
458 +
459 +#endif /* CONFIG_JZRISC */
460 +
461 /* build blast_xxx_range, protected_blast_xxx_range */
462 #define __BUILD_BLAST_CACHE_RANGE(pfx, desc, hitop, prot) \
463 static inline void prot##blast_##pfx##cache##_range(unsigned long start, \
464 @@ -432,13 +603,73 @@ static inline void prot##blast_##pfx##ca
465 __##pfx##flush_epilogue \
466 }
467
468 +#ifndef CONFIG_JZRISC
469 __BUILD_BLAST_CACHE_RANGE(d, dcache, Hit_Writeback_Inv_D, protected_)
470 +#endif
471 __BUILD_BLAST_CACHE_RANGE(s, scache, Hit_Writeback_Inv_SD, protected_)
472 +#ifndef CONFIG_JZRISC
473 __BUILD_BLAST_CACHE_RANGE(i, icache, Hit_Invalidate_I, protected_)
474 __BUILD_BLAST_CACHE_RANGE(d, dcache, Hit_Writeback_Inv_D, )
475 +#endif
476 __BUILD_BLAST_CACHE_RANGE(s, scache, Hit_Writeback_Inv_SD, )
477 /* blast_inv_dcache_range */
478 __BUILD_BLAST_CACHE_RANGE(inv_d, dcache, Hit_Invalidate_D, )
479 __BUILD_BLAST_CACHE_RANGE(inv_s, scache, Hit_Invalidate_SD, )
480
481 +#ifdef CONFIG_JZRISC
482 +
483 +static inline void protected_blast_dcache_range(unsigned long start,
484 + unsigned long end)
485 +{
486 + unsigned long lsize = cpu_dcache_line_size();
487 + unsigned long addr = start & ~(lsize - 1);
488 + unsigned long aend = (end - 1) & ~(lsize - 1);
489 +
490 + while (1) {
491 + protected_cache_op(Hit_Writeback_Inv_D, addr);
492 + if (addr == aend)
493 + break;
494 + addr += lsize;
495 + }
496 + SYNC_WB();
497 +}
498 +
499 +static inline void protected_blast_icache_range(unsigned long start,
500 + unsigned long end)
501 +{
502 + unsigned long lsize = cpu_icache_line_size();
503 + unsigned long addr = start & ~(lsize - 1);
504 + unsigned long aend = (end - 1) & ~(lsize - 1);
505 +
506 + K0_TO_K1();
507 +
508 + while (1) {
509 + protected_cache_op(Hit_Invalidate_I, addr);
510 + if (addr == aend)
511 + break;
512 + addr += lsize;
513 + }
514 + INVALIDATE_BTB();
515 +
516 + K1_TO_K0();
517 +}
518 +
519 +static inline void blast_dcache_range(unsigned long start,
520 + unsigned long end)
521 +{
522 + unsigned long lsize = cpu_dcache_line_size();
523 + unsigned long addr = start & ~(lsize - 1);
524 + unsigned long aend = (end - 1) & ~(lsize - 1);
525 +
526 + while (1) {
527 + cache_op(Hit_Writeback_Inv_D, addr);
528 + if (addr == aend)
529 + break;
530 + addr += lsize;
531 + }
532 + SYNC_WB();
533 +}
534 +
535 +#endif /* CONFIG_JZRISC */
536 +
537 #endif /* _ASM_R4KCACHE_H */
538 --- a/arch/mips/include/asm/suspend.h
539 +++ b/arch/mips/include/asm/suspend.h
540 @@ -2,6 +2,9 @@
541 #define __ASM_SUSPEND_H
542
543 static inline int arch_prepare_suspend(void) { return 0; }
544 +#if defined(CONFIG_PM) && defined(CONFIG_JZSOC)
545 +extern int jz_pm_init(void);
546 +#endif
547
548 /* References to section boundaries */
549 extern const void __nosave_begin, __nosave_end;
550 --- a/arch/mips/kernel/cpu-probe.c
551 +++ b/arch/mips/kernel/cpu-probe.c
552 @@ -160,6 +160,7 @@ void __init check_wait(void)
553 case CPU_BCM6348:
554 case CPU_BCM6358:
555 case CPU_CAVIUM_OCTEON:
556 + case CPU_JZRISC:
557 cpu_wait = r4k_wait;
558 break;
559
560 @@ -902,6 +903,23 @@ static inline void cpu_probe_cavium(stru
561 }
562 }
563
564 +static inline void cpu_probe_ingenic(struct cpuinfo_mips *c, unsigned int cpu)
565 +{
566 + decode_configs(c);
567 + c->options &= ~MIPS_CPU_COUNTER; /* JZRISC does not implement the CP0 counter. */
568 + switch (c->processor_id & 0xff00) {
569 + case PRID_IMP_JZRISC:
570 + c->cputype = CPU_JZRISC;
571 + c->isa_level = MIPS_CPU_ISA_M32R1;
572 + c->tlbsize = 32;
573 + __cpu_name[cpu] = "Ingenic JZRISC";
574 + break;
575 + default:
576 + panic("Unknown Ingenic Processor ID!");
577 + break;
578 + }
579 +}
580 +
581 const char *__cpu_name[NR_CPUS];
582
583 __cpuinit void cpu_probe(void)
584 @@ -939,6 +957,9 @@ __cpuinit void cpu_probe(void)
585 case PRID_COMP_CAVIUM:
586 cpu_probe_cavium(c, cpu);
587 break;
588 + case PRID_COMP_INGENIC:
589 + cpu_probe_ingenic(c, cpu);
590 + break;
591 }
592
593 BUG_ON(!__cpu_name[cpu]);
594 --- a/arch/mips/mm/c-r4k.c
595 +++ b/arch/mips/mm/c-r4k.c
596 @@ -928,6 +928,36 @@ static void __cpuinit probe_pcache(void)
597 c->dcache.waybit = 0;
598 break;
599
600 + case CPU_JZRISC:
601 + config1 = read_c0_config1();
602 + config1 = (config1 >> 22) & 0x07;
603 + if (config1 == 0x07)
604 + config1 = 10;
605 + else
606 + config1 = config1 + 11;
607 + config1 += 2;
608 + icache_size = (1 << config1);
609 + c->icache.linesz = 32;
610 + c->icache.ways = 4;
611 + c->icache.waybit = __ffs(icache_size / c->icache.ways);
612 +
613 + config1 = read_c0_config1();
614 + config1 = (config1 >> 13) & 0x07;
615 + if (config1 == 0x07)
616 + config1 = 10;
617 + else
618 + config1 = config1 + 11;
619 + config1 += 2;
620 + dcache_size = (1 << config1);
621 + c->dcache.linesz = 32;
622 + c->dcache.ways = 4;
623 + c->dcache.waybit = __ffs(dcache_size / c->dcache.ways);
624 +
625 + c->dcache.flags = 0;
626 + c->options |= MIPS_CPU_PREFETCH;
627 +
628 + break;
629 +
630 default:
631 if (!(config & MIPS_CONF_M))
632 panic("Don't know how to probe P-caches on this cpu.");
633 --- a/arch/mips/mm/cache.c
634 +++ b/arch/mips/mm/cache.c
635 @@ -52,6 +52,8 @@ void (*_dma_cache_wback)(unsigned long s
636 void (*_dma_cache_inv)(unsigned long start, unsigned long size);
637
638 EXPORT_SYMBOL(_dma_cache_wback_inv);
639 +EXPORT_SYMBOL(_dma_cache_wback);
640 +EXPORT_SYMBOL(_dma_cache_inv);
641
642 #endif /* CONFIG_DMA_NONCOHERENT */
643
644 --- a/arch/mips/mm/tlbex.c
645 +++ b/arch/mips/mm/tlbex.c
646 @@ -389,6 +389,11 @@ static void __cpuinit build_tlb_write_en
647 tlbw(p);
648 break;
649
650 + case CPU_JZRISC:
651 + tlbw(p);
652 + uasm_i_nop(p);
653 + break;
654 +
655 default:
656 panic("No TLB refill handler yet (CPU type: %d)",
657 current_cpu_data.cputype);
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