target/linux/lantiq/patches/0014-MIPS-lantiq-adds-xway-spi.patch

   1 From e29263339db41d49d79482c93463c4c0cbe764d7 Mon Sep 17 00:00:00 2001
   2 From: John Crispin <blogic@openwrt.org>
   3 Date: Fri, 30 Sep 2011 14:23:42 +0200
   4 Subject: [PATCH 14/24] MIPS: lantiq: adds xway spi
   5
   6 ---
   7  .../mips/include/asm/mach-lantiq/lantiq_platform.h |    9 +
   8  .../mips/include/asm/mach-lantiq/xway/lantiq_irq.h |    2 +
   9  .../mips/include/asm/mach-lantiq/xway/lantiq_soc.h |    1 +
  10  drivers/spi/Kconfig                                |    8 +
  11  drivers/spi/Makefile                               |    2 +-
  12  drivers/spi/spi-xway.c                             | 1062 ++++++++++++++++++++
  13  6 files changed, 1083 insertions(+), 1 deletions(-)
  14  create mode 100644 drivers/spi/spi-xway.c
  15
  16 --- a/arch/mips/include/asm/mach-lantiq/lantiq_platform.h
  17 +++ b/arch/mips/include/asm/mach-lantiq/lantiq_platform.h
  18 @@ -50,4 +50,13 @@ struct ltq_eth_data {
  19         int mii_mode;
  20  };
  21
  22 +
  23 +struct ltq_spi_platform_data {
  24 +       u16 num_chipselect;
  25 +};
  26 +
  27 +struct ltq_spi_controller_data {
  28 +       unsigned gpio;
  29 +};
  30 +
  31  #endif
  32 --- a/arch/mips/include/asm/mach-lantiq/xway/lantiq_irq.h
  33 +++ b/arch/mips/include/asm/mach-lantiq/xway/lantiq_irq.h
  34 @@ -27,6 +27,8 @@
  35
  36  #define LTQ_SSC_TIR            (INT_NUM_IM0_IRL0 + 15)
  37  #define LTQ_SSC_RIR            (INT_NUM_IM0_IRL0 + 14)
  38 +#define LTQ_SSC_TIR_AR9                (INT_NUM_IM0_IRL0 + 14)
  39 +#define LTQ_SSC_RIR_AR9                (INT_NUM_IM0_IRL0 + 15)
  40  #define LTQ_SSC_EIR            (INT_NUM_IM0_IRL0 + 16)
  41
  42  #define LTQ_MEI_DYING_GASP_INT (INT_NUM_IM1_IRL0 + 21)
  43 --- a/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h
  44 +++ b/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h
  45 @@ -81,6 +81,7 @@
  46
  47  #define PMU_DMA                        0x0020
  48  #define PMU_USB                        0x8041
  49 +#define PMU_SPI                        0x0100
  50  #define PMU_LED                        0x0800
  51  #define PMU_GPT                        0x1000
  52  #define PMU_PPE                        0x2000
  53 --- a/drivers/spi/Kconfig
  54 +++ b/drivers/spi/Kconfig
  55 @@ -393,6 +393,14 @@ config SPI_NUC900
  56         help
  57           SPI driver for Nuvoton NUC900 series ARM SoCs
  58
  59 +config SPI_XWAY
  60 +       tristate "Lantiq XWAY SPI controller"
  61 +       depends on LANTIQ && SOC_TYPE_XWAY
  62 +       select SPI_BITBANG
  63 +       help
  64 +         This driver supports the Lantiq SoC SPI controller in master
  65 +         mode.
  66 +
  67  #
  68  # Add new SPI master controllers in alphabetical order above this line
  69  #
  70 --- a/drivers/spi/Makefile
  71 +++ b/drivers/spi/Makefile
  72 @@ -60,4 +60,5 @@ obj-$(CONFIG_SPI_TLE62X0)             += spi-tle62x
  73  obj-$(CONFIG_SPI_TOPCLIFF_PCH)         += spi-topcliff-pch.o
  74  obj-$(CONFIG_SPI_TXX9)                 += spi-txx9.o
  75  obj-$(CONFIG_SPI_XILINX)               += spi-xilinx.o
  76 +obj-$(CONFIG_SPI_XWAY)                 += spi-xway.o
  77
  78 --- /dev/null
  79 +++ b/drivers/spi/spi-xway.c
  80 @@ -0,0 +1,1062 @@
  81 +/*
  82 + * Lantiq SoC SPI controller
  83 + *
  84 + * Copyright (C) 2011 Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>
  85 + *
  86 + * This program is free software; you can distribute it and/or modify it
  87 + * under the terms of the GNU General Public License (Version 2) as
  88 + * published by the Free Software Foundation.
  89 + */
  90 +
  91 +#include <linux/init.h>
  92 +#include <linux/module.h>
  93 +#include <linux/workqueue.h>
  94 +#include <linux/platform_device.h>
  95 +#include <linux/io.h>
  96 +#include <linux/sched.h>
  97 +#include <linux/delay.h>
  98 +#include <linux/interrupt.h>
  99 +#include <linux/completion.h>
 100 +#include <linux/spinlock.h>
 101 +#include <linux/err.h>
 102 +#include <linux/clk.h>
 103 +#include <linux/gpio.h>
 104 +#include <linux/spi/spi.h>
 105 +#include <linux/spi/spi_bitbang.h>
 106 +
 107 +#include <lantiq_soc.h>
 108 +#include <lantiq_platform.h>
 109 +
 110 +#define LTQ_SPI_CLC            0x00    /* Clock control */
 111 +#define LTQ_SPI_PISEL          0x04    /* Port input select */
 112 +#define LTQ_SPI_ID             0x08    /* Identification */
 113 +#define LTQ_SPI_CON            0x10    /* Control */
 114 +#define LTQ_SPI_STAT           0x14    /* Status */
 115 +#define LTQ_SPI_WHBSTATE       0x18    /* Write HW modified state */
 116 +#define LTQ_SPI_TB             0x20    /* Transmit buffer */
 117 +#define LTQ_SPI_RB             0x24    /* Receive buffer */
 118 +#define LTQ_SPI_RXFCON         0x30    /* Receive FIFO control */
 119 +#define LTQ_SPI_TXFCON         0x34    /* Transmit FIFO control */
 120 +#define LTQ_SPI_FSTAT          0x38    /* FIFO status */
 121 +#define LTQ_SPI_BRT            0x40    /* Baudrate timer */
 122 +#define LTQ_SPI_BRSTAT         0x44    /* Baudrate timer status */
 123 +#define LTQ_SPI_SFCON          0x60    /* Serial frame control */
 124 +#define LTQ_SPI_SFSTAT         0x64    /* Serial frame status */
 125 +#define LTQ_SPI_GPOCON         0x70    /* General purpose output control */
 126 +#define LTQ_SPI_GPOSTAT                0x74    /* General purpose output status */
 127 +#define LTQ_SPI_FGPO           0x78    /* Forced general purpose output */
 128 +#define LTQ_SPI_RXREQ          0x80    /* Receive request */
 129 +#define LTQ_SPI_RXCNT          0x84    /* Receive count */
 130 +#define LTQ_SPI_DMACON         0xEC    /* DMA control */
 131 +#define LTQ_SPI_IRNEN          0xF4    /* Interrupt node enable */
 132 +#define LTQ_SPI_IRNICR         0xF8    /* Interrupt node interrupt capture */
 133 +#define LTQ_SPI_IRNCR          0xFC    /* Interrupt node control */
 134 +
 135 +#define LTQ_SPI_CLC_SMC_SHIFT  16      /* Clock divider for sleep mode */
 136 +#define LTQ_SPI_CLC_SMC_MASK   0xFF
 137 +#define LTQ_SPI_CLC_RMC_SHIFT  8       /* Clock divider for normal run mode */
 138 +#define LTQ_SPI_CLC_RMC_MASK   0xFF
 139 +#define LTQ_SPI_CLC_DISS       BIT(1)  /* Disable status bit */
 140 +#define LTQ_SPI_CLC_DISR       BIT(0)  /* Disable request bit */
 141 +
 142 +#define LTQ_SPI_ID_TXFS_SHIFT  24      /* Implemented TX FIFO size */
 143 +#define LTQ_SPI_ID_TXFS_MASK   0x3F
 144 +#define LTQ_SPI_ID_RXFS_SHIFT  16      /* Implemented RX FIFO size */
 145 +#define LTQ_SPI_ID_RXFS_MASK   0x3F
 146 +#define LTQ_SPI_ID_REV_MASK    0x1F    /* Hardware revision number */
 147 +#define LTQ_SPI_ID_CFG         BIT(5)  /* DMA interface support */
 148 +
 149 +#define LTQ_SPI_CON_BM_SHIFT   16      /* Data width selection */
 150 +#define LTQ_SPI_CON_BM_MASK    0x1F
 151 +#define LTQ_SPI_CON_EM         BIT(24) /* Echo mode */
 152 +#define LTQ_SPI_CON_IDLE       BIT(23) /* Idle bit value */
 153 +#define LTQ_SPI_CON_ENBV       BIT(22) /* Enable byte valid control */
 154 +#define LTQ_SPI_CON_RUEN       BIT(12) /* Receive underflow error enable */
 155 +#define LTQ_SPI_CON_TUEN       BIT(11) /* Transmit underflow error enable */
 156 +#define LTQ_SPI_CON_AEN                BIT(10) /* Abort error enable */
 157 +#define LTQ_SPI_CON_REN                BIT(9)  /* Receive overflow error enable */
 158 +#define LTQ_SPI_CON_TEN                BIT(8)  /* Transmit overflow error enable */
 159 +#define LTQ_SPI_CON_LB         BIT(7)  /* Loopback control */
 160 +#define LTQ_SPI_CON_PO         BIT(6)  /* Clock polarity control */
 161 +#define LTQ_SPI_CON_PH         BIT(5)  /* Clock phase control */
 162 +#define LTQ_SPI_CON_HB         BIT(4)  /* Heading control */
 163 +#define LTQ_SPI_CON_RXOFF      BIT(1)  /* Switch receiver off */
 164 +#define LTQ_SPI_CON_TXOFF      BIT(0)  /* Switch transmitter off */
 165 +
 166 +#define LTQ_SPI_STAT_RXBV_MASK 0x7
 167 +#define LTQ_SPI_STAT_RXBV_SHIFT        28
 168 +#define LTQ_SPI_STAT_BSY       BIT(13) /* Busy flag */
 169 +#define LTQ_SPI_STAT_RUE       BIT(12) /* Receive underflow error flag */
 170 +#define LTQ_SPI_STAT_TUE       BIT(11) /* Transmit underflow error flag */
 171 +#define LTQ_SPI_STAT_AE                BIT(10) /* Abort error flag */
 172 +#define LTQ_SPI_STAT_RE                BIT(9)  /* Receive error flag */
 173 +#define LTQ_SPI_STAT_TE                BIT(8)  /* Transmit error flag */
 174 +#define LTQ_SPI_STAT_MS                BIT(1)  /* Master/slave select bit */
 175 +#define LTQ_SPI_STAT_EN                BIT(0)  /* Enable bit */
 176 +
 177 +#define LTQ_SPI_WHBSTATE_SETTUE        BIT(15) /* Set transmit underflow error flag */
 178 +#define LTQ_SPI_WHBSTATE_SETAE BIT(14) /* Set abort error flag */
 179 +#define LTQ_SPI_WHBSTATE_SETRE BIT(13) /* Set receive error flag */
 180 +#define LTQ_SPI_WHBSTATE_SETTE BIT(12) /* Set transmit error flag */
 181 +#define LTQ_SPI_WHBSTATE_CLRTUE        BIT(11) /* Clear transmit underflow error flag */
 182 +#define LTQ_SPI_WHBSTATE_CLRAE BIT(10) /* Clear abort error flag */
 183 +#define LTQ_SPI_WHBSTATE_CLRRE BIT(9)  /* Clear receive error flag */
 184 +#define LTQ_SPI_WHBSTATE_CLRTE BIT(8)  /* Clear transmit error flag */
 185 +#define LTQ_SPI_WHBSTATE_SETME BIT(7)  /* Set mode error flag */
 186 +#define LTQ_SPI_WHBSTATE_CLRME BIT(6)  /* Clear mode error flag */
 187 +#define LTQ_SPI_WHBSTATE_SETRUE        BIT(5)  /* Set receive underflow error flag */
 188 +#define LTQ_SPI_WHBSTATE_CLRRUE        BIT(4)  /* Clear receive underflow error flag */
 189 +#define LTQ_SPI_WHBSTATE_SETMS BIT(3)  /* Set master select bit */
 190 +#define LTQ_SPI_WHBSTATE_CLRMS BIT(2)  /* Clear master select bit */
 191 +#define LTQ_SPI_WHBSTATE_SETEN BIT(1)  /* Set enable bit (operational mode) */
 192 +#define LTQ_SPI_WHBSTATE_CLREN BIT(0)  /* Clear enable bit (config mode */
 193 +#define LTQ_SPI_WHBSTATE_CLR_ERRORS    0x0F50
 194 +
 195 +#define LTQ_SPI_RXFCON_RXFITL_SHIFT    8       /* FIFO interrupt trigger level */
 196 +#define LTQ_SPI_RXFCON_RXFITL_MASK     0x3F
 197 +#define LTQ_SPI_RXFCON_RXFLU           BIT(1)  /* FIFO flush */
 198 +#define LTQ_SPI_RXFCON_RXFEN           BIT(0)  /* FIFO enable */
 199 +
 200 +#define LTQ_SPI_TXFCON_TXFITL_SHIFT    8       /* FIFO interrupt trigger level */
 201 +#define LTQ_SPI_TXFCON_TXFITL_MASK     0x3F
 202 +#define LTQ_SPI_TXFCON_TXFLU           BIT(1)  /* FIFO flush */
 203 +#define LTQ_SPI_TXFCON_TXFEN           BIT(0)  /* FIFO enable */
 204 +
 205 +#define LTQ_SPI_FSTAT_RXFFL_MASK       0x3f
 206 +#define LTQ_SPI_FSTAT_RXFFL_SHIFT      0
 207 +#define LTQ_SPI_FSTAT_TXFFL_MASK       0x3f
 208 +#define LTQ_SPI_FSTAT_TXFFL_SHIFT      8
 209 +
 210 +#define LTQ_SPI_GPOCON_ISCSBN_SHIFT    8
 211 +#define LTQ_SPI_GPOCON_INVOUTN_SHIFT   0
 212 +
 213 +#define LTQ_SPI_FGPO_SETOUTN_SHIFT     8
 214 +#define LTQ_SPI_FGPO_CLROUTN_SHIFT     0
 215 +
 216 +#define LTQ_SPI_RXREQ_RXCNT_MASK       0xFFFF  /* Receive count value */
 217 +#define LTQ_SPI_RXCNT_TODO_MASK                0xFFFF  /* Recevie to-do value */
 218 +
 219 +#define LTQ_SPI_IRNEN_F                BIT(3)  /* Frame end interrupt request */
 220 +#define LTQ_SPI_IRNEN_E                BIT(2)  /* Error end interrupt request */
 221 +#define LTQ_SPI_IRNEN_T                BIT(1)  /* Transmit end interrupt request */
 222 +#define LTQ_SPI_IRNEN_R                BIT(0)  /* Receive end interrupt request */
 223 +#define LTQ_SPI_IRNEN_ALL      0xF
 224 +
 225 +/* Hard-wired GPIOs used by SPI controller */
 226 +#define LTQ_SPI_GPIO_DI        16
 227 +#define LTQ_SPI_GPIO_DO                17
 228 +#define LTQ_SPI_GPIO_CLK       18
 229 +
 230 +struct ltq_spi {
 231 +       struct spi_bitbang      bitbang;
 232 +       struct completion       done;
 233 +       spinlock_t              lock;
 234 +
 235 +       struct device           *dev;
 236 +       void __iomem            *base;
 237 +       struct clk              *clk;
 238 +
 239 +       int                     status;
 240 +       int                     irq[3];
 241 +
 242 +       const u8                *tx;
 243 +       u8                      *rx;
 244 +       u32                     tx_cnt;
 245 +       u32                     rx_cnt;
 246 +       u32                     len;
 247 +       struct spi_transfer     *curr_transfer;
 248 +
 249 +       u32 (*get_tx) (struct ltq_spi *);
 250 +
 251 +       u16                     txfs;
 252 +       u16                     rxfs;
 253 +       unsigned                dma_support:1;
 254 +       unsigned                cfg_mode:1;
 255 +
 256 +};
 257 +
 258 +struct ltq_spi_controller_state {
 259 +       void (*cs_activate) (struct spi_device *);
 260 +       void (*cs_deactivate) (struct spi_device *);
 261 +};
 262 +
 263 +struct ltq_spi_irq_map {
 264 +       char            *name;
 265 +       irq_handler_t   handler;
 266 +};
 267 +
 268 +struct ltq_spi_cs_gpio_map {
 269 +       unsigned        gpio;
 270 +       unsigned        altsel0;
 271 +       unsigned        altsel1;
 272 +};
 273 +
 274 +static inline struct ltq_spi *ltq_spi_to_hw(struct spi_device *spi)
 275 +{
 276 +       return spi_master_get_devdata(spi->master);
 277 +}
 278 +
 279 +static inline u32 ltq_spi_reg_read(struct ltq_spi *hw, u32 reg)
 280 +{
 281 +       return ioread32be(hw->base + reg);
 282 +}
 283 +
 284 +static inline void ltq_spi_reg_write(struct ltq_spi *hw, u32 val, u32 reg)
 285 +{
 286 +       iowrite32be(val, hw->base + reg);
 287 +}
 288 +
 289 +static inline void ltq_spi_reg_setbit(struct ltq_spi *hw, u32 bits, u32 reg)
 290 +{
 291 +       u32 val;
 292 +
 293 +       val = ltq_spi_reg_read(hw, reg);
 294 +       val |= bits;
 295 +       ltq_spi_reg_write(hw, val, reg);
 296 +}
 297 +
 298 +static inline void ltq_spi_reg_clearbit(struct ltq_spi *hw, u32 bits, u32 reg)
 299 +{
 300 +       u32 val;
 301 +
 302 +       val = ltq_spi_reg_read(hw, reg);
 303 +       val &= ~bits;
 304 +       ltq_spi_reg_write(hw, val, reg);
 305 +}
 306 +
 307 +static void ltq_spi_hw_enable(struct ltq_spi *hw)
 308 +{
 309 +       u32 clc;
 310 +
 311 +       /* Power-up mdule */
 312 +       ltq_pmu_enable(PMU_SPI);
 313 +
 314 +       /*
 315 +        * Set clock divider for run mode to 1 to
 316 +        * run at same frequency as FPI bus
 317 +        */
 318 +       clc = (1 << LTQ_SPI_CLC_RMC_SHIFT);
 319 +       ltq_spi_reg_write(hw, clc, LTQ_SPI_CLC);
 320 +}
 321 +
 322 +static void ltq_spi_hw_disable(struct ltq_spi *hw)
 323 +{
 324 +       /* Set clock divider to 0 and set module disable bit */
 325 +       ltq_spi_reg_write(hw, LTQ_SPI_CLC_DISS, LTQ_SPI_CLC);
 326 +
 327 +       /* Power-down mdule */
 328 +       ltq_pmu_disable(PMU_SPI);
 329 +}
 330 +
 331 +static void ltq_spi_reset_fifos(struct ltq_spi *hw)
 332 +{
 333 +       u32 val;
 334 +
 335 +       /*
 336 +        * Enable and flush FIFOs. Set interrupt trigger level to
 337 +        * half of FIFO count implemented in hardware.
 338 +        */
 339 +       if (hw->txfs > 1) {
 340 +               val = hw->txfs << (LTQ_SPI_TXFCON_TXFITL_SHIFT - 1);
 341 +               val |= LTQ_SPI_TXFCON_TXFEN | LTQ_SPI_TXFCON_TXFLU;
 342 +               ltq_spi_reg_write(hw, val, LTQ_SPI_TXFCON);
 343 +       }
 344 +
 345 +       if (hw->rxfs > 1) {
 346 +               val = hw->rxfs << (LTQ_SPI_RXFCON_RXFITL_SHIFT - 1);
 347 +               val |= LTQ_SPI_RXFCON_RXFEN | LTQ_SPI_RXFCON_RXFLU;
 348 +               ltq_spi_reg_write(hw, val, LTQ_SPI_RXFCON);
 349 +       }
 350 +}
 351 +
 352 +static inline int ltq_spi_wait_ready(struct ltq_spi *hw)
 353 +{
 354 +       u32 stat;
 355 +       unsigned long timeout;
 356 +
 357 +       timeout = jiffies + msecs_to_jiffies(200);
 358 +
 359 +       do {
 360 +               stat = ltq_spi_reg_read(hw, LTQ_SPI_STAT);
 361 +               if (!(stat & LTQ_SPI_STAT_BSY))
 362 +                       return 0;
 363 +
 364 +               cond_resched();
 365 +       } while (!time_after_eq(jiffies, timeout));
 366 +
 367 +       dev_err(hw->dev, "SPI wait ready timed out\n");
 368 +
 369 +       return -ETIMEDOUT;
 370 +}
 371 +
 372 +static void ltq_spi_config_mode_set(struct ltq_spi *hw)
 373 +{
 374 +       if (hw->cfg_mode)
 375 +               return;
 376 +
 377 +       /*
 378 +        * Putting the SPI module in config mode is only safe if no
 379 +        * transfer is in progress as indicated by busy flag STATE.BSY.
 380 +        */
 381 +       if (ltq_spi_wait_ready(hw)) {
 382 +               ltq_spi_reset_fifos(hw);
 383 +               hw->status = -ETIMEDOUT;
 384 +       }
 385 +       ltq_spi_reg_write(hw, LTQ_SPI_WHBSTATE_CLREN, LTQ_SPI_WHBSTATE);
 386 +
 387 +       hw->cfg_mode = 1;
 388 +}
 389 +
 390 +static void ltq_spi_run_mode_set(struct ltq_spi *hw)
 391 +{
 392 +       if (!hw->cfg_mode)
 393 +               return;
 394 +
 395 +       ltq_spi_reg_write(hw, LTQ_SPI_WHBSTATE_SETEN, LTQ_SPI_WHBSTATE);
 396 +
 397 +       hw->cfg_mode = 0;
 398 +}
 399 +
 400 +static u32 ltq_spi_tx_word_u8(struct ltq_spi *hw)
 401 +{
 402 +       const u8 *tx = hw->tx;
 403 +       u32 data = *tx++;
 404 +
 405 +       hw->tx_cnt++;
 406 +       hw->tx++;
 407 +
 408 +       return data;
 409 +}
 410 +
 411 +static u32 ltq_spi_tx_word_u16(struct ltq_spi *hw)
 412 +{
 413 +       const u16 *tx = (u16 *) hw->tx;
 414 +       u32 data = *tx++;
 415 +
 416 +       hw->tx_cnt += 2;
 417 +       hw->tx += 2;
 418 +
 419 +       return data;
 420 +}
 421 +
 422 +static u32 ltq_spi_tx_word_u32(struct ltq_spi *hw)
 423 +{
 424 +       const u32 *tx = (u32 *) hw->tx;
 425 +       u32 data = *tx++;
 426 +
 427 +       hw->tx_cnt += 4;
 428 +       hw->tx += 4;
 429 +
 430 +       return data;
 431 +}
 432 +
 433 +static void ltq_spi_bits_per_word_set(struct spi_device *spi)
 434 +{
 435 +       struct ltq_spi *hw = ltq_spi_to_hw(spi);
 436 +       u32 bm;
 437 +       u8 bits_per_word = spi->bits_per_word;
 438 +
 439 +       /*
 440 +        * Use either default value of SPI device or value
 441 +        * from current transfer.
 442 +        */
 443 +       if (hw->curr_transfer && hw->curr_transfer->bits_per_word)
 444 +               bits_per_word = hw->curr_transfer->bits_per_word;
 445 +
 446 +       if (bits_per_word <= 8)
 447 +               hw->get_tx = ltq_spi_tx_word_u8;
 448 +       else if (bits_per_word <= 16)
 449 +               hw->get_tx = ltq_spi_tx_word_u16;
 450 +       else if (bits_per_word <= 32)
 451 +               hw->get_tx = ltq_spi_tx_word_u32;
 452 +
 453 +       /* CON.BM value = bits_per_word - 1 */
 454 +       bm = (bits_per_word - 1) << LTQ_SPI_CON_BM_SHIFT;
 455 +
 456 +       ltq_spi_reg_clearbit(hw, LTQ_SPI_CON_BM_MASK <<
 457 +                            LTQ_SPI_CON_BM_SHIFT, LTQ_SPI_CON);
 458 +       ltq_spi_reg_setbit(hw, bm, LTQ_SPI_CON);
 459 +}
 460 +
 461 +static void ltq_spi_speed_set(struct spi_device *spi)
 462 +{
 463 +       struct ltq_spi *hw = ltq_spi_to_hw(spi);
 464 +       u32 br, max_speed_hz, spi_clk;
 465 +       u32 speed_hz = spi->max_speed_hz;
 466 +
 467 +       /*
 468 +        * Use either default value of SPI device or value
 469 +        * from current transfer.
 470 +        */
 471 +       if (hw->curr_transfer && hw->curr_transfer->speed_hz)
 472 +               speed_hz = hw->curr_transfer->speed_hz;
 473 +
 474 +       /*
 475 +        * SPI module clock is derived from FPI bus clock dependent on
 476 +        * divider value in CLC.RMS which is always set to 1.
 477 +        */
 478 +       spi_clk = clk_get_rate(hw->clk);
 479 +
 480 +       /*
 481 +        * Maximum SPI clock frequency in master mode is half of
 482 +        * SPI module clock frequency. Maximum reload value of
 483 +        * baudrate generator BR is 2^16.
 484 +        */
 485 +       max_speed_hz = spi_clk / 2;
 486 +       if (speed_hz >= max_speed_hz)
 487 +               br = 0;
 488 +       else
 489 +               br = (max_speed_hz / speed_hz) - 1;
 490 +
 491 +       if (br > 0xFFFF)
 492 +               br = 0xFFFF;
 493 +
 494 +       ltq_spi_reg_write(hw, br, LTQ_SPI_BRT);
 495 +}
 496 +
 497 +static void ltq_spi_clockmode_set(struct spi_device *spi)
 498 +{
 499 +       struct ltq_spi *hw = ltq_spi_to_hw(spi);
 500 +       u32 con;
 501 +
 502 +       con = ltq_spi_reg_read(hw, LTQ_SPI_CON);
 503 +
 504 +       /*
 505 +        * SPI mode mapping in CON register:
 506 +        * Mode CPOL CPHA CON.PO CON.PH
 507 +        *  0    0    0      0      1
 508 +        *  1    0    1      0      0
 509 +        *  2    1    0      1      1
 510 +        *  3    1    1      1      0
 511 +        */
 512 +       if (spi->mode & SPI_CPHA)
 513 +               con &= ~LTQ_SPI_CON_PH;
 514 +       else
 515 +               con |= LTQ_SPI_CON_PH;
 516 +
 517 +       if (spi->mode & SPI_CPOL)
 518 +               con |= LTQ_SPI_CON_PO;
 519 +       else
 520 +               con &= ~LTQ_SPI_CON_PO;
 521 +
 522 +       /* Set heading control */
 523 +       if (spi->mode & SPI_LSB_FIRST)
 524 +               con &= ~LTQ_SPI_CON_HB;
 525 +       else
 526 +               con |= LTQ_SPI_CON_HB;
 527 +
 528 +       ltq_spi_reg_write(hw, con, LTQ_SPI_CON);
 529 +}
 530 +
 531 +static void ltq_spi_xmit_set(struct ltq_spi *hw, struct spi_transfer *t)
 532 +{
 533 +       u32 con;
 534 +
 535 +       con = ltq_spi_reg_read(hw, LTQ_SPI_CON);
 536 +
 537 +       if (t) {
 538 +               if (t->tx_buf && t->rx_buf) {
 539 +                       con &= ~(LTQ_SPI_CON_TXOFF | LTQ_SPI_CON_RXOFF);
 540 +               } else if (t->rx_buf) {
 541 +                       con &= ~LTQ_SPI_CON_RXOFF;
 542 +                       con |= LTQ_SPI_CON_TXOFF;
 543 +               } else if (t->tx_buf) {
 544 +                       con &= ~LTQ_SPI_CON_TXOFF;
 545 +                       con |= LTQ_SPI_CON_RXOFF;
 546 +               }
 547 +       } else
 548 +               con |= (LTQ_SPI_CON_TXOFF | LTQ_SPI_CON_RXOFF);
 549 +
 550 +       ltq_spi_reg_write(hw, con, LTQ_SPI_CON);
 551 +}
 552 +
 553 +static void ltq_spi_gpio_cs_activate(struct spi_device *spi)
 554 +{
 555 +       struct ltq_spi_controller_data *cdata = spi->controller_data;
 556 +       int val = spi->mode & SPI_CS_HIGH ? 1 : 0;
 557 +
 558 +       gpio_set_value(cdata->gpio, val);
 559 +}
 560 +
 561 +static void ltq_spi_gpio_cs_deactivate(struct spi_device *spi)
 562 +{
 563 +       struct ltq_spi_controller_data *cdata = spi->controller_data;
 564 +       int val = spi->mode & SPI_CS_HIGH ? 0 : 1;
 565 +
 566 +       gpio_set_value(cdata->gpio, val);
 567 +}
 568 +
 569 +static void ltq_spi_internal_cs_activate(struct spi_device *spi)
 570 +{
 571 +       struct ltq_spi *hw = ltq_spi_to_hw(spi);
 572 +       u32 fgpo;
 573 +
 574 +       fgpo = (1 << (spi->chip_select + LTQ_SPI_FGPO_CLROUTN_SHIFT));
 575 +       ltq_spi_reg_setbit(hw, fgpo, LTQ_SPI_FGPO);
 576 +}
 577 +
 578 +static void ltq_spi_internal_cs_deactivate(struct spi_device *spi)
 579 +{
 580 +       struct ltq_spi *hw = ltq_spi_to_hw(spi);
 581 +       u32 fgpo;
 582 +
 583 +       fgpo = (1 << (spi->chip_select + LTQ_SPI_FGPO_SETOUTN_SHIFT));
 584 +       ltq_spi_reg_setbit(hw, fgpo, LTQ_SPI_FGPO);
 585 +}
 586 +
 587 +static void ltq_spi_chipselect(struct spi_device *spi, int cs)
 588 +{
 589 +       struct ltq_spi *hw = ltq_spi_to_hw(spi);
 590 +       struct ltq_spi_controller_state *cstate = spi->controller_state;
 591 +
 592 +       switch (cs) {
 593 +       case BITBANG_CS_ACTIVE:
 594 +               ltq_spi_bits_per_word_set(spi);
 595 +               ltq_spi_speed_set(spi);
 596 +               ltq_spi_clockmode_set(spi);
 597 +               ltq_spi_run_mode_set(hw);
 598 +
 599 +               cstate->cs_activate(spi);
 600 +               break;
 601 +
 602 +       case BITBANG_CS_INACTIVE:
 603 +               cstate->cs_deactivate(spi);
 604 +
 605 +               ltq_spi_config_mode_set(hw);
 606 +
 607 +               break;
 608 +       }
 609 +}
 610 +
 611 +static int ltq_spi_setup_transfer(struct spi_device *spi,
 612 +                                 struct spi_transfer *t)
 613 +{
 614 +       struct ltq_spi *hw = ltq_spi_to_hw(spi);
 615 +       u8 bits_per_word = spi->bits_per_word;
 616 +
 617 +       hw->curr_transfer = t;
 618 +
 619 +       if (t && t->bits_per_word)
 620 +               bits_per_word = t->bits_per_word;
 621 +
 622 +       if (bits_per_word > 32)
 623 +               return -EINVAL;
 624 +
 625 +       ltq_spi_config_mode_set(hw);
 626 +
 627 +       return 0;
 628 +}
 629 +
 630 +static const struct ltq_spi_cs_gpio_map ltq_spi_cs[] = {
 631 +       { 15, 1, 0 },
 632 +       { 22, 1, 0 },
 633 +       { 13, 0, 1 },
 634 +       { 10, 0, 1 },
 635 +       {  9, 0, 1 },
 636 +       { 11, 1, 1 },
 637 +};
 638 +
 639 +static int ltq_spi_setup(struct spi_device *spi)
 640 +{
 641 +       struct ltq_spi *hw = ltq_spi_to_hw(spi);
 642 +       struct ltq_spi_controller_data *cdata = spi->controller_data;
 643 +       struct ltq_spi_controller_state *cstate;
 644 +       u32 gpocon, fgpo;
 645 +       int ret;
 646 +
 647 +       /* Set default word length to 8 if not set */
 648 +       if (!spi->bits_per_word)
 649 +               spi->bits_per_word = 8;
 650 +
 651 +       if (spi->bits_per_word > 32)
 652 +               return -EINVAL;
 653 +
 654 +       if (!spi->controller_state) {
 655 +               cstate = kzalloc(sizeof(struct ltq_spi_controller_state),
 656 +                                GFP_KERNEL);
 657 +               if (!cstate)
 658 +                       return -ENOMEM;
 659 +
 660 +               spi->controller_state = cstate;
 661 +       } else
 662 +               return 0;
 663 +
 664 +       /*
 665 +        * Up to six GPIOs can be connected to the SPI module
 666 +        * via GPIO alternate function to control the chip select lines.
 667 +        * For more flexibility in board layout this driver can also control
 668 +        * the CS lines via GPIO API. If GPIOs should be used, board setup code
 669 +        * have to register the SPI device with struct ltq_spi_controller_data
 670 +        * attached.
 671 +        */
 672 +       if (cdata && cdata->gpio) {
 673 +               ret = gpio_request(cdata->gpio, "spi-cs");
 674 +               if (ret)
 675 +                       return -EBUSY;
 676 +
 677 +               ret = spi->mode & SPI_CS_HIGH ? 0 : 1;
 678 +               gpio_direction_output(cdata->gpio, ret);
 679 +
 680 +               cstate->cs_activate = ltq_spi_gpio_cs_activate;
 681 +               cstate->cs_deactivate = ltq_spi_gpio_cs_deactivate;
 682 +       } else {
 683 +               ret = ltq_gpio_request(ltq_spi_cs[spi->chip_select].gpio,
 684 +                               ltq_spi_cs[spi->chip_select].altsel0,
 685 +                               ltq_spi_cs[spi->chip_select].altsel1,
 686 +                               1, "spi-cs");
 687 +               if (ret)
 688 +                       return -EBUSY;
 689 +
 690 +               gpocon = (1 << (spi->chip_select +
 691 +                               LTQ_SPI_GPOCON_ISCSBN_SHIFT));
 692 +
 693 +               if (spi->mode & SPI_CS_HIGH)
 694 +                       gpocon |= (1 << spi->chip_select);
 695 +
 696 +               fgpo = (1 << (spi->chip_select + LTQ_SPI_FGPO_SETOUTN_SHIFT));
 697 +
 698 +               ltq_spi_reg_setbit(hw, gpocon, LTQ_SPI_GPOCON);
 699 +               ltq_spi_reg_setbit(hw, fgpo, LTQ_SPI_FGPO);
 700 +
 701 +               cstate->cs_activate = ltq_spi_internal_cs_activate;
 702 +               cstate->cs_deactivate = ltq_spi_internal_cs_deactivate;
 703 +       }
 704 +
 705 +       return 0;
 706 +}
 707 +
 708 +static void ltq_spi_cleanup(struct spi_device *spi)
 709 +{
 710 +       struct ltq_spi_controller_data *cdata = spi->controller_data;
 711 +       struct ltq_spi_controller_state *cstate = spi->controller_state;
 712 +       unsigned gpio;
 713 +
 714 +       if (cdata && cdata->gpio)
 715 +               gpio = cdata->gpio;
 716 +       else
 717 +               gpio = ltq_spi_cs[spi->chip_select].gpio;
 718 +
 719 +       gpio_free(gpio);
 720 +       kfree(cstate);
 721 +}
 722 +
 723 +static void ltq_spi_txfifo_write(struct ltq_spi *hw)
 724 +{
 725 +       u32 fstat, data;
 726 +       u16 fifo_space;
 727 +
 728 +       /* Determine how much FIFOs are free for TX data */
 729 +       fstat = ltq_spi_reg_read(hw, LTQ_SPI_FSTAT);
 730 +       fifo_space = hw->txfs - ((fstat >> LTQ_SPI_FSTAT_TXFFL_SHIFT) &
 731 +                                       LTQ_SPI_FSTAT_TXFFL_MASK);
 732 +
 733 +       if (!fifo_space)
 734 +               return;
 735 +
 736 +       while (hw->tx_cnt < hw->len && fifo_space) {
 737 +               data = hw->get_tx(hw);
 738 +               ltq_spi_reg_write(hw, data, LTQ_SPI_TB);
 739 +               fifo_space--;
 740 +       }
 741 +}
 742 +
 743 +static void ltq_spi_rxfifo_read(struct ltq_spi *hw)
 744 +{
 745 +       u32 fstat, data, *rx32;
 746 +       u16 fifo_fill;
 747 +       u8 rxbv, shift, *rx8;
 748 +
 749 +       /* Determine how much FIFOs are filled with RX data */
 750 +       fstat = ltq_spi_reg_read(hw, LTQ_SPI_FSTAT);
 751 +       fifo_fill = ((fstat >> LTQ_SPI_FSTAT_RXFFL_SHIFT)
 752 +                       & LTQ_SPI_FSTAT_RXFFL_MASK);
 753 +
 754 +       if (!fifo_fill)
 755 +               return;
 756 +
 757 +       /*
 758 +        * The 32 bit FIFO is always used completely independent from the
 759 +        * bits_per_word value. Thus four bytes have to be read at once
 760 +        * per FIFO.
 761 +        */
 762 +       rx32 = (u32 *) hw->rx;
 763 +       while (hw->len - hw->rx_cnt >= 4 && fifo_fill) {
 764 +               *rx32++ = ltq_spi_reg_read(hw, LTQ_SPI_RB);
 765 +               hw->rx_cnt += 4;
 766 +               hw->rx += 4;
 767 +               fifo_fill--;
 768 +       }
 769 +
 770 +       /*
 771 +        * If there are remaining bytes, read byte count from STAT.RXBV
 772 +        * register and read the data byte-wise.
 773 +        */
 774 +       while (fifo_fill && hw->rx_cnt < hw->len) {
 775 +               rxbv = (ltq_spi_reg_read(hw, LTQ_SPI_STAT) >>
 776 +                       LTQ_SPI_STAT_RXBV_SHIFT) & LTQ_SPI_STAT_RXBV_MASK;
 777 +               data = ltq_spi_reg_read(hw, LTQ_SPI_RB);
 778 +
 779 +               shift = (rxbv - 1) * 8;
 780 +               rx8 = hw->rx;
 781 +
 782 +               while (rxbv) {
 783 +                       *rx8++ = (data >> shift) & 0xFF;
 784 +                       rxbv--;
 785 +                       shift -= 8;
 786 +                       hw->rx_cnt++;
 787 +                       hw->rx++;
 788 +               }
 789 +
 790 +               fifo_fill--;
 791 +       }
 792 +}
 793 +
 794 +static void ltq_spi_rxreq_set(struct ltq_spi *hw)
 795 +{
 796 +       u32 rxreq, rxreq_max, rxtodo;
 797 +
 798 +       rxtodo = ltq_spi_reg_read(hw, LTQ_SPI_RXCNT) & LTQ_SPI_RXCNT_TODO_MASK;
 799 +
 800 +       /*
 801 +        * In RX-only mode the serial clock is activated only after writing
 802 +        * the expected amount of RX bytes into RXREQ register.
 803 +        * To avoid receive overflows at high clocks it is better to request
 804 +        * only the amount of bytes that fits into all FIFOs. This value
 805 +        * depends on the FIFO size implemented in hardware.
 806 +        */
 807 +       rxreq = hw->len - hw->rx_cnt;
 808 +       rxreq_max = hw->rxfs << 2;
 809 +       rxreq = min(rxreq_max, rxreq);
 810 +
 811 +       if (!rxtodo && rxreq)
 812 +               ltq_spi_reg_write(hw, rxreq, LTQ_SPI_RXREQ);
 813 +}
 814 +
 815 +static inline void ltq_spi_complete(struct ltq_spi *hw)
 816 +{
 817 +       complete(&hw->done);
 818 +}
 819 +
 820 +irqreturn_t ltq_spi_tx_irq(int irq, void *data)
 821 +{
 822 +       struct ltq_spi *hw = data;
 823 +       unsigned long flags;
 824 +       int completed = 0;
 825 +
 826 +       spin_lock_irqsave(&hw->lock, flags);
 827 +
 828 +       if (hw->tx_cnt < hw->len)
 829 +               ltq_spi_txfifo_write(hw);
 830 +
 831 +       if (hw->tx_cnt == hw->len)
 832 +               completed = 1;
 833 +
 834 +       spin_unlock_irqrestore(&hw->lock, flags);
 835 +
 836 +       if (completed)
 837 +               ltq_spi_complete(hw);
 838 +
 839 +       return IRQ_HANDLED;
 840 +}
 841 +
 842 +irqreturn_t ltq_spi_rx_irq(int irq, void *data)
 843 +{
 844 +       struct ltq_spi *hw = data;
 845 +       unsigned long flags;
 846 +       int completed = 0;
 847 +
 848 +       spin_lock_irqsave(&hw->lock, flags);
 849 +
 850 +       if (hw->rx_cnt < hw->len) {
 851 +               ltq_spi_rxfifo_read(hw);
 852 +
 853 +               if (hw->tx && hw->tx_cnt < hw->len)
 854 +                       ltq_spi_txfifo_write(hw);
 855 +       }
 856 +
 857 +       if (hw->rx_cnt == hw->len)
 858 +               completed = 1;
 859 +       else if (!hw->tx)
 860 +               ltq_spi_rxreq_set(hw);
 861 +
 862 +       spin_unlock_irqrestore(&hw->lock, flags);
 863 +
 864 +       if (completed)
 865 +               ltq_spi_complete(hw);
 866 +
 867 +       return IRQ_HANDLED;
 868 +}
 869 +
 870 +irqreturn_t ltq_spi_err_irq(int irq, void *data)
 871 +{
 872 +       struct ltq_spi *hw = data;
 873 +       unsigned long flags;
 874 +
 875 +       spin_lock_irqsave(&hw->lock, flags);
 876 +
 877 +       /* Disable all interrupts */
 878 +       ltq_spi_reg_clearbit(hw, LTQ_SPI_IRNEN_ALL, LTQ_SPI_IRNEN);
 879 +
 880 +       /* Clear all error flags */
 881 +       ltq_spi_reg_write(hw, LTQ_SPI_WHBSTATE_CLR_ERRORS, LTQ_SPI_WHBSTATE);
 882 +
 883 +       /* Flush FIFOs */
 884 +       ltq_spi_reg_setbit(hw, LTQ_SPI_RXFCON_RXFLU, LTQ_SPI_RXFCON);
 885 +       ltq_spi_reg_setbit(hw, LTQ_SPI_TXFCON_TXFLU, LTQ_SPI_TXFCON);
 886 +
 887 +       hw->status = -EIO;
 888 +       spin_unlock_irqrestore(&hw->lock, flags);
 889 +
 890 +       ltq_spi_complete(hw);
 891 +
 892 +       return IRQ_HANDLED;
 893 +}
 894 +
 895 +static int ltq_spi_txrx_bufs(struct spi_device *spi, struct spi_transfer *t)
 896 +{
 897 +       struct ltq_spi *hw = ltq_spi_to_hw(spi);
 898 +       u32 irq_flags = 0;
 899 +
 900 +       hw->tx = t->tx_buf;
 901 +       hw->rx = t->rx_buf;
 902 +       hw->len = t->len;
 903 +       hw->tx_cnt = 0;
 904 +       hw->rx_cnt = 0;
 905 +       hw->status = 0;
 906 +       INIT_COMPLETION(hw->done);
 907 +
 908 +       ltq_spi_xmit_set(hw, t);
 909 +
 910 +       /* Enable error interrupts */
 911 +       ltq_spi_reg_setbit(hw, LTQ_SPI_IRNEN_E, LTQ_SPI_IRNEN);
 912 +
 913 +       if (hw->tx) {
 914 +               /* Initially fill TX FIFO with as much data as possible */
 915 +               ltq_spi_txfifo_write(hw);
 916 +               irq_flags |= LTQ_SPI_IRNEN_T;
 917 +
 918 +               /* Always enable RX interrupt in Full Duplex mode */
 919 +               if (hw->rx)
 920 +                       irq_flags |= LTQ_SPI_IRNEN_R;
 921 +       } else if (hw->rx) {
 922 +               /* Start RX clock */
 923 +               ltq_spi_rxreq_set(hw);
 924 +
 925 +               /* Enable RX interrupt to receive data from RX FIFOs */
 926 +               irq_flags |= LTQ_SPI_IRNEN_R;
 927 +       }
 928 +
 929 +       /* Enable TX or RX interrupts */
 930 +       ltq_spi_reg_setbit(hw, irq_flags, LTQ_SPI_IRNEN);
 931 +       wait_for_completion_interruptible(&hw->done);
 932 +
 933 +       /* Disable all interrupts */
 934 +       ltq_spi_reg_clearbit(hw, LTQ_SPI_IRNEN_ALL, LTQ_SPI_IRNEN);
 935 +
 936 +       /*
 937 +        * Return length of current transfer for bitbang utility code if
 938 +        * no errors occured during transmission.
 939 +        */
 940 +       if (!hw->status)
 941 +               hw->status = hw->len;
 942 +
 943 +       return hw->status;
 944 +}
 945 +
 946 +static const struct ltq_spi_irq_map ltq_spi_irqs[] = {
 947 +       { "spi_tx", ltq_spi_tx_irq },
 948 +       { "spi_rx", ltq_spi_rx_irq },
 949 +       { "spi_err", ltq_spi_err_irq },
 950 +};
 951 +
 952 +static int __init ltq_spi_probe(struct platform_device *pdev)
 953 +{
 954 +       struct spi_master *master;
 955 +       struct resource *r;
 956 +       struct ltq_spi *hw;
 957 +       struct ltq_spi_platform_data *pdata = pdev->dev.platform_data;
 958 +       int ret, i;
 959 +       u32 data, id;
 960 +
 961 +       master = spi_alloc_master(&pdev->dev, sizeof(struct ltq_spi));
 962 +       if (!master) {
 963 +               dev_err(&pdev->dev, "spi_alloc_master\n");
 964 +               ret = -ENOMEM;
 965 +               goto err;
 966 +       }
 967 +
 968 +       hw = spi_master_get_devdata(master);
 969 +
 970 +       r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 971 +       if (r == NULL) {
 972 +               dev_err(&pdev->dev, "platform_get_resource\n");
 973 +               ret = -ENOENT;
 974 +               goto err_master;
 975 +       }
 976 +
 977 +       r = devm_request_mem_region(&pdev->dev, r->start, resource_size(r),
 978 +                       pdev->name);
 979 +       if (!r) {
 980 +               dev_err(&pdev->dev, "devm_request_mem_region\n");
 981 +               ret = -ENXIO;
 982 +               goto err_master;
 983 +       }
 984 +
 985 +       hw->base = devm_ioremap_nocache(&pdev->dev, r->start, resource_size(r));
 986 +       if (!hw->base) {
 987 +               dev_err(&pdev->dev, "devm_ioremap_nocache\n");
 988 +               ret = -ENXIO;
 989 +               goto err_master;
 990 +       }
 991 +
 992 +       hw->clk = clk_get(&pdev->dev, "fpi");
 993 +       if (IS_ERR(hw->clk)) {
 994 +               dev_err(&pdev->dev, "clk_get\n");
 995 +               ret = PTR_ERR(hw->clk);
 996 +               goto err_master;
 997 +       }
 998 +
 999 +       memset(hw->irq, 0, sizeof(hw->irq));
1000 +       for (i = 0; i < ARRAY_SIZE(ltq_spi_irqs); i++) {
1001 +               ret = platform_get_irq_byname(pdev, ltq_spi_irqs[i].name);
1002 +               if (0 > ret) {
1003 +                       dev_err(&pdev->dev, "platform_get_irq_byname\n");
1004 +                       goto err_irq;
1005 +               }
1006 +
1007 +               hw->irq[i] = ret;
1008 +               ret = request_irq(hw->irq[i], ltq_spi_irqs[i].handler,
1009 +                                 0, ltq_spi_irqs[i].name, hw);
1010 +               if (ret) {
1011 +                       dev_err(&pdev->dev, "request_irq\n");
1012 +                       goto err_irq;
1013 +               }
1014 +       }
1015 +
1016 +       hw->bitbang.master = spi_master_get(master);
1017 +       hw->bitbang.chipselect = ltq_spi_chipselect;
1018 +       hw->bitbang.setup_transfer = ltq_spi_setup_transfer;
1019 +       hw->bitbang.txrx_bufs = ltq_spi_txrx_bufs;
1020 +
1021 +       master->bus_num = pdev->id;
1022 +       master->num_chipselect = pdata->num_chipselect;
1023 +       master->setup = ltq_spi_setup;
1024 +       master->cleanup = ltq_spi_cleanup;
1025 +
1026 +       hw->dev = &pdev->dev;
1027 +       init_completion(&hw->done);
1028 +       spin_lock_init(&hw->lock);
1029 +
1030 +       /* Set GPIO alternate functions to SPI */
1031 +       ltq_gpio_request(LTQ_SPI_GPIO_DI, 1, 0, 0, "spi-di");
1032 +       ltq_gpio_request(LTQ_SPI_GPIO_DO, 1, 0, 1, "spi-do");
1033 +       ltq_gpio_request(LTQ_SPI_GPIO_CLK, 1, 0, 1, "spi-clk");
1034 +
1035 +       ltq_spi_hw_enable(hw);
1036 +
1037 +       /* Read module capabilities */
1038 +       id = ltq_spi_reg_read(hw, LTQ_SPI_ID);
1039 +       hw->txfs = (id >> LTQ_SPI_ID_TXFS_SHIFT) & LTQ_SPI_ID_TXFS_MASK;
1040 +       hw->rxfs = (id >> LTQ_SPI_ID_TXFS_SHIFT) & LTQ_SPI_ID_TXFS_MASK;
1041 +       hw->dma_support = (id & LTQ_SPI_ID_CFG) ? 1 : 0;
1042 +
1043 +       ltq_spi_config_mode_set(hw);
1044 +
1045 +       /* Enable error checking, disable TX/RX, set idle value high */
1046 +       data = LTQ_SPI_CON_RUEN | LTQ_SPI_CON_AEN |
1047 +           LTQ_SPI_CON_TEN | LTQ_SPI_CON_REN |
1048 +           LTQ_SPI_CON_TXOFF | LTQ_SPI_CON_RXOFF | LTQ_SPI_CON_IDLE;
1049 +       ltq_spi_reg_write(hw, data, LTQ_SPI_CON);
1050 +
1051 +       /* Enable master mode and clear error flags */
1052 +       ltq_spi_reg_write(hw, LTQ_SPI_WHBSTATE_SETMS |
1053 +                         LTQ_SPI_WHBSTATE_CLR_ERRORS, LTQ_SPI_WHBSTATE);
1054 +
1055 +       /* Reset GPIO/CS registers */
1056 +       ltq_spi_reg_write(hw, 0x0, LTQ_SPI_GPOCON);
1057 +       ltq_spi_reg_write(hw, 0xFF00, LTQ_SPI_FGPO);
1058 +
1059 +       /* Enable and flush FIFOs */
1060 +       ltq_spi_reset_fifos(hw);
1061 +
1062 +       ret = spi_bitbang_start(&hw->bitbang);
1063 +       if (ret) {
1064 +               dev_err(&pdev->dev, "spi_bitbang_start\n");
1065 +               goto err_bitbang;
1066 +       }
1067 +
1068 +       platform_set_drvdata(pdev, hw);
1069 +
1070 +       pr_info("Lantiq SoC SPI controller rev %u (TXFS %u, RXFS %u, DMA %u)\n",
1071 +               id & LTQ_SPI_ID_REV_MASK, hw->txfs, hw->rxfs, hw->dma_support);
1072 +
1073 +       return 0;
1074 +
1075 +err_bitbang:
1076 +       ltq_spi_hw_disable(hw);
1077 +
1078 +err_irq:
1079 +       clk_put(hw->clk);
1080 +
1081 +       for (; i > 0; i--)
1082 +               free_irq(hw->irq[i], hw);
1083 +
1084 +err_master:
1085 +       spi_master_put(master);
1086 +
1087 +err:
1088 +       return ret;
1089 +}
1090 +
1091 +static int __exit ltq_spi_remove(struct platform_device *pdev)
1092 +{
1093 +       struct ltq_spi *hw = platform_get_drvdata(pdev);
1094 +       int ret, i;
1095 +
1096 +       ret = spi_bitbang_stop(&hw->bitbang);
1097 +       if (ret)
1098 +               return ret;
1099 +
1100 +       platform_set_drvdata(pdev, NULL);
1101 +
1102 +       ltq_spi_config_mode_set(hw);
1103 +       ltq_spi_hw_disable(hw);
1104 +
1105 +       for (i = 0; i < ARRAY_SIZE(hw->irq); i++)
1106 +               if (0 < hw->irq[i])
1107 +                       free_irq(hw->irq[i], hw);
1108 +
1109 +       gpio_free(LTQ_SPI_GPIO_DI);
1110 +       gpio_free(LTQ_SPI_GPIO_DO);
1111 +       gpio_free(LTQ_SPI_GPIO_CLK);
1112 +
1113 +       clk_put(hw->clk);
1114 +       spi_master_put(hw->bitbang.master);
1115 +
1116 +       return 0;
1117 +}
1118 +
1119 +static struct platform_driver ltq_spi_driver = {
1120 +       .driver = {
1121 +                  .name = "ltq-spi",
1122 +                  .owner = THIS_MODULE,
1123 +                  },
1124 +       .remove = __exit_p(ltq_spi_remove),
1125 +};
1126 +
1127 +static int __init ltq_spi_init(void)
1128 +{
1129 +       return platform_driver_probe(&ltq_spi_driver, ltq_spi_probe);
1130 +}
1131 +module_init(ltq_spi_init);
1132 +
1133 +static void __exit ltq_spi_exit(void)
1134 +{
1135 +       platform_driver_unregister(&ltq_spi_driver);
1136 +}
1137 +module_exit(ltq_spi_exit);
1138 +
1139 +MODULE_DESCRIPTION("Lantiq SoC SPI controller driver");
1140 +MODULE_AUTHOR("Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>");
1141 +MODULE_LICENSE("GPL");
1142 +MODULE_ALIAS("platform:ltq-spi");