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fix restart on platforms without a setup_switch()
[openwrt.git] / package / b43 / src / dma.c
1 /*
2
3 Broadcom B43 wireless driver
4
5 DMA ringbuffer and descriptor allocation/management
6
7 Copyright (c) 2005, 2006 Michael Buesch <mb@bu3sch.de>
8
9 Some code in this file is derived from the b44.c driver
10 Copyright (C) 2002 David S. Miller
11 Copyright (C) Pekka Pietikainen
12
13 This program is free software; you can redistribute it and/or modify
14 it under the terms of the GNU General Public License as published by
15 the Free Software Foundation; either version 2 of the License, or
16 (at your option) any later version.
17
18 This program is distributed in the hope that it will be useful,
19 but WITHOUT ANY WARRANTY; without even the implied warranty of
20 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 GNU General Public License for more details.
22
23 You should have received a copy of the GNU General Public License
24 along with this program; see the file COPYING. If not, write to
25 the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor,
26 Boston, MA 02110-1301, USA.
27
28 */
29
30 #include "b43.h"
31 #include "dma.h"
32 #include "main.h"
33 #include "debugfs.h"
34 #include "xmit.h"
35
36 #include <linux/dma-mapping.h>
37 #include <linux/pci.h>
38 #include <linux/delay.h>
39 #include <linux/skbuff.h>
40 #include <linux/etherdevice.h>
41
42
43 /* 32bit DMA ops. */
44 static
45 struct b43_dmadesc_generic *op32_idx2desc(struct b43_dmaring *ring,
46 int slot,
47 struct b43_dmadesc_meta **meta)
48 {
49 struct b43_dmadesc32 *desc;
50
51 *meta = &(ring->meta[slot]);
52 desc = ring->descbase;
53 desc = &(desc[slot]);
54
55 return (struct b43_dmadesc_generic *)desc;
56 }
57
58 static void op32_fill_descriptor(struct b43_dmaring *ring,
59 struct b43_dmadesc_generic *desc,
60 dma_addr_t dmaaddr, u16 bufsize,
61 int start, int end, int irq)
62 {
63 struct b43_dmadesc32 *descbase = ring->descbase;
64 int slot;
65 u32 ctl;
66 u32 addr;
67 u32 addrext;
68
69 slot = (int)(&(desc->dma32) - descbase);
70 B43_WARN_ON(!(slot >= 0 && slot < ring->nr_slots));
71
72 addr = (u32) (dmaaddr & ~SSB_DMA_TRANSLATION_MASK);
73 addrext = (u32) (dmaaddr & SSB_DMA_TRANSLATION_MASK)
74 >> SSB_DMA_TRANSLATION_SHIFT;
75 addr |= ssb_dma_translation(ring->dev->dev);
76 ctl = (bufsize - ring->frameoffset)
77 & B43_DMA32_DCTL_BYTECNT;
78 if (slot == ring->nr_slots - 1)
79 ctl |= B43_DMA32_DCTL_DTABLEEND;
80 if (start)
81 ctl |= B43_DMA32_DCTL_FRAMESTART;
82 if (end)
83 ctl |= B43_DMA32_DCTL_FRAMEEND;
84 if (irq)
85 ctl |= B43_DMA32_DCTL_IRQ;
86 ctl |= (addrext << B43_DMA32_DCTL_ADDREXT_SHIFT)
87 & B43_DMA32_DCTL_ADDREXT_MASK;
88
89 desc->dma32.control = cpu_to_le32(ctl);
90 desc->dma32.address = cpu_to_le32(addr);
91 }
92
93 static void op32_poke_tx(struct b43_dmaring *ring, int slot)
94 {
95 b43_dma_write(ring, B43_DMA32_TXINDEX,
96 (u32) (slot * sizeof(struct b43_dmadesc32)));
97 }
98
99 static void op32_tx_suspend(struct b43_dmaring *ring)
100 {
101 b43_dma_write(ring, B43_DMA32_TXCTL, b43_dma_read(ring, B43_DMA32_TXCTL)
102 | B43_DMA32_TXSUSPEND);
103 }
104
105 static void op32_tx_resume(struct b43_dmaring *ring)
106 {
107 b43_dma_write(ring, B43_DMA32_TXCTL, b43_dma_read(ring, B43_DMA32_TXCTL)
108 & ~B43_DMA32_TXSUSPEND);
109 }
110
111 static int op32_get_current_rxslot(struct b43_dmaring *ring)
112 {
113 u32 val;
114
115 val = b43_dma_read(ring, B43_DMA32_RXSTATUS);
116 val &= B43_DMA32_RXDPTR;
117
118 return (val / sizeof(struct b43_dmadesc32));
119 }
120
121 static void op32_set_current_rxslot(struct b43_dmaring *ring, int slot)
122 {
123 b43_dma_write(ring, B43_DMA32_RXINDEX,
124 (u32) (slot * sizeof(struct b43_dmadesc32)));
125 }
126
127 static const struct b43_dma_ops dma32_ops = {
128 .idx2desc = op32_idx2desc,
129 .fill_descriptor = op32_fill_descriptor,
130 .poke_tx = op32_poke_tx,
131 .tx_suspend = op32_tx_suspend,
132 .tx_resume = op32_tx_resume,
133 .get_current_rxslot = op32_get_current_rxslot,
134 .set_current_rxslot = op32_set_current_rxslot,
135 };
136
137 /* 64bit DMA ops. */
138 static
139 struct b43_dmadesc_generic *op64_idx2desc(struct b43_dmaring *ring,
140 int slot,
141 struct b43_dmadesc_meta **meta)
142 {
143 struct b43_dmadesc64 *desc;
144
145 *meta = &(ring->meta[slot]);
146 desc = ring->descbase;
147 desc = &(desc[slot]);
148
149 return (struct b43_dmadesc_generic *)desc;
150 }
151
152 static void op64_fill_descriptor(struct b43_dmaring *ring,
153 struct b43_dmadesc_generic *desc,
154 dma_addr_t dmaaddr, u16 bufsize,
155 int start, int end, int irq)
156 {
157 struct b43_dmadesc64 *descbase = ring->descbase;
158 int slot;
159 u32 ctl0 = 0, ctl1 = 0;
160 u32 addrlo, addrhi;
161 u32 addrext;
162
163 slot = (int)(&(desc->dma64) - descbase);
164 B43_WARN_ON(!(slot >= 0 && slot < ring->nr_slots));
165
166 addrlo = (u32) (dmaaddr & 0xFFFFFFFF);
167 addrhi = (((u64) dmaaddr >> 32) & ~SSB_DMA_TRANSLATION_MASK);
168 addrext = (((u64) dmaaddr >> 32) & SSB_DMA_TRANSLATION_MASK)
169 >> SSB_DMA_TRANSLATION_SHIFT;
170 addrhi |= (ssb_dma_translation(ring->dev->dev) << 1);
171 if (slot == ring->nr_slots - 1)
172 ctl0 |= B43_DMA64_DCTL0_DTABLEEND;
173 if (start)
174 ctl0 |= B43_DMA64_DCTL0_FRAMESTART;
175 if (end)
176 ctl0 |= B43_DMA64_DCTL0_FRAMEEND;
177 if (irq)
178 ctl0 |= B43_DMA64_DCTL0_IRQ;
179 ctl1 |= (bufsize - ring->frameoffset)
180 & B43_DMA64_DCTL1_BYTECNT;
181 ctl1 |= (addrext << B43_DMA64_DCTL1_ADDREXT_SHIFT)
182 & B43_DMA64_DCTL1_ADDREXT_MASK;
183
184 desc->dma64.control0 = cpu_to_le32(ctl0);
185 desc->dma64.control1 = cpu_to_le32(ctl1);
186 desc->dma64.address_low = cpu_to_le32(addrlo);
187 desc->dma64.address_high = cpu_to_le32(addrhi);
188 }
189
190 static void op64_poke_tx(struct b43_dmaring *ring, int slot)
191 {
192 b43_dma_write(ring, B43_DMA64_TXINDEX,
193 (u32) (slot * sizeof(struct b43_dmadesc64)));
194 }
195
196 static void op64_tx_suspend(struct b43_dmaring *ring)
197 {
198 b43_dma_write(ring, B43_DMA64_TXCTL, b43_dma_read(ring, B43_DMA64_TXCTL)
199 | B43_DMA64_TXSUSPEND);
200 }
201
202 static void op64_tx_resume(struct b43_dmaring *ring)
203 {
204 b43_dma_write(ring, B43_DMA64_TXCTL, b43_dma_read(ring, B43_DMA64_TXCTL)
205 & ~B43_DMA64_TXSUSPEND);
206 }
207
208 static int op64_get_current_rxslot(struct b43_dmaring *ring)
209 {
210 u32 val;
211
212 val = b43_dma_read(ring, B43_DMA64_RXSTATUS);
213 val &= B43_DMA64_RXSTATDPTR;
214
215 return (val / sizeof(struct b43_dmadesc64));
216 }
217
218 static void op64_set_current_rxslot(struct b43_dmaring *ring, int slot)
219 {
220 b43_dma_write(ring, B43_DMA64_RXINDEX,
221 (u32) (slot * sizeof(struct b43_dmadesc64)));
222 }
223
224 static const struct b43_dma_ops dma64_ops = {
225 .idx2desc = op64_idx2desc,
226 .fill_descriptor = op64_fill_descriptor,
227 .poke_tx = op64_poke_tx,
228 .tx_suspend = op64_tx_suspend,
229 .tx_resume = op64_tx_resume,
230 .get_current_rxslot = op64_get_current_rxslot,
231 .set_current_rxslot = op64_set_current_rxslot,
232 };
233
234 static inline int free_slots(struct b43_dmaring *ring)
235 {
236 return (ring->nr_slots - ring->used_slots);
237 }
238
239 static inline int next_slot(struct b43_dmaring *ring, int slot)
240 {
241 B43_WARN_ON(!(slot >= -1 && slot <= ring->nr_slots - 1));
242 if (slot == ring->nr_slots - 1)
243 return 0;
244 return slot + 1;
245 }
246
247 static inline int prev_slot(struct b43_dmaring *ring, int slot)
248 {
249 B43_WARN_ON(!(slot >= 0 && slot <= ring->nr_slots - 1));
250 if (slot == 0)
251 return ring->nr_slots - 1;
252 return slot - 1;
253 }
254
255 #ifdef CONFIG_B43_DEBUG
256 static void update_max_used_slots(struct b43_dmaring *ring,
257 int current_used_slots)
258 {
259 if (current_used_slots <= ring->max_used_slots)
260 return;
261 ring->max_used_slots = current_used_slots;
262 if (b43_debug(ring->dev, B43_DBG_DMAVERBOSE)) {
263 b43dbg(ring->dev->wl,
264 "max_used_slots increased to %d on %s ring %d\n",
265 ring->max_used_slots,
266 ring->tx ? "TX" : "RX", ring->index);
267 }
268 }
269 #else
270 static inline
271 void update_max_used_slots(struct b43_dmaring *ring, int current_used_slots)
272 {
273 }
274 #endif /* DEBUG */
275
276 /* Request a slot for usage. */
277 static inline int request_slot(struct b43_dmaring *ring)
278 {
279 int slot;
280
281 B43_WARN_ON(!ring->tx);
282 B43_WARN_ON(ring->stopped);
283 B43_WARN_ON(free_slots(ring) == 0);
284
285 slot = next_slot(ring, ring->current_slot);
286 ring->current_slot = slot;
287 ring->used_slots++;
288
289 update_max_used_slots(ring, ring->used_slots);
290
291 return slot;
292 }
293
294 /* Mac80211-queue to b43-ring mapping */
295 static struct b43_dmaring *priority_to_txring(struct b43_wldev *dev,
296 int queue_priority)
297 {
298 struct b43_dmaring *ring;
299
300 /*FIXME: For now we always run on TX-ring-1 */
301 return dev->dma.tx_ring1;
302
303 /* 0 = highest priority */
304 switch (queue_priority) {
305 default:
306 B43_WARN_ON(1);
307 /* fallthrough */
308 case 0:
309 ring = dev->dma.tx_ring3;
310 break;
311 case 1:
312 ring = dev->dma.tx_ring2;
313 break;
314 case 2:
315 ring = dev->dma.tx_ring1;
316 break;
317 case 3:
318 ring = dev->dma.tx_ring0;
319 break;
320 }
321
322 return ring;
323 }
324
325 /* b43-ring to mac80211-queue mapping */
326 static inline int txring_to_priority(struct b43_dmaring *ring)
327 {
328 static const u8 idx_to_prio[] = { 3, 2, 1, 0, };
329 unsigned int index;
330
331 /*FIXME: have only one queue, for now */
332 return 0;
333
334 index = ring->index;
335 if (B43_WARN_ON(index >= ARRAY_SIZE(idx_to_prio)))
336 index = 0;
337 return idx_to_prio[index];
338 }
339
340 static u16 b43_dmacontroller_base(enum b43_dmatype type, int controller_idx)
341 {
342 static const u16 map64[] = {
343 B43_MMIO_DMA64_BASE0,
344 B43_MMIO_DMA64_BASE1,
345 B43_MMIO_DMA64_BASE2,
346 B43_MMIO_DMA64_BASE3,
347 B43_MMIO_DMA64_BASE4,
348 B43_MMIO_DMA64_BASE5,
349 };
350 static const u16 map32[] = {
351 B43_MMIO_DMA32_BASE0,
352 B43_MMIO_DMA32_BASE1,
353 B43_MMIO_DMA32_BASE2,
354 B43_MMIO_DMA32_BASE3,
355 B43_MMIO_DMA32_BASE4,
356 B43_MMIO_DMA32_BASE5,
357 };
358
359 if (type == B43_DMA_64BIT) {
360 B43_WARN_ON(!(controller_idx >= 0 &&
361 controller_idx < ARRAY_SIZE(map64)));
362 return map64[controller_idx];
363 }
364 B43_WARN_ON(!(controller_idx >= 0 &&
365 controller_idx < ARRAY_SIZE(map32)));
366 return map32[controller_idx];
367 }
368
369 static inline
370 dma_addr_t map_descbuffer(struct b43_dmaring *ring,
371 unsigned char *buf, size_t len, int tx)
372 {
373 dma_addr_t dmaaddr;
374
375 if (tx) {
376 dmaaddr = dma_map_single(ring->dev->dev->dev,
377 buf, len, DMA_TO_DEVICE);
378 } else {
379 dmaaddr = dma_map_single(ring->dev->dev->dev,
380 buf, len, DMA_FROM_DEVICE);
381 }
382
383 return dmaaddr;
384 }
385
386 static inline
387 void unmap_descbuffer(struct b43_dmaring *ring,
388 dma_addr_t addr, size_t len, int tx)
389 {
390 if (tx) {
391 dma_unmap_single(ring->dev->dev->dev, addr, len, DMA_TO_DEVICE);
392 } else {
393 dma_unmap_single(ring->dev->dev->dev,
394 addr, len, DMA_FROM_DEVICE);
395 }
396 }
397
398 static inline
399 void sync_descbuffer_for_cpu(struct b43_dmaring *ring,
400 dma_addr_t addr, size_t len)
401 {
402 B43_WARN_ON(ring->tx);
403 dma_sync_single_for_cpu(ring->dev->dev->dev,
404 addr, len, DMA_FROM_DEVICE);
405 }
406
407 static inline
408 void sync_descbuffer_for_device(struct b43_dmaring *ring,
409 dma_addr_t addr, size_t len)
410 {
411 B43_WARN_ON(ring->tx);
412 dma_sync_single_for_device(ring->dev->dev->dev,
413 addr, len, DMA_FROM_DEVICE);
414 }
415
416 static inline
417 void free_descriptor_buffer(struct b43_dmaring *ring,
418 struct b43_dmadesc_meta *meta)
419 {
420 if (meta->skb) {
421 dev_kfree_skb_any(meta->skb);
422 meta->skb = NULL;
423 }
424 }
425
426 static int alloc_ringmemory(struct b43_dmaring *ring)
427 {
428 struct device *dev = ring->dev->dev->dev;
429 gfp_t flags = GFP_KERNEL;
430
431 /* The specs call for 4K buffers for 30- and 32-bit DMA with 4K
432 * alignment and 8K buffers for 64-bit DMA with 8K alignment. Testing
433 * has shown that 4K is sufficient for the latter as long as the buffer
434 * does not cross an 8K boundary.
435 *
436 * For unknown reasons - possibly a hardware error - the BCM4311 rev
437 * 02, which uses 64-bit DMA, needs the ring buffer in very low memory,
438 * which accounts for the GFP_DMA flag below.
439 */
440 if (ring->type == B43_DMA_64BIT)
441 flags |= GFP_DMA;
442 ring->descbase = dma_alloc_coherent(dev, B43_DMA_RINGMEMSIZE,
443 &(ring->dmabase), flags);
444 if (!ring->descbase) {
445 b43err(ring->dev->wl, "DMA ringmemory allocation failed\n");
446 return -ENOMEM;
447 }
448 memset(ring->descbase, 0, B43_DMA_RINGMEMSIZE);
449
450 return 0;
451 }
452
453 static void free_ringmemory(struct b43_dmaring *ring)
454 {
455 struct device *dev = ring->dev->dev->dev;
456
457 dma_free_coherent(dev, B43_DMA_RINGMEMSIZE,
458 ring->descbase, ring->dmabase);
459 }
460
461 /* Reset the RX DMA channel */
462 static int b43_dmacontroller_rx_reset(struct b43_wldev *dev, u16 mmio_base,
463 enum b43_dmatype type)
464 {
465 int i;
466 u32 value;
467 u16 offset;
468
469 might_sleep();
470
471 offset = (type == B43_DMA_64BIT) ? B43_DMA64_RXCTL : B43_DMA32_RXCTL;
472 b43_write32(dev, mmio_base + offset, 0);
473 for (i = 0; i < 10; i++) {
474 offset = (type == B43_DMA_64BIT) ? B43_DMA64_RXSTATUS :
475 B43_DMA32_RXSTATUS;
476 value = b43_read32(dev, mmio_base + offset);
477 if (type == B43_DMA_64BIT) {
478 value &= B43_DMA64_RXSTAT;
479 if (value == B43_DMA64_RXSTAT_DISABLED) {
480 i = -1;
481 break;
482 }
483 } else {
484 value &= B43_DMA32_RXSTATE;
485 if (value == B43_DMA32_RXSTAT_DISABLED) {
486 i = -1;
487 break;
488 }
489 }
490 msleep(1);
491 }
492 if (i != -1) {
493 b43err(dev->wl, "DMA RX reset timed out\n");
494 return -ENODEV;
495 }
496
497 return 0;
498 }
499
500 /* Reset the TX DMA channel */
501 static int b43_dmacontroller_tx_reset(struct b43_wldev *dev, u16 mmio_base,
502 enum b43_dmatype type)
503 {
504 int i;
505 u32 value;
506 u16 offset;
507
508 might_sleep();
509
510 for (i = 0; i < 10; i++) {
511 offset = (type == B43_DMA_64BIT) ? B43_DMA64_TXSTATUS :
512 B43_DMA32_TXSTATUS;
513 value = b43_read32(dev, mmio_base + offset);
514 if (type == B43_DMA_64BIT) {
515 value &= B43_DMA64_TXSTAT;
516 if (value == B43_DMA64_TXSTAT_DISABLED ||
517 value == B43_DMA64_TXSTAT_IDLEWAIT ||
518 value == B43_DMA64_TXSTAT_STOPPED)
519 break;
520 } else {
521 value &= B43_DMA32_TXSTATE;
522 if (value == B43_DMA32_TXSTAT_DISABLED ||
523 value == B43_DMA32_TXSTAT_IDLEWAIT ||
524 value == B43_DMA32_TXSTAT_STOPPED)
525 break;
526 }
527 msleep(1);
528 }
529 offset = (type == B43_DMA_64BIT) ? B43_DMA64_TXCTL : B43_DMA32_TXCTL;
530 b43_write32(dev, mmio_base + offset, 0);
531 for (i = 0; i < 10; i++) {
532 offset = (type == B43_DMA_64BIT) ? B43_DMA64_TXSTATUS :
533 B43_DMA32_TXSTATUS;
534 value = b43_read32(dev, mmio_base + offset);
535 if (type == B43_DMA_64BIT) {
536 value &= B43_DMA64_TXSTAT;
537 if (value == B43_DMA64_TXSTAT_DISABLED) {
538 i = -1;
539 break;
540 }
541 } else {
542 value &= B43_DMA32_TXSTATE;
543 if (value == B43_DMA32_TXSTAT_DISABLED) {
544 i = -1;
545 break;
546 }
547 }
548 msleep(1);
549 }
550 if (i != -1) {
551 b43err(dev->wl, "DMA TX reset timed out\n");
552 return -ENODEV;
553 }
554 /* ensure the reset is completed. */
555 msleep(1);
556
557 return 0;
558 }
559
560 /* Check if a DMA mapping address is invalid. */
561 static bool b43_dma_mapping_error(struct b43_dmaring *ring,
562 dma_addr_t addr,
563 size_t buffersize)
564 {
565 if (unlikely(dma_mapping_error(addr)))
566 return 1;
567
568 switch (ring->type) {
569 case B43_DMA_30BIT:
570 if ((u64)addr + buffersize > (1ULL << 30))
571 return 1;
572 break;
573 case B43_DMA_32BIT:
574 if ((u64)addr + buffersize > (1ULL << 32))
575 return 1;
576 break;
577 case B43_DMA_64BIT:
578 /* Currently we can't have addresses beyond
579 * 64bit in the kernel. */
580 break;
581 }
582
583 /* The address is OK. */
584 return 0;
585 }
586
587 static int setup_rx_descbuffer(struct b43_dmaring *ring,
588 struct b43_dmadesc_generic *desc,
589 struct b43_dmadesc_meta *meta, gfp_t gfp_flags)
590 {
591 struct b43_rxhdr_fw4 *rxhdr;
592 struct b43_hwtxstatus *txstat;
593 dma_addr_t dmaaddr;
594 struct sk_buff *skb;
595
596 B43_WARN_ON(ring->tx);
597
598 skb = __dev_alloc_skb(ring->rx_buffersize, gfp_flags);
599 if (unlikely(!skb))
600 return -ENOMEM;
601 dmaaddr = map_descbuffer(ring, skb->data, ring->rx_buffersize, 0);
602 if (b43_dma_mapping_error(ring, dmaaddr, ring->rx_buffersize)) {
603 /* ugh. try to realloc in zone_dma */
604 gfp_flags |= GFP_DMA;
605
606 dev_kfree_skb_any(skb);
607
608 skb = __dev_alloc_skb(ring->rx_buffersize, gfp_flags);
609 if (unlikely(!skb))
610 return -ENOMEM;
611 dmaaddr = map_descbuffer(ring, skb->data,
612 ring->rx_buffersize, 0);
613 }
614
615 if (b43_dma_mapping_error(ring, dmaaddr, ring->rx_buffersize)) {
616 dev_kfree_skb_any(skb);
617 return -EIO;
618 }
619
620 meta->skb = skb;
621 meta->dmaaddr = dmaaddr;
622 ring->ops->fill_descriptor(ring, desc, dmaaddr,
623 ring->rx_buffersize, 0, 0, 0);
624
625 rxhdr = (struct b43_rxhdr_fw4 *)(skb->data);
626 rxhdr->frame_len = 0;
627 txstat = (struct b43_hwtxstatus *)(skb->data);
628 txstat->cookie = 0;
629
630 return 0;
631 }
632
633 /* Allocate the initial descbuffers.
634 * This is used for an RX ring only.
635 */
636 static int alloc_initial_descbuffers(struct b43_dmaring *ring)
637 {
638 int i, err = -ENOMEM;
639 struct b43_dmadesc_generic *desc;
640 struct b43_dmadesc_meta *meta;
641
642 for (i = 0; i < ring->nr_slots; i++) {
643 desc = ring->ops->idx2desc(ring, i, &meta);
644
645 err = setup_rx_descbuffer(ring, desc, meta, GFP_KERNEL);
646 if (err) {
647 b43err(ring->dev->wl,
648 "Failed to allocate initial descbuffers\n");
649 goto err_unwind;
650 }
651 }
652 mb();
653 ring->used_slots = ring->nr_slots;
654 err = 0;
655 out:
656 return err;
657
658 err_unwind:
659 for (i--; i >= 0; i--) {
660 desc = ring->ops->idx2desc(ring, i, &meta);
661
662 unmap_descbuffer(ring, meta->dmaaddr, ring->rx_buffersize, 0);
663 dev_kfree_skb(meta->skb);
664 }
665 goto out;
666 }
667
668 /* Do initial setup of the DMA controller.
669 * Reset the controller, write the ring busaddress
670 * and switch the "enable" bit on.
671 */
672 static int dmacontroller_setup(struct b43_dmaring *ring)
673 {
674 int err = 0;
675 u32 value;
676 u32 addrext;
677 u32 trans = ssb_dma_translation(ring->dev->dev);
678
679 if (ring->tx) {
680 if (ring->type == B43_DMA_64BIT) {
681 u64 ringbase = (u64) (ring->dmabase);
682
683 addrext = ((ringbase >> 32) & SSB_DMA_TRANSLATION_MASK)
684 >> SSB_DMA_TRANSLATION_SHIFT;
685 value = B43_DMA64_TXENABLE;
686 value |= (addrext << B43_DMA64_TXADDREXT_SHIFT)
687 & B43_DMA64_TXADDREXT_MASK;
688 b43_dma_write(ring, B43_DMA64_TXCTL, value);
689 b43_dma_write(ring, B43_DMA64_TXRINGLO,
690 (ringbase & 0xFFFFFFFF));
691 b43_dma_write(ring, B43_DMA64_TXRINGHI,
692 ((ringbase >> 32) &
693 ~SSB_DMA_TRANSLATION_MASK)
694 | (trans << 1));
695 } else {
696 u32 ringbase = (u32) (ring->dmabase);
697
698 addrext = (ringbase & SSB_DMA_TRANSLATION_MASK)
699 >> SSB_DMA_TRANSLATION_SHIFT;
700 value = B43_DMA32_TXENABLE;
701 value |= (addrext << B43_DMA32_TXADDREXT_SHIFT)
702 & B43_DMA32_TXADDREXT_MASK;
703 b43_dma_write(ring, B43_DMA32_TXCTL, value);
704 b43_dma_write(ring, B43_DMA32_TXRING,
705 (ringbase & ~SSB_DMA_TRANSLATION_MASK)
706 | trans);
707 }
708 } else {
709 err = alloc_initial_descbuffers(ring);
710 if (err)
711 goto out;
712 if (ring->type == B43_DMA_64BIT) {
713 u64 ringbase = (u64) (ring->dmabase);
714
715 addrext = ((ringbase >> 32) & SSB_DMA_TRANSLATION_MASK)
716 >> SSB_DMA_TRANSLATION_SHIFT;
717 value = (ring->frameoffset << B43_DMA64_RXFROFF_SHIFT);
718 value |= B43_DMA64_RXENABLE;
719 value |= (addrext << B43_DMA64_RXADDREXT_SHIFT)
720 & B43_DMA64_RXADDREXT_MASK;
721 b43_dma_write(ring, B43_DMA64_RXCTL, value);
722 b43_dma_write(ring, B43_DMA64_RXRINGLO,
723 (ringbase & 0xFFFFFFFF));
724 b43_dma_write(ring, B43_DMA64_RXRINGHI,
725 ((ringbase >> 32) &
726 ~SSB_DMA_TRANSLATION_MASK)
727 | (trans << 1));
728 b43_dma_write(ring, B43_DMA64_RXINDEX, ring->nr_slots *
729 sizeof(struct b43_dmadesc64));
730 } else {
731 u32 ringbase = (u32) (ring->dmabase);
732
733 addrext = (ringbase & SSB_DMA_TRANSLATION_MASK)
734 >> SSB_DMA_TRANSLATION_SHIFT;
735 value = (ring->frameoffset << B43_DMA32_RXFROFF_SHIFT);
736 value |= B43_DMA32_RXENABLE;
737 value |= (addrext << B43_DMA32_RXADDREXT_SHIFT)
738 & B43_DMA32_RXADDREXT_MASK;
739 b43_dma_write(ring, B43_DMA32_RXCTL, value);
740 b43_dma_write(ring, B43_DMA32_RXRING,
741 (ringbase & ~SSB_DMA_TRANSLATION_MASK)
742 | trans);
743 b43_dma_write(ring, B43_DMA32_RXINDEX, ring->nr_slots *
744 sizeof(struct b43_dmadesc32));
745 }
746 }
747
748 out:
749 return err;
750 }
751
752 /* Shutdown the DMA controller. */
753 static void dmacontroller_cleanup(struct b43_dmaring *ring)
754 {
755 if (ring->tx) {
756 b43_dmacontroller_tx_reset(ring->dev, ring->mmio_base,
757 ring->type);
758 if (ring->type == B43_DMA_64BIT) {
759 b43_dma_write(ring, B43_DMA64_TXRINGLO, 0);
760 b43_dma_write(ring, B43_DMA64_TXRINGHI, 0);
761 } else
762 b43_dma_write(ring, B43_DMA32_TXRING, 0);
763 } else {
764 b43_dmacontroller_rx_reset(ring->dev, ring->mmio_base,
765 ring->type);
766 if (ring->type == B43_DMA_64BIT) {
767 b43_dma_write(ring, B43_DMA64_RXRINGLO, 0);
768 b43_dma_write(ring, B43_DMA64_RXRINGHI, 0);
769 } else
770 b43_dma_write(ring, B43_DMA32_RXRING, 0);
771 }
772 }
773
774 static void free_all_descbuffers(struct b43_dmaring *ring)
775 {
776 struct b43_dmadesc_generic *desc;
777 struct b43_dmadesc_meta *meta;
778 int i;
779
780 if (!ring->used_slots)
781 return;
782 for (i = 0; i < ring->nr_slots; i++) {
783 desc = ring->ops->idx2desc(ring, i, &meta);
784
785 if (!meta->skb) {
786 B43_WARN_ON(!ring->tx);
787 continue;
788 }
789 if (ring->tx) {
790 unmap_descbuffer(ring, meta->dmaaddr,
791 meta->skb->len, 1);
792 } else {
793 unmap_descbuffer(ring, meta->dmaaddr,
794 ring->rx_buffersize, 0);
795 }
796 free_descriptor_buffer(ring, meta);
797 }
798 }
799
800 static u64 supported_dma_mask(struct b43_wldev *dev)
801 {
802 u32 tmp;
803 u16 mmio_base;
804
805 tmp = b43_read32(dev, SSB_TMSHIGH);
806 if (tmp & SSB_TMSHIGH_DMA64)
807 return DMA_64BIT_MASK;
808 mmio_base = b43_dmacontroller_base(0, 0);
809 b43_write32(dev, mmio_base + B43_DMA32_TXCTL, B43_DMA32_TXADDREXT_MASK);
810 tmp = b43_read32(dev, mmio_base + B43_DMA32_TXCTL);
811 if (tmp & B43_DMA32_TXADDREXT_MASK)
812 return DMA_32BIT_MASK;
813
814 return DMA_30BIT_MASK;
815 }
816
817 /* Main initialization function. */
818 static
819 struct b43_dmaring *b43_setup_dmaring(struct b43_wldev *dev,
820 int controller_index,
821 int for_tx,
822 enum b43_dmatype type)
823 {
824 struct b43_dmaring *ring;
825 int err;
826 int nr_slots;
827 dma_addr_t dma_test;
828
829 ring = kzalloc(sizeof(*ring), GFP_KERNEL);
830 if (!ring)
831 goto out;
832 ring->type = type;
833
834 nr_slots = B43_RXRING_SLOTS;
835 if (for_tx)
836 nr_slots = B43_TXRING_SLOTS;
837
838 ring->meta = kcalloc(nr_slots, sizeof(struct b43_dmadesc_meta),
839 GFP_KERNEL);
840 if (!ring->meta)
841 goto err_kfree_ring;
842 if (for_tx) {
843 ring->txhdr_cache = kcalloc(nr_slots,
844 b43_txhdr_size(dev),
845 GFP_KERNEL);
846 if (!ring->txhdr_cache)
847 goto err_kfree_meta;
848
849 /* test for ability to dma to txhdr_cache */
850 dma_test = dma_map_single(dev->dev->dev,
851 ring->txhdr_cache,
852 b43_txhdr_size(dev),
853 DMA_TO_DEVICE);
854
855 if (b43_dma_mapping_error(ring, dma_test, b43_txhdr_size(dev))) {
856 /* ugh realloc */
857 kfree(ring->txhdr_cache);
858 ring->txhdr_cache = kcalloc(nr_slots,
859 b43_txhdr_size(dev),
860 GFP_KERNEL | GFP_DMA);
861 if (!ring->txhdr_cache)
862 goto err_kfree_meta;
863
864 dma_test = dma_map_single(dev->dev->dev,
865 ring->txhdr_cache,
866 b43_txhdr_size(dev),
867 DMA_TO_DEVICE);
868
869 if (b43_dma_mapping_error(ring, dma_test,
870 b43_txhdr_size(dev)))
871 goto err_kfree_txhdr_cache;
872 }
873
874 dma_unmap_single(dev->dev->dev,
875 dma_test, b43_txhdr_size(dev),
876 DMA_TO_DEVICE);
877 }
878
879 ring->dev = dev;
880 ring->nr_slots = nr_slots;
881 ring->mmio_base = b43_dmacontroller_base(type, controller_index);
882 ring->index = controller_index;
883 if (type == B43_DMA_64BIT)
884 ring->ops = &dma64_ops;
885 else
886 ring->ops = &dma32_ops;
887 if (for_tx) {
888 ring->tx = 1;
889 ring->current_slot = -1;
890 } else {
891 if (ring->index == 0) {
892 ring->rx_buffersize = B43_DMA0_RX_BUFFERSIZE;
893 ring->frameoffset = B43_DMA0_RX_FRAMEOFFSET;
894 } else if (ring->index == 3) {
895 ring->rx_buffersize = B43_DMA3_RX_BUFFERSIZE;
896 ring->frameoffset = B43_DMA3_RX_FRAMEOFFSET;
897 } else
898 B43_WARN_ON(1);
899 }
900 spin_lock_init(&ring->lock);
901 #ifdef CONFIG_B43_DEBUG
902 ring->last_injected_overflow = jiffies;
903 #endif
904
905 err = alloc_ringmemory(ring);
906 if (err)
907 goto err_kfree_txhdr_cache;
908 err = dmacontroller_setup(ring);
909 if (err)
910 goto err_free_ringmemory;
911
912 out:
913 return ring;
914
915 err_free_ringmemory:
916 free_ringmemory(ring);
917 err_kfree_txhdr_cache:
918 kfree(ring->txhdr_cache);
919 err_kfree_meta:
920 kfree(ring->meta);
921 err_kfree_ring:
922 kfree(ring);
923 ring = NULL;
924 goto out;
925 }
926
927 /* Main cleanup function. */
928 static void b43_destroy_dmaring(struct b43_dmaring *ring)
929 {
930 if (!ring)
931 return;
932
933 b43dbg(ring->dev->wl, "DMA-%u 0x%04X (%s) max used slots: %d/%d\n",
934 (unsigned int)(ring->type),
935 ring->mmio_base,
936 (ring->tx) ? "TX" : "RX", ring->max_used_slots, ring->nr_slots);
937 /* Device IRQs are disabled prior entering this function,
938 * so no need to take care of concurrency with rx handler stuff.
939 */
940 dmacontroller_cleanup(ring);
941 free_all_descbuffers(ring);
942 free_ringmemory(ring);
943
944 kfree(ring->txhdr_cache);
945 kfree(ring->meta);
946 kfree(ring);
947 }
948
949 void b43_dma_free(struct b43_wldev *dev)
950 {
951 struct b43_dma *dma = &dev->dma;
952
953 b43_destroy_dmaring(dma->rx_ring3);
954 dma->rx_ring3 = NULL;
955 b43_destroy_dmaring(dma->rx_ring0);
956 dma->rx_ring0 = NULL;
957
958 b43_destroy_dmaring(dma->tx_ring5);
959 dma->tx_ring5 = NULL;
960 b43_destroy_dmaring(dma->tx_ring4);
961 dma->tx_ring4 = NULL;
962 b43_destroy_dmaring(dma->tx_ring3);
963 dma->tx_ring3 = NULL;
964 b43_destroy_dmaring(dma->tx_ring2);
965 dma->tx_ring2 = NULL;
966 b43_destroy_dmaring(dma->tx_ring1);
967 dma->tx_ring1 = NULL;
968 b43_destroy_dmaring(dma->tx_ring0);
969 dma->tx_ring0 = NULL;
970 }
971
972 int b43_dma_init(struct b43_wldev *dev)
973 {
974 struct b43_dma *dma = &dev->dma;
975 struct b43_dmaring *ring;
976 int err;
977 u64 dmamask;
978 enum b43_dmatype type;
979
980 dmamask = supported_dma_mask(dev);
981 switch (dmamask) {
982 default:
983 B43_WARN_ON(1);
984 case DMA_30BIT_MASK:
985 type = B43_DMA_30BIT;
986 break;
987 case DMA_32BIT_MASK:
988 type = B43_DMA_32BIT;
989 break;
990 case DMA_64BIT_MASK:
991 type = B43_DMA_64BIT;
992 break;
993 }
994 err = ssb_dma_set_mask(dev->dev, dmamask);
995 if (err) {
996 b43err(dev->wl, "The machine/kernel does not support "
997 "the required DMA mask (0x%08X%08X)\n",
998 (unsigned int)((dmamask & 0xFFFFFFFF00000000ULL) >> 32),
999 (unsigned int)(dmamask & 0x00000000FFFFFFFFULL));
1000 return -EOPNOTSUPP;
1001 }
1002
1003 err = -ENOMEM;
1004 /* setup TX DMA channels. */
1005 ring = b43_setup_dmaring(dev, 0, 1, type);
1006 if (!ring)
1007 goto out;
1008 dma->tx_ring0 = ring;
1009
1010 ring = b43_setup_dmaring(dev, 1, 1, type);
1011 if (!ring)
1012 goto err_destroy_tx0;
1013 dma->tx_ring1 = ring;
1014
1015 ring = b43_setup_dmaring(dev, 2, 1, type);
1016 if (!ring)
1017 goto err_destroy_tx1;
1018 dma->tx_ring2 = ring;
1019
1020 ring = b43_setup_dmaring(dev, 3, 1, type);
1021 if (!ring)
1022 goto err_destroy_tx2;
1023 dma->tx_ring3 = ring;
1024
1025 ring = b43_setup_dmaring(dev, 4, 1, type);
1026 if (!ring)
1027 goto err_destroy_tx3;
1028 dma->tx_ring4 = ring;
1029
1030 ring = b43_setup_dmaring(dev, 5, 1, type);
1031 if (!ring)
1032 goto err_destroy_tx4;
1033 dma->tx_ring5 = ring;
1034
1035 /* setup RX DMA channels. */
1036 ring = b43_setup_dmaring(dev, 0, 0, type);
1037 if (!ring)
1038 goto err_destroy_tx5;
1039 dma->rx_ring0 = ring;
1040
1041 if (dev->dev->id.revision < 5) {
1042 ring = b43_setup_dmaring(dev, 3, 0, type);
1043 if (!ring)
1044 goto err_destroy_rx0;
1045 dma->rx_ring3 = ring;
1046 }
1047
1048 b43dbg(dev->wl, "%u-bit DMA initialized\n",
1049 (unsigned int)type);
1050 err = 0;
1051 out:
1052 return err;
1053
1054 err_destroy_rx0:
1055 b43_destroy_dmaring(dma->rx_ring0);
1056 dma->rx_ring0 = NULL;
1057 err_destroy_tx5:
1058 b43_destroy_dmaring(dma->tx_ring5);
1059 dma->tx_ring5 = NULL;
1060 err_destroy_tx4:
1061 b43_destroy_dmaring(dma->tx_ring4);
1062 dma->tx_ring4 = NULL;
1063 err_destroy_tx3:
1064 b43_destroy_dmaring(dma->tx_ring3);
1065 dma->tx_ring3 = NULL;
1066 err_destroy_tx2:
1067 b43_destroy_dmaring(dma->tx_ring2);
1068 dma->tx_ring2 = NULL;
1069 err_destroy_tx1:
1070 b43_destroy_dmaring(dma->tx_ring1);
1071 dma->tx_ring1 = NULL;
1072 err_destroy_tx0:
1073 b43_destroy_dmaring(dma->tx_ring0);
1074 dma->tx_ring0 = NULL;
1075 goto out;
1076 }
1077
1078 /* Generate a cookie for the TX header. */
1079 static u16 generate_cookie(struct b43_dmaring *ring, int slot)
1080 {
1081 u16 cookie = 0x1000;
1082
1083 /* Use the upper 4 bits of the cookie as
1084 * DMA controller ID and store the slot number
1085 * in the lower 12 bits.
1086 * Note that the cookie must never be 0, as this
1087 * is a special value used in RX path.
1088 * It can also not be 0xFFFF because that is special
1089 * for multicast frames.
1090 */
1091 switch (ring->index) {
1092 case 0:
1093 cookie = 0x1000;
1094 break;
1095 case 1:
1096 cookie = 0x2000;
1097 break;
1098 case 2:
1099 cookie = 0x3000;
1100 break;
1101 case 3:
1102 cookie = 0x4000;
1103 break;
1104 case 4:
1105 cookie = 0x5000;
1106 break;
1107 case 5:
1108 cookie = 0x6000;
1109 break;
1110 default:
1111 B43_WARN_ON(1);
1112 }
1113 B43_WARN_ON(slot & ~0x0FFF);
1114 cookie |= (u16) slot;
1115
1116 return cookie;
1117 }
1118
1119 /* Inspect a cookie and find out to which controller/slot it belongs. */
1120 static
1121 struct b43_dmaring *parse_cookie(struct b43_wldev *dev, u16 cookie, int *slot)
1122 {
1123 struct b43_dma *dma = &dev->dma;
1124 struct b43_dmaring *ring = NULL;
1125
1126 switch (cookie & 0xF000) {
1127 case 0x1000:
1128 ring = dma->tx_ring0;
1129 break;
1130 case 0x2000:
1131 ring = dma->tx_ring1;
1132 break;
1133 case 0x3000:
1134 ring = dma->tx_ring2;
1135 break;
1136 case 0x4000:
1137 ring = dma->tx_ring3;
1138 break;
1139 case 0x5000:
1140 ring = dma->tx_ring4;
1141 break;
1142 case 0x6000:
1143 ring = dma->tx_ring5;
1144 break;
1145 default:
1146 B43_WARN_ON(1);
1147 }
1148 *slot = (cookie & 0x0FFF);
1149 B43_WARN_ON(!(ring && *slot >= 0 && *slot < ring->nr_slots));
1150
1151 return ring;
1152 }
1153
1154 static int dma_tx_fragment(struct b43_dmaring *ring,
1155 struct sk_buff *skb,
1156 struct ieee80211_tx_control *ctl)
1157 {
1158 const struct b43_dma_ops *ops = ring->ops;
1159 u8 *header;
1160 int slot, old_top_slot, old_used_slots;
1161 int err;
1162 struct b43_dmadesc_generic *desc;
1163 struct b43_dmadesc_meta *meta;
1164 struct b43_dmadesc_meta *meta_hdr;
1165 struct sk_buff *bounce_skb;
1166 u16 cookie;
1167 size_t hdrsize = b43_txhdr_size(ring->dev);
1168
1169 #define SLOTS_PER_PACKET 2
1170 B43_WARN_ON(skb_shinfo(skb)->nr_frags);
1171
1172 old_top_slot = ring->current_slot;
1173 old_used_slots = ring->used_slots;
1174
1175 /* Get a slot for the header. */
1176 slot = request_slot(ring);
1177 desc = ops->idx2desc(ring, slot, &meta_hdr);
1178 memset(meta_hdr, 0, sizeof(*meta_hdr));
1179
1180 header = &(ring->txhdr_cache[slot * hdrsize]);
1181 cookie = generate_cookie(ring, slot);
1182 err = b43_generate_txhdr(ring->dev, header,
1183 skb->data, skb->len, ctl, cookie);
1184 if (unlikely(err)) {
1185 ring->current_slot = old_top_slot;
1186 ring->used_slots = old_used_slots;
1187 return err;
1188 }
1189
1190 meta_hdr->dmaaddr = map_descbuffer(ring, (unsigned char *)header,
1191 hdrsize, 1);
1192 if (b43_dma_mapping_error(ring, meta_hdr->dmaaddr, hdrsize)) {
1193 ring->current_slot = old_top_slot;
1194 ring->used_slots = old_used_slots;
1195 return -EIO;
1196 }
1197 ops->fill_descriptor(ring, desc, meta_hdr->dmaaddr,
1198 hdrsize, 1, 0, 0);
1199
1200 /* Get a slot for the payload. */
1201 slot = request_slot(ring);
1202 desc = ops->idx2desc(ring, slot, &meta);
1203 memset(meta, 0, sizeof(*meta));
1204
1205 memcpy(&meta->txstat.control, ctl, sizeof(*ctl));
1206 meta->skb = skb;
1207 meta->is_last_fragment = 1;
1208
1209 meta->dmaaddr = map_descbuffer(ring, skb->data, skb->len, 1);
1210 /* create a bounce buffer in zone_dma on mapping failure. */
1211 if (b43_dma_mapping_error(ring, meta->dmaaddr, skb->len)) {
1212 bounce_skb = __dev_alloc_skb(skb->len, GFP_ATOMIC | GFP_DMA);
1213 if (!bounce_skb) {
1214 ring->current_slot = old_top_slot;
1215 ring->used_slots = old_used_slots;
1216 err = -ENOMEM;
1217 goto out_unmap_hdr;
1218 }
1219
1220 memcpy(skb_put(bounce_skb, skb->len), skb->data, skb->len);
1221 dev_kfree_skb_any(skb);
1222 skb = bounce_skb;
1223 meta->skb = skb;
1224 meta->dmaaddr = map_descbuffer(ring, skb->data, skb->len, 1);
1225 if (b43_dma_mapping_error(ring, meta->dmaaddr, skb->len)) {
1226 ring->current_slot = old_top_slot;
1227 ring->used_slots = old_used_slots;
1228 err = -EIO;
1229 goto out_free_bounce;
1230 }
1231 }
1232
1233 ops->fill_descriptor(ring, desc, meta->dmaaddr, skb->len, 0, 1, 1);
1234
1235 if (ctl->flags & IEEE80211_TXCTL_SEND_AFTER_DTIM) {
1236 /* Tell the firmware about the cookie of the last
1237 * mcast frame, so it can clear the more-data bit in it. */
1238 b43_shm_write16(ring->dev, B43_SHM_SHARED,
1239 B43_SHM_SH_MCASTCOOKIE, cookie);
1240 }
1241 /* Now transfer the whole frame. */
1242 wmb();
1243 ops->poke_tx(ring, next_slot(ring, slot));
1244 return 0;
1245
1246 out_free_bounce:
1247 dev_kfree_skb_any(skb);
1248 out_unmap_hdr:
1249 unmap_descbuffer(ring, meta_hdr->dmaaddr,
1250 hdrsize, 1);
1251 return err;
1252 }
1253
1254 static inline int should_inject_overflow(struct b43_dmaring *ring)
1255 {
1256 #ifdef CONFIG_B43_DEBUG
1257 if (unlikely(b43_debug(ring->dev, B43_DBG_DMAOVERFLOW))) {
1258 /* Check if we should inject another ringbuffer overflow
1259 * to test handling of this situation in the stack. */
1260 unsigned long next_overflow;
1261
1262 next_overflow = ring->last_injected_overflow + HZ;
1263 if (time_after(jiffies, next_overflow)) {
1264 ring->last_injected_overflow = jiffies;
1265 b43dbg(ring->dev->wl,
1266 "Injecting TX ring overflow on "
1267 "DMA controller %d\n", ring->index);
1268 return 1;
1269 }
1270 }
1271 #endif /* CONFIG_B43_DEBUG */
1272 return 0;
1273 }
1274
1275 int b43_dma_tx(struct b43_wldev *dev,
1276 struct sk_buff *skb, struct ieee80211_tx_control *ctl)
1277 {
1278 struct b43_dmaring *ring;
1279 struct ieee80211_hdr *hdr;
1280 int err = 0;
1281 unsigned long flags;
1282
1283 if (unlikely(skb->len < 2 + 2 + 6)) {
1284 /* Too short, this can't be a valid frame. */
1285 return -EINVAL;
1286 }
1287
1288 hdr = (struct ieee80211_hdr *)skb->data;
1289 if (ctl->flags & IEEE80211_TXCTL_SEND_AFTER_DTIM) {
1290 /* The multicast ring will be sent after the DTIM */
1291 ring = dev->dma.tx_ring4;
1292 /* Set the more-data bit. Ucode will clear it on
1293 * the last frame for us. */
1294 hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_MOREDATA);
1295 } else {
1296 /* Decide by priority where to put this frame. */
1297 ring = priority_to_txring(dev, ctl->queue);
1298 }
1299
1300 spin_lock_irqsave(&ring->lock, flags);
1301 B43_WARN_ON(!ring->tx);
1302 if (unlikely(free_slots(ring) < SLOTS_PER_PACKET)) {
1303 b43warn(dev->wl, "DMA queue overflow\n");
1304 err = -ENOSPC;
1305 goto out_unlock;
1306 }
1307 /* Check if the queue was stopped in mac80211,
1308 * but we got called nevertheless.
1309 * That would be a mac80211 bug. */
1310 B43_WARN_ON(ring->stopped);
1311
1312 err = dma_tx_fragment(ring, skb, ctl);
1313 if (unlikely(err == -ENOKEY)) {
1314 /* Drop this packet, as we don't have the encryption key
1315 * anymore and must not transmit it unencrypted. */
1316 dev_kfree_skb_any(skb);
1317 err = 0;
1318 goto out_unlock;
1319 }
1320 if (unlikely(err)) {
1321 b43err(dev->wl, "DMA tx mapping failure\n");
1322 goto out_unlock;
1323 }
1324 ring->nr_tx_packets++;
1325 if ((free_slots(ring) < SLOTS_PER_PACKET) ||
1326 should_inject_overflow(ring)) {
1327 /* This TX ring is full. */
1328 ieee80211_stop_queue(dev->wl->hw, txring_to_priority(ring));
1329 ring->stopped = 1;
1330 if (b43_debug(dev, B43_DBG_DMAVERBOSE)) {
1331 b43dbg(dev->wl, "Stopped TX ring %d\n", ring->index);
1332 }
1333 }
1334 out_unlock:
1335 spin_unlock_irqrestore(&ring->lock, flags);
1336
1337 return err;
1338 }
1339
1340 void b43_dma_handle_txstatus(struct b43_wldev *dev,
1341 const struct b43_txstatus *status)
1342 {
1343 const struct b43_dma_ops *ops;
1344 struct b43_dmaring *ring;
1345 struct b43_dmadesc_generic *desc;
1346 struct b43_dmadesc_meta *meta;
1347 int slot;
1348
1349 ring = parse_cookie(dev, status->cookie, &slot);
1350 if (unlikely(!ring))
1351 return;
1352 B43_WARN_ON(!irqs_disabled());
1353 spin_lock(&ring->lock);
1354
1355 B43_WARN_ON(!ring->tx);
1356 ops = ring->ops;
1357 while (1) {
1358 B43_WARN_ON(!(slot >= 0 && slot < ring->nr_slots));
1359 desc = ops->idx2desc(ring, slot, &meta);
1360
1361 if (meta->skb)
1362 unmap_descbuffer(ring, meta->dmaaddr, meta->skb->len,
1363 1);
1364 else
1365 unmap_descbuffer(ring, meta->dmaaddr,
1366 b43_txhdr_size(dev), 1);
1367
1368 if (meta->is_last_fragment) {
1369 B43_WARN_ON(!meta->skb);
1370 /* Call back to inform the ieee80211 subsystem about the
1371 * status of the transmission.
1372 * Some fields of txstat are already filled in dma_tx().
1373 */
1374 if (status->acked) {
1375 meta->txstat.flags |= IEEE80211_TX_STATUS_ACK;
1376 } else {
1377 if (!(meta->txstat.control.flags
1378 & IEEE80211_TXCTL_NO_ACK))
1379 meta->txstat.excessive_retries = 1;
1380 }
1381 if (status->frame_count == 0) {
1382 /* The frame was not transmitted at all. */
1383 meta->txstat.retry_count = 0;
1384 } else
1385 meta->txstat.retry_count = status->frame_count - 1;
1386 ieee80211_tx_status_irqsafe(dev->wl->hw, meta->skb,
1387 &(meta->txstat));
1388 /* skb is freed by ieee80211_tx_status_irqsafe() */
1389 meta->skb = NULL;
1390 } else {
1391 /* No need to call free_descriptor_buffer here, as
1392 * this is only the txhdr, which is not allocated.
1393 */
1394 B43_WARN_ON(meta->skb);
1395 }
1396
1397 /* Everything unmapped and free'd. So it's not used anymore. */
1398 ring->used_slots--;
1399
1400 if (meta->is_last_fragment)
1401 break;
1402 slot = next_slot(ring, slot);
1403 }
1404 dev->stats.last_tx = jiffies;
1405 if (ring->stopped) {
1406 B43_WARN_ON(free_slots(ring) < SLOTS_PER_PACKET);
1407 ieee80211_wake_queue(dev->wl->hw, txring_to_priority(ring));
1408 ring->stopped = 0;
1409 if (b43_debug(dev, B43_DBG_DMAVERBOSE)) {
1410 b43dbg(dev->wl, "Woke up TX ring %d\n", ring->index);
1411 }
1412 }
1413
1414 spin_unlock(&ring->lock);
1415 }
1416
1417 void b43_dma_get_tx_stats(struct b43_wldev *dev,
1418 struct ieee80211_tx_queue_stats *stats)
1419 {
1420 const int nr_queues = dev->wl->hw->queues;
1421 struct b43_dmaring *ring;
1422 struct ieee80211_tx_queue_stats_data *data;
1423 unsigned long flags;
1424 int i;
1425
1426 for (i = 0; i < nr_queues; i++) {
1427 data = &(stats->data[i]);
1428 ring = priority_to_txring(dev, i);
1429
1430 spin_lock_irqsave(&ring->lock, flags);
1431 data->len = ring->used_slots / SLOTS_PER_PACKET;
1432 data->limit = ring->nr_slots / SLOTS_PER_PACKET;
1433 data->count = ring->nr_tx_packets;
1434 spin_unlock_irqrestore(&ring->lock, flags);
1435 }
1436 }
1437
1438 static void dma_rx(struct b43_dmaring *ring, int *slot)
1439 {
1440 const struct b43_dma_ops *ops = ring->ops;
1441 struct b43_dmadesc_generic *desc;
1442 struct b43_dmadesc_meta *meta;
1443 struct b43_rxhdr_fw4 *rxhdr;
1444 struct sk_buff *skb;
1445 u16 len;
1446 int err;
1447 dma_addr_t dmaaddr;
1448
1449 desc = ops->idx2desc(ring, *slot, &meta);
1450
1451 sync_descbuffer_for_cpu(ring, meta->dmaaddr, ring->rx_buffersize);
1452 skb = meta->skb;
1453
1454 if (ring->index == 3) {
1455 /* We received an xmit status. */
1456 struct b43_hwtxstatus *hw = (struct b43_hwtxstatus *)skb->data;
1457 int i = 0;
1458
1459 while (hw->cookie == 0) {
1460 if (i > 100)
1461 break;
1462 i++;
1463 udelay(2);
1464 barrier();
1465 }
1466 b43_handle_hwtxstatus(ring->dev, hw);
1467 /* recycle the descriptor buffer. */
1468 sync_descbuffer_for_device(ring, meta->dmaaddr,
1469 ring->rx_buffersize);
1470
1471 return;
1472 }
1473 rxhdr = (struct b43_rxhdr_fw4 *)skb->data;
1474 len = le16_to_cpu(rxhdr->frame_len);
1475 if (len == 0) {
1476 int i = 0;
1477
1478 do {
1479 udelay(2);
1480 barrier();
1481 len = le16_to_cpu(rxhdr->frame_len);
1482 } while (len == 0 && i++ < 5);
1483 if (unlikely(len == 0)) {
1484 /* recycle the descriptor buffer. */
1485 sync_descbuffer_for_device(ring, meta->dmaaddr,
1486 ring->rx_buffersize);
1487 goto drop;
1488 }
1489 }
1490 if (unlikely(len > ring->rx_buffersize)) {
1491 /* The data did not fit into one descriptor buffer
1492 * and is split over multiple buffers.
1493 * This should never happen, as we try to allocate buffers
1494 * big enough. So simply ignore this packet.
1495 */
1496 int cnt = 0;
1497 s32 tmp = len;
1498
1499 while (1) {
1500 desc = ops->idx2desc(ring, *slot, &meta);
1501 /* recycle the descriptor buffer. */
1502 sync_descbuffer_for_device(ring, meta->dmaaddr,
1503 ring->rx_buffersize);
1504 *slot = next_slot(ring, *slot);
1505 cnt++;
1506 tmp -= ring->rx_buffersize;
1507 if (tmp <= 0)
1508 break;
1509 }
1510 b43err(ring->dev->wl, "DMA RX buffer too small "
1511 "(len: %u, buffer: %u, nr-dropped: %d)\n",
1512 len, ring->rx_buffersize, cnt);
1513 goto drop;
1514 }
1515
1516 dmaaddr = meta->dmaaddr;
1517 err = setup_rx_descbuffer(ring, desc, meta, GFP_ATOMIC);
1518 if (unlikely(err)) {
1519 b43dbg(ring->dev->wl, "DMA RX: setup_rx_descbuffer() failed\n");
1520 sync_descbuffer_for_device(ring, dmaaddr, ring->rx_buffersize);
1521 goto drop;
1522 }
1523
1524 unmap_descbuffer(ring, dmaaddr, ring->rx_buffersize, 0);
1525 skb_put(skb, len + ring->frameoffset);
1526 skb_pull(skb, ring->frameoffset);
1527
1528 b43_rx(ring->dev, skb, rxhdr);
1529 drop:
1530 return;
1531 }
1532
1533 void b43_dma_rx(struct b43_dmaring *ring)
1534 {
1535 const struct b43_dma_ops *ops = ring->ops;
1536 int slot, current_slot;
1537 int used_slots = 0;
1538
1539 B43_WARN_ON(ring->tx);
1540 current_slot = ops->get_current_rxslot(ring);
1541 B43_WARN_ON(!(current_slot >= 0 && current_slot < ring->nr_slots));
1542
1543 slot = ring->current_slot;
1544 for (; slot != current_slot; slot = next_slot(ring, slot)) {
1545 dma_rx(ring, &slot);
1546 update_max_used_slots(ring, ++used_slots);
1547 }
1548 ops->set_current_rxslot(ring, slot);
1549 ring->current_slot = slot;
1550 }
1551
1552 static void b43_dma_tx_suspend_ring(struct b43_dmaring *ring)
1553 {
1554 unsigned long flags;
1555
1556 spin_lock_irqsave(&ring->lock, flags);
1557 B43_WARN_ON(!ring->tx);
1558 ring->ops->tx_suspend(ring);
1559 spin_unlock_irqrestore(&ring->lock, flags);
1560 }
1561
1562 static void b43_dma_tx_resume_ring(struct b43_dmaring *ring)
1563 {
1564 unsigned long flags;
1565
1566 spin_lock_irqsave(&ring->lock, flags);
1567 B43_WARN_ON(!ring->tx);
1568 ring->ops->tx_resume(ring);
1569 spin_unlock_irqrestore(&ring->lock, flags);
1570 }
1571
1572 void b43_dma_tx_suspend(struct b43_wldev *dev)
1573 {
1574 b43_power_saving_ctl_bits(dev, B43_PS_AWAKE);
1575 b43_dma_tx_suspend_ring(dev->dma.tx_ring0);
1576 b43_dma_tx_suspend_ring(dev->dma.tx_ring1);
1577 b43_dma_tx_suspend_ring(dev->dma.tx_ring2);
1578 b43_dma_tx_suspend_ring(dev->dma.tx_ring3);
1579 b43_dma_tx_suspend_ring(dev->dma.tx_ring4);
1580 b43_dma_tx_suspend_ring(dev->dma.tx_ring5);
1581 }
1582
1583 void b43_dma_tx_resume(struct b43_wldev *dev)
1584 {
1585 b43_dma_tx_resume_ring(dev->dma.tx_ring5);
1586 b43_dma_tx_resume_ring(dev->dma.tx_ring4);
1587 b43_dma_tx_resume_ring(dev->dma.tx_ring3);
1588 b43_dma_tx_resume_ring(dev->dma.tx_ring2);
1589 b43_dma_tx_resume_ring(dev->dma.tx_ring1);
1590 b43_dma_tx_resume_ring(dev->dma.tx_ring0);
1591 b43_power_saving_ctl_bits(dev, 0);
1592 }
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