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Also forgot adding the adm5120_info file
[openwrt.git] / target / linux / ar7-2.6 / files / drivers / net / cpmac.c
1 /*
2 * $Id$
3 *
4 * Copyright (C) 2006, 2007 OpenWrt.org
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
19 */
20
21 #include <linux/module.h>
22 #include <linux/init.h>
23 #include <linux/moduleparam.h>
24
25 #include <linux/sched.h>
26 #include <linux/kernel.h> /* printk() */
27 #include <linux/slab.h>
28 #include <linux/errno.h>
29 #include <linux/types.h>
30 #include <linux/delay.h>
31
32 #include <linux/netdevice.h>
33 #include <linux/etherdevice.h>
34 #include <linux/ethtool.h>
35 #include <linux/skbuff.h>
36 #include <linux/mii.h>
37 #include <linux/phy.h>
38 #include <linux/platform_device.h>
39 #include <asm/ar7/ar7.h>
40 #include <asm/gpio.h>
41
42 MODULE_AUTHOR("Eugene Konev");
43 MODULE_DESCRIPTION("TI AR7 ethernet driver (CPMAC)");
44 MODULE_LICENSE("GPL");
45
46 /* Register definitions */
47 struct cpmac_control_regs {
48 volatile u32 revision;
49 volatile u32 control;
50 volatile u32 teardown;
51 volatile u32 unused;
52 };
53
54 struct cpmac_int_regs {
55 volatile u32 stat_raw;
56 volatile u32 stat_masked;
57 volatile u32 enable;
58 volatile u32 clear;
59 };
60
61 struct cpmac_stats {
62 volatile u32 good;
63 volatile u32 bcast;
64 volatile u32 mcast;
65 volatile u32 pause;
66 volatile u32 crc_error;
67 volatile u32 align_error;
68 volatile u32 oversized;
69 volatile u32 jabber;
70 volatile u32 undersized;
71 volatile u32 fragment;
72 volatile u32 filtered;
73 volatile u32 qos_filtered;
74 volatile u32 octets;
75 };
76
77 struct cpmac_regs {
78 struct cpmac_control_regs tx_ctrl;
79 struct cpmac_control_regs rx_ctrl;
80 volatile u32 unused1[56];
81 volatile u32 mbp;
82 /* MBP bits */
83 #define MBP_RXPASSCRC 0x40000000
84 #define MBP_RXQOS 0x20000000
85 #define MBP_RXNOCHAIN 0x10000000
86 #define MBP_RXCMF 0x01000000
87 #define MBP_RXSHORT 0x00800000
88 #define MBP_RXCEF 0x00400000
89 #define MBP_RXPROMISC 0x00200000
90 #define MBP_PROMISCCHAN(chan) (((chan) & 0x7) << 16)
91 #define MBP_RXBCAST 0x00002000
92 #define MBP_BCASTCHAN(chan) (((chan) & 0x7) << 8)
93 #define MBP_RXMCAST 0x00000020
94 #define MBP_MCASTCHAN(chan) ((chan) & 0x7)
95 volatile u32 unicast_enable;
96 volatile u32 unicast_clear;
97 volatile u32 max_len;
98 volatile u32 buffer_offset;
99 volatile u32 filter_flow_threshold;
100 volatile u32 unused2[2];
101 volatile u32 flow_thre[8];
102 volatile u32 free_buffer[8];
103 volatile u32 mac_control;
104 #define MAC_TXPTYPE 0x00000200
105 #define MAC_TXPACE 0x00000040
106 #define MAC_MII 0x00000020
107 #define MAC_TXFLOW 0x00000010
108 #define MAC_RXFLOW 0x00000008
109 #define MAC_MTEST 0x00000004
110 #define MAC_LOOPBACK 0x00000002
111 #define MAC_FDX 0x00000001
112 volatile u32 mac_status;
113 #define MACST_QOS 0x4
114 #define MACST_RXFLOW 0x2
115 #define MACST_TXFLOW 0x1
116 volatile u32 emc_control;
117 volatile u32 unused3;
118 struct cpmac_int_regs tx_int;
119 volatile u32 mac_int_vector;
120 /* Int Status bits */
121 #define INTST_STATUS 0x80000
122 #define INTST_HOST 0x40000
123 #define INTST_RX 0x20000
124 #define INTST_TX 0x10000
125 volatile u32 mac_eoi_vector;
126 volatile u32 unused4[2];
127 struct cpmac_int_regs rx_int;
128 volatile u32 mac_int_stat_raw;
129 volatile u32 mac_int_stat_masked;
130 volatile u32 mac_int_enable;
131 volatile u32 mac_int_clear;
132 volatile u32 mac_addr_low[8];
133 volatile u32 mac_addr_mid;
134 volatile u32 mac_addr_high;
135 volatile u32 mac_hash_low;
136 volatile u32 mac_hash_high;
137 volatile u32 boff_test;
138 volatile u32 pac_test;
139 volatile u32 rx_pause;
140 volatile u32 tx_pause;
141 volatile u32 unused5[2];
142 struct cpmac_stats rx_stats;
143 struct cpmac_stats tx_stats;
144 volatile u32 unused6[232];
145 volatile u32 tx_ptr[8];
146 volatile u32 rx_ptr[8];
147 volatile u32 tx_ack[8];
148 volatile u32 rx_ack[8];
149
150 };
151
152 struct cpmac_mdio_regs {
153 volatile u32 version;
154 volatile u32 control;
155 #define MDIOC_IDLE 0x80000000
156 #define MDIOC_ENABLE 0x40000000
157 #define MDIOC_PREAMBLE 0x00100000
158 #define MDIOC_FAULT 0x00080000
159 #define MDIOC_FAULTDETECT 0x00040000
160 #define MDIOC_INTTEST 0x00020000
161 #define MDIOC_CLKDIV(div) ((div) & 0xff)
162 volatile u32 alive;
163 volatile u32 link;
164 struct cpmac_int_regs link_int;
165 struct cpmac_int_regs user_int;
166 u32 unused[20];
167 volatile u32 access;
168 #define MDIO_BUSY 0x80000000
169 #define MDIO_WRITE 0x40000000
170 #define MDIO_REG(reg) (((reg) & 0x1f) << 21)
171 #define MDIO_PHY(phy) (((phy) & 0x1f) << 16)
172 #define MDIO_DATA(data) ((data) & 0xffff)
173 volatile u32 physel;
174 };
175
176 /* Descriptor */
177 struct cpmac_desc {
178 u32 hw_next;
179 u32 hw_data;
180 u16 buflen;
181 u16 bufflags;
182 u16 datalen;
183 u16 dataflags;
184 /* Flags bits */
185 #define CPMAC_SOP 0x8000
186 #define CPMAC_EOP 0x4000
187 #define CPMAC_OWN 0x2000
188 #define CPMAC_EOQ 0x1000
189 u32 jiffies;
190 struct sk_buff *skb;
191 struct cpmac_desc *next;
192 };
193
194 struct cpmac_priv {
195 struct net_device_stats stats;
196 spinlock_t lock;
197 int free_tx_channels;
198 struct cpmac_desc *tx_pool;
199 struct cpmac_desc *rx_channels[8];
200 struct cpmac_desc *tx_channels[8];
201 struct cpmac_regs *regs;
202 struct mii_bus *mii_bus;
203 struct phy_device *phy;
204 char phy_name[BUS_ID_SIZE];
205 unsigned long pages;
206 int order;
207 struct plat_cpmac_data *config;
208 int oldlink, oldspeed, oldduplex;
209 u32 msg_enable;
210 };
211
212 static irqreturn_t cpmac_irq(int, void *);
213 void cpmac_exit(void);
214
215 #ifdef CPMAC_DEBUG
216 static void cpmac_dump_regs(u32 *base, int count)
217 {
218 int i;
219 for (i = 0; i < (count + 3) / 4; i++) {
220 if (i % 4 == 0) printk("\nCPMAC[0x%04x]:", i * 4);
221 printk(" 0x%08x", *(base + i));
222 }
223 printk("\n");
224 }
225 #endif
226
227 static int cpmac_mdio_read(struct mii_bus *bus, int phy_id, int regnum)
228 {
229 struct cpmac_mdio_regs *regs = (struct cpmac_mdio_regs *)bus->priv;
230 volatile u32 val;
231
232 while ((val = regs->access) & MDIO_BUSY);
233 regs->access = MDIO_BUSY | MDIO_REG(regnum & 0x1f) |
234 MDIO_PHY(phy_id & 0x1f);
235 while ((val = regs->access) & MDIO_BUSY);
236
237 return val & 0xffff;
238 }
239
240 static int cpmac_mdio_write(struct mii_bus *bus, int phy_id, int regnum, u16 val)
241 {
242 struct cpmac_mdio_regs *regs = (struct cpmac_mdio_regs *)bus->priv;
243 volatile u32 tmp;
244
245 while ((tmp = regs->access) & MDIO_BUSY);
246 regs->access = MDIO_BUSY | MDIO_WRITE |
247 MDIO_REG(regnum & 0x1f) | MDIO_PHY(phy_id & 0x1f) |
248 val;
249
250 return 0;
251 }
252
253 static int cpmac_mdio_reset(struct mii_bus *bus)
254 {
255 struct cpmac_mdio_regs *regs = (struct cpmac_mdio_regs *)bus->priv;
256
257 ar7_device_reset(AR7_RESET_BIT_MDIO);
258 regs->control = MDIOC_ENABLE |
259 MDIOC_CLKDIV(ar7_cpmac_freq() / 2200000 - 1);
260
261 return 0;
262 }
263
264 static int mii_irqs[PHY_MAX_ADDR] = { PHY_POLL, };
265
266 struct mii_bus cpmac_mii = {
267 .name = "cpmac-mii",
268 .read = cpmac_mdio_read,
269 .write = cpmac_mdio_write,
270 .reset = cpmac_mdio_reset,
271 .irq = mii_irqs,
272 };
273
274 int cpmac_config(struct net_device *dev, struct ifmap *map)
275 {
276 if (dev->flags & IFF_UP)
277 return -EBUSY;
278
279 /* Don't allow changing the I/O address */
280 if (map->base_addr != dev->base_addr)
281 return -EOPNOTSUPP;
282
283 /* ignore other fields */
284 return 0;
285 }
286
287 int cpmac_set_mac_address(struct net_device *dev, void *addr)
288 {
289 struct sockaddr *sa = addr;
290
291 if (dev->flags & IFF_UP)
292 return -EBUSY;
293
294 memcpy(dev->dev_addr, sa->sa_data, dev->addr_len);
295
296 return 0;
297 }
298
299 void cpmac_set_multicast_list(struct net_device *dev)
300 {
301 struct dev_mc_list *iter;
302 int i;
303 int hash, tmp;
304 int hashlo = 0, hashhi = 0;
305 struct cpmac_priv *priv = netdev_priv(dev);
306
307 if(dev->flags & IFF_PROMISC) {
308 priv->regs->mbp &= ~MBP_PROMISCCHAN(0); /* promisc channel 0 */
309 priv->regs->mbp |= MBP_RXPROMISC;
310 } else {
311 priv->regs->mbp &= ~MBP_RXPROMISC;
312 if(dev->flags & IFF_ALLMULTI) {
313 /* enable all multicast mode */
314 priv->regs->mac_hash_low = 0xffffffff;
315 priv->regs->mac_hash_high = 0xffffffff;
316 } else {
317 for(i = 0, iter = dev->mc_list; i < dev->mc_count;
318 i++, iter = iter->next) {
319 hash = 0;
320 tmp = iter->dmi_addr[0];
321 hash ^= (tmp >> 2) ^ (tmp << 4);
322 tmp = iter->dmi_addr[1];
323 hash ^= (tmp >> 4) ^ (tmp << 2);
324 tmp = iter->dmi_addr[2];
325 hash ^= (tmp >> 6) ^ tmp;
326 tmp = iter->dmi_addr[4];
327 hash ^= (tmp >> 2) ^ (tmp << 4);
328 tmp = iter->dmi_addr[5];
329 hash ^= (tmp >> 4) ^ (tmp << 2);
330 tmp = iter->dmi_addr[6];
331 hash ^= (tmp >> 6) ^ tmp;
332 hash &= 0x3f;
333 if(hash < 32) {
334 hashlo |= 1<<hash;
335 } else {
336 hashhi |= 1<<(hash - 32);
337 }
338 }
339
340 priv->regs->mac_hash_low = hashlo;
341 priv->regs->mac_hash_high = hashhi;
342 }
343 }
344 }
345
346 static void cpmac_rx(struct net_device *dev, int channel)
347 {
348 struct cpmac_desc *pkt;
349 struct sk_buff *skb;
350 char *data;
351 struct cpmac_priv *priv = netdev_priv(dev);
352
353 spin_lock(&priv->lock);
354 pkt = priv->rx_channels[channel];
355 if (!pkt) {
356 if (printk_ratelimit())
357 printk(KERN_NOTICE "%s: rx: spurious interrupt\n",
358 dev->name);
359 priv->stats.rx_errors++;
360 return;
361 }
362
363 priv->regs->rx_ack[channel] = virt_to_phys(pkt);
364 dma_cache_inv((u32)pkt, 16);
365 if (!pkt->datalen) {
366 if (printk_ratelimit())
367 printk(KERN_NOTICE "%s: rx: spurious interrupt\n",
368 dev->name);
369 priv->stats.rx_errors++;
370 return;
371 }
372 skb = dev_alloc_skb(1536);
373 if (!skb) {
374 if (printk_ratelimit())
375 printk(KERN_NOTICE "%s: rx: low on mem - packet dropped\n",
376 dev->name);
377 priv->stats.rx_dropped++;
378 } else {
379 data = (char *)phys_to_virt(pkt->hw_data);
380 dma_cache_inv((u32)data, pkt->datalen);
381 skb_put(pkt->skb, pkt->datalen);
382 pkt->skb->protocol = eth_type_trans(pkt->skb, dev);
383 pkt->skb->ip_summed = CHECKSUM_NONE;
384 priv->stats.rx_packets++;
385 priv->stats.rx_bytes += pkt->datalen;
386 netif_rx(pkt->skb);
387 skb_reserve(skb, 2);
388 skb->dev = dev;
389 pkt->skb = skb;
390 pkt->hw_data = virt_to_phys(skb->data);
391 }
392 spin_unlock(&priv->lock);
393 pkt->buflen = 1500 + ETH_HLEN + 4;
394 pkt->datalen = 0;
395 pkt->dataflags = CPMAC_OWN;
396 dma_cache_wback_inv((u32)pkt, 16);
397 priv->regs->rx_ptr[channel] = virt_to_phys(pkt);
398 }
399
400 struct cpmac_desc *cpmac_get_desc(struct net_device *dev)
401 {
402 struct cpmac_desc *pkt;
403 struct cpmac_priv *priv = netdev_priv(dev);
404 pkt = priv->tx_pool;
405 priv->tx_pool = pkt->next;
406 pkt->next = NULL;
407 if (priv->tx_pool == NULL)
408 netif_stop_queue(dev);
409 return pkt;
410 }
411
412 void cpmac_release_desc(struct net_device *dev, struct cpmac_desc *pkt)
413 {
414 struct cpmac_priv *priv = netdev_priv(dev);
415 struct cpmac_desc *p;
416 p = pkt;
417 while (p->next) p = p->next;
418 p->next = priv->tx_pool;
419 priv->tx_pool = pkt;
420 }
421
422 int cpmac_start_xmit(struct sk_buff *skb, struct net_device *dev)
423 {
424 unsigned long flags;
425 int i, len, frag;
426 skb_frag_t *this_frag;
427 void *data;
428 struct cpmac_desc *head, *tail, *curr;
429 struct cpmac_priv *priv = netdev_priv(dev);
430
431 BUG_ON(priv->free_tx_channels < 1);
432 len = skb->len;
433 if (len < ETH_ZLEN) {
434 if (skb_padto(skb, ETH_ZLEN)) {
435 if (printk_ratelimit())
436 printk(KERN_NOTICE "%s: padding failed, dropping\n",
437 dev->name);
438 spin_lock_irqsave(&priv->lock, flags);
439 priv->stats.tx_dropped++;
440 spin_unlock_irqrestore(&priv->lock, flags);
441 return -ENOMEM;
442 }
443 len = ETH_ZLEN;
444 }
445 spin_lock_irqsave(&priv->lock, flags);
446 dev->trans_start = jiffies;
447 for (i = 0; i < 8; i++)
448 if (!priv->tx_channels[i])
449 break;
450
451 BUG_ON(i == 8);
452
453 head = cpmac_get_desc(dev);
454 priv->tx_channels[i] = head;
455 head->jiffies = dev->trans_start;
456 if (!(--priv->free_tx_channels))
457 netif_stop_queue(dev);
458 spin_unlock_irqrestore(&priv->lock, flags);
459
460 head->dataflags = CPMAC_SOP | CPMAC_OWN;
461 head->skb = skb;
462 head->hw_data = virt_to_phys(skb->data);
463 dma_cache_wback_inv((u32)skb->data, len);
464 head->buflen = len;
465 head->datalen = len;
466 tail = head;
467 for (frag = 0; frag < skb_shinfo(skb)->nr_frags; frag++) {
468 dma_cache_wback_inv((u32)tail, 16);
469 this_frag = &skb_shinfo(skb)->frags[frag];
470 curr = cpmac_get_desc(dev);
471 data = page_address(this_frag->page) +
472 this_frag->page_offset;
473 curr->hw_data = virt_to_phys(data);
474 curr->buflen = this_frag->size;
475 curr->datalen = this_frag->size;
476 curr->dataflags = CPMAC_OWN;
477 dma_cache_wback_inv((u32)data, len);
478 tail->hw_next = virt_to_phys(curr);
479 tail->next = curr;
480 tail = curr;
481 }
482 tail->hw_next = 0;
483 tail->dataflags |= CPMAC_EOP;
484 dma_cache_wback_inv((u32)tail, 16);
485 priv->regs->tx_ptr[i] = virt_to_phys(head);
486 return 0;
487 }
488
489 void cpmac_end_xmit(struct net_device *dev, int channel)
490 {
491 struct cpmac_desc *pkt;
492 struct cpmac_priv *priv = netdev_priv(dev);
493
494 spin_lock(&priv->lock);
495 pkt = priv->tx_channels[channel];
496 priv->tx_channels[channel] = NULL;
497 priv->free_tx_channels++;
498 priv->regs->tx_ack[channel] = virt_to_phys(pkt);
499 if (pkt) {
500 priv->stats.tx_packets++;
501 priv->stats.tx_bytes += pkt->skb->len;
502 dev_kfree_skb_irq(pkt->skb);
503 cpmac_release_desc(dev, pkt);
504 if (netif_queue_stopped(dev))
505 netif_wake_queue(dev);
506 } else {
507 if (printk_ratelimit())
508 printk(KERN_NOTICE "%s: end_xmit: spurious interrupt\n",
509 dev->name);
510 }
511 spin_unlock(&priv->lock);
512 }
513
514 static irqreturn_t cpmac_irq(int irq, void *dev_id)
515 {
516 struct net_device *dev = (struct net_device *)dev_id;
517 struct cpmac_priv *priv = netdev_priv(dev);
518 u32 status;
519
520 if (!dev)
521 return IRQ_NONE;
522
523 status = priv->regs->mac_int_vector;
524
525 if (status & INTST_TX) {
526 cpmac_end_xmit(dev, (status & 7));
527 }
528
529 if (status & INTST_RX) {
530 cpmac_rx(dev, (status >> 8) & 7);
531 }
532
533 if (status & INTST_HOST) { /* host interrupt ??? */
534 printk("%s: host int, something bad happened...\n", dev->name);
535 printk("%s: mac status: 0x%08x\n", dev->name,
536 priv->regs->mac_status);
537 }
538
539 if (status & INTST_STATUS) { /* status interrupt ??? */
540 printk("%s: status int, what are we gonna do?\n", dev->name);
541 }
542
543 priv->regs->mac_eoi_vector = 0;
544 return IRQ_HANDLED;
545 }
546
547 void cpmac_tx_timeout(struct net_device *dev)
548 {
549 int i;
550 struct cpmac_priv *priv = netdev_priv(dev);
551 struct cpmac_desc *pkt = NULL, *tmp;
552
553 priv->stats.tx_errors++;
554 for (i = 0; i < 8; i++) {
555 tmp = priv->tx_channels[i];
556 if (tmp && (!pkt || (pkt->jiffies > tmp->jiffies)))
557 pkt = tmp;
558 }
559 if (pkt) {
560 printk("Transmit timeout at %ld, latency %ld\n", jiffies,
561 jiffies - pkt->jiffies);
562 for (i = 0; i < 8; i++)
563 if (priv->tx_channels[i] == pkt)
564 priv->tx_channels[i] = NULL;
565 dev_kfree_skb(pkt->skb);
566 cpmac_release_desc(dev, pkt);
567 priv->free_tx_channels++;
568 netif_wake_queue(dev);
569 }
570 }
571
572 int cpmac_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
573 {
574 struct cpmac_priv *priv = netdev_priv(dev);
575 if (!(netif_running(dev)))
576 return -EINVAL;
577 if (!priv->phy)
578 return -EINVAL;
579 return phy_mii_ioctl(priv->phy, if_mii(ifr), cmd);
580 }
581
582 static int cpmac_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
583 {
584 struct cpmac_priv *priv = netdev_priv(dev);
585
586 if (priv->phy)
587 return phy_ethtool_gset(priv->phy, cmd);
588
589 return -EINVAL;
590 }
591
592 static int cpmac_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
593 {
594 struct cpmac_priv *priv = netdev_priv(dev);
595
596 if (!capable(CAP_NET_ADMIN))
597 return -EPERM;
598
599 if (priv->phy)
600 return phy_ethtool_sset(priv->phy, cmd);
601
602 return -EINVAL;
603 }
604
605 static void cpmac_get_drvinfo(struct net_device *dev,
606 struct ethtool_drvinfo *info)
607 {
608 strcpy(info->driver, "cpmac");
609 strcpy(info->version, "0.0.3");
610 info->fw_version[0] = '\0';
611 sprintf(info->bus_info, "%s", "cpmac");
612 info->regdump_len = 0;
613 }
614
615 static const struct ethtool_ops cpmac_ethtool_ops = {
616 .get_settings = cpmac_get_settings,
617 .set_settings = cpmac_set_settings,
618 .get_drvinfo = cpmac_get_drvinfo,
619 .get_link = ethtool_op_get_link,
620 };
621
622 static struct net_device_stats *cpmac_stats(struct net_device *dev)
623 {
624 struct cpmac_priv *priv = netdev_priv(dev);
625
626 if (netif_device_present(dev))
627 return &priv->stats;
628
629 return NULL;
630 }
631
632 static int cpmac_change_mtu(struct net_device *dev, int mtu)
633 {
634 unsigned long flags;
635 struct cpmac_priv *priv = netdev_priv(dev);
636 spinlock_t *lock = &priv->lock;
637
638 if ((mtu < 68) || (mtu > 1500))
639 return -EINVAL;
640
641 spin_lock_irqsave(lock, flags);
642 dev->mtu = mtu;
643 spin_unlock_irqrestore(lock, flags);
644
645 return 0;
646 }
647
648 static void cpmac_reset(struct net_device *dev)
649 {
650 int i;
651 struct cpmac_priv *priv = netdev_priv(dev);
652
653 ar7_device_reset(priv->config->reset_bit);
654 priv->regs->rx_ctrl.control &= ~1;
655 priv->regs->tx_ctrl.control &= ~1;
656 for (i = 0; i < 8; i++) {
657 priv->regs->tx_ptr[i] = 0;
658 priv->regs->rx_ptr[i] = 0;
659 }
660 priv->regs->mac_control &= ~MAC_MII; /* disable mii */
661 }
662
663 static void cpmac_adjust_link(struct net_device *dev)
664 {
665 struct cpmac_priv *priv = netdev_priv(dev);
666 unsigned long flags;
667 int new_state = 0;
668
669 spin_lock_irqsave(&priv->lock, flags);
670 if (priv->phy->link) {
671 if (priv->phy->duplex != priv->oldduplex) {
672 new_state = 1;
673 priv->oldduplex = priv->phy->duplex;
674 }
675
676 if (priv->phy->speed != priv->oldspeed) {
677 new_state = 1;
678 priv->oldspeed = priv->phy->speed;
679 }
680
681 if (!priv->oldlink) {
682 new_state = 1;
683 priv->oldlink = 1;
684 netif_schedule(dev);
685 }
686 } else if (priv->oldlink) {
687 new_state = 1;
688 priv->oldlink = 0;
689 priv->oldspeed = 0;
690 priv->oldduplex = -1;
691 }
692
693 if (new_state)
694 phy_print_status(priv->phy);
695
696 spin_unlock_irqrestore(&priv->lock, flags);
697 }
698
699 int cpmac_open(struct net_device *dev)
700 {
701 int i, j, res;
702 struct cpmac_priv *priv = netdev_priv(dev);
703 struct cpmac_desc *pkt;
704 struct sk_buff *skb;
705
706 /* priv->phy = phy_connect(dev, priv->phy_name, &cpmac_adjust_link,
707 0, PHY_INTERFACE_MODE_MII);*/
708 priv->phy = phy_connect(dev, priv->phy_name, &cpmac_adjust_link, 0);
709 if (IS_ERR(priv->phy)) {
710 printk(KERN_ERR "%s: Could not attach to PHY\n", dev->name);
711 return PTR_ERR(priv->phy);
712 }
713
714 if (!request_mem_region(dev->mem_start, dev->mem_end -
715 dev->mem_start, dev->name)) {
716 printk("%s: failed to request registers\n",
717 dev->name);
718 res = -ENXIO;
719 goto fail_reserve;
720 }
721
722 priv->regs = ioremap_nocache(dev->mem_start, dev->mem_end -
723 dev->mem_start);
724 if (!priv->regs) {
725 printk("%s: failed to remap registers\n", dev->name);
726 res = -ENXIO;
727 goto fail_remap;
728 }
729
730 priv->order = get_order(4096);
731 priv->pages = __get_dma_pages(GFP_KERNEL, priv->order);
732 if (!priv->pages) {
733 res = -ENOMEM;
734 goto fail_alloc;
735 }
736 memset((char *)priv->pages, 0, 4096);
737
738 priv->tx_pool = NULL;
739
740 for (i = 0; i < 4096 / sizeof(struct cpmac_desc); i++) {
741 pkt = (struct cpmac_desc *)
742 (priv->pages + i * sizeof(struct cpmac_desc));
743 memset(pkt, sizeof(struct cpmac_desc), 0);
744 if (i < 8) {
745 skb = alloc_skb(1500 + ETH_HLEN + 6, GFP_KERNEL);
746 if (!skb) {
747 for(j = 0; j < i - 1; j++)
748 kfree_skb(priv->rx_channels[j]->skb);
749 free_pages(priv->pages, priv->order);
750 res = -ENOMEM;
751 goto fail_alloc;
752 }
753 skb_reserve(skb, 2);
754 skb->dev = dev;
755 pkt->skb = skb;
756 pkt->hw_data = virt_to_phys(skb->data);
757 pkt->buflen = 1500 + ETH_HLEN + 4;
758 pkt->dataflags = CPMAC_OWN;
759 dma_cache_wback_inv((u32)pkt, 16);
760 priv->rx_channels[i] = pkt;
761 priv->tx_channels[i] = NULL;
762 } else {
763 pkt->next = priv->tx_pool;
764 priv->tx_pool = pkt;
765 }
766 }
767
768 cpmac_reset(dev);
769 priv->free_tx_channels = 8;
770
771 for (i = 0; i < 8; i++) {
772 priv->regs->tx_ptr[i] = 0;
773 priv->regs->rx_ptr[i] = virt_to_phys(priv->rx_channels[i]);
774 }
775
776 priv->regs->mbp = MBP_RXNOCHAIN | MBP_RXSHORT | MBP_RXBCAST |
777 MBP_RXMCAST;
778 priv->regs->unicast_enable = 0xff;
779 priv->regs->unicast_clear = 0;
780 priv->regs->buffer_offset = 0;
781 for (i = 0; i < 8; i++)
782 priv->regs->mac_addr_low[i] = dev->dev_addr[5];
783 priv->regs->mac_addr_mid = dev->dev_addr[4];
784 priv->regs->mac_addr_high = dev->dev_addr[0] | (dev->dev_addr[1] << 8)
785 | (dev->dev_addr[2] << 16) | (dev->dev_addr[3] << 24);
786 priv->regs->max_len = 1536;
787 priv->regs->rx_int.enable = 0xff;
788 priv->regs->rx_int.clear = 0;
789 priv->regs->tx_int.enable = 0xff;
790 priv->regs->tx_int.clear = 0;
791 priv->regs->mac_int_enable = 3;
792 priv->regs->mac_int_clear = 0xfc;
793
794 if((res = request_irq(dev->irq, cpmac_irq, SA_INTERRUPT,
795 dev->name, dev))) {
796 printk("%s: failed to obtain irq\n", dev->name);
797 goto fail_irq;
798 }
799
800 priv->regs->rx_ctrl.control |= 1;
801 priv->regs->tx_ctrl.control |= 1;
802 priv->regs->mac_control |= MAC_MII | MAC_FDX;
803
804 priv->phy->state = PHY_CHANGELINK;
805 phy_start(priv->phy);
806
807 netif_start_queue(dev);
808
809 return 0;
810
811 fail_irq:
812 for(i = 0; i < 8; i++)
813 if (priv->rx_channels[i]->skb)
814 kfree_skb(priv->rx_channels[i]->skb);
815 free_pages(priv->pages, priv->order);
816
817 fail_alloc:
818 iounmap(priv->regs);
819
820 fail_remap:
821 release_mem_region(dev->mem_start, dev->mem_end -
822 dev->mem_start);
823
824 fail_reserve:
825 phy_disconnect(priv->phy);
826
827 return res;
828 }
829
830 int cpmac_stop(struct net_device *dev)
831 {
832 int i;
833 struct cpmac_priv *priv = netdev_priv(dev);
834
835 netif_stop_queue(dev);
836
837 phy_stop(priv->phy);
838 phy_disconnect(priv->phy);
839 priv->phy = NULL;
840
841 cpmac_reset(dev);
842
843 for (i = 0; i < 8; i++) {
844 priv->regs->rx_ptr[i] = 0;
845 priv->regs->tx_ptr[i] = 0;
846 priv->regs->mbp = 0;
847 }
848
849 free_irq(dev->irq, dev);
850 release_mem_region(dev->mem_start, dev->mem_end -
851 dev->mem_start);
852
853 for(i = 0; i < 8; i++)
854 if (priv->rx_channels[i]->skb)
855 kfree_skb(priv->rx_channels[i]->skb);
856 if (priv->pages)
857 free_pages(priv->pages, priv->order);
858
859 return 0;
860 }
861
862 static int external_switch = 0;
863
864 int __devinit cpmac_probe(struct platform_device *pdev)
865 {
866 int i, rc, phy_id;
867 struct resource *res;
868 struct cpmac_priv *priv;
869 struct net_device *dev;
870 struct plat_cpmac_data *pdata;
871
872 if (strcmp(pdev->name, "cpmac") != 0)
873 return -ENODEV;
874
875 pdata = pdev->dev.platform_data;
876
877 for (phy_id = 0; phy_id < PHY_MAX_ADDR; phy_id++) {
878 if (!(pdata->phy_mask & (1 << phy_id)))
879 continue;
880 if (!cpmac_mii.phy_map[phy_id])
881 continue;
882 break;
883 }
884
885 if (phy_id == PHY_MAX_ADDR) {
886 if (external_switch) {
887 phy_id = 0;
888 } else {
889 printk("cpmac: no PHY present\n");
890 return -ENODEV;
891 }
892 }
893
894 dev = alloc_etherdev(sizeof(struct cpmac_priv));
895
896 if (!dev) {
897 printk(KERN_ERR "cpmac: Unable to allocate net_device structure!\n");
898 return -ENOMEM;
899 }
900
901 SET_MODULE_OWNER(dev);
902 platform_set_drvdata(pdev, dev);
903 priv = netdev_priv(dev);
904
905 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "regs");
906 if (!res) {
907 rc = -ENODEV;
908 goto fail;
909 }
910
911 dev->mem_start = res->start;
912 dev->mem_end = res->end;
913 dev->irq = platform_get_irq_byname(pdev, "irq");
914
915 dev->mtu = 1500;
916 dev->open = cpmac_open;
917 dev->stop = cpmac_stop;
918 dev->set_config = cpmac_config;
919 dev->hard_start_xmit = cpmac_start_xmit;
920 dev->do_ioctl = cpmac_ioctl;
921 dev->get_stats = cpmac_stats;
922 dev->change_mtu = cpmac_change_mtu;
923 dev->set_mac_address = cpmac_set_mac_address;
924 dev->set_multicast_list = cpmac_set_multicast_list;
925 dev->tx_timeout = cpmac_tx_timeout;
926 dev->ethtool_ops = &cpmac_ethtool_ops;
927
928 memset(priv, 0, sizeof(struct cpmac_priv));
929 spin_lock_init(&priv->lock);
930 priv->msg_enable = netif_msg_init(NETIF_MSG_WOL, 0x3fff);
931 priv->config = pdata;
932 memcpy(dev->dev_addr, priv->config->dev_addr, sizeof(dev->dev_addr));
933 if (phy_id == 31) {
934 snprintf(priv->phy_name, BUS_ID_SIZE, PHY_ID_FMT,
935 cpmac_mii.id, phy_id);
936 } else {
937 snprintf(priv->phy_name, BUS_ID_SIZE, "fixed@%d:%d", 100, 1);
938 }
939
940 if ((rc = register_netdev(dev))) {
941 printk("cpmac: error %i registering device %s\n",
942 rc, dev->name);
943 goto fail;
944 }
945
946 printk("cpmac: device %s (regs: %p, irq: %d, phy: %s, mac: ",
947 dev->name, (u32 *)dev->mem_start, dev->irq,
948 priv->phy_name);
949 for (i = 0; i < 6; i++) {
950 printk("%02x", dev->dev_addr[i]);
951 if (i < 5) printk(":");
952 else printk(")\n");
953 }
954
955 return 0;
956
957 fail:
958 free_netdev(dev);
959 return rc;
960 }
961
962 static int __devexit cpmac_remove(struct platform_device *pdev)
963 {
964 struct net_device *dev = platform_get_drvdata(pdev);
965 unregister_netdev(dev);
966 free_netdev(dev);
967 return 0;
968 }
969
970 static struct platform_driver cpmac_driver = {
971 .driver.name = "cpmac",
972 .probe = cpmac_probe,
973 .remove = cpmac_remove,
974 };
975
976 int __devinit cpmac_init(void)
977 {
978 volatile u32 mask;
979 int i, res;
980 cpmac_mii.priv = (struct cpmac_mdio_regs *)
981 ioremap_nocache(AR7_REGS_MDIO, sizeof(struct cpmac_mdio_regs));
982
983 if (!cpmac_mii.priv) {
984 printk("Can't ioremap mdio registers\n");
985 return -ENXIO;
986 }
987
988 #warning FIXME: unhardcode gpio&reset bits
989 ar7_gpio_disable(26);
990 ar7_gpio_disable(27);
991 /* ar7_device_reset(17);
992 ar7_device_reset(21);
993 ar7_device_reset(26);*/
994
995 cpmac_mii.reset(&cpmac_mii);
996
997 for (i = 0; i < 300000; i++) {
998 mask = ((struct cpmac_mdio_regs *)cpmac_mii.priv)->alive;
999 if (mask)
1000 break;
1001 }
1002
1003 mask &= 0x7fffffff;
1004 if (mask & (mask - 1)) {
1005 external_switch = 1;
1006 mask = 0;
1007 }
1008
1009 cpmac_mii.phy_mask = ~(mask | 0x80000000);
1010
1011 res = mdiobus_register(&cpmac_mii);
1012 if (res)
1013 goto fail_mii;
1014
1015 res = platform_driver_register(&cpmac_driver);
1016 if (res)
1017 goto fail_cpmac;
1018
1019 return 0;
1020
1021 fail_cpmac:
1022 mdiobus_unregister(&cpmac_mii);
1023
1024 fail_mii:
1025 iounmap(cpmac_mii.priv);
1026
1027 return res;
1028 }
1029
1030 void __devexit cpmac_exit(void)
1031 {
1032 platform_driver_unregister(&cpmac_driver);
1033 mdiobus_unregister(&cpmac_mii);
1034 }
1035
1036 module_init(cpmac_init);
1037 module_exit(cpmac_exit);
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