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bcm63xx: add missing bits from extirq support
[openwrt.git] / target / linux / lantiq / patches-3.2 / 0040-I2C-MIPS-lantiq-add-FALC-ON-i2c-bus-master.patch
1 From 97050437c6a3ce59ce2c5a8286b9bc1c9f1b3b60 Mon Sep 17 00:00:00 2001
2 From: John Crispin <blogic@openwrt.org>
3 Date: Fri, 4 Nov 2011 16:00:34 +0100
4 Subject: [PATCH 40/70] I2C: MIPS: lantiq: add FALC-ON i2c bus master
5
6 This patch adds the driver needed to make the I2C bus work on FALC-ON SoCs.
7
8 Signed-off-by: Thomas Langer <thomas.langer@lantiq.com>
9 Signed-off-by: John Crispin <blogic@openwrt.org>
10 Cc: linux-i2c@vger.kernel.org
11 ---
12 .../include/asm/mach-lantiq/falcon/lantiq_soc.h | 5 +
13 arch/mips/lantiq/falcon/clk.c | 44 -
14 arch/mips/lantiq/falcon/devices.c | 16 +
15 arch/mips/lantiq/falcon/devices.h | 1 +
16 arch/mips/lantiq/falcon/mach-easy98000.c | 1 +
17 drivers/i2c/busses/Kconfig | 10 +
18 drivers/i2c/busses/Makefile | 1 +
19 drivers/i2c/busses/i2c-falcon.c | 1040 ++++++++++++++++++++
20 8 files changed, 1074 insertions(+), 44 deletions(-)
21 delete mode 100644 arch/mips/lantiq/falcon/clk.c
22 create mode 100644 drivers/i2c/busses/i2c-falcon.c
23
24 diff --git a/arch/mips/include/asm/mach-lantiq/falcon/lantiq_soc.h b/arch/mips/include/asm/mach-lantiq/falcon/lantiq_soc.h
25 index 120c56c..fff5ecd 100644
26 --- a/arch/mips/include/asm/mach-lantiq/falcon/lantiq_soc.h
27 +++ b/arch/mips/include/asm/mach-lantiq/falcon/lantiq_soc.h
28 @@ -72,6 +72,10 @@
29 #define LTQ_PADCTRL4_BASE_ADDR 0x1E800600
30 #define LTQ_PADCTRL4_SIZE 0x0100
31
32 +/* I2C */
33 +#define GPON_I2C_BASE 0x1E200000
34 +#define GPON_I2C_SIZE 0x00010000
35 +
36 /* CHIP ID */
37 #define LTQ_STATUS_BASE_ADDR 0x1E802000
38
39 @@ -106,6 +110,7 @@
40 #define ACTS_PADCTRL2 0x00200000
41 #define ACTS_PADCTRL3 0x00200000
42 #define ACTS_PADCTRL4 0x00400000
43 +#define ACTS_I2C_ACT 0x00004000
44
45 /* global register ranges */
46 extern __iomem void *ltq_ebu_membase;
47 diff --git a/arch/mips/lantiq/falcon/clk.c b/arch/mips/lantiq/falcon/clk.c
48 deleted file mode 100644
49 index afe1b52..0000000
50 --- a/arch/mips/lantiq/falcon/clk.c
51 +++ /dev/null
52 @@ -1,44 +0,0 @@
53 -/*
54 - * This program is free software; you can redistribute it and/or modify it
55 - * under the terms of the GNU General Public License version 2 as published
56 - * by the Free Software Foundation.
57 - *
58 - * Copyright (C) 2011 Thomas Langer <thomas.langer@lantiq.com>
59 - * Copyright (C) 2011 John Crispin <blogic@openwrt.org>
60 - */
61 -
62 -#include <linux/ioport.h>
63 -#include <linux/export.h>
64 -
65 -#include <lantiq_soc.h>
66 -
67 -#include "devices.h"
68 -
69 -/* CPU0 Clock Control Register */
70 -#define LTQ_SYS1_CPU0CC 0x0040
71 -/* clock divider bit */
72 -#define LTQ_CPU0CC_CPUDIV 0x0001
73 -
74 -unsigned int
75 -ltq_get_io_region_clock(void)
76 -{
77 - return CLOCK_200M;
78 -}
79 -EXPORT_SYMBOL(ltq_get_io_region_clock);
80 -
81 -unsigned int
82 -ltq_get_cpu_hz(void)
83 -{
84 - if (ltq_sys1_r32(LTQ_SYS1_CPU0CC) & LTQ_CPU0CC_CPUDIV)
85 - return CLOCK_200M;
86 - else
87 - return CLOCK_400M;
88 -}
89 -EXPORT_SYMBOL(ltq_get_cpu_hz);
90 -
91 -unsigned int
92 -ltq_get_fpi_hz(void)
93 -{
94 - return CLOCK_100M;
95 -}
96 -EXPORT_SYMBOL(ltq_get_fpi_hz);
97 diff --git a/arch/mips/lantiq/falcon/devices.c b/arch/mips/lantiq/falcon/devices.c
98 index 92ec571..e684ed4 100644
99 --- a/arch/mips/lantiq/falcon/devices.c
100 +++ b/arch/mips/lantiq/falcon/devices.c
101 @@ -134,3 +134,19 @@ falcon_register_spi_flash(struct spi_board_info *data)
102 spi_register_board_info(data, 1);
103 platform_device_register(&ltq_spi);
104 }
105 +
106 +/* i2c */
107 +static struct resource falcon_i2c_resources[] = {
108 + MEM_RES("i2c", GPON_I2C_BASE, GPON_I2C_SIZE),
109 + IRQ_RES(i2c_lb, FALCON_IRQ_I2C_LBREQ),
110 + IRQ_RES(i2c_b, FALCON_IRQ_I2C_BREQ),
111 + IRQ_RES(i2c_err, FALCON_IRQ_I2C_I2C_ERR),
112 + IRQ_RES(i2c_p, FALCON_IRQ_I2C_I2C_P),
113 +};
114 +
115 +void __init
116 +falcon_register_i2c(void)
117 +{
118 + platform_device_register_simple("i2c-falcon", 0,
119 + falcon_i2c_resources, ARRAY_SIZE(falcon_i2c_resources));
120 +}
121 diff --git a/arch/mips/lantiq/falcon/devices.h b/arch/mips/lantiq/falcon/devices.h
122 index 5e6f720..d81edbe 100644
123 --- a/arch/mips/lantiq/falcon/devices.h
124 +++ b/arch/mips/lantiq/falcon/devices.h
125 @@ -20,5 +20,6 @@ extern void falcon_register_nand(void);
126 extern void falcon_register_gpio(void);
127 extern void falcon_register_gpio_extra(void);
128 extern void falcon_register_spi_flash(struct spi_board_info *data);
129 +extern void falcon_register_i2c(void);
130
131 #endif
132 diff --git a/arch/mips/lantiq/falcon/mach-easy98000.c b/arch/mips/lantiq/falcon/mach-easy98000.c
133 index 1a7caad..fc5720d 100644
134 --- a/arch/mips/lantiq/falcon/mach-easy98000.c
135 +++ b/arch/mips/lantiq/falcon/mach-easy98000.c
136 @@ -98,6 +98,7 @@ easy98000_init_common(void)
137 {
138 spi_register_board_info(&easy98000_spi_gpio_devices, 1);
139 platform_device_register(&easy98000_spi_gpio_device);
140 + falcon_register_i2c();
141 }
142
143 static void __init
144 diff --git a/drivers/i2c/busses/Kconfig b/drivers/i2c/busses/Kconfig
145 index a3afac4..41be6cc 100644
146 --- a/drivers/i2c/busses/Kconfig
147 +++ b/drivers/i2c/busses/Kconfig
148 @@ -369,6 +369,16 @@ config I2C_DESIGNWARE_PCI
149 This driver can also be built as a module. If so, the module
150 will be called i2c-designware-pci.
151
152 +config I2C_FALCON
153 + tristate "Falcon I2C interface"
154 + depends on SOC_FALCON
155 + help
156 + If you say yes to this option, support will be included for the
157 + Lantiq FALC-ON I2C core.
158 +
159 + This driver can also be built as a module. If so, the module
160 + will be called i2c-falcon.
161 +
162 config I2C_GPIO
163 tristate "GPIO-based bitbanging I2C"
164 depends on GENERIC_GPIO
165 diff --git a/drivers/i2c/busses/Makefile b/drivers/i2c/busses/Makefile
166 index fba6da6..36239c8 100644
167 --- a/drivers/i2c/busses/Makefile
168 +++ b/drivers/i2c/busses/Makefile
169 @@ -37,6 +37,7 @@ obj-$(CONFIG_I2C_DESIGNWARE_PLATFORM) += i2c-designware-platform.o
170 i2c-designware-platform-objs := i2c-designware-platdrv.o i2c-designware-core.o
171 obj-$(CONFIG_I2C_DESIGNWARE_PCI) += i2c-designware-pci.o
172 i2c-designware-pci-objs := i2c-designware-pcidrv.o i2c-designware-core.o
173 +obj-$(CONFIG_I2C_FALCON) += i2c-falcon.o
174 obj-$(CONFIG_I2C_GPIO) += i2c-gpio.o
175 obj-$(CONFIG_I2C_HIGHLANDER) += i2c-highlander.o
176 obj-$(CONFIG_I2C_IBM_IIC) += i2c-ibm_iic.o
177 diff --git a/drivers/i2c/busses/i2c-falcon.c b/drivers/i2c/busses/i2c-falcon.c
178 new file mode 100644
179 index 0000000..fc4f0eb
180 --- /dev/null
181 +++ b/drivers/i2c/busses/i2c-falcon.c
182 @@ -0,0 +1,1040 @@
183 +/*
184 + * Lantiq FALC(tm) ON - I2C bus adapter
185 + *
186 + * Parts based on i2c-designware.c and other i2c drivers from Linux 2.6.33
187 + *
188 + * This program is free software; you can redistribute it and/or modify
189 + * it under the terms of the GNU General Public License as published by
190 + * the Free Software Foundation; either version 2 of the License, or
191 + * (at your option) any later version.
192 + *
193 + * This program is distributed in the hope that it will be useful,
194 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
195 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
196 + * GNU General Public License for more details.
197 + *
198 + * You should have received a copy of the GNU General Public License
199 + * along with this program; if not, write to the Free Software
200 + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
201 + *
202 + * Copyright (C) 2010 Thomas Langer <thomas.langer@lantiq.com>
203 + */
204 +
205 +/*
206 + * CURRENT ISSUES:
207 + * - no high speed support
208 + * - supports only master mode
209 + * - ten bit mode is not tested (no slave devices)
210 + */
211 +
212 +#include <linux/kernel.h>
213 +#include <linux/module.h>
214 +#include <linux/delay.h>
215 +#include <linux/slab.h>
216 +#include <linux/i2c.h>
217 +#include <linux/clk.h>
218 +#include <linux/errno.h>
219 +#include <linux/sched.h>
220 +#include <linux/err.h>
221 +#include <linux/interrupt.h>
222 +#include <linux/platform_device.h>
223 +#include <linux/io.h>
224 +#include <linux/err.h>
225 +#include <linux/gpio.h>
226 +
227 +#include <lantiq_soc.h>
228 +
229 +/* I2C Identification Register */
230 +/* Module ID */
231 +#define I2C_ID_ID_MASK 0x0000FF00
232 +/* field offset */
233 +#define I2C_ID_ID_OFFSET 8
234 +/* Revision */
235 +#define I2C_ID_REV_MASK 0x000000FF
236 +/* field offset */
237 +#define I2C_ID_REV_OFFSET 0
238 +
239 +/* I2C Error Interrupt Request Source Status Register */
240 +/* TXF_OFL */
241 +#define I2C_ERR_IRQSS_TXF_OFL 0x00000008
242 +/* TXF_UFL */
243 +#define I2C_ERR_IRQSS_TXF_UFL 0x00000004
244 +/* RXF_OFL */
245 +#define I2C_ERR_IRQSS_RXF_OFL 0x00000002
246 +/* RXF_UFL */
247 +#define I2C_ERR_IRQSS_RXF_UFL 0x00000001
248 +
249 +/* I2C Bus Status Register */
250 +/* Bus Status */
251 +#define I2C_BUS_STAT_BS_MASK 0x00000003
252 +/* I2C Bus is free. */
253 +#define I2C_BUS_STAT_BS_FREE 0x00000000
254 +/*
255 + * The device is working as master and has claimed the control
256 + * on the I2C-bus (busy master).
257 + */
258 +#define I2C_BUS_STAT_BS_BM 0x00000002
259 +
260 +/* I2C Interrupt Clear Register */
261 +/* Clear */
262 +#define I2C_ICR_BREQ_INT_CLR 0x00000008
263 +/* Clear */
264 +#define I2C_ICR_LBREQ_INT_CLR 0x00000004
265 +
266 +/* I2C RUN Control Register */
267 +/* Enable */
268 +#define I2C_RUN_CTRL_RUN_EN 0x00000001
269 +
270 +/* I2C Kernel Clock Control Register */
271 +/* field offset */
272 +#define I2C_CLC_RMC_OFFSET 8
273 +/* Enable */
274 +#define I2C_IMSC_I2C_P_INT_EN 0x00000020
275 +/* Enable */
276 +#define I2C_IMSC_I2C_ERR_INT_EN 0x00000010
277 +/* Enable */
278 +#define I2C_IMSC_BREQ_INT_EN 0x00000008
279 +/* Enable */
280 +#define I2C_IMSC_LBREQ_INT_EN 0x00000004
281 +
282 +/* I2C Fractional Divider Configuration Register */
283 +/* field offset */
284 +#define I2C_FDIV_CFG_INC_OFFSET 16
285 +/* field offset */
286 +#define I2C_FDIV_CFG_DEC_OFFSET 0
287 +
288 +/* I2C Fractional Divider (highspeed mode) Configuration Register */
289 +/* field offset */
290 +#define I2C_FDIV_HIGH_CFG_INC_OFFSET 16
291 +/* field offset */
292 +#define I2C_FDIV_HIGH_CFG_DEC_OFFSET 0
293 +
294 +/* I2C Address Register */
295 +/* Enable */
296 +#define I2C_ADDR_CFG_SOPE_EN 0x00200000
297 +/* Enable */
298 +#define I2C_ADDR_CFG_SONA_EN 0x00100000
299 +/* Enable */
300 +#define I2C_ADDR_CFG_MnS_EN 0x00080000
301 +
302 +/* I2C Protocol Interrupt Request Source Status Register */
303 +/* RX */
304 +#define I2C_P_IRQSS_RX 0x00000040
305 +/* TX_END */
306 +#define I2C_P_IRQSS_TX_END 0x00000020
307 +/* NACK */
308 +#define I2C_P_IRQSS_NACK 0x00000010
309 +/* AL */
310 +#define I2C_P_IRQSS_AL 0x00000008
311 +
312 +/* I2C Raw Interrupt Status Register */
313 +/* Read: Interrupt occurred. */
314 +#define I2C_RIS_I2C_P_INT_INTOCC 0x00000020
315 +/* Read: Interrupt occurred. */
316 +#define I2C_RIS_I2C_ERR_INT_INTOCC 0x00000010
317 +
318 +/* I2C End Data Control Register */
319 +/*
320 + * Set End of Transmission - Note: Do not write '1' to this bit when bus is
321 + * free. This will cause an abort after the first byte when a new transfer
322 + * is started.
323 + */
324 +#define I2C_ENDD_CTRL_SETEND 0x00000002
325 +/* TX FIFO Flow Control */
326 +#define I2C_FIFO_CFG_TXFC 0x00020000
327 +/* RX FIFO Flow Control */
328 +#define I2C_FIFO_CFG_RXFC 0x00010000
329 +/* Word aligned (character alignment of four characters) */
330 +#define I2C_FIFO_CFG_TXFA_TXFA2 0x00002000
331 +/* Word aligned (character alignment of four characters) */
332 +#define I2C_FIFO_CFG_RXFA_RXFA2 0x00000200
333 +/* 1 word */
334 +#define I2C_FIFO_CFG_TXBS_TXBS0 0x00000000
335 +/* 1 word */
336 +#define I2C_FIFO_CFG_RXBS_RXBS0 0x00000000
337 +
338 +
339 +/* I2C register structure */
340 +struct gpon_reg_i2c {
341 + /* I2C Kernel Clock Control Register */
342 + unsigned int clc; /* 0x00000000 */
343 + /* Reserved */
344 + unsigned int res_0; /* 0x00000004 */
345 + /* I2C Identification Register */
346 + unsigned int id; /* 0x00000008 */
347 + /* Reserved */
348 + unsigned int res_1; /* 0x0000000C */
349 + /*
350 + * I2C RUN Control Register - This register enables and disables the I2C
351 + * peripheral. Before enabling, the I2C has to be configured properly.
352 + * After enabling no configuration is possible
353 + */
354 + unsigned int run_ctrl; /* 0x00000010 */
355 + /*
356 + * I2C End Data Control Register - This register is used to either turn
357 + * around the data transmission direction or to address another slave
358 + * without sending a stop condition. Also the software can stop the
359 + * slave-transmitter by sending a not-accolade when working as
360 + * master-receiver or even stop data transmission immediately when
361 + * operating as master-transmitter. The writing to the bits of this
362 + * control register is only effective when in MASTER RECEIVES BYTES,
363 + * MASTER TRANSMITS BYTES, MASTER RESTART or SLAVE RECEIVE BYTES state
364 + */
365 + unsigned int endd_ctrl; /* 0x00000014 */
366 + /*
367 + * I2C Fractional Divider Configuration Register - These register is
368 + * used to program the fractional divider of the I2C bus. Before the
369 + * peripheral is switched on by setting the RUN-bit the two (fixed)
370 + * values for the two operating frequencies are programmed into these
371 + * (configuration) registers. The Register FDIV_HIGH_CFG has the same
372 + * layout as I2C_FDIV_CFG.
373 + */
374 + unsigned int fdiv_cfg; /* 0x00000018 */
375 + /*
376 + * I2C Fractional Divider (highspeed mode) Configuration Register
377 + * These register is used to program the fractional divider of the I2C
378 + * bus. Before the peripheral is switched on by setting the RUN-bit the
379 + * two (fixed) values for the two operating frequencies are programmed
380 + * into these (configuration) registers. The Register FDIV_CFG has the
381 + * same layout as I2C_FDIV_CFG.
382 + */
383 + unsigned int fdiv_high_cfg; /* 0x0000001C */
384 + /* I2C Address Configuration Register */
385 + unsigned int addr_cfg; /* 0x00000020 */
386 + /*
387 + * I2C Bus Status Register - This register gives a status information
388 + * of the I2C. This additional information can be used by the software
389 + * to start proper actions.
390 + */
391 + unsigned int bus_stat; /* 0x00000024 */
392 + /* I2C FIFO Configuration Register */
393 + unsigned int fifo_cfg; /* 0x00000028 */
394 + /* I2C Maximum Received Packet Size Register */
395 + unsigned int mrps_ctrl; /* 0x0000002C */
396 + /* I2C Received Packet Size Status Register */
397 + unsigned int rps_stat; /* 0x00000030 */
398 + /* I2C Transmit Packet Size Register */
399 + unsigned int tps_ctrl; /* 0x00000034 */
400 + /* I2C Filled FIFO Stages Status Register */
401 + unsigned int ffs_stat; /* 0x00000038 */
402 + /* Reserved */
403 + unsigned int res_2; /* 0x0000003C */
404 + /* I2C Timing Configuration Register */
405 + unsigned int tim_cfg; /* 0x00000040 */
406 + /* Reserved */
407 + unsigned int res_3[7]; /* 0x00000044 */
408 + /* I2C Error Interrupt Request Source Mask Register */
409 + unsigned int err_irqsm; /* 0x00000060 */
410 + /* I2C Error Interrupt Request Source Status Register */
411 + unsigned int err_irqss; /* 0x00000064 */
412 + /* I2C Error Interrupt Request Source Clear Register */
413 + unsigned int err_irqsc; /* 0x00000068 */
414 + /* Reserved */
415 + unsigned int res_4; /* 0x0000006C */
416 + /* I2C Protocol Interrupt Request Source Mask Register */
417 + unsigned int p_irqsm; /* 0x00000070 */
418 + /* I2C Protocol Interrupt Request Source Status Register */
419 + unsigned int p_irqss; /* 0x00000074 */
420 + /* I2C Protocol Interrupt Request Source Clear Register */
421 + unsigned int p_irqsc; /* 0x00000078 */
422 + /* Reserved */
423 + unsigned int res_5; /* 0x0000007C */
424 + /* I2C Raw Interrupt Status Register */
425 + unsigned int ris; /* 0x00000080 */
426 + /* I2C Interrupt Mask Control Register */
427 + unsigned int imsc; /* 0x00000084 */
428 + /* I2C Masked Interrupt Status Register */
429 + unsigned int mis; /* 0x00000088 */
430 + /* I2C Interrupt Clear Register */
431 + unsigned int icr; /* 0x0000008C */
432 + /* I2C Interrupt Set Register */
433 + unsigned int isr; /* 0x00000090 */
434 + /* I2C DMA Enable Register */
435 + unsigned int dmae; /* 0x00000094 */
436 + /* Reserved */
437 + unsigned int res_6[8154]; /* 0x00000098 */
438 + /* I2C Transmit Data Register */
439 + unsigned int txd; /* 0x00008000 */
440 + /* Reserved */
441 + unsigned int res_7[4095]; /* 0x00008004 */
442 + /* I2C Receive Data Register */
443 + unsigned int rxd; /* 0x0000C000 */
444 + /* Reserved */
445 + unsigned int res_8[4095]; /* 0x0000C004 */
446 +};
447 +
448 +/* mapping for access macros */
449 +#define i2c ((struct gpon_reg_i2c *)priv->membase)
450 +#define reg_r32(reg) __raw_readl(reg)
451 +#define reg_w32(val, reg) __raw_writel(val, reg)
452 +#define reg_w32_mask(clear, set, reg) \
453 + reg_w32((reg_r32(reg) & ~(clear)) | (set), reg)
454 +#define reg_r32_table(reg, idx) reg_r32(&((uint32_t *)&reg)[idx])
455 +#define reg_w32_table(val, reg, idx) reg_w32(val, &((uint32_t *)&reg)[idx])
456 +
457 +#define i2c_r32(reg) reg_r32(&i2c->reg)
458 +#define i2c_w32(val, reg) reg_w32(val, &i2c->reg)
459 +#define i2c_w32_mask(clear, set, reg) reg_w32_mask(clear, set, &i2c->reg)
460 +
461 +#define DRV_NAME "i2c-falcon"
462 +#define DRV_VERSION "1.01"
463 +
464 +#define FALCON_I2C_BUSY_TIMEOUT 20 /* ms */
465 +
466 +#ifdef DEBUG
467 +#define FALCON_I2C_XFER_TIMEOUT (25 * HZ)
468 +#else
469 +#define FALCON_I2C_XFER_TIMEOUT HZ
470 +#endif
471 +#if defined(DEBUG) && 0
472 +#define PRINTK(arg...) pr_info(arg)
473 +#else
474 +#define PRINTK(arg...) do {} while (0)
475 +#endif
476 +
477 +#define FALCON_I2C_IMSC_DEFAULT_MASK (I2C_IMSC_I2C_P_INT_EN | \
478 + I2C_IMSC_I2C_ERR_INT_EN)
479 +
480 +#define FALCON_I2C_ARB_LOST (1 << 0)
481 +#define FALCON_I2C_NACK (1 << 1)
482 +#define FALCON_I2C_RX_UFL (1 << 2)
483 +#define FALCON_I2C_RX_OFL (1 << 3)
484 +#define FALCON_I2C_TX_UFL (1 << 4)
485 +#define FALCON_I2C_TX_OFL (1 << 5)
486 +
487 +struct falcon_i2c {
488 + struct mutex mutex;
489 +
490 + enum {
491 + FALCON_I2C_MODE_100 = 1,
492 + FALCON_I2C_MODE_400 = 2,
493 + FALCON_I2C_MODE_3400 = 3
494 + } mode; /* current speed mode */
495 +
496 + struct clk *clk; /* clock input for i2c hardware block */
497 + struct gpon_reg_i2c __iomem *membase; /* base of mapped registers */
498 + int irq_lb, irq_b, irq_err, irq_p; /* last burst, burst, error,
499 + protocol IRQs */
500 +
501 + struct i2c_adapter adap;
502 + struct device *dev;
503 +
504 + struct completion cmd_complete;
505 +
506 + /* message transfer data */
507 + /* current message */
508 + struct i2c_msg *current_msg;
509 + /* number of messages to handle */
510 + int msgs_num;
511 + /* current buffer */
512 + u8 *msg_buf;
513 + /* remaining length of current buffer */
514 + u32 msg_buf_len;
515 + /* error status of the current transfer */
516 + int msg_err;
517 +
518 + /* master status codes */
519 + enum {
520 + STATUS_IDLE,
521 + STATUS_ADDR, /* address phase */
522 + STATUS_WRITE,
523 + STATUS_READ,
524 + STATUS_READ_END,
525 + STATUS_STOP
526 + } status;
527 +};
528 +
529 +static irqreturn_t falcon_i2c_isr(int irq, void *dev_id);
530 +
531 +static inline void enable_burst_irq(struct falcon_i2c *priv)
532 +{
533 + i2c_w32_mask(0, I2C_IMSC_LBREQ_INT_EN | I2C_IMSC_BREQ_INT_EN, imsc);
534 +}
535 +static inline void disable_burst_irq(struct falcon_i2c *priv)
536 +{
537 + i2c_w32_mask(I2C_IMSC_LBREQ_INT_EN | I2C_IMSC_BREQ_INT_EN, 0, imsc);
538 +}
539 +
540 +static void prepare_msg_send_addr(struct falcon_i2c *priv)
541 +{
542 + struct i2c_msg *msg = priv->current_msg;
543 + int rd = !!(msg->flags & I2C_M_RD);
544 + u16 addr = msg->addr;
545 +
546 + /* new i2c_msg */
547 + priv->msg_buf = msg->buf;
548 + priv->msg_buf_len = msg->len;
549 + if (rd)
550 + priv->status = STATUS_READ;
551 + else
552 + priv->status = STATUS_WRITE;
553 +
554 + /* send slave address */
555 + if (msg->flags & I2C_M_TEN) {
556 + i2c_w32(0xf0 | ((addr & 0x300) >> 7) | rd, txd);
557 + i2c_w32(addr & 0xff, txd);
558 + } else
559 + i2c_w32((addr & 0x7f) << 1 | rd, txd);
560 +}
561 +
562 +static void set_tx_len(struct falcon_i2c *priv)
563 +{
564 + struct i2c_msg *msg = priv->current_msg;
565 + int len = (msg->flags & I2C_M_TEN) ? 2 : 1;
566 +
567 + PRINTK("set_tx_len %cX\n", (msg->flags & I2C_M_RD) ? ('R') : ('T'));
568 +
569 + priv->status = STATUS_ADDR;
570 +
571 + if (!(msg->flags & I2C_M_RD)) {
572 + len += msg->len;
573 + } else {
574 + /* set maximum received packet size (before rx int!) */
575 + i2c_w32(msg->len, mrps_ctrl);
576 + }
577 + i2c_w32(len, tps_ctrl);
578 + enable_burst_irq(priv);
579 +}
580 +
581 +static int falcon_i2c_hw_init(struct i2c_adapter *adap)
582 +{
583 + struct falcon_i2c *priv = i2c_get_adapdata(adap);
584 +
585 + /* disable bus */
586 + i2c_w32_mask(I2C_RUN_CTRL_RUN_EN, 0, run_ctrl);
587 +
588 +#ifndef DEBUG
589 + /* set normal operation clock divider */
590 + i2c_w32(1 << I2C_CLC_RMC_OFFSET, clc);
591 +#else
592 + /* for debugging a higher divider value! */
593 + i2c_w32(0xF0 << I2C_CLC_RMC_OFFSET, clc);
594 +#endif
595 +
596 + /* set frequency */
597 + if (priv->mode == FALCON_I2C_MODE_100) {
598 + dev_dbg(priv->dev, "set standard mode (100 kHz)\n");
599 + i2c_w32(0, fdiv_high_cfg);
600 + i2c_w32((1 << I2C_FDIV_CFG_INC_OFFSET) |
601 + (499 << I2C_FDIV_CFG_DEC_OFFSET),
602 + fdiv_cfg);
603 + } else if (priv->mode == FALCON_I2C_MODE_400) {
604 + dev_dbg(priv->dev, "set fast mode (400 kHz)\n");
605 + i2c_w32(0, fdiv_high_cfg);
606 + i2c_w32((1 << I2C_FDIV_CFG_INC_OFFSET) |
607 + (124 << I2C_FDIV_CFG_DEC_OFFSET),
608 + fdiv_cfg);
609 + } else if (priv->mode == FALCON_I2C_MODE_3400) {
610 + dev_dbg(priv->dev, "set high mode (3.4 MHz)\n");
611 + i2c_w32(0, fdiv_cfg);
612 + /* TODO recalculate value for 100MHz input */
613 + i2c_w32((41 << I2C_FDIV_HIGH_CFG_INC_OFFSET) |
614 + (152 << I2C_FDIV_HIGH_CFG_DEC_OFFSET),
615 + fdiv_high_cfg);
616 + } else {
617 + dev_warn(priv->dev, "unknown mode\n");
618 + return -ENODEV;
619 + }
620 +
621 + /* configure fifo */
622 + i2c_w32(I2C_FIFO_CFG_TXFC | /* tx fifo as flow controller */
623 + I2C_FIFO_CFG_RXFC | /* rx fifo as flow controller */
624 + I2C_FIFO_CFG_TXFA_TXFA2 | /* tx fifo 4-byte aligned */
625 + I2C_FIFO_CFG_RXFA_RXFA2 | /* rx fifo 4-byte aligned */
626 + I2C_FIFO_CFG_TXBS_TXBS0 | /* tx fifo burst size is 1 word */
627 + I2C_FIFO_CFG_RXBS_RXBS0, /* rx fifo burst size is 1 word */
628 + fifo_cfg);
629 +
630 + /* configure address */
631 + i2c_w32(I2C_ADDR_CFG_SOPE_EN | /* generate stop when no more data
632 + in the fifo */
633 + I2C_ADDR_CFG_SONA_EN | /* generate stop when NA received */
634 + I2C_ADDR_CFG_MnS_EN | /* we are master device */
635 + 0, /* our slave address (not used!) */
636 + addr_cfg);
637 +
638 + /* enable bus */
639 + i2c_w32_mask(0, I2C_RUN_CTRL_RUN_EN, run_ctrl);
640 +
641 + return 0;
642 +}
643 +
644 +static int falcon_i2c_wait_bus_not_busy(struct falcon_i2c *priv)
645 +{
646 + int timeout = FALCON_I2C_BUSY_TIMEOUT;
647 +
648 + while ((i2c_r32(bus_stat) & I2C_BUS_STAT_BS_MASK)
649 + != I2C_BUS_STAT_BS_FREE) {
650 + if (timeout <= 0) {
651 + dev_warn(priv->dev, "timeout waiting for bus ready\n");
652 + return -ETIMEDOUT;
653 + }
654 + timeout--;
655 + mdelay(1);
656 + }
657 +
658 + return 0;
659 +}
660 +
661 +static void falcon_i2c_tx(struct falcon_i2c *priv, int last)
662 +{
663 + if (priv->msg_buf_len && priv->msg_buf) {
664 + i2c_w32(*priv->msg_buf, txd);
665 +
666 + if (--priv->msg_buf_len)
667 + priv->msg_buf++;
668 + else
669 + priv->msg_buf = NULL;
670 + } else
671 + last = 1;
672 +
673 + if (last)
674 + disable_burst_irq(priv);
675 +}
676 +
677 +static void falcon_i2c_rx(struct falcon_i2c *priv, int last)
678 +{
679 + u32 fifo_stat, timeout;
680 + if (priv->msg_buf_len && priv->msg_buf) {
681 + timeout = 5000000;
682 + do {
683 + fifo_stat = i2c_r32(ffs_stat);
684 + } while (!fifo_stat && --timeout);
685 + if (!timeout) {
686 + last = 1;
687 + PRINTK("\nrx timeout\n");
688 + goto err;
689 + }
690 + while (fifo_stat) {
691 + *priv->msg_buf = i2c_r32(rxd);
692 + if (--priv->msg_buf_len)
693 + priv->msg_buf++;
694 + else {
695 + priv->msg_buf = NULL;
696 + last = 1;
697 + break;
698 + }
699 + #if 0
700 + fifo_stat = i2c_r32(ffs_stat);
701 + #else
702 + /* do not read more than burst size, otherwise no "last
703 + burst" is generated and the transaction is blocked! */
704 + fifo_stat = 0;
705 + #endif
706 + }
707 + } else {
708 + last = 1;
709 + }
710 +err:
711 + if (last) {
712 + disable_burst_irq(priv);
713 +
714 + if (priv->status == STATUS_READ_END) {
715 + /* do the STATUS_STOP and complete() here, as sometimes
716 + the tx_end is already seen before this is finished */
717 + priv->status = STATUS_STOP;
718 + complete(&priv->cmd_complete);
719 + } else {
720 + i2c_w32(I2C_ENDD_CTRL_SETEND, endd_ctrl);
721 + priv->status = STATUS_READ_END;
722 + }
723 + }
724 +}
725 +
726 +static void falcon_i2c_xfer_init(struct falcon_i2c *priv)
727 +{
728 + /* enable interrupts */
729 + i2c_w32(FALCON_I2C_IMSC_DEFAULT_MASK, imsc);
730 +
731 + /* trigger transfer of first msg */
732 + set_tx_len(priv);
733 +}
734 +
735 +static void dump_msgs(struct i2c_msg msgs[], int num, int rx)
736 +{
737 +#if defined(DEBUG)
738 + int i, j;
739 + pr_info("Messages %d %s\n", num, rx ? "out" : "in");
740 + for (i = 0; i < num; i++) {
741 + pr_info("%2d %cX Msg(%d) addr=0x%X: ", i,
742 + (msgs[i].flags & I2C_M_RD) ? ('R') : ('T'),
743 + msgs[i].len, msgs[i].addr);
744 + if (!(msgs[i].flags & I2C_M_RD) || rx) {
745 + for (j = 0; j < msgs[i].len; j++)
746 + printk("%02X ", msgs[i].buf[j]);
747 + }
748 + printk("\n");
749 + }
750 +#endif
751 +}
752 +
753 +static void falcon_i2c_release_bus(struct falcon_i2c *priv)
754 +{
755 + if ((i2c_r32(bus_stat) & I2C_BUS_STAT_BS_MASK) == I2C_BUS_STAT_BS_BM)
756 + i2c_w32(I2C_ENDD_CTRL_SETEND, endd_ctrl);
757 +}
758 +
759 +static int falcon_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[],
760 + int num)
761 +{
762 + struct falcon_i2c *priv = i2c_get_adapdata(adap);
763 + int ret;
764 +
765 + dev_dbg(priv->dev, "xfer %u messages\n", num);
766 + dump_msgs(msgs, num, 0);
767 +
768 + mutex_lock(&priv->mutex);
769 +
770 + INIT_COMPLETION(priv->cmd_complete);
771 + priv->current_msg = msgs;
772 + priv->msgs_num = num;
773 + priv->msg_err = 0;
774 + priv->status = STATUS_IDLE;
775 +
776 + /* wait for the bus to become ready */
777 + ret = falcon_i2c_wait_bus_not_busy(priv);
778 + if (ret)
779 + goto done;
780 +
781 + while (priv->msgs_num) {
782 + /* start the transfers */
783 + falcon_i2c_xfer_init(priv);
784 +
785 + /* wait for transfers to complete */
786 + ret = wait_for_completion_interruptible_timeout(
787 + &priv->cmd_complete, FALCON_I2C_XFER_TIMEOUT);
788 + if (ret == 0) {
789 + dev_err(priv->dev, "controller timed out\n");
790 + falcon_i2c_hw_init(adap);
791 + ret = -ETIMEDOUT;
792 + goto done;
793 + } else if (ret < 0)
794 + goto done;
795 +
796 + if (priv->msg_err) {
797 + if (priv->msg_err & FALCON_I2C_NACK)
798 + ret = -ENXIO;
799 + else
800 + ret = -EREMOTEIO;
801 + goto done;
802 + }
803 + if (--priv->msgs_num)
804 + priv->current_msg++;
805 + }
806 + /* no error? */
807 + ret = num;
808 +
809 +done:
810 + falcon_i2c_release_bus(priv);
811 +
812 + mutex_unlock(&priv->mutex);
813 +
814 + if (ret >= 0)
815 + dump_msgs(msgs, num, 1);
816 +
817 + PRINTK("XFER ret %d\n", ret);
818 + return ret;
819 +}
820 +
821 +static irqreturn_t falcon_i2c_isr_burst(int irq, void *dev_id)
822 +{
823 + struct falcon_i2c *priv = dev_id;
824 + struct i2c_msg *msg = priv->current_msg;
825 + int last = (irq == priv->irq_lb);
826 +
827 + if (last)
828 + PRINTK("LB ");
829 + else
830 + PRINTK("B ");
831 +
832 + if (msg->flags & I2C_M_RD) {
833 + switch (priv->status) {
834 + case STATUS_ADDR:
835 + PRINTK("X");
836 + prepare_msg_send_addr(priv);
837 + disable_burst_irq(priv);
838 + break;
839 + case STATUS_READ:
840 + case STATUS_READ_END:
841 + PRINTK("R");
842 + falcon_i2c_rx(priv, last);
843 + break;
844 + default:
845 + disable_burst_irq(priv);
846 + PRINTK("Status R %d\n", priv->status);
847 + break;
848 + }
849 + } else {
850 + switch (priv->status) {
851 + case STATUS_ADDR:
852 + PRINTK("x");
853 + prepare_msg_send_addr(priv);
854 + break;
855 + case STATUS_WRITE:
856 + PRINTK("w");
857 + falcon_i2c_tx(priv, last);
858 + break;
859 + default:
860 + disable_burst_irq(priv);
861 + PRINTK("Status W %d\n", priv->status);
862 + break;
863 + }
864 + }
865 +
866 + i2c_w32(I2C_ICR_BREQ_INT_CLR | I2C_ICR_LBREQ_INT_CLR, icr);
867 + return IRQ_HANDLED;
868 +}
869 +
870 +static void falcon_i2c_isr_prot(struct falcon_i2c *priv)
871 +{
872 + u32 i_pro = i2c_r32(p_irqss);
873 +
874 + PRINTK("i2c-p");
875 +
876 + /* not acknowledge */
877 + if (i_pro & I2C_P_IRQSS_NACK) {
878 + priv->msg_err |= FALCON_I2C_NACK;
879 + PRINTK(" nack");
880 + }
881 +
882 + /* arbitration lost */
883 + if (i_pro & I2C_P_IRQSS_AL) {
884 + priv->msg_err |= FALCON_I2C_ARB_LOST;
885 + PRINTK(" arb-lost");
886 + }
887 + /* tx -> rx switch */
888 + if (i_pro & I2C_P_IRQSS_RX)
889 + PRINTK(" rx");
890 +
891 + /* tx end */
892 + if (i_pro & I2C_P_IRQSS_TX_END)
893 + PRINTK(" txend");
894 + PRINTK("\n");
895 +
896 + if (!priv->msg_err) {
897 + /* tx -> rx switch */
898 + if (i_pro & I2C_P_IRQSS_RX) {
899 + priv->status = STATUS_READ;
900 + enable_burst_irq(priv);
901 + }
902 + if (i_pro & I2C_P_IRQSS_TX_END) {
903 + if (priv->status == STATUS_READ)
904 + priv->status = STATUS_READ_END;
905 + else {
906 + disable_burst_irq(priv);
907 + priv->status = STATUS_STOP;
908 + }
909 + }
910 + }
911 +
912 + i2c_w32(i_pro, p_irqsc);
913 +}
914 +
915 +static irqreturn_t falcon_i2c_isr(int irq, void *dev_id)
916 +{
917 + u32 i_raw, i_err = 0;
918 + struct falcon_i2c *priv = dev_id;
919 +
920 + i_raw = i2c_r32(mis);
921 + PRINTK("i_raw 0x%08X\n", i_raw);
922 +
923 + /* error interrupt */
924 + if (i_raw & I2C_RIS_I2C_ERR_INT_INTOCC) {
925 + i_err = i2c_r32(err_irqss);
926 + PRINTK("i_err 0x%08X bus_stat 0x%04X\n",
927 + i_err, i2c_r32(bus_stat));
928 +
929 + /* tx fifo overflow (8) */
930 + if (i_err & I2C_ERR_IRQSS_TXF_OFL)
931 + priv->msg_err |= FALCON_I2C_TX_OFL;
932 +
933 + /* tx fifo underflow (4) */
934 + if (i_err & I2C_ERR_IRQSS_TXF_UFL)
935 + priv->msg_err |= FALCON_I2C_TX_UFL;
936 +
937 + /* rx fifo overflow (2) */
938 + if (i_err & I2C_ERR_IRQSS_RXF_OFL)
939 + priv->msg_err |= FALCON_I2C_RX_OFL;
940 +
941 + /* rx fifo underflow (1) */
942 + if (i_err & I2C_ERR_IRQSS_RXF_UFL)
943 + priv->msg_err |= FALCON_I2C_RX_UFL;
944 +
945 + i2c_w32(i_err, err_irqsc);
946 + }
947 +
948 + /* protocol interrupt */
949 + if (i_raw & I2C_RIS_I2C_P_INT_INTOCC)
950 + falcon_i2c_isr_prot(priv);
951 +
952 + if ((priv->msg_err) || (priv->status == STATUS_STOP))
953 + complete(&priv->cmd_complete);
954 +
955 + return IRQ_HANDLED;
956 +}
957 +
958 +static u32 falcon_i2c_functionality(struct i2c_adapter *adap)
959 +{
960 + return I2C_FUNC_I2C |
961 + I2C_FUNC_10BIT_ADDR |
962 + I2C_FUNC_SMBUS_EMUL;
963 +}
964 +
965 +static struct i2c_algorithm falcon_i2c_algorithm = {
966 + .master_xfer = falcon_i2c_xfer,
967 + .functionality = falcon_i2c_functionality,
968 +};
969 +
970 +static int __devinit falcon_i2c_probe(struct platform_device *pdev)
971 +{
972 + int ret = 0;
973 + struct falcon_i2c *priv;
974 + struct i2c_adapter *adap;
975 + struct resource *mmres, *ioarea,
976 + *irqres_lb, *irqres_b, *irqres_err, *irqres_p;
977 + struct clk *clk;
978 +
979 + dev_dbg(&pdev->dev, "probing\n");
980 +
981 + mmres = platform_get_resource(pdev, IORESOURCE_MEM, 0);
982 + irqres_lb = platform_get_resource_byname(pdev, IORESOURCE_IRQ,
983 + "i2c_lb");
984 + irqres_b = platform_get_resource_byname(pdev, IORESOURCE_IRQ, "i2c_b");
985 + irqres_err = platform_get_resource_byname(pdev, IORESOURCE_IRQ,
986 + "i2c_err");
987 + irqres_p = platform_get_resource_byname(pdev, IORESOURCE_IRQ, "i2c_p");
988 +
989 + if (!mmres || !irqres_lb || !irqres_b || !irqres_err || !irqres_p) {
990 + dev_err(&pdev->dev, "no resources\n");
991 + return -ENODEV;
992 + }
993 +
994 + clk = clk_get_fpi();
995 + if (IS_ERR(clk)) {
996 + dev_err(&pdev->dev, "failed to get fpi clk\n");
997 + return -ENOENT;
998 + }
999 +
1000 + if (clk_get_rate(clk) != 100000000) {
1001 + dev_err(&pdev->dev, "input clock is not 100MHz\n");
1002 + return -ENOENT;
1003 + }
1004 + clk = clk_get(&pdev->dev, NULL);
1005 + if (IS_ERR(clk)) {
1006 + dev_err(&pdev->dev, "failed to get i2c clk\n");
1007 + return -ENOENT;
1008 + }
1009 +
1010 + /* allocate private data */
1011 + priv = kzalloc(sizeof(*priv), GFP_KERNEL);
1012 + if (!priv) {
1013 + dev_err(&pdev->dev, "can't allocate private data\n");
1014 + return -ENOMEM;
1015 + }
1016 +
1017 + adap = &priv->adap;
1018 + i2c_set_adapdata(adap, priv);
1019 + adap->owner = THIS_MODULE;
1020 + adap->class = I2C_CLASS_HWMON | I2C_CLASS_SPD;
1021 + strlcpy(adap->name, DRV_NAME "-adapter", sizeof(adap->name));
1022 + adap->algo = &falcon_i2c_algorithm;
1023 +
1024 + priv->mode = FALCON_I2C_MODE_100;
1025 + priv->clk = clk;
1026 + priv->dev = &pdev->dev;
1027 +
1028 + init_completion(&priv->cmd_complete);
1029 + mutex_init(&priv->mutex);
1030 +
1031 + if (ltq_gpio_request(&pdev->dev, 107, 0, 0, DRV_NAME":sda") ||
1032 + ltq_gpio_request(&pdev->dev, 108, 0, 0, DRV_NAME":scl"))
1033 + {
1034 + dev_err(&pdev->dev, "I2C gpios not available\n");
1035 + ret = -ENXIO;
1036 + goto err_free_priv;
1037 + }
1038 +
1039 + ioarea = request_mem_region(mmres->start, resource_size(mmres),
1040 + pdev->name);
1041 +
1042 + if (ioarea == NULL) {
1043 + dev_err(&pdev->dev, "I2C region already claimed\n");
1044 + ret = -ENXIO;
1045 + goto err_free_gpio;
1046 + }
1047 +
1048 + /* map memory */
1049 + priv->membase = ioremap_nocache(mmres->start & ~KSEG1,
1050 + resource_size(mmres));
1051 + if (priv->membase == NULL) {
1052 + ret = -ENOMEM;
1053 + goto err_release_region;
1054 + }
1055 +
1056 + priv->irq_lb = irqres_lb->start;
1057 + ret = request_irq(priv->irq_lb, falcon_i2c_isr_burst, IRQF_DISABLED,
1058 + irqres_lb->name, priv);
1059 + if (ret) {
1060 + dev_err(&pdev->dev, "can't get last burst IRQ %d\n",
1061 + irqres_lb->start);
1062 + ret = -ENODEV;
1063 + goto err_unmap_mem;
1064 + }
1065 +
1066 + priv->irq_b = irqres_b->start;
1067 + ret = request_irq(priv->irq_b, falcon_i2c_isr_burst, IRQF_DISABLED,
1068 + irqres_b->name, priv);
1069 + if (ret) {
1070 + dev_err(&pdev->dev, "can't get burst IRQ %d\n",
1071 + irqres_b->start);
1072 + ret = -ENODEV;
1073 + goto err_free_lb_irq;
1074 + }
1075 +
1076 + priv->irq_err = irqres_err->start;
1077 + ret = request_irq(priv->irq_err, falcon_i2c_isr, IRQF_DISABLED,
1078 + irqres_err->name, priv);
1079 + if (ret) {
1080 + dev_err(&pdev->dev, "can't get error IRQ %d\n",
1081 + irqres_err->start);
1082 + ret = -ENODEV;
1083 + goto err_free_b_irq;
1084 + }
1085 +
1086 + priv->irq_p = irqres_p->start;
1087 + ret = request_irq(priv->irq_p, falcon_i2c_isr, IRQF_DISABLED,
1088 + irqres_p->name, priv);
1089 + if (ret) {
1090 + dev_err(&pdev->dev, "can't get protocol IRQ %d\n",
1091 + irqres_p->start);
1092 + ret = -ENODEV;
1093 + goto err_free_err_irq;
1094 + }
1095 +
1096 + dev_dbg(&pdev->dev, "mapped io-space to %p\n", priv->membase);
1097 + dev_dbg(&pdev->dev, "use IRQs %d, %d, %d, %d\n", irqres_lb->start,
1098 + irqres_b->start, irqres_err->start, irqres_p->start);
1099 +
1100 + /* add our adapter to the i2c stack */
1101 + ret = i2c_add_numbered_adapter(adap);
1102 + if (ret) {
1103 + dev_err(&pdev->dev, "can't register I2C adapter\n");
1104 + goto err_free_p_irq;
1105 + }
1106 +
1107 + platform_set_drvdata(pdev, priv);
1108 + i2c_set_adapdata(adap, priv);
1109 +
1110 + /* print module version information */
1111 + dev_dbg(&pdev->dev, "module id=%u revision=%u\n",
1112 + (i2c_r32(id) & I2C_ID_ID_MASK) >> I2C_ID_ID_OFFSET,
1113 + (i2c_r32(id) & I2C_ID_REV_MASK) >> I2C_ID_REV_OFFSET);
1114 +
1115 + /* initialize HW */
1116 + ret = falcon_i2c_hw_init(adap);
1117 + if (ret) {
1118 + dev_err(&pdev->dev, "can't configure adapter\n");
1119 + goto err_remove_adapter;
1120 + }
1121 +
1122 + dev_info(&pdev->dev, "version %s\n", DRV_VERSION);
1123 +
1124 + return 0;
1125 +
1126 +err_remove_adapter:
1127 + i2c_del_adapter(adap);
1128 + platform_set_drvdata(pdev, NULL);
1129 +
1130 +err_free_p_irq:
1131 + free_irq(priv->irq_p, priv);
1132 +
1133 +err_free_err_irq:
1134 + free_irq(priv->irq_err, priv);
1135 +
1136 +err_free_b_irq:
1137 + free_irq(priv->irq_b, priv);
1138 +
1139 +err_free_lb_irq:
1140 + free_irq(priv->irq_lb, priv);
1141 +
1142 +err_unmap_mem:
1143 + iounmap(priv->membase);
1144 +
1145 +err_release_region:
1146 + release_mem_region(mmres->start, resource_size(mmres));
1147 +
1148 +err_free_gpio:
1149 + gpio_free(108);
1150 + gpio_free(107);
1151 +
1152 +err_free_priv:
1153 + kfree(priv);
1154 +
1155 + return ret;
1156 +}
1157 +
1158 +static int __devexit falcon_i2c_remove(struct platform_device *pdev)
1159 +{
1160 + struct falcon_i2c *priv = platform_get_drvdata(pdev);
1161 + struct resource *mmres;
1162 +
1163 + /* disable bus */
1164 + i2c_w32_mask(I2C_RUN_CTRL_RUN_EN, 0, run_ctrl);
1165 +
1166 + /* remove driver */
1167 + platform_set_drvdata(pdev, NULL);
1168 + i2c_del_adapter(&priv->adap);
1169 +
1170 + free_irq(priv->irq_lb, priv);
1171 + free_irq(priv->irq_b, priv);
1172 + free_irq(priv->irq_err, priv);
1173 + free_irq(priv->irq_p, priv);
1174 +
1175 + iounmap(priv->membase);
1176 +
1177 + gpio_free(108);
1178 + gpio_free(107);
1179 +
1180 + kfree(priv);
1181 +
1182 + mmres = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1183 + release_mem_region(mmres->start, resource_size(mmres));
1184 +
1185 + dev_dbg(&pdev->dev, "removed\n");
1186 +
1187 + return 0;
1188 +}
1189 +
1190 +static struct platform_driver falcon_i2c_driver = {
1191 + .probe = falcon_i2c_probe,
1192 + .remove = __devexit_p(falcon_i2c_remove),
1193 + .driver = {
1194 + .name = DRV_NAME,
1195 + .owner = THIS_MODULE,
1196 + },
1197 +};
1198 +
1199 +static int __init falcon_i2c_init(void)
1200 +{
1201 + int ret;
1202 +
1203 + ret = platform_driver_register(&falcon_i2c_driver);
1204 +
1205 + if (ret)
1206 + pr_debug(DRV_NAME ": can't register platform driver\n");
1207 +
1208 + return ret;
1209 +}
1210 +
1211 +static void __exit falcon_i2c_exit(void)
1212 +{
1213 + platform_driver_unregister(&falcon_i2c_driver);
1214 +}
1215 +
1216 +module_init(falcon_i2c_init);
1217 +module_exit(falcon_i2c_exit);
1218 +
1219 +MODULE_DESCRIPTION("Lantiq FALC(tm) ON - I2C bus adapter");
1220 +MODULE_ALIAS("platform:" DRV_NAME);
1221 +MODULE_LICENSE("GPL");
1222 +MODULE_VERSION(DRV_VERSION);
1223 --
1224 1.7.7.1
1225
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