toolchain/gcc/patches/4.3.5/946-avr32_fix_32bit_div_2.patch

   1 --- a/gcc/config/avr32/lib1funcs.S
   2 +++ b/gcc/config/avr32/lib1funcs.S
   3 @@ -2271,7 +2271,7 @@ __avr32_f32_div:
   4
   5          tst     r12, r12
   6          moveq   r9, 0
   7 -        breq    12
   8 +        breq    12f
   9
  10          /* Unpack op1*/
  11          /* exp: r9 */
  12 @@ -2467,9 +2467,14 @@ __divsf_return_op1:
  13          reteq   0       /* Return zero if number/inf*/
  14          ret     -1      /* Return NaN*/
  15  4:
  16 -        /* Op2 is zero ? */
  17 +        /* Op1 is zero ? */
  18          tst     r12,r12
  19          reteq   -1      /* 0.0/0.0 is NaN */
  20 +        /* Op1 is Nan? */
  21 +        lsr     r9, r12, 24
  22 +        breq    11f /*If number is subnormal*/
  23 +        cp      r9, 0xff
  24 +        brhs    2b  /* Check op1 for NaN or Inf */
  25          /* Nonzero/0.0 is Inf. Sign bit will be shifted in before returning*/
  26         mov_imm r12, 0xff000000
  27          rjmp    __divsf_return_op1