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Fix tx error handling (#2552). Make rx ring size actually configurable through
[openwrt.git] / package / rt2x00 / src / rt73usb.c
1 /*
2 Copyright (C) 2004 - 2007 rt2x00 SourceForge Project
3 <http://rt2x00.serialmonkey.com>
4
5 This program is free software; you can redistribute it and/or modify
6 it under the terms of the GNU General Public License as published by
7 the Free Software Foundation; either version 2 of the License, or
8 (at your option) any later version.
9
10 This program is distributed in the hope that it will be useful,
11 but WITHOUT ANY WARRANTY; without even the implied warranty of
12 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 GNU General Public License for more details.
14
15 You should have received a copy of the GNU General Public License
16 along with this program; if not, write to the
17 Free Software Foundation, Inc.,
18 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
19 */
20
21 /*
22 Module: rt73usb
23 Abstract: rt73usb device specific routines.
24 Supported chipsets: rt2571W & rt2671.
25 */
26
27 /*
28 * Set enviroment defines for rt2x00.h
29 */
30 #define DRV_NAME "rt73usb"
31
32 #include <linux/kernel.h>
33 #include <linux/module.h>
34 #include <linux/version.h>
35 #include <linux/init.h>
36 #include <linux/usb.h>
37 #include <linux/delay.h>
38 #include <linux/etherdevice.h>
39
40 #include "rt2x00.h"
41 #include "rt2x00lib.h"
42 #include "rt2x00usb.h"
43 #include "rt73usb.h"
44
45 /*
46 * Register access.
47 * All access to the CSR registers will go through the methods
48 * rt73usb_register_read and rt73usb_register_write.
49 * BBP and RF register require indirect register access,
50 * and use the CSR registers BBPCSR and RFCSR to achieve this.
51 * These indirect registers work with busy bits,
52 * and we will try maximal REGISTER_BUSY_COUNT times to access
53 * the register while taking a REGISTER_BUSY_DELAY us delay
54 * between each attampt. When the busy bit is still set at that time,
55 * the access attempt is considered to have failed,
56 * and we will print an error.
57 */
58 static inline void rt73usb_register_read(
59 const struct rt2x00_dev *rt2x00dev,
60 const u16 offset, u32 *value)
61 {
62 __le32 reg;
63 rt2x00usb_vendor_request(
64 rt2x00dev, USB_MULTI_READ, USB_VENDOR_REQUEST_IN,
65 offset, 0x00, &reg, sizeof(u32), REGISTER_TIMEOUT);
66 *value = le32_to_cpu(reg);
67 }
68
69 static inline void rt73usb_register_multiread(
70 const struct rt2x00_dev *rt2x00dev,
71 const u16 offset, void *value, const u32 length)
72 {
73 rt2x00usb_vendor_request(
74 rt2x00dev, USB_MULTI_READ, USB_VENDOR_REQUEST_IN,
75 offset, 0x00, value, length,
76 REGISTER_TIMEOUT * (length / sizeof(u32)));
77 }
78
79 static inline void rt73usb_register_write(
80 const struct rt2x00_dev *rt2x00dev,
81 const u16 offset, u32 value)
82 {
83 __le32 reg = cpu_to_le32(value);
84 rt2x00usb_vendor_request(
85 rt2x00dev, USB_MULTI_WRITE, USB_VENDOR_REQUEST_OUT,
86 offset, 0x00, &reg, sizeof(u32), REGISTER_TIMEOUT);
87 }
88
89 static inline void rt73usb_register_multiwrite(
90 const struct rt2x00_dev *rt2x00dev,
91 const u16 offset, void *value, const u32 length)
92 {
93 rt2x00usb_vendor_request(
94 rt2x00dev, USB_MULTI_WRITE, USB_VENDOR_REQUEST_OUT,
95 offset, 0x00, value, length,
96 REGISTER_TIMEOUT * (length / sizeof(u32)));
97 }
98
99 static u32 rt73usb_bbp_check(const struct rt2x00_dev *rt2x00dev)
100 {
101 u32 reg;
102 unsigned int i;
103
104 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
105 rt73usb_register_read(rt2x00dev, PHY_CSR3, &reg);
106 if (!rt2x00_get_field32(reg, PHY_CSR3_BUSY))
107 break;
108 udelay(REGISTER_BUSY_DELAY);
109 }
110
111 return reg;
112 }
113
114 static void rt73usb_bbp_write(const struct rt2x00_dev *rt2x00dev,
115 const u8 reg_id, const u8 value)
116 {
117 u32 reg;
118
119 /*
120 * Wait until the BBP becomes ready.
121 */
122 reg = rt73usb_bbp_check(rt2x00dev);
123 if (rt2x00_get_field32(reg, PHY_CSR3_BUSY)) {
124 ERROR(rt2x00dev, "PHY_CSR3 register busy. Write failed.\n");
125 return;
126 }
127
128 /*
129 * Write the data into the BBP.
130 */
131 reg = 0;
132 rt2x00_set_field32(&reg, PHY_CSR3_VALUE, value);
133 rt2x00_set_field32(&reg, PHY_CSR3_REGNUM, reg_id);
134 rt2x00_set_field32(&reg, PHY_CSR3_BUSY, 1);
135 rt2x00_set_field32(&reg, PHY_CSR3_READ_CONTROL, 0);
136
137 rt73usb_register_write(rt2x00dev, PHY_CSR3, reg);
138 }
139
140 static void rt73usb_bbp_read(const struct rt2x00_dev *rt2x00dev,
141 const u8 reg_id, u8 *value)
142 {
143 u32 reg;
144
145 /*
146 * Wait until the BBP becomes ready.
147 */
148 reg = rt73usb_bbp_check(rt2x00dev);
149 if (rt2x00_get_field32(reg, PHY_CSR3_BUSY)) {
150 ERROR(rt2x00dev, "PHY_CSR3 register busy. Read failed.\n");
151 return;
152 }
153
154 /*
155 * Write the request into the BBP.
156 */
157 reg =0;
158 rt2x00_set_field32(&reg, PHY_CSR3_REGNUM, reg_id);
159 rt2x00_set_field32(&reg, PHY_CSR3_BUSY, 1);
160 rt2x00_set_field32(&reg, PHY_CSR3_READ_CONTROL, 1);
161
162 rt73usb_register_write(rt2x00dev, PHY_CSR3, reg);
163
164 /*
165 * Wait until the BBP becomes ready.
166 */
167 reg = rt73usb_bbp_check(rt2x00dev);
168 if (rt2x00_get_field32(reg, PHY_CSR3_BUSY)) {
169 ERROR(rt2x00dev, "PHY_CSR3 register busy. Read failed.\n");
170 *value = 0xff;
171 return;
172 }
173
174 *value = rt2x00_get_field32(reg, PHY_CSR3_VALUE);
175 }
176
177 static void rt73usb_rf_write(const struct rt2x00_dev *rt2x00dev,
178 const u32 value)
179 {
180 u32 reg;
181 unsigned int i;
182
183 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
184 rt73usb_register_read(rt2x00dev, PHY_CSR4, &reg);
185 if (!rt2x00_get_field32(reg, PHY_CSR4_BUSY))
186 goto rf_write;
187 udelay(REGISTER_BUSY_DELAY);
188 }
189
190 ERROR(rt2x00dev, "PHY_CSR4 register busy. Write failed.\n");
191 return;
192
193 rf_write:
194 reg = 0;
195 rt2x00_set_field32(&reg, PHY_CSR4_VALUE, value);
196 rt2x00_set_field32(&reg, PHY_CSR4_NUMBER_OF_BITS, 20);
197 rt2x00_set_field32(&reg, PHY_CSR4_IF_SELECT, 0);
198 rt2x00_set_field32(&reg, PHY_CSR4_BUSY, 1);
199
200 rt73usb_register_write(rt2x00dev, PHY_CSR4, reg);
201 }
202
203 #ifdef CONFIG_RT2X00_LIB_DEBUGFS
204 #define CSR_OFFSET(__word) ( CSR_REG_BASE + ((__word) * sizeof(u32)) )
205
206 static void rt73usb_read_csr(struct rt2x00_dev *rt2x00dev,
207 const unsigned long word, void *data)
208 {
209 rt73usb_register_read(rt2x00dev, CSR_OFFSET(word), data);
210 }
211
212 static void rt73usb_write_csr(struct rt2x00_dev *rt2x00dev,
213 const unsigned long word, void *data)
214 {
215 rt73usb_register_write(rt2x00dev, CSR_OFFSET(word), *((u32*)data));
216 }
217
218 static void rt73usb_read_eeprom(struct rt2x00_dev *rt2x00dev,
219 const unsigned long word, void *data)
220 {
221 rt2x00_eeprom_read(rt2x00dev, word, data);
222 }
223
224 static void rt73usb_write_eeprom(struct rt2x00_dev *rt2x00dev,
225 const unsigned long word, void *data)
226 {
227 rt2x00_eeprom_write(rt2x00dev, word, *((u16*)data));
228 }
229
230 static void rt73usb_read_bbp(struct rt2x00_dev *rt2x00dev,
231 const unsigned long word, void *data)
232 {
233 rt73usb_bbp_read(rt2x00dev, word, data);
234 }
235
236 static void rt73usb_write_bbp(struct rt2x00_dev *rt2x00dev,
237 const unsigned long word, void *data)
238 {
239 rt73usb_bbp_write(rt2x00dev, word, *((u8*)data));
240 }
241
242 static const struct rt2x00debug rt73usb_rt2x00debug = {
243 .owner = THIS_MODULE,
244 .reg_csr = {
245 .read = rt73usb_read_csr,
246 .write = rt73usb_write_csr,
247 .word_size = sizeof(u32),
248 .word_count = CSR_REG_SIZE / sizeof(u32),
249 },
250 .reg_eeprom = {
251 .read = rt73usb_read_eeprom,
252 .write = rt73usb_write_eeprom,
253 .word_size = sizeof(u16),
254 .word_count = EEPROM_SIZE / sizeof(u16),
255 },
256 .reg_bbp = {
257 .read = rt73usb_read_bbp,
258 .write = rt73usb_write_bbp,
259 .word_size = sizeof(u8),
260 .word_count = BBP_SIZE / sizeof(u8),
261 },
262 };
263 #endif /* CONFIG_RT2X00_LIB_DEBUGFS */
264
265 /*
266 * Configuration handlers.
267 */
268 static void rt73usb_config_bssid(struct rt2x00_dev *rt2x00dev, u8 *bssid)
269 {
270 u32 reg[2];
271
272 memset(&reg, 0, sizeof(reg));
273 memcpy(&reg, bssid, ETH_ALEN);
274
275 rt2x00_set_field32(&reg[1], MAC_CSR5_BSS_ID_MASK, 3);
276
277 /*
278 * The BSSID is passed to us as an array of bytes,
279 * that array is little endian, so no need for byte ordering.
280 */
281 rt73usb_register_multiwrite(rt2x00dev, MAC_CSR4, &reg, sizeof(reg));
282 }
283
284 static void rt73usb_config_promisc(struct rt2x00_dev *rt2x00dev,
285 const int promisc)
286 {
287 u32 reg;
288
289 rt73usb_register_read(rt2x00dev, TXRX_CSR0, &reg);
290 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_NOT_TO_ME, !promisc);
291 rt73usb_register_write(rt2x00dev, TXRX_CSR0, reg);
292 }
293
294 static void rt73usb_config_type(struct rt2x00_dev *rt2x00dev,
295 const int type)
296 {
297 u32 reg;
298
299 rt73usb_register_write(rt2x00dev, TXRX_CSR9, 0);
300
301 /*
302 * Apply hardware packet filter.
303 */
304 rt73usb_register_read(rt2x00dev, TXRX_CSR0, &reg);
305
306 if (!is_monitor_present(&rt2x00dev->interface) &&
307 (type == IEEE80211_IF_TYPE_IBSS || type == IEEE80211_IF_TYPE_STA))
308 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_TO_DS, 1);
309 else
310 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_TO_DS, 0);
311
312 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_CRC, 1);
313 if (is_monitor_present(&rt2x00dev->interface)) {
314 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_PHYSICAL, 0);
315 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_CONTROL, 0);
316 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_VERSION_ERROR, 0);
317 } else {
318 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_PHYSICAL, 1);
319 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_CONTROL, 1);
320 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_VERSION_ERROR, 1);
321 }
322
323 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_MULTICAST, 0);
324 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_BORADCAST, 0);
325
326 rt73usb_register_write(rt2x00dev, TXRX_CSR0, reg);
327
328 /*
329 * Enable synchronisation.
330 */
331 rt73usb_register_read(rt2x00dev, TXRX_CSR9, &reg);
332 if (is_interface_present(&rt2x00dev->interface)) {
333 rt2x00_set_field32(&reg, TXRX_CSR9_TSF_TICKING, 1);
334 rt2x00_set_field32(&reg, TXRX_CSR9_TBTT_ENABLE, 1);
335 }
336
337 rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_GEN, 0);
338 if (type == IEEE80211_IF_TYPE_IBSS || type == IEEE80211_IF_TYPE_AP)
339 rt2x00_set_field32(&reg, TXRX_CSR9_TSF_SYNC, 2);
340 else if (type == IEEE80211_IF_TYPE_STA)
341 rt2x00_set_field32(&reg, TXRX_CSR9_TSF_SYNC, 1);
342 else if (is_monitor_present(&rt2x00dev->interface) &&
343 !is_interface_present(&rt2x00dev->interface))
344 rt2x00_set_field32(&reg, TXRX_CSR9_TSF_SYNC, 0);
345
346 rt73usb_register_write(rt2x00dev, TXRX_CSR9, reg);
347 }
348
349 static void rt73usb_config_channel(struct rt2x00_dev *rt2x00dev,
350 const int value, const int channel, const int txpower)
351 {
352 u8 reg = 0;
353 u32 rf1 = rt2x00dev->rf1;
354 u32 rf2 = value;
355 u32 rf3 = rt2x00dev->rf3;
356 u32 rf4 = 0;
357
358 if (rt2x00_rf(&rt2x00dev->chip, RF5225) ||
359 rt2x00_rf(&rt2x00dev->chip, RF2527))
360 rf2 |= 0x00004000;
361
362 if (rt2x00_rf(&rt2x00dev->chip, RF5225)) {
363 if (channel <= 14)
364 rf3 = 0x00068455;
365 else if (channel >= 36 && channel <= 48)
366 rf3 = 0x0009be55;
367 else if (channel >= 52 && channel <= 64)
368 rf3 = 0x0009ae55;
369 else if (channel >= 100 && channel <= 112)
370 rf3 = 0x000bae55;
371 else
372 rf3 = 0x000bbe55;
373 }
374
375 if (channel < 14) {
376 if (channel & 0x01)
377 rf4 = 0x000fea0b;
378 else
379 rf4 = 0x000fea1f;
380 } else if (channel == 14) {
381 rf4 = 0x000fea13;
382 } else {
383 switch (channel) {
384 case 36:
385 case 56:
386 case 116:
387 case 136:
388 rf4 = 0x000fea23;
389 break;
390 case 40:
391 case 60:
392 case 100:
393 case 120:
394 case 140:
395 rf4 = 0x000fea03;
396 break;
397 case 44:
398 case 64:
399 case 104:
400 case 124:
401 rf4 = 0x000fea0b;
402 break;
403 case 48:
404 case 108:
405 case 128:
406 rf4 = 0x000fea13;
407 break;
408 case 52:
409 case 112:
410 case 132:
411 rf4 = 0x000fea1b;
412 break;
413 case 149:
414 rf4 = 0x000fea1f;
415 break;
416 case 153:
417 rf4 = 0x000fea27;
418 break;
419 case 157:
420 rf4 = 0x000fea07;
421 break;
422 case 161:
423 rf4 = 0x000fea0f;
424 break;
425 case 165:
426 rf4 = 0x000fea17;
427 break;
428 }
429 }
430
431 if (rt2x00_rf(&rt2x00dev->chip, RF2527) ||
432 rt2x00_rf(&rt2x00dev->chip, RF5225))
433 rf4 |= 0x00010000;
434
435 /*
436 * Set TXpower.
437 */
438 rt2x00_set_field32(&rf3, RF3_TXPOWER, TXPOWER_TO_DEV(txpower));
439
440 /*
441 * Set Frequency offset.
442 */
443 rt2x00_set_field32(&rf4, RF4_FREQ_OFFSET, rt2x00dev->freq_offset);
444
445 rt73usb_bbp_read(rt2x00dev, 3, &reg);
446 if (rt2x00_rf(&rt2x00dev->chip, RF5225) ||
447 rt2x00_rf(&rt2x00dev->chip, RF2527))
448 reg &= ~0x01;
449 else
450 reg |= 0x01;
451 rt73usb_bbp_write(rt2x00dev, 3, reg);
452
453 rt73usb_rf_write(rt2x00dev, rf1);
454 rt73usb_rf_write(rt2x00dev, rf2);
455 rt73usb_rf_write(rt2x00dev, rf3 & ~0x00000004);
456 rt73usb_rf_write(rt2x00dev, rf4);
457
458 rt73usb_rf_write(rt2x00dev, rf1);
459 rt73usb_rf_write(rt2x00dev, rf2);
460 rt73usb_rf_write(rt2x00dev, rf3 | 0x00000004);
461 rt73usb_rf_write(rt2x00dev, rf4);
462
463 rt73usb_rf_write(rt2x00dev, rf1);
464 rt73usb_rf_write(rt2x00dev, rf2);
465 rt73usb_rf_write(rt2x00dev, rf3 & ~0x00000004);
466 rt73usb_rf_write(rt2x00dev, rf4);
467
468 msleep(1);
469
470 /*
471 * Update rf fields
472 */
473 rt2x00dev->rf1 = rf1;
474 rt2x00dev->rf2 = rf2;
475 rt2x00dev->rf3 = rf3;
476 rt2x00dev->rf4 = rf4;
477 rt2x00dev->tx_power = txpower;
478 }
479
480 static void rt73usb_config_txpower(struct rt2x00_dev *rt2x00dev,
481 const int txpower)
482 {
483 rt2x00_set_field32(&rt2x00dev->rf3, RF3_TXPOWER,
484 TXPOWER_TO_DEV(txpower));
485
486 rt73usb_rf_write(rt2x00dev, rt2x00dev->rf1);
487 rt73usb_rf_write(rt2x00dev, rt2x00dev->rf2);
488 rt73usb_rf_write(rt2x00dev, rt2x00dev->rf3 & ~0x00000004);
489 rt73usb_rf_write(rt2x00dev, rt2x00dev->rf4);
490
491 rt73usb_rf_write(rt2x00dev, rt2x00dev->rf1);
492 rt73usb_rf_write(rt2x00dev, rt2x00dev->rf2);
493 rt73usb_rf_write(rt2x00dev, rt2x00dev->rf3 | 0x00000004);
494 rt73usb_rf_write(rt2x00dev, rt2x00dev->rf4);
495
496 rt73usb_rf_write(rt2x00dev, rt2x00dev->rf1);
497 rt73usb_rf_write(rt2x00dev, rt2x00dev->rf2);
498 rt73usb_rf_write(rt2x00dev, rt2x00dev->rf3 & ~0x00000004);
499 rt73usb_rf_write(rt2x00dev, rt2x00dev->rf4);
500 }
501
502 static void rt73usb_config_antenna(struct rt2x00_dev *rt2x00dev,
503 const int antenna_tx, const int antenna_rx)
504 {
505 u32 reg;
506 u8 r3;
507 u8 r4;
508 u8 r77;
509
510 rt73usb_register_read(rt2x00dev, PHY_CSR0, &reg);
511
512 if (rt2x00dev->curr_hwmode == HWMODE_A) {
513 if (test_bit(CONFIG_EXTERNAL_LNA, &rt2x00dev->flags)) {
514 rt73usb_bbp_write(rt2x00dev, 17, 0x38);
515 rt73usb_bbp_write(rt2x00dev, 96, 0x78);
516 rt73usb_bbp_write(rt2x00dev, 104, 0x48);
517 rt73usb_bbp_write(rt2x00dev, 75, 0x80);
518 rt73usb_bbp_write(rt2x00dev, 86, 0x80);
519 rt73usb_bbp_write(rt2x00dev, 88, 0x80);
520 } else {
521 rt73usb_bbp_write(rt2x00dev, 17, 0x28);
522 rt73usb_bbp_write(rt2x00dev, 96, 0x58);
523 rt73usb_bbp_write(rt2x00dev, 104, 0x38);
524 rt73usb_bbp_write(rt2x00dev, 75, 0xfe);
525 rt73usb_bbp_write(rt2x00dev, 86, 0xfe);
526 rt73usb_bbp_write(rt2x00dev, 88, 0xfe);
527 }
528 rt73usb_bbp_write(rt2x00dev, 35, 0x60);
529 rt73usb_bbp_write(rt2x00dev, 97, 0x58);
530 rt73usb_bbp_write(rt2x00dev, 98, 0x58);
531
532 rt2x00_set_field32(&reg, PHY_CSR0_PA_PE_BG, 0);
533 rt2x00_set_field32(&reg, PHY_CSR0_PA_PE_A, 1);
534 } else {
535 if (test_bit(CONFIG_EXTERNAL_LNA, &rt2x00dev->flags)) {
536 rt73usb_bbp_write(rt2x00dev, 17, 0x30);
537 rt73usb_bbp_write(rt2x00dev, 96, 0x68);
538 rt73usb_bbp_write(rt2x00dev, 104, 0x3c);
539 rt73usb_bbp_write(rt2x00dev, 75, 0x80);
540 rt73usb_bbp_write(rt2x00dev, 86, 0x80);
541 rt73usb_bbp_write(rt2x00dev, 88, 0x80);
542 } else {
543 rt73usb_bbp_write(rt2x00dev, 17, 0x20);
544 rt73usb_bbp_write(rt2x00dev, 96, 0x48);
545 rt73usb_bbp_write(rt2x00dev, 104, 0x2c);
546 rt73usb_bbp_write(rt2x00dev, 75, 0xfe);
547 rt73usb_bbp_write(rt2x00dev, 86, 0xfe);
548 rt73usb_bbp_write(rt2x00dev, 88, 0xfe);
549 }
550 rt73usb_bbp_write(rt2x00dev, 35, 0x50);
551 rt73usb_bbp_write(rt2x00dev, 97, 0x48);
552 rt73usb_bbp_write(rt2x00dev, 98, 0x48);
553
554 rt2x00_set_field32(&reg, PHY_CSR0_PA_PE_BG, 1);
555 rt2x00_set_field32(&reg, PHY_CSR0_PA_PE_A, 0);
556 }
557
558 rt73usb_register_write(rt2x00dev, PHY_CSR0, reg);
559
560 rt73usb_bbp_read(rt2x00dev, 3, &r3);
561 rt73usb_bbp_read(rt2x00dev, 4, &r4);
562 rt73usb_bbp_read(rt2x00dev, 77, &r77);
563
564 rt2x00_set_field8(&r3, BBP_R3_SMART_MODE, 0);
565
566 if (rt2x00_rf(&rt2x00dev->chip, RF5226) ||
567 rt2x00_rf(&rt2x00dev->chip, RF5225)) {
568 if (antenna_rx == ANTENNA_DIVERSITY) {
569 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA, 2);
570 if (rt2x00dev->curr_hwmode != HWMODE_A)
571 rt2x00_set_field8(&r4, BBP_R4_RX_BG_MODE, 1);
572 rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END,
573 test_bit(CONFIG_FRAME_TYPE, &rt2x00dev->flags));
574 } else if (antenna_rx == ANTENNA_A) {
575 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA, 1);
576 rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END,
577 test_bit(CONFIG_FRAME_TYPE, &rt2x00dev->flags));
578 if (rt2x00dev->curr_hwmode == HWMODE_A)
579 rt2x00_set_field8(&r77, BBP_R77_PAIR, 0);
580 else
581 rt2x00_set_field8(&r77, BBP_R77_PAIR, 3);
582 rt73usb_bbp_write(rt2x00dev, 77, r77);
583 } else if (antenna_rx == ANTENNA_B) {
584 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA, 1);
585 rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END,
586 test_bit(CONFIG_FRAME_TYPE, &rt2x00dev->flags));
587 if (rt2x00dev->curr_hwmode == HWMODE_A)
588 rt2x00_set_field8(&r77, BBP_R77_PAIR, 3);
589 else
590 rt2x00_set_field8(&r77, BBP_R77_PAIR, 0);
591 rt73usb_bbp_write(rt2x00dev, 77, r77);
592 }
593 } else if (rt2x00_rf(&rt2x00dev->chip, RF2528) ||
594 rt2x00_rf(&rt2x00dev->chip, RF2527)) {
595 if (antenna_rx == ANTENNA_DIVERSITY) {
596 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA, 2);
597 rt2x00_set_field8(&r4, BBP_R4_RX_BG_MODE, 1);
598 rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END,
599 test_bit(CONFIG_FRAME_TYPE, &rt2x00dev->flags));
600 } else if (antenna_rx == ANTENNA_A) {
601 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA, 1);
602 rt2x00_set_field8(&r4, BBP_R4_RX_BG_MODE, 1);
603 rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END,
604 test_bit(CONFIG_FRAME_TYPE, &rt2x00dev->flags));
605 rt2x00_set_field8(&r77, BBP_R77_PAIR, 3);
606 rt73usb_bbp_write(rt2x00dev, 77, r77);
607 } else if (antenna_rx == ANTENNA_B) {
608 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA, 1);
609 rt2x00_set_field8(&r4, BBP_R4_RX_BG_MODE, 1);
610 rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END,
611 test_bit(CONFIG_FRAME_TYPE, &rt2x00dev->flags));
612 rt2x00_set_field8(&r77, BBP_R77_PAIR, 0);
613 }
614 }
615
616 rt73usb_bbp_write(rt2x00dev, 3, r3);
617 rt73usb_bbp_write(rt2x00dev, 4, r4);
618 }
619
620 static void rt73usb_config_duration(struct rt2x00_dev *rt2x00dev,
621 const int short_slot_time, const int beacon_int)
622 {
623 u32 reg;
624
625 rt73usb_register_read(rt2x00dev, MAC_CSR9, &reg);
626 rt2x00_set_field32(&reg, MAC_CSR9_SLOT_TIME,
627 short_slot_time ? SHORT_SLOT_TIME : SLOT_TIME);
628 rt73usb_register_write(rt2x00dev, MAC_CSR9, reg);
629
630 rt73usb_register_read(rt2x00dev, MAC_CSR8, &reg);
631 rt2x00_set_field32(&reg, MAC_CSR8_SIFS, SIFS);
632 rt2x00_set_field32(&reg, MAC_CSR8_SIFS_AFTER_RX_OFDM, 3);
633 rt2x00_set_field32(&reg, MAC_CSR8_EIFS, EIFS);
634 rt73usb_register_write(rt2x00dev, MAC_CSR8, reg);
635
636 rt73usb_register_read(rt2x00dev, TXRX_CSR0, &reg);
637 rt2x00_set_field32(&reg, TXRX_CSR0_TSF_OFFSET, IEEE80211_HEADER);
638 rt73usb_register_write(rt2x00dev, TXRX_CSR0, reg);
639
640 rt73usb_register_read(rt2x00dev, TXRX_CSR4, &reg);
641 rt2x00_set_field32(&reg, TXRX_CSR4_AUTORESPOND_ENABLE, 1);
642 rt73usb_register_write(rt2x00dev, TXRX_CSR4, reg);
643
644 rt73usb_register_read(rt2x00dev, TXRX_CSR9, &reg);
645 rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_INTERVAL, beacon_int * 16);
646 rt73usb_register_write(rt2x00dev, TXRX_CSR9, reg);
647 }
648
649 static void rt73usb_config_rate(struct rt2x00_dev *rt2x00dev, const int rate)
650 {
651 struct ieee80211_conf *conf = &rt2x00dev->hw->conf;
652 u32 reg;
653 u32 value;
654 u32 preamble;
655
656 preamble = DEVICE_GET_RATE_FIELD(rate, PREAMBLE)
657 ? SHORT_PREAMBLE : PREAMBLE;
658
659 reg = DEVICE_GET_RATE_FIELD(rate, RATEMASK) & DEV_BASIC_RATE;
660
661 rt73usb_register_write(rt2x00dev, TXRX_CSR5, reg);
662
663 rt73usb_register_read(rt2x00dev, TXRX_CSR0, &reg);
664 value = ((conf->flags & IEEE80211_CONF_SHORT_SLOT_TIME) ?
665 SHORT_DIFS : DIFS) +
666 PLCP + preamble + get_duration(ACK_SIZE, 10);
667 rt2x00_set_field32(&reg, TXRX_CSR0_RX_ACK_TIMEOUT, value);
668 rt73usb_register_write(rt2x00dev, TXRX_CSR0, reg);
669
670 rt73usb_register_read(rt2x00dev, TXRX_CSR4, &reg);
671 if (preamble == SHORT_PREAMBLE)
672 rt2x00_set_field32(&reg, TXRX_CSR4_AUTORESPOND_PREAMBLE, 1);
673 else
674 rt2x00_set_field32(&reg, TXRX_CSR4_AUTORESPOND_PREAMBLE, 0);
675 rt73usb_register_write(rt2x00dev, TXRX_CSR4, reg);
676 }
677
678 static void rt73usb_config_phymode(struct rt2x00_dev *rt2x00dev,
679 const int phymode)
680 {
681 struct ieee80211_hw_mode *mode;
682 struct ieee80211_rate *rate;
683
684 if (phymode == MODE_IEEE80211A)
685 rt2x00dev->curr_hwmode = HWMODE_A;
686 else if (phymode == MODE_IEEE80211B)
687 rt2x00dev->curr_hwmode = HWMODE_B;
688 else
689 rt2x00dev->curr_hwmode = HWMODE_G;
690
691 mode = &rt2x00dev->hwmodes[rt2x00dev->curr_hwmode];
692 rate = &mode->rates[mode->num_rates - 1];
693
694 rt73usb_config_rate(rt2x00dev, rate->val2);
695 }
696
697 static void rt73usb_config_mac_addr(struct rt2x00_dev *rt2x00dev, u8 *addr)
698 {
699 u32 reg[2];
700
701 memset(&reg, 0, sizeof(reg));
702 memcpy(&reg, addr, ETH_ALEN);
703
704 rt2x00_set_field32(&reg[1], MAC_CSR3_UNICAST_TO_ME_MASK, 0xff);
705
706 /*
707 * The MAC address is passed to us as an array of bytes,
708 * that array is little endian, so no need for byte ordering.
709 */
710 rt73usb_register_multiwrite(rt2x00dev, MAC_CSR2, &reg, sizeof(reg));
711 }
712
713 /*
714 * LED functions.
715 */
716 static void rt73usb_enable_led(struct rt2x00_dev *rt2x00dev)
717 {
718 u32 reg;
719
720 rt73usb_register_read(rt2x00dev, MAC_CSR14, &reg);
721 rt2x00_set_field32(&reg, MAC_CSR14_ON_PERIOD, 70);
722 rt2x00_set_field32(&reg, MAC_CSR14_OFF_PERIOD, 30);
723 rt73usb_register_write(rt2x00dev, MAC_CSR14, reg);
724
725 rt2x00_set_field16(&rt2x00dev->led_reg, MCU_LEDCS_RADIO_STATUS, 1);
726 if (rt2x00dev->rx_status.phymode == MODE_IEEE80211A)
727 rt2x00_set_field16(
728 &rt2x00dev->led_reg, MCU_LEDCS_LINK_A_STATUS, 1);
729 else
730 rt2x00_set_field16(
731 &rt2x00dev->led_reg, MCU_LEDCS_LINK_BG_STATUS, 1);
732
733 rt2x00usb_vendor_request(
734 rt2x00dev, USB_LED_CONTROL, USB_VENDOR_REQUEST_OUT,
735 0x00, rt2x00dev->led_reg, NULL, 0, REGISTER_TIMEOUT);
736 }
737
738 static void rt73usb_disable_led(struct rt2x00_dev *rt2x00dev)
739 {
740 rt2x00_set_field16(&rt2x00dev->led_reg, MCU_LEDCS_RADIO_STATUS, 0);
741 rt2x00_set_field16(&rt2x00dev->led_reg, MCU_LEDCS_LINK_BG_STATUS, 0);
742 rt2x00_set_field16(&rt2x00dev->led_reg, MCU_LEDCS_LINK_A_STATUS, 0);
743
744 rt2x00usb_vendor_request(
745 rt2x00dev, USB_LED_CONTROL, USB_VENDOR_REQUEST_OUT,
746 0x00, rt2x00dev->led_reg, NULL, 0, REGISTER_TIMEOUT);
747 }
748
749 static void rt73usb_activity_led(struct rt2x00_dev *rt2x00dev, int rssi)
750 {
751 u32 led;
752
753 if (rt2x00dev->led_mode != LED_MODE_SIGNAL_STRENGTH)
754 return;
755
756 /*
757 * Led handling requires a positive value for the rssi,
758 * to do that correctly we need to add the correction.
759 */
760 rssi += rt2x00dev->rssi_offset;
761
762 if (rssi <= 30)
763 led = 0;
764 else if (rssi <= 39)
765 led = 1;
766 else if (rssi <= 49)
767 led = 2;
768 else if (rssi <= 53)
769 led = 3;
770 else if (rssi <= 63)
771 led = 4;
772 else
773 led = 5;
774
775 rt2x00usb_vendor_request(
776 rt2x00dev, USB_LED_CONTROL, USB_VENDOR_REQUEST_OUT,
777 led, rt2x00dev->led_reg, NULL, 0, REGISTER_TIMEOUT);
778 }
779
780 /*
781 * Link tuning
782 */
783 static void rt73usb_link_tuner(struct rt2x00_dev *rt2x00dev)
784 {
785 int rssi = rt2x00_get_link_rssi(&rt2x00dev->link);
786 u32 reg;
787 u8 r17;
788 u8 up_bound;
789 u8 low_bound;
790
791 /*
792 * Update Led strength
793 */
794 rt73usb_activity_led(rt2x00dev, rssi);
795
796 rt73usb_bbp_read(rt2x00dev, 17, &r17);
797
798 /*
799 * Determine r17 bounds.
800 */
801 if (rt2x00dev->rx_status.phymode == MODE_IEEE80211A) {
802 low_bound = 0x28;
803 up_bound = 0x48;
804
805 if (test_bit(CONFIG_EXTERNAL_LNA, &rt2x00dev->flags)) {
806 low_bound += 0x10;
807 up_bound += 0x10;
808 }
809 } else {
810 if (rssi > -82) {
811 low_bound = 0x1c;
812 up_bound = 0x40;
813 } else if (rssi > -84) {
814 low_bound = 0x1c;
815 up_bound = 0x20;
816 } else {
817 low_bound = 0x1c;
818 up_bound = 0x1c;
819 }
820
821 if (test_bit(CONFIG_EXTERNAL_LNA, &rt2x00dev->flags)) {
822 low_bound += 0x14;
823 up_bound += 0x10;
824 }
825 }
826
827 /*
828 * Special big-R17 for very short distance
829 */
830 if (rssi > -35) {
831 if (r17 != 0x60)
832 rt73usb_bbp_write(rt2x00dev, 17, 0x60);
833 return;
834 }
835
836 /*
837 * Special big-R17 for short distance
838 */
839 if (rssi >= -58) {
840 if (r17 != up_bound)
841 rt73usb_bbp_write(rt2x00dev, 17, up_bound);
842 return;
843 }
844
845 /*
846 * Special big-R17 for middle-short distance
847 */
848 if (rssi >= -66) {
849 low_bound += 0x10;
850 if (r17 != low_bound)
851 rt73usb_bbp_write(rt2x00dev, 17, low_bound);
852 return;
853 }
854
855 /*
856 * Special mid-R17 for middle distance
857 */
858 if (rssi >= -74) {
859 if (r17 != (low_bound + 0x10))
860 rt73usb_bbp_write(rt2x00dev, 17, low_bound + 0x08);
861 return;
862 }
863
864 /*
865 * Special case: Change up_bound based on the rssi.
866 * Lower up_bound when rssi is weaker then -74 dBm.
867 */
868 up_bound -= 2 * (-74 - rssi);
869 if (low_bound > up_bound)
870 up_bound = low_bound;
871
872 if (r17 > up_bound) {
873 rt73usb_bbp_write(rt2x00dev, 17, up_bound);
874 return;
875 }
876
877 /*
878 * r17 does not yet exceed upper limit, continue and base
879 * the r17 tuning on the false CCA count.
880 */
881 rt73usb_register_read(rt2x00dev, STA_CSR1, &reg);
882 reg = rt2x00_get_field32(reg, STA_CSR1_FALSE_CCA_ERROR);
883 rt2x00dev->link.false_cca =
884 rt2x00_get_field32(reg, STA_CSR1_FALSE_CCA_ERROR);
885
886 if (rt2x00dev->link.false_cca > 512 && r17 < up_bound) {
887 r17 += 4;
888 if (r17 > up_bound)
889 r17 = up_bound;
890 rt73usb_bbp_write(rt2x00dev, 17, r17);
891 rt2x00dev->rx_status.noise = r17;
892 } else if (rt2x00dev->link.false_cca < 100 && r17 > low_bound) {
893 r17 -= 4;
894 if (r17 < low_bound)
895 r17 = low_bound;
896 rt73usb_bbp_write(rt2x00dev, 17, r17);
897 rt2x00dev->rx_status.noise = r17;
898 }
899 }
900
901 /*
902 * Firmware name function.
903 */
904 static char *rt73usb_get_fw_name(struct rt2x00_dev *rt2x00dev)
905 {
906 return FIRMWARE_RT2571;
907 }
908
909 /*
910 * Initialization functions.
911 */
912 static int rt73usb_load_firmware(struct rt2x00_dev *rt2x00dev, void *data,
913 const size_t len)
914 {
915 unsigned int i;
916 int status;
917 u32 reg;
918 char buf[64];
919 char *ptr = data;
920 int buflen;
921
922 /*
923 * Wait for stable hardware.
924 */
925 for (i = 0; i < 100; i++) {
926 rt73usb_register_read(rt2x00dev, MAC_CSR0, &reg);
927 if (reg)
928 break;
929 msleep(1);
930 }
931
932 if (!reg) {
933 ERROR(rt2x00dev, "Unstable hardware.\n");
934 return -EBUSY;
935 }
936
937 /*
938 * Write firmware to device.
939 */
940 for (i = 0; i < len; i += sizeof(buf)) {
941 buflen = min(len - i, sizeof(buf));
942 memcpy(buf, ptr, buflen);
943 rt73usb_register_multiwrite(rt2x00dev, FIRMWARE_IMAGE_BASE + i,
944 buf, buflen);
945 ptr += buflen;
946 }
947
948 /*
949 * Send firmware request to device to load firmware,
950 * we need to specify a long timeout time.
951 */
952 status = rt2x00usb_vendor_request(rt2x00dev, USB_DEVICE_MODE,
953 USB_VENDOR_REQUEST_OUT, 0x00, USB_MODE_FIRMWARE,
954 NULL, 0, REGISTER_TIMEOUT_FIRMWARE);
955 if (status < 0) {
956 ERROR(rt2x00dev, "Failed to write Firmware to device.\n");
957 return status;
958 }
959
960 rt73usb_disable_led(rt2x00dev);
961
962 return 0;
963 }
964
965 static int rt73usb_init_registers(struct rt2x00_dev *rt2x00dev)
966 {
967 u32 reg;
968
969 if (rt2x00dev->ops->lib->set_device_state(rt2x00dev, STATE_AWAKE))
970 return -EBUSY;
971
972 rt73usb_register_write(rt2x00dev, MAC_CSR10, 0x00000718);
973
974 rt73usb_register_read(rt2x00dev, TXRX_CSR0, &reg);
975 rt2x00_set_field32(&reg, TXRX_CSR0_AUTO_TX_SEQ, 1);
976 rt2x00_set_field32(&reg, TXRX_CSR0_DISABLE_RX, 1);
977 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_ACK_CTS, 1);
978 rt2x00_set_field32(&reg, TXRX_CSR0_TX_WITHOUT_WAITING, 0);
979 rt73usb_register_write(rt2x00dev, TXRX_CSR0, reg);
980
981 rt73usb_register_write(rt2x00dev, TXRX_CSR1, 0x9eaa9eaf);
982 rt73usb_register_write(rt2x00dev, TXRX_CSR2, 0x8a8b8c8d);
983 rt73usb_register_write(rt2x00dev, TXRX_CSR3, 0x00858687);
984
985 rt73usb_register_write(rt2x00dev, TXRX_CSR7, 0x2e31353b);
986 rt73usb_register_write(rt2x00dev, TXRX_CSR8, 0x2a2a2a2c);
987
988 rt73usb_register_write(rt2x00dev, TXRX_CSR15, 0x0000000f);
989
990 rt73usb_register_write(rt2x00dev, MAC_CSR6, 0x00000fff);
991
992 rt73usb_register_write(rt2x00dev, MAC_CSR13, 0x00007f00);
993
994 rt73usb_register_write(rt2x00dev, SEC_CSR0, 0x00000000);
995 rt73usb_register_write(rt2x00dev, SEC_CSR1, 0x00000000);
996 rt73usb_register_write(rt2x00dev, SEC_CSR5, 0x00000000);
997
998 reg = 0x000023b0;
999 if (rt2x00_rf(&rt2x00dev->chip, RF5225) ||
1000 rt2x00_rf(&rt2x00dev->chip, RF2527))
1001 rt2x00_set_field32(&reg, PHY_CSR1_RF_RPI, 1);
1002 rt73usb_register_write(rt2x00dev, PHY_CSR1, reg);
1003
1004 rt73usb_register_write(rt2x00dev, PHY_CSR5, 0x00040a06);
1005 rt73usb_register_write(rt2x00dev, PHY_CSR6, 0x00080606);
1006 rt73usb_register_write(rt2x00dev, PHY_CSR7, 0x00000408);
1007
1008 rt73usb_register_read(rt2x00dev, AC_TXOP_CSR0, &reg);
1009 rt2x00_set_field32(&reg, AC_TXOP_CSR0_AC0_TX_OP, 0);
1010 rt2x00_set_field32(&reg, AC_TXOP_CSR0_AC1_TX_OP, 0);
1011 rt73usb_register_write(rt2x00dev, AC_TXOP_CSR0, reg);
1012
1013 rt73usb_register_read(rt2x00dev, AC_TXOP_CSR1, &reg);
1014 rt2x00_set_field32(&reg, AC_TXOP_CSR1_AC2_TX_OP, 192);
1015 rt2x00_set_field32(&reg, AC_TXOP_CSR1_AC3_TX_OP, 48);
1016 rt73usb_register_write(rt2x00dev, AC_TXOP_CSR1, reg);
1017
1018 rt73usb_register_read(rt2x00dev, MAC_CSR9, &reg);
1019 rt2x00_set_field32(&reg, MAC_CSR9_CW_SELECT, 0);
1020 rt73usb_register_write(rt2x00dev, MAC_CSR9, reg);
1021
1022 /*
1023 * We must clear the error counters.
1024 * These registers are cleared on read,
1025 * so we may pass a useless variable to store the value.
1026 */
1027 rt73usb_register_read(rt2x00dev, STA_CSR0, &reg);
1028 rt73usb_register_read(rt2x00dev, STA_CSR1, &reg);
1029 rt73usb_register_read(rt2x00dev, STA_CSR2, &reg);
1030
1031 /*
1032 * Reset MAC and BBP registers.
1033 */
1034 reg = 0;
1035 rt2x00_set_field32(&reg, MAC_CSR1_SOFT_RESET, 1);
1036 rt2x00_set_field32(&reg, MAC_CSR1_BBP_RESET, 1);
1037 rt73usb_register_write(rt2x00dev, MAC_CSR1, reg);
1038
1039 rt73usb_register_read(rt2x00dev, MAC_CSR1, &reg);
1040 rt2x00_set_field32(&reg, MAC_CSR1_SOFT_RESET, 0);
1041 rt2x00_set_field32(&reg, MAC_CSR1_BBP_RESET, 0);
1042 rt73usb_register_write(rt2x00dev, MAC_CSR1, reg);
1043
1044 rt73usb_register_read(rt2x00dev, MAC_CSR1, &reg);
1045 rt2x00_set_field32(&reg, MAC_CSR1_HOST_READY, 1);
1046 rt73usb_register_write(rt2x00dev, MAC_CSR1, reg);
1047
1048 return 0;
1049 }
1050
1051 static int rt73usb_init_bbp(struct rt2x00_dev *rt2x00dev)
1052 {
1053 unsigned int i;
1054 u16 eeprom;
1055 u8 reg_id;
1056 u8 value;
1057
1058 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1059 rt73usb_bbp_read(rt2x00dev, 0, &value);
1060 if ((value != 0xff) && (value != 0x00))
1061 goto continue_csr_init;
1062 NOTICE(rt2x00dev, "Waiting for BBP register.\n");
1063 udelay(REGISTER_BUSY_DELAY);
1064 }
1065
1066 ERROR(rt2x00dev, "BBP register access failed, aborting.\n");
1067 return -EACCES;
1068
1069 continue_csr_init:
1070 rt73usb_bbp_write(rt2x00dev, 3, 0x80);
1071 rt73usb_bbp_write(rt2x00dev, 15, 0x30);
1072 rt73usb_bbp_write(rt2x00dev, 17, 0x20);
1073 rt73usb_bbp_write(rt2x00dev, 21, 0xc8);
1074 rt73usb_bbp_write(rt2x00dev, 22, 0x38);
1075 rt73usb_bbp_write(rt2x00dev, 23, 0x06);
1076 rt73usb_bbp_write(rt2x00dev, 24, 0xfe);
1077 rt73usb_bbp_write(rt2x00dev, 25, 0x0a);
1078 rt73usb_bbp_write(rt2x00dev, 26, 0x0d);
1079 rt73usb_bbp_write(rt2x00dev, 32, 0x0b);
1080 rt73usb_bbp_write(rt2x00dev, 34, 0x12);
1081 rt73usb_bbp_write(rt2x00dev, 37, 0x07);
1082 rt73usb_bbp_write(rt2x00dev, 39, 0xf8);
1083 rt73usb_bbp_write(rt2x00dev, 41, 0x60);
1084 rt73usb_bbp_write(rt2x00dev, 53, 0x10);
1085 rt73usb_bbp_write(rt2x00dev, 54, 0x18);
1086 rt73usb_bbp_write(rt2x00dev, 60, 0x10);
1087 rt73usb_bbp_write(rt2x00dev, 61, 0x04);
1088 rt73usb_bbp_write(rt2x00dev, 62, 0x04);
1089 rt73usb_bbp_write(rt2x00dev, 75, 0xfe);
1090 rt73usb_bbp_write(rt2x00dev, 86, 0xfe);
1091 rt73usb_bbp_write(rt2x00dev, 88, 0xfe);
1092 rt73usb_bbp_write(rt2x00dev, 90, 0x0f);
1093 rt73usb_bbp_write(rt2x00dev, 99, 0x00);
1094 rt73usb_bbp_write(rt2x00dev, 102, 0x16);
1095 rt73usb_bbp_write(rt2x00dev, 107, 0x04);
1096
1097 DEBUG(rt2x00dev, "Start initialization from EEPROM...\n");
1098 for (i = 0; i < EEPROM_BBP_SIZE; i++) {
1099 rt2x00_eeprom_read(rt2x00dev, EEPROM_BBP_START + i, &eeprom);
1100
1101 if (eeprom != 0xffff && eeprom != 0x0000) {
1102 reg_id = rt2x00_get_field16(eeprom, EEPROM_BBP_REG_ID);
1103 value = rt2x00_get_field16(eeprom, EEPROM_BBP_VALUE);
1104 DEBUG(rt2x00dev, "BBP: 0x%02x, value: 0x%02x.\n",
1105 reg_id, value);
1106 rt73usb_bbp_write(rt2x00dev, reg_id, value);
1107 }
1108 }
1109 DEBUG(rt2x00dev, "...End initialization from EEPROM.\n");
1110
1111 return 0;
1112 }
1113
1114 /*
1115 * Device state switch handlers.
1116 */
1117 static void rt73usb_toggle_rx(struct rt2x00_dev *rt2x00dev,
1118 enum dev_state state)
1119 {
1120 u32 reg;
1121
1122 rt73usb_register_read(rt2x00dev, TXRX_CSR0, &reg);
1123 rt2x00_set_field32(&reg, TXRX_CSR0_DISABLE_RX,
1124 state == STATE_RADIO_RX_OFF);
1125 rt73usb_register_write(rt2x00dev, TXRX_CSR0, reg);
1126 }
1127
1128 static int rt73usb_enable_radio(struct rt2x00_dev *rt2x00dev)
1129 {
1130 /*
1131 * Initialize all registers.
1132 */
1133 if (rt73usb_init_registers(rt2x00dev) ||
1134 rt73usb_init_bbp(rt2x00dev)) {
1135 ERROR(rt2x00dev, "Register initialization failed.\n");
1136 return -EIO;
1137 }
1138
1139 rt2x00usb_enable_radio(rt2x00dev);
1140
1141 /*
1142 * Enable LED
1143 */
1144 rt73usb_enable_led(rt2x00dev);
1145
1146 return 0;
1147 }
1148
1149 static void rt73usb_disable_radio(struct rt2x00_dev *rt2x00dev)
1150 {
1151 /*
1152 * Disable LED
1153 */
1154 rt73usb_disable_led(rt2x00dev);
1155
1156 rt73usb_register_write(rt2x00dev, MAC_CSR10, 0x00001818);
1157
1158 /*
1159 * Disable synchronisation.
1160 */
1161 rt73usb_register_write(rt2x00dev, TXRX_CSR9, 0);
1162
1163 rt2x00usb_disable_radio(rt2x00dev);
1164 }
1165
1166 static int rt73usb_set_state(struct rt2x00_dev *rt2x00dev,
1167 enum dev_state state)
1168 {
1169 u32 reg;
1170 unsigned int i;
1171 char put_to_sleep;
1172 char current_state;
1173
1174 put_to_sleep = (state != STATE_AWAKE);
1175
1176 if (!put_to_sleep)
1177 rt2x00usb_vendor_request(rt2x00dev,
1178 USB_DEVICE_MODE, USB_VENDOR_REQUEST_OUT,
1179 0x00, USB_MODE_WAKEUP, NULL, 0, REGISTER_TIMEOUT);
1180
1181 rt73usb_register_read(rt2x00dev, MAC_CSR12, &reg);
1182 rt2x00_set_field32(&reg, MAC_CSR12_FORCE_WAKEUP, !put_to_sleep);
1183 rt2x00_set_field32(&reg, MAC_CSR12_PUT_TO_SLEEP, put_to_sleep);
1184 rt73usb_register_write(rt2x00dev, MAC_CSR12, reg);
1185
1186 if (put_to_sleep)
1187 rt2x00usb_vendor_request(rt2x00dev,
1188 USB_DEVICE_MODE, USB_VENDOR_REQUEST_OUT,
1189 0x00, USB_MODE_SLEEP, NULL, 0, REGISTER_TIMEOUT);
1190
1191 /*
1192 * Device is not guaranteed to be in the requested state yet.
1193 * We must wait until the register indicates that the
1194 * device has entered the correct state.
1195 */
1196 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1197 rt73usb_register_read(rt2x00dev, MAC_CSR12, &reg);
1198 current_state = rt2x00_get_field32(reg,
1199 MAC_CSR12_BBP_CURRENT_STATE);
1200 if (current_state == !put_to_sleep)
1201 return 0;
1202 msleep(10);
1203 }
1204
1205 NOTICE(rt2x00dev, "Device failed to enter state %d, "
1206 "current device state %d.\n", !put_to_sleep, current_state);
1207
1208 return -EBUSY;
1209 }
1210
1211 static int rt73usb_set_device_state(struct rt2x00_dev *rt2x00dev,
1212 enum dev_state state)
1213 {
1214 int retval = 0;
1215
1216 switch (state) {
1217 case STATE_RADIO_ON:
1218 retval = rt73usb_enable_radio(rt2x00dev);
1219 break;
1220 case STATE_RADIO_OFF:
1221 rt73usb_disable_radio(rt2x00dev);
1222 break;
1223 case STATE_RADIO_RX_ON:
1224 case STATE_RADIO_RX_OFF:
1225 rt73usb_toggle_rx(rt2x00dev, state);
1226 break;
1227 case STATE_DEEP_SLEEP:
1228 case STATE_SLEEP:
1229 case STATE_STANDBY:
1230 case STATE_AWAKE:
1231 retval = rt73usb_set_state(rt2x00dev, state);
1232 break;
1233 default:
1234 retval = -ENOTSUPP;
1235 break;
1236 }
1237
1238 return retval;
1239 }
1240
1241 /*
1242 * TX descriptor initialization
1243 */
1244 static void rt73usb_write_tx_desc(struct rt2x00_dev *rt2x00dev,
1245 struct data_entry *entry, struct data_desc *txd,
1246 struct data_entry_desc *desc, struct ieee80211_hdr *ieee80211hdr,
1247 unsigned int length, struct ieee80211_tx_control *control)
1248 {
1249 u32 word;
1250
1251 /*
1252 * Start writing the descriptor words.
1253 */
1254 rt2x00_desc_read(txd, 1, &word);
1255 rt2x00_set_field32(&word, TXD_W1_HOST_Q_ID, desc->queue);
1256 rt2x00_set_field32(&word, TXD_W1_AIFSN, entry->ring->tx_params.aifs);
1257 rt2x00_set_field32(&word, TXD_W1_CWMIN, entry->ring->tx_params.cw_min);
1258 rt2x00_set_field32(&word, TXD_W1_CWMAX, entry->ring->tx_params.cw_max);
1259 rt2x00_set_field32(&word, TXD_W1_IV_OFFSET, IEEE80211_HEADER);
1260 rt2x00_set_field32(&word, TXD_W1_HW_SEQUENCE, 1);
1261 rt2x00_desc_write(txd, 1, word);
1262
1263 rt2x00_desc_read(txd, 2, &word);
1264 rt2x00_set_field32(&word, TXD_W2_PLCP_SIGNAL, desc->signal);
1265 rt2x00_set_field32(&word, TXD_W2_PLCP_SERVICE, desc->service);
1266 rt2x00_set_field32(&word, TXD_W2_PLCP_LENGTH_LOW, desc->length_low);
1267 rt2x00_set_field32(&word, TXD_W2_PLCP_LENGTH_HIGH, desc->length_high);
1268 rt2x00_desc_write(txd, 2, word);
1269
1270 rt2x00_desc_read(txd, 5, &word);
1271 rt2x00_set_field32(&word, TXD_W5_TX_POWER,
1272 TXPOWER_TO_DEV(control->power_level));
1273 rt2x00_set_field32(&word, TXD_W5_WAITING_DMA_DONE_INT, 1);
1274 rt2x00_desc_write(txd, 5, word);
1275
1276 rt2x00_desc_read(txd, 0, &word);
1277 rt2x00_set_field32(&word, TXD_W0_VALID, 1);
1278 rt2x00_set_field32(&word, TXD_W0_MORE_FRAG,
1279 test_bit(ENTRY_TXD_MORE_FRAG, &entry->flags));
1280 rt2x00_set_field32(&word, TXD_W0_ACK,
1281 test_bit(ENTRY_TXD_REQ_ACK, &entry->flags));
1282 rt2x00_set_field32(&word, TXD_W0_TIMESTAMP,
1283 test_bit(ENTRY_TXD_REQ_TIMESTAMP, &entry->flags));
1284 rt2x00_set_field32(&word, TXD_W0_OFDM,
1285 test_bit(ENTRY_TXD_OFDM_RATE, &entry->flags));
1286 rt2x00_set_field32(&word, TXD_W0_IFS, desc->ifs);
1287 rt2x00_set_field32(&word, TXD_W0_RETRY_MODE, 0);
1288 rt2x00_set_field32(&word, TXD_W0_TKIP_MIC, 0);
1289 rt2x00_set_field32(&word, TXD_W0_DATABYTE_COUNT, length);
1290 rt2x00_set_field32(&word, TXD_W0_CIPHER_ALG, CIPHER_NONE);
1291 rt2x00_desc_write(txd, 0, word);
1292 }
1293
1294 /*
1295 * TX data initialization
1296 */
1297 static void rt73usb_kick_tx_queue(struct rt2x00_dev *rt2x00dev, int queue)
1298 {
1299 u32 reg;
1300
1301 if (queue != IEEE80211_TX_QUEUE_BEACON)
1302 return;
1303
1304 rt73usb_register_read(rt2x00dev, TXRX_CSR9, &reg);
1305 if (!rt2x00_get_field32(reg, TXRX_CSR9_BEACON_GEN)) {
1306 rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_GEN, 1);
1307 rt73usb_register_write(rt2x00dev, TXRX_CSR9, reg);
1308 }
1309 }
1310
1311 /*
1312 * RX control handlers
1313 */
1314 static int rt73usb_agc_to_rssi(struct rt2x00_dev *rt2x00dev, int rxd_w1)
1315 {
1316 u16 eeprom;
1317 char offset;
1318 char lna;
1319
1320 lna = rt2x00_get_field32(rxd_w1, RXD_W1_RSSI_LNA);
1321 switch (lna) {
1322 case 3:
1323 offset = 90;
1324 break;
1325 case 2:
1326 offset = 74;
1327 break;
1328 case 1:
1329 offset = 64;
1330 break;
1331 default:
1332 return 0;
1333 }
1334
1335 if (rt2x00dev->rx_status.phymode == MODE_IEEE80211A) {
1336 if (test_bit(CONFIG_EXTERNAL_LNA, &rt2x00dev->flags)) {
1337 if (lna == 3 || lna == 2)
1338 offset += 10;
1339 } else {
1340 if (lna == 3)
1341 offset += 6;
1342 else if (lna == 2)
1343 offset += 8;
1344 }
1345
1346 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_A, &eeprom);
1347 offset -= rt2x00_get_field16(eeprom, EEPROM_RSSI_OFFSET_A_1);
1348 } else {
1349 if (test_bit(CONFIG_EXTERNAL_LNA, &rt2x00dev->flags))
1350 offset += 14;
1351
1352 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_BG, &eeprom);
1353 offset -= rt2x00_get_field16(eeprom, EEPROM_RSSI_OFFSET_BG_1);
1354 }
1355
1356 return rt2x00_get_field32(rxd_w1, RXD_W1_RSSI_AGC) * 2 - offset;
1357 }
1358
1359 static int rt73usb_fill_rxdone(struct data_entry *entry,
1360 int *signal, int *rssi, int *ofdm)
1361 {
1362 struct data_desc *rxd = (struct data_desc*)entry->skb->data;
1363 u32 word0;
1364 u32 word1;
1365
1366 rt2x00_desc_read(rxd, 0, &word0);
1367 rt2x00_desc_read(rxd, 1, &word1);
1368
1369 /*
1370 * TODO: Don't we need to keep statistics
1371 * updated about these errors?
1372 */
1373 if (rt2x00_get_field32(word0, RXD_W0_CRC) ||
1374 rt2x00_get_field32(word0, RXD_W0_CIPHER_ERROR))
1375 return -EINVAL;
1376
1377 /*
1378 * Obtain the status about this packet.
1379 */
1380 *signal = rt2x00_get_field32(word1, RXD_W1_SIGNAL);
1381 *rssi = rt73usb_agc_to_rssi(entry->ring->rt2x00dev, word1);
1382 *ofdm = rt2x00_get_field32(word0, RXD_W0_OFDM);
1383
1384 /*
1385 * Pull the skb to clear the descriptor area.
1386 */
1387 skb_pull(entry->skb, entry->ring->desc_size);
1388
1389 return rt2x00_get_field32(word0, RXD_W0_DATABYTE_COUNT);
1390 }
1391
1392 /*
1393 * Device initialization functions.
1394 */
1395 static int rt73usb_alloc_eeprom(struct rt2x00_dev *rt2x00dev)
1396 {
1397 u16 word;
1398 u8 *mac;
1399 char value;
1400
1401 /*
1402 * Allocate the eeprom memory, check the eeprom width
1403 * and copy the entire eeprom into this allocated memory.
1404 */
1405 rt2x00dev->eeprom = kzalloc(EEPROM_SIZE, GFP_KERNEL);
1406 if (!rt2x00dev->eeprom)
1407 return -ENOMEM;
1408
1409 rt2x00usb_vendor_request(
1410 rt2x00dev, USB_EEPROM_READ, USB_VENDOR_REQUEST_IN,
1411 EEPROM_BASE, 0x00, rt2x00dev->eeprom, EEPROM_SIZE,
1412 REGISTER_TIMEOUT * (EEPROM_SIZE / sizeof(u16)));
1413
1414 /*
1415 * Start validation of the data that has been read.
1416 */
1417 mac = rt2x00_eeprom_addr(rt2x00dev, EEPROM_MAC_ADDR_0);
1418 if (!is_valid_ether_addr(mac)) {
1419 random_ether_addr(mac);
1420 EEPROM(rt2x00dev, "MAC: " MAC_FMT "\n", MAC_ARG(mac));
1421 }
1422
1423 rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &word);
1424 if (word == 0xffff) {
1425 rt2x00_set_field16(&word, EEPROM_ANTENNA_NUM, 2);
1426 rt2x00_set_field16(&word, EEPROM_ANTENNA_TX_DEFAULT, 2);
1427 rt2x00_set_field16(&word, EEPROM_ANTENNA_RX_DEFAULT, 2);
1428 rt2x00_set_field16(&word, EEPROM_ANTENNA_FRAME_TYPE, 0);
1429 rt2x00_set_field16(&word, EEPROM_ANTENNA_DYN_TXAGC, 0);
1430 rt2x00_set_field16(&word, EEPROM_ANTENNA_HARDWARE_RADIO, 0);
1431 rt2x00_set_field16(&word, EEPROM_ANTENNA_RF_TYPE, RF5226);
1432 rt2x00_eeprom_write(rt2x00dev, EEPROM_ANTENNA, word);
1433 EEPROM(rt2x00dev, "Antenna: 0x%04x\n", word);
1434 }
1435
1436 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &word);
1437 if (word == 0xffff) {
1438 rt2x00_set_field16(&word, EEPROM_NIC_EXTERNAL_LNA, 0);
1439 rt2x00_eeprom_write(rt2x00dev, EEPROM_NIC, word);
1440 EEPROM(rt2x00dev, "NIC: 0x%04x\n", word);
1441 }
1442
1443 rt2x00_eeprom_read(rt2x00dev, EEPROM_LED, &word);
1444 if (word == 0xffff) {
1445 rt2x00_set_field16(&word, EEPROM_LED_POLARITY_RDY_G, 0);
1446 rt2x00_set_field16(&word, EEPROM_LED_POLARITY_RDY_A, 0);
1447 rt2x00_set_field16(&word, EEPROM_LED_POLARITY_ACT, 0);
1448 rt2x00_set_field16(&word, EEPROM_LED_POLARITY_GPIO_0, 0);
1449 rt2x00_set_field16(&word, EEPROM_LED_POLARITY_GPIO_1, 0);
1450 rt2x00_set_field16(&word, EEPROM_LED_POLARITY_GPIO_2, 0);
1451 rt2x00_set_field16(&word, EEPROM_LED_POLARITY_GPIO_3, 0);
1452 rt2x00_set_field16(&word, EEPROM_LED_POLARITY_GPIO_4, 0);
1453 rt2x00_set_field16(&word, EEPROM_LED_LED_MODE,
1454 LED_MODE_DEFAULT);
1455 rt2x00_eeprom_write(rt2x00dev, EEPROM_LED, word);
1456 EEPROM(rt2x00dev, "Led: 0x%04x\n", word);
1457 }
1458
1459 rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &word);
1460 if (word == 0xffff) {
1461 rt2x00_set_field16(&word, EEPROM_FREQ_OFFSET, 0);
1462 rt2x00_set_field16(&word, EEPROM_FREQ_SEQ, 0);
1463 rt2x00_eeprom_write(rt2x00dev, EEPROM_FREQ, word);
1464 EEPROM(rt2x00dev, "Freq: 0x%04x\n", word);
1465 }
1466
1467 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_BG, &word);
1468 if (word == 0xffff) {
1469 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_1, 0);
1470 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_2, 0);
1471 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_BG, word);
1472 EEPROM(rt2x00dev, "RSSI OFFSET BG: 0x%04x\n", word);
1473 } else {
1474 value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_BG_1);
1475 if (value < -10 || value > 10)
1476 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_1, 0);
1477 value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_BG_2);
1478 if (value < -10 || value > 10)
1479 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_2, 0);
1480 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_BG, word);
1481 }
1482
1483 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_A, &word);
1484 if (word == 0xffff) {
1485 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_1, 0);
1486 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_2, 0);
1487 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_A, word);
1488 EEPROM(rt2x00dev, "RSSI OFFSET BG: 0x%04x\n", word);
1489 } else {
1490 value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_A_1);
1491 if (value < -10 || value > 10)
1492 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_1, 0);
1493 value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_A_2);
1494 if (value < -10 || value > 10)
1495 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_2, 0);
1496 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_A, word);
1497 }
1498
1499 return 0;
1500 }
1501
1502 static int rt73usb_init_eeprom(struct rt2x00_dev *rt2x00dev)
1503 {
1504 u32 reg;
1505 u16 value;
1506 u16 eeprom;
1507
1508 /*
1509 * Read EEPROM word for configuration.
1510 */
1511 rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
1512
1513 /*
1514 * Identify RF chipset.
1515 */
1516 value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RF_TYPE);
1517 rt73usb_register_read(rt2x00dev, MAC_CSR0, &reg);
1518 rt2x00_set_chip(rt2x00dev, RT2571, value, reg);
1519
1520 if (!rt2x00_rf(&rt2x00dev->chip, RF5226) &&
1521 !rt2x00_rf(&rt2x00dev->chip, RF2528) &&
1522 !rt2x00_rf(&rt2x00dev->chip, RF5225) &&
1523 !rt2x00_rf(&rt2x00dev->chip, RF2527)) {
1524 ERROR(rt2x00dev, "Invalid RF chipset detected.\n");
1525 return -ENODEV;
1526 }
1527
1528 /*
1529 * Identify default antenna configuration.
1530 */
1531 rt2x00dev->hw->conf.antenna_sel_tx = rt2x00_get_field16(eeprom,
1532 EEPROM_ANTENNA_TX_DEFAULT);
1533 rt2x00dev->hw->conf.antenna_sel_rx = rt2x00_get_field16(eeprom,
1534 EEPROM_ANTENNA_RX_DEFAULT);
1535
1536 /*
1537 * Read the Frame type.
1538 */
1539 if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_FRAME_TYPE))
1540 __set_bit(CONFIG_FRAME_TYPE, &rt2x00dev->flags);
1541
1542 /*
1543 * Read frequency offset.
1544 */
1545 rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &eeprom);
1546 rt2x00dev->freq_offset =
1547 rt2x00_get_field16(eeprom, EEPROM_FREQ_OFFSET);
1548
1549 /*
1550 * Read external LNA informations.
1551 */
1552 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &eeprom);
1553
1554 if (rt2x00_get_field16(eeprom, EEPROM_NIC_EXTERNAL_LNA))
1555 __set_bit(CONFIG_EXTERNAL_LNA, &rt2x00dev->flags);
1556
1557 /*
1558 * Store led settings, for correct led behaviour.
1559 */
1560 rt2x00_eeprom_read(rt2x00dev, EEPROM_LED, &eeprom);
1561
1562 rt2x00_set_field16(&rt2x00dev->led_reg, MCU_LEDCS_LED_MODE,
1563 rt2x00dev->led_mode);
1564 rt2x00_set_field16(&rt2x00dev->led_reg, MCU_LEDCS_POLARITY_GPIO_0,
1565 rt2x00_get_field16(eeprom, EEPROM_LED_POLARITY_GPIO_0));
1566 rt2x00_set_field16(&rt2x00dev->led_reg, MCU_LEDCS_POLARITY_GPIO_1,
1567 rt2x00_get_field16(eeprom, EEPROM_LED_POLARITY_GPIO_1));
1568 rt2x00_set_field16(&rt2x00dev->led_reg, MCU_LEDCS_POLARITY_GPIO_2,
1569 rt2x00_get_field16(eeprom, EEPROM_LED_POLARITY_GPIO_2));
1570 rt2x00_set_field16(&rt2x00dev->led_reg, MCU_LEDCS_POLARITY_GPIO_3,
1571 rt2x00_get_field16(eeprom, EEPROM_LED_POLARITY_GPIO_3));
1572 rt2x00_set_field16(&rt2x00dev->led_reg, MCU_LEDCS_POLARITY_GPIO_4,
1573 rt2x00_get_field16(eeprom, EEPROM_LED_POLARITY_GPIO_4));
1574 rt2x00_set_field16(&rt2x00dev->led_reg, MCU_LEDCS_POLARITY_ACT,
1575 rt2x00_get_field16(eeprom, EEPROM_LED_POLARITY_ACT));
1576 rt2x00_set_field16(&rt2x00dev->led_reg, MCU_LEDCS_POLARITY_READY_BG,
1577 rt2x00_get_field16(eeprom, EEPROM_LED_POLARITY_RDY_G));
1578 rt2x00_set_field16(&rt2x00dev->led_reg, MCU_LEDCS_POLARITY_READY_A,
1579 rt2x00_get_field16(eeprom, EEPROM_LED_POLARITY_RDY_A));
1580
1581 return 0;
1582 }
1583
1584 static const struct {
1585 unsigned int chip;
1586 u32 val[3];
1587 } rf_vals[] = {
1588 { RF5226, { 0x00002c0c, 0x00068255 } },
1589 { RF2528, { 0x00002c0c, 0x00068255 } },
1590 { RF5225, { 0x00002ccc, 0x00000000 } },
1591 { RF2527, { 0x00002ccc, 0x00068455 } },
1592 };
1593
1594 /*
1595 * RF value list for RF5226, RF2528, RF5225 & RF2527
1596 * Supports: 2.4 GHz
1597 */
1598 static const u32 rf_vals_bg[] = {
1599 0x00000786, 0x00000786, 0x0000078a, 0x0000078a, 0x0000078e,
1600 0x0000078e, 0x00000792, 0x00000792, 0x00000796, 0x00000796,
1601 0x0000079a, 0x0000079a, 0x0000079e, 0x000007a2
1602 };
1603
1604 /*
1605 * RF value list for RF5226 & RF5225 (supplement to vals_bg)
1606 * Supports: 5.2 GHz
1607 */
1608 static const u32 rf_vals_a_5x[] = {
1609 0x0000099a, 0x000009a2, 0x000009a6, 0x000009aa, 0x000009ae,
1610 0x000009b2, 0x000009ba, 0x000009be, 0x00000a2a, 0x00000a2e,
1611 0x00000a32, 0x00000a36, 0x00000a3a, 0x00000a82, 0x00000a86,
1612 0x00000a8a, 0x00000a8e, 0x00000a92, 0x00000a9a, 0x00000aa2,
1613 0x00000aa6, 0x00000aae, 0x00000ab2, 0x00000ab6
1614 };
1615
1616 static void rt73usb_init_hw_mode(struct rt2x00_dev *rt2x00dev)
1617 {
1618 struct hw_mode_spec *spec = &rt2x00dev->spec;
1619 u8 *txpower;
1620 unsigned int i;
1621
1622 /*
1623 * Initialize all hw fields.
1624 */
1625 rt2x00dev->hw->flags = IEEE80211_HW_HOST_GEN_BEACON_TEMPLATE |
1626 IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING |
1627 IEEE80211_HW_WEP_INCLUDE_IV |
1628 IEEE80211_HW_DATA_NULLFUNC_ACK |
1629 IEEE80211_HW_NO_TKIP_WMM_HWACCEL |
1630 IEEE80211_HW_MONITOR_DURING_OPER |
1631 IEEE80211_HW_NO_PROBE_FILTERING;
1632 rt2x00dev->hw->extra_tx_headroom = TXD_DESC_SIZE;
1633 rt2x00dev->hw->max_rssi = MAX_RX_SSI;
1634 rt2x00dev->hw->max_noise = MAX_RX_NOISE;
1635 rt2x00dev->hw->queues = 5;
1636
1637 SET_IEEE80211_DEV(rt2x00dev->hw, &rt2x00dev_usb(rt2x00dev)->dev);
1638 SET_IEEE80211_PERM_ADDR(rt2x00dev->hw,
1639 rt2x00_eeprom_addr(rt2x00dev, EEPROM_MAC_ADDR_0));
1640
1641 /*
1642 * Set device specific, but channel independent RF values.
1643 */
1644 for (i = 0; i < ARRAY_SIZE(rf_vals); i++) {
1645 if (rt2x00_rf(&rt2x00dev->chip, rf_vals[i].chip)) {
1646 rt2x00dev->rf1 = rf_vals[i].val[0];
1647 rt2x00dev->rf3 = rf_vals[i].val[1];
1648 }
1649 }
1650
1651 /*
1652 * Convert tx_power array in eeprom.
1653 */
1654 txpower = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_G_START);
1655 for (i = 0; i < 14; i++)
1656 txpower[i] = TXPOWER_FROM_DEV(txpower[i]);
1657
1658 /*
1659 * Initialize hw_mode information.
1660 */
1661 spec->num_modes = 2;
1662 spec->num_rates = 12;
1663 spec->num_channels = 14;
1664 spec->tx_power_a = NULL;
1665 spec->tx_power_bg = txpower;
1666 spec->tx_power_default = DEFAULT_TXPOWER;
1667 spec->chan_val_a = NULL;
1668 spec->chan_val_bg = rf_vals_bg;
1669
1670 if (rt2x00_rf(&rt2x00dev->chip, RF5225) ||
1671 rt2x00_rf(&rt2x00dev->chip, RF5226)) {
1672 spec->num_modes = 3;
1673 spec->num_channels += 24;
1674
1675 txpower = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_A_START);
1676 for (i = 0; i < 14; i++)
1677 txpower[i] = TXPOWER_FROM_DEV(txpower[i]);
1678
1679 spec->tx_power_a = txpower;
1680 spec->chan_val_a = rf_vals_a_5x;
1681 }
1682 }
1683
1684 static int rt73usb_init_hw(struct rt2x00_dev *rt2x00dev)
1685 {
1686 int retval;
1687
1688 /*
1689 * Allocate eeprom data.
1690 */
1691 retval = rt73usb_alloc_eeprom(rt2x00dev);
1692 if (retval)
1693 return retval;
1694
1695 retval = rt73usb_init_eeprom(rt2x00dev);
1696 if (retval)
1697 return retval;
1698
1699 /*
1700 * Initialize hw specifications.
1701 */
1702 rt73usb_init_hw_mode(rt2x00dev);
1703
1704 /*
1705 * This device requires firmware
1706 */
1707 __set_bit(FIRMWARE_REQUIRED, &rt2x00dev->flags);
1708
1709 /*
1710 * Set the rssi offset.
1711 */
1712 rt2x00dev->rssi_offset = DEFAULT_RSSI_OFFSET;
1713
1714 return 0;
1715 }
1716
1717 /*
1718 * IEEE80211 stack callback functions.
1719 */
1720 static int rt73usb_get_stats(struct ieee80211_hw *hw,
1721 struct ieee80211_low_level_stats *stats)
1722 {
1723 struct rt2x00_dev *rt2x00dev = hw->priv;
1724 u32 reg;
1725
1726 /*
1727 * Update FCS error count from register.
1728 * The dot11ACKFailureCount, dot11RTSFailureCount and
1729 * dot11RTSSuccessCount are updated in interrupt time.
1730 */
1731 rt73usb_register_read(rt2x00dev, STA_CSR0, &reg);
1732 rt2x00dev->low_level_stats.dot11FCSErrorCount +=
1733 rt2x00_get_field32(reg, STA_CSR0_FCS_ERROR);
1734
1735 memcpy(stats, &rt2x00dev->low_level_stats, sizeof(*stats));
1736
1737 return 0;
1738 }
1739
1740 static int rt73usb_set_retry_limit(struct ieee80211_hw *hw,
1741 u32 short_retry, u32 long_retry)
1742 {
1743 struct rt2x00_dev *rt2x00dev = hw->priv;
1744 u32 reg;
1745
1746 rt73usb_register_read(rt2x00dev, TXRX_CSR4, &reg);
1747 rt2x00_set_field32(&reg, TXRX_CSR4_LONG_RETRY_LIMIT, long_retry);
1748 rt2x00_set_field32(&reg, TXRX_CSR4_SHORT_RETRY_LIMIT, short_retry);
1749 rt73usb_register_write(rt2x00dev, TXRX_CSR4, reg);
1750
1751 return 0;
1752 }
1753
1754 static u64 rt73usb_get_tsf(struct ieee80211_hw *hw)
1755 {
1756 struct rt2x00_dev *rt2x00dev = hw->priv;
1757 u64 tsf;
1758 u32 reg;
1759
1760 rt73usb_register_read(rt2x00dev, TXRX_CSR13, &reg);
1761 tsf = (u64)rt2x00_get_field32(reg, TXRX_CSR13_HIGH_TSFTIMER) << 32;
1762 rt73usb_register_read(rt2x00dev, TXRX_CSR12, &reg);
1763 tsf |= rt2x00_get_field32(reg, TXRX_CSR12_LOW_TSFTIMER);
1764
1765 return tsf;
1766 }
1767
1768 static void rt73usb_reset_tsf(struct ieee80211_hw *hw)
1769 {
1770 struct rt2x00_dev *rt2x00dev = hw->priv;
1771
1772 rt73usb_register_write(rt2x00dev, TXRX_CSR12, 0);
1773 rt73usb_register_write(rt2x00dev, TXRX_CSR13, 0);
1774 }
1775
1776 static const struct ieee80211_ops rt73usb_mac80211_ops = {
1777 .tx = rt2x00lib_tx,
1778 .reset = rt2x00lib_reset,
1779 .add_interface = rt2x00lib_add_interface,
1780 .remove_interface = rt2x00lib_remove_interface,
1781 .config = rt2x00lib_config,
1782 .config_interface = rt2x00lib_config_interface,
1783 .set_multicast_list = rt2x00lib_set_multicast_list,
1784 .get_stats = rt73usb_get_stats,
1785 .set_retry_limit = rt73usb_set_retry_limit,
1786 .conf_tx = rt2x00lib_conf_tx,
1787 .get_tx_stats = rt2x00lib_get_tx_stats,
1788 .get_tsf = rt73usb_get_tsf,
1789 .reset_tsf = rt73usb_reset_tsf,
1790 .beacon_update = rt2x00usb_beacon_update,
1791 };
1792
1793 static const struct rt2x00lib_ops rt73usb_rt2x00_ops = {
1794 .init_hw = rt73usb_init_hw,
1795 .get_fw_name = rt73usb_get_fw_name,
1796 .load_firmware = rt73usb_load_firmware,
1797 .initialize = rt2x00usb_initialize,
1798 .uninitialize = rt2x00usb_uninitialize,
1799 .set_device_state = rt73usb_set_device_state,
1800 .link_tuner = rt73usb_link_tuner,
1801 .write_tx_desc = rt73usb_write_tx_desc,
1802 .write_tx_data = rt2x00usb_write_tx_data,
1803 .kick_tx_queue = rt73usb_kick_tx_queue,
1804 .fill_rxdone = rt73usb_fill_rxdone,
1805 .config_type = rt73usb_config_type,
1806 .config_phymode = rt73usb_config_phymode,
1807 .config_channel = rt73usb_config_channel,
1808 .config_mac_addr = rt73usb_config_mac_addr,
1809 .config_bssid = rt73usb_config_bssid,
1810 .config_promisc = rt73usb_config_promisc,
1811 .config_txpower = rt73usb_config_txpower,
1812 .config_antenna = rt73usb_config_antenna,
1813 .config_duration = rt73usb_config_duration,
1814 };
1815
1816 static const struct rt2x00_ops rt73usb_ops = {
1817 .name = DRV_NAME,
1818 .rxd_size = RXD_DESC_SIZE,
1819 .txd_size = TXD_DESC_SIZE,
1820 .lib = &rt73usb_rt2x00_ops,
1821 .hw = &rt73usb_mac80211_ops,
1822 #ifdef CONFIG_RT2X00_LIB_DEBUGFS
1823 .debugfs = &rt73usb_rt2x00debug,
1824 #endif /* CONFIG_RT2X00_LIB_DEBUGFS */
1825 };
1826
1827 /*
1828 * rt73usb module information.
1829 */
1830 static struct usb_device_id rt73usb_device_table[] = {
1831 /* AboCom */
1832 { USB_DEVICE(0x07b8, 0xb21d), USB_DEVICE_DATA(&rt73usb_ops) },
1833 /* Askey */
1834 { USB_DEVICE(0x1690, 0x0722), USB_DEVICE_DATA(&rt73usb_ops) },
1835 /* ASUS */
1836 { USB_DEVICE(0x0b05, 0x1723), USB_DEVICE_DATA(&rt73usb_ops) },
1837 { USB_DEVICE(0x0b05, 0x1724), USB_DEVICE_DATA(&rt73usb_ops) },
1838 /* Belkin */
1839 { USB_DEVICE(0x050d, 0x7050), USB_DEVICE_DATA(&rt73usb_ops) },
1840 { USB_DEVICE(0x050d, 0x705a), USB_DEVICE_DATA(&rt73usb_ops) },
1841 { USB_DEVICE(0x050d, 0x905b), USB_DEVICE_DATA(&rt73usb_ops) },
1842 /* Billionton */
1843 { USB_DEVICE(0x1631, 0xc019), USB_DEVICE_DATA(&rt73usb_ops) },
1844 /* CNet */
1845 { USB_DEVICE(0x1371, 0x9022), USB_DEVICE_DATA(&rt73usb_ops) },
1846 { USB_DEVICE(0x1371, 0x9032), USB_DEVICE_DATA(&rt73usb_ops) },
1847 /* Conceptronic */
1848 { USB_DEVICE(0x14b2, 0x3c22), USB_DEVICE_DATA(&rt73usb_ops) },
1849 /* D-Link */
1850 { USB_DEVICE(0x07d1, 0x3c03), USB_DEVICE_DATA(&rt73usb_ops) },
1851 { USB_DEVICE(0x07d1, 0x3c04), USB_DEVICE_DATA(&rt73usb_ops) },
1852 /* Gemtek */
1853 { USB_DEVICE(0x15a9, 0x0004), USB_DEVICE_DATA(&rt73usb_ops) },
1854 /* Gigabyte */
1855 { USB_DEVICE(0x1044, 0x8008), USB_DEVICE_DATA(&rt73usb_ops) },
1856 { USB_DEVICE(0x1044, 0x800a), USB_DEVICE_DATA(&rt73usb_ops) },
1857 /* Huawei-3Com */
1858 { USB_DEVICE(0x1472, 0x0009), USB_DEVICE_DATA(&rt73usb_ops) },
1859 /* Hercules */
1860 { USB_DEVICE(0x06f8, 0xe010), USB_DEVICE_DATA(&rt73usb_ops) },
1861 { USB_DEVICE(0x06f8, 0xe020), USB_DEVICE_DATA(&rt73usb_ops) },
1862 /* Linksys */
1863 { USB_DEVICE(0x13b1, 0x0020), USB_DEVICE_DATA(&rt73usb_ops) },
1864 { USB_DEVICE(0x13b1, 0x0023), USB_DEVICE_DATA(&rt73usb_ops) },
1865 /* MSI */
1866 { USB_DEVICE(0x0db0, 0x6877), USB_DEVICE_DATA(&rt73usb_ops) },
1867 { USB_DEVICE(0x0db0, 0xa861), USB_DEVICE_DATA(&rt73usb_ops) },
1868 { USB_DEVICE(0x0db0, 0xa874), USB_DEVICE_DATA(&rt73usb_ops) },
1869 /* Ralink */
1870 { USB_DEVICE(0x148f, 0x2573), USB_DEVICE_DATA(&rt73usb_ops) },
1871 { USB_DEVICE(0x148f, 0x2671), USB_DEVICE_DATA(&rt73usb_ops) },
1872 /* Qcom */
1873 { USB_DEVICE(0x18e8, 0x6196), USB_DEVICE_DATA(&rt73usb_ops) },
1874 { USB_DEVICE(0x18e8, 0x6229), USB_DEVICE_DATA(&rt73usb_ops) },
1875 /* Sitecom */
1876 { USB_DEVICE(0x0df6, 0x9712), USB_DEVICE_DATA(&rt73usb_ops) },
1877 { USB_DEVICE(0x0df6, 0x90ac), USB_DEVICE_DATA(&rt73usb_ops) },
1878 /* Surecom */
1879 { USB_DEVICE(0x0769, 0x31f3), USB_DEVICE_DATA(&rt73usb_ops) },
1880 /* Planex */
1881 { USB_DEVICE(0x2019, 0xab01), USB_DEVICE_DATA(&rt73usb_ops) },
1882 { USB_DEVICE(0x2019, 0xab50), USB_DEVICE_DATA(&rt73usb_ops) },
1883 { 0, }
1884 };
1885
1886 MODULE_AUTHOR(DRV_PROJECT);
1887 MODULE_VERSION(DRV_VERSION);
1888 MODULE_DESCRIPTION("Ralink RT73 USB Wireless LAN driver.");
1889 MODULE_SUPPORTED_DEVICE("Ralink RT2571W & RT2671 USB chipset based cards");
1890 MODULE_DEVICE_TABLE(usb, rt73usb_device_table);
1891 MODULE_FIRMWARE(FIRMWARE_RT2571);
1892 MODULE_LICENSE("GPL");
1893
1894 static struct usb_driver rt73usb_driver = {
1895 .name = DRV_NAME,
1896 .id_table = rt73usb_device_table,
1897 .probe = rt2x00usb_probe,
1898 .disconnect = rt2x00usb_disconnect,
1899 #ifdef CONFIG_PM
1900 .suspend = rt2x00usb_suspend,
1901 .resume = rt2x00usb_resume,
1902 #endif /* CONFIG_PM */
1903 };
1904
1905 static int __init rt73usb_init(void)
1906 {
1907 return usb_register(&rt73usb_driver);
1908 }
1909
1910 static void __exit rt73usb_exit(void)
1911 {
1912 usb_deregister(&rt73usb_driver);
1913 }
1914
1915 module_init(rt73usb_init);
1916 module_exit(rt73usb_exit);
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