2 * Sonics Silicon Backplane
3 * Broadcom MIPS core driver
5 * Copyright 2005, Broadcom Corporation
6 * Copyright 2006, 2007, Michael Buesch <mb@bu3sch.de>
7 * Copyright 2006, 2007, Felix Fietkau <nbd@openwrt.org>
9 * Licensed under the GNU/GPL. See COPYING for details.
12 #include <linux/ssb/ssb.h>
14 #include <linux/serial.h>
15 #include <linux/serial_core.h>
16 #include <linux/serial_reg.h>
19 #include "../ssb_private.h"
21 #define mips_read32(mcore, offset) ssb_read32((mcore)->dev, offset)
22 #define mips_write32(mcore, offset, value) ssb_write32((mcore)->dev, offset, value)
23 #define extif_read32(extif, offset) ssb_read32((extif)->dev, offset)
24 #define extif_write32(extif, offset, value) ssb_write32((extif)->dev, offset, value)
26 static const u32 ipsflag_irq_mask
[] = {
34 static const u32 ipsflag_irq_shift
[] = {
36 SSB_IPSFLAG_IRQ1_SHIFT
,
37 SSB_IPSFLAG_IRQ2_SHIFT
,
38 SSB_IPSFLAG_IRQ3_SHIFT
,
39 SSB_IPSFLAG_IRQ4_SHIFT
,
42 static inline u32
ssb_irqflag(struct ssb_device
*dev
)
44 return ssb_read32(dev
, SSB_TPSFLAG
) & SSB_TPSFLAG_BPFLAG
;
47 /* Get the MIPS IRQ assignment for a specified device.
48 * If unassigned, 0 is returned.
50 unsigned int ssb_mips_irq(struct ssb_device
*dev
)
52 struct ssb_bus
*bus
= dev
->bus
;
58 irqflag
= ssb_irqflag(dev
);
59 ipsflag
= ssb_read32(bus
->mipscore
.dev
, SSB_IPSFLAG
);
60 for (irq
= 1; irq
<= 4; irq
++) {
61 tmp
= ((ipsflag
& ipsflag_irq_mask
[irq
]) >> ipsflag_irq_shift
[irq
]);
71 static void clear_irq(struct ssb_bus
*bus
, unsigned int irq
)
73 struct ssb_device
*dev
= bus
->mipscore
.dev
;
75 /* Clear the IRQ in the MIPScore backplane registers */
77 ssb_write32(dev
, SSB_INTVEC
, 0);
79 ssb_write32(dev
, SSB_IPSFLAG
,
80 ssb_read32(dev
, SSB_IPSFLAG
) |
81 ipsflag_irq_mask
[irq
]);
85 static void set_irq(struct ssb_device
*dev
, unsigned int irq
)
87 unsigned int oldirq
= ssb_mips_irq(dev
);
88 struct ssb_bus
*bus
= dev
->bus
;
89 struct ssb_device
*mdev
= bus
->mipscore
.dev
;
90 u32 irqflag
= ssb_irqflag(dev
);
94 ssb_dprintk(KERN_INFO PFX
95 "set_irq: core 0x%04x, irq %d => %d\n",
96 dev
->id
.coreid
, oldirq
, irq
);
97 /* clear the old irq */
99 ssb_write32(mdev
, SSB_INTVEC
, (~(1 << irqflag
) & ssb_read32(mdev
, SSB_INTVEC
)));
101 clear_irq(bus
, oldirq
);
103 /* assign the new one */
105 ssb_write32(mdev
, SSB_INTVEC
, ((1 << irqflag
) & ssb_read32(mdev
, SSB_INTVEC
)));
107 irqflag
<<= ipsflag_irq_shift
[irq
];
108 irqflag
|= (ssb_read32(mdev
, SSB_IPSFLAG
) & ~ipsflag_irq_mask
[irq
]);
109 ssb_write32(mdev
, SSB_IPSFLAG
, irqflag
);
112 static int ssb_extif_serial_init(struct ssb_extif
*dev
, struct ssb_serial_port
*ports
)
114 //TODO if (EXTIF available
116 extifregs_t
*eir
= (extifregs_t
*) regs
;
119 /* Determine external UART register base */
120 sb
= (sbconfig_t
*)((ulong
) eir
+ SBCONFIGOFF
);
121 base
= EXTIF_CFGIF_BASE(sb_base(R_REG(&sb
->sbadmatch1
)));
126 /* Disable GPIO interrupt initially */
127 W_REG(&eir
->gpiointpolarity
, 0);
128 W_REG(&eir
->gpiointmask
, 0);
130 /* Search for external UARTs */
132 for (i
= 0; i
< 2; i
++) {
133 regs
= (void *) REG_MAP(base
+ (i
* 8), 8);
134 if (BCMINIT(serial_exists
)(regs
)) {
135 /* Set GPIO 1 to be the external UART IRQ */
136 W_REG(&eir
->gpiointmask
, 2);
138 add(regs
, irq
, 13500000, 0);
142 /* Add internal UART if enabled */
143 if (R_REG(&eir
->corecontrol
) & CC_UE
)
145 add((void *) &eir
->uartdata
, irq
, sb_clock(sbh
), 2);
152 static void ssb_mips_serial_init(struct ssb_mipscore
*mcore
)
154 struct ssb_bus
*bus
= mcore
->dev
->bus
;
157 mcore
->nr_serial_ports
= ssb_extif_serial_init(&bus
->extif
, mcore
->serial_ports
);
158 else if (bus
->chipco
.dev
)
159 mcore
->nr_serial_ports
= ssb_chipco_serial_init(&bus
->chipco
, mcore
->serial_ports
);
161 mcore
->nr_serial_ports
= 0;
164 static void ssb_mips_flash_detect(struct ssb_mipscore
*mcore
)
166 struct ssb_bus
*bus
= mcore
->dev
->bus
;
168 if (bus
->chipco
.dev
) {
169 mcore
->flash_window
= 0x1c000000;
170 mcore
->flash_window_size
= 0x800000;
172 mcore
->flash_window
= 0x1fc00000;
173 mcore
->flash_window_size
= 0x400000;
177 static void ssb_extif_timing_init(struct ssb_extif
*extif
, u32 ns
)
181 /* Initialize extif so we can get to the LEDs and external UART */
182 extif_write32(extif
, SSB_EXTIF_PROG_CFG
, SSB_EXTCFG_EN
);
184 /* Set timing for the flash */
185 tmp
= ceildiv(10, ns
) << SSB_PROG_WCNT_3_SHIFT
;
186 tmp
|= ceildiv(40, ns
) << SSB_PROG_WCNT_1_SHIFT
;
187 tmp
|= ceildiv(120, ns
);
188 extif_write32(extif
, SSB_EXTIF_PROG_WAITCNT
, tmp
);
190 /* Set programmable interface timing for external uart */
191 tmp
= ceildiv(10, ns
) << SSB_PROG_WCNT_3_SHIFT
;
192 tmp
|= ceildiv(20, ns
) << SSB_PROG_WCNT_2_SHIFT
;
193 tmp
|= ceildiv(100, ns
) << SSB_PROG_WCNT_1_SHIFT
;
194 tmp
|= ceildiv(120, ns
);
195 extif_write32(extif
, SSB_EXTIF_PROG_WAITCNT
, tmp
);
198 static inline void ssb_extif_get_clockcontrol(struct ssb_extif
*extif
,
199 u32
*pll_type
, u32
*n
, u32
*m
)
201 *pll_type
= SSB_PLLTYPE_1
;
202 *n
= extif_read32(extif
, SSB_EXTIF_CLOCK_N
);
203 *m
= extif_read32(extif
, SSB_EXTIF_CLOCK_SB
);
206 u32
ssb_cpu_clock(struct ssb_mipscore
*mcore
)
208 struct ssb_bus
*bus
= mcore
->dev
->bus
;
209 u32 pll_type
, n
, m
, rate
= 0;
211 if (bus
->extif
.dev
) {
212 ssb_extif_get_clockcontrol(&bus
->extif
, &pll_type
, &n
, &m
);
213 } else if (bus
->chipco
.dev
) {
214 if (bus
->chip_id
== 0x5365)
215 /* FIXME: is this override really necessary? */
218 ssb_chipco_get_clockcontrol(&bus
->chipco
, &pll_type
, &n
, &m
);
222 rate
= ssb_calc_clock_rate(pll_type
, n
, m
);
223 if (pll_type
== SSB_PLLTYPE_6
)
229 void ssb_mipscore_init(struct ssb_mipscore
*mcore
)
231 struct ssb_bus
*bus
= mcore
->dev
->bus
;
232 struct ssb_device
*dev
;
233 unsigned long hz
, ns
;
237 return; /* We don't have a MIPS core */
239 ssb_dprintk(KERN_INFO PFX
"Initializing MIPS core...\n");
241 hz
= ssb_clockspeed(bus
);
244 ns
= 1000000000 / hz
;
247 ssb_extif_timing_init(&bus
->extif
, ns
);
248 else if (bus
->chipco
.dev
)
249 ssb_chipco_timing_init(&bus
->chipco
, ns
);
251 /* Assign IRQs to all cores on the bus, start with irq line 2, because serial usually takes 1 */
252 for (irq
= 2, i
= 0; i
< bus
->nr_devices
; i
++) {
253 dev
= &(bus
->devices
[i
]);
254 dev
->irq
= ssb_mips_irq(dev
) + 2;
255 switch(dev
->id
.coreid
) {
256 case SSB_DEV_USB11_HOST
:
257 /* shouldn't need a separate irq line for non-4710, most of them have a proper
258 * external usb controller on the pci */
259 if ((bus
->chip_id
== 0x4710) && (irq
<= 4)) {
264 case SSB_DEV_ETHERNET
:
266 case SSB_DEV_USB20_HOST
:
267 /* These devices get their own IRQ line if available, the rest goes on IRQ0 */
275 ssb_mips_serial_init(mcore
);
276 ssb_mips_flash_detect(mcore
);
279 EXPORT_SYMBOL(ssb_mips_irq
);
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