projects / openwrt.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
history | raw | HEAD
[x86] alix2, geos: Adjust CFLAGS
[openwrt.git] / target / linux / xburst / patches-2.6.36 / 200-udc.patch
1 From 7668895419d2fe3d7f371b239088f329c019e7e3 Mon Sep 17 00:00:00 2001
2 From: Lars-Peter Clausen <lars@metafoo.de>
3 Date: Sat, 24 Apr 2010 12:18:46 +0200
4 Subject: [PATCH] Add jz4740 udc driver
5
6 ---
7 drivers/usb/gadget/Kconfig | 14 +
8 drivers/usb/gadget/Makefile | 1 +
9 drivers/usb/gadget/gadget_chips.h | 9 +
10 drivers/usb/gadget/jz4740_udc.c | 2437 +++++++++++++++++++++++++++++++++++++
11 drivers/usb/gadget/jz4740_udc.h | 100 ++
12 5 files changed, 2561 insertions(+), 0 deletions(-)
13 create mode 100644 drivers/usb/gadget/jz4740_udc.c
14 create mode 100644 drivers/usb/gadget/jz4740_udc.h
15
16 --- a/drivers/usb/gadget/Kconfig
17 +++ b/drivers/usb/gadget/Kconfig
18 @@ -121,11 +121,25 @@ choice
19 #
20 # Integrated controllers
21 #
22 +config USB_GADGET_JZ4740
23 + boolean "JZ4740 UDC"
24 + depends on MACH_JZ4740
25 + select USB_GADGET_SELECTED
26 + select USB_GADGET_DUALSPEED
27 + help
28 + Select this to support the Ingenic JZ4740 processor
29 + high speed USB device controller.
30 +
31 +config USB_JZ4740
32 + tristate
33 + depends on USB_GADGET_JZ4740
34 + default USB_GADGET
35
36 config USB_GADGET_AT91
37 boolean "Atmel AT91 USB Device Port"
38 depends on ARCH_AT91 && !ARCH_AT91SAM9RL && !ARCH_AT91CAP9 && !ARCH_AT91SAM9G45
39 select USB_GADGET_SELECTED
40 +
41 help
42 Many Atmel AT91 processors (such as the AT91RM2000) have a
43 full speed USB Device Port with support for five configurable
44 --- a/drivers/usb/gadget/Makefile
45 +++ b/drivers/usb/gadget/Makefile
46 @@ -28,6 +28,7 @@ obj-$(CONFIG_USB_FSL_QE) += fsl_qe_udc.o
47 obj-$(CONFIG_USB_CI13XXX) += ci13xxx_udc.o
48 obj-$(CONFIG_USB_S3C_HSOTG) += s3c-hsotg.o
49 obj-$(CONFIG_USB_LANGWELL) += langwell_udc.o
50 +obj-$(CONFIG_USB_JZ4740) += jz4740_udc.o
51
52 #
53 # USB gadget drivers
54 --- a/drivers/usb/gadget/gadget_chips.h
55 +++ b/drivers/usb/gadget/gadget_chips.h
56 @@ -15,6 +15,12 @@
57 #ifndef __GADGET_CHIPS_H
58 #define __GADGET_CHIPS_H
59
60 +#ifdef CONFIG_USB_GADGET_JZ4740
61 +#define gadget_is_jz4740(g) !strcmp("ingenic_hsusb", (g)->name)
62 +#else
63 +#define gadget_is_jz4740(g) 0
64 +#endif
65 +
66 #ifdef CONFIG_USB_GADGET_NET2280
67 #define gadget_is_net2280(g) !strcmp("net2280", (g)->name)
68 #else
69 @@ -200,6 +206,9 @@ static inline int usb_gadget_controller_
70 return 0x25;
71 else if (gadget_is_s3c_hsotg(gadget))
72 return 0x26;
73 + else if (gadget_is_jz4740(gadget))
74 + return 0x27;
75 +
76 return -ENOENT;
77 }
78
79 --- /dev/null
80 +++ b/drivers/usb/gadget/jz4740_udc.c
81 @@ -0,0 +1,2437 @@
82 +/*
83 + * linux/drivers/usb/gadget/jz4740_udc.c
84 + *
85 + * Ingenic JZ4740 on-chip high speed USB device controller
86 + *
87 + * Copyright (C) 2006 - 2008 Ingenic Semiconductor Inc.
88 + * Author: <jlwei@ingenic.cn>
89 + *
90 + * This program is free software; you can redistribute it and/or modify
91 + * it under the terms of the GNU General Public License as published by
92 + * the Free Software Foundation; either version 2 of the License, or
93 + * (at your option) any later version.
94 + */
95 +
96 +/*
97 + * This device has ep0, two bulk-in/interrupt-in endpoints, and one bulk-out endpoint.
98 + *
99 + * - Endpoint numbering is fixed: ep0, ep1in-int, ep2in-bulk, ep1out-bulk.
100 + * - DMA works with bulk-in (channel 1) and bulk-out (channel 2) endpoints.
101 + */
102 +
103 +#include <linux/kernel.h>
104 +#include <linux/module.h>
105 +#include <linux/platform_device.h>
106 +#include <linux/delay.h>
107 +#include <linux/ioport.h>
108 +#include <linux/slab.h>
109 +#include <linux/errno.h>
110 +#include <linux/init.h>
111 +#include <linux/list.h>
112 +#include <linux/interrupt.h>
113 +#include <linux/proc_fs.h>
114 +#include <linux/usb.h>
115 +#include <linux/usb/gadget.h>
116 +#include <linux/clk.h>
117 +
118 +#include <asm/byteorder.h>
119 +#include <asm/io.h>
120 +#include <asm/irq.h>
121 +#include <asm/system.h>
122 +#include <asm/mach-jz4740/clock.h>
123 +
124 +#include "jz4740_udc.h"
125 +
126 +#define JZ_REG_UDC_FADDR 0x00 /* Function Address 8-bit */
127 +#define JZ_REG_UDC_POWER 0x01 /* Power Management 8-bit */
128 +#define JZ_REG_UDC_INTRIN 0x02 /* Interrupt IN 16-bit */
129 +#define JZ_REG_UDC_INTROUT 0x04 /* Interrupt OUT 16-bit */
130 +#define JZ_REG_UDC_INTRINE 0x06 /* Intr IN enable 16-bit */
131 +#define JZ_REG_UDC_INTROUTE 0x08 /* Intr OUT enable 16-bit */
132 +#define JZ_REG_UDC_INTRUSB 0x0a /* Interrupt USB 8-bit */
133 +#define JZ_REG_UDC_INTRUSBE 0x0b /* Interrupt USB Enable 8-bit */
134 +#define JZ_REG_UDC_FRAME 0x0c /* Frame number 16-bit */
135 +#define JZ_REG_UDC_INDEX 0x0e /* Index register 8-bit */
136 +#define JZ_REG_UDC_TESTMODE 0x0f /* USB test mode 8-bit */
137 +
138 +#define JZ_REG_UDC_CSR0 0x12 /* EP0 CSR 8-bit */
139 +#define JZ_REG_UDC_INMAXP 0x10 /* EP1-2 IN Max Pkt Size 16-bit */
140 +#define JZ_REG_UDC_INCSR 0x12 /* EP1-2 IN CSR LSB 8/16bit */
141 +#define JZ_REG_UDC_INCSRH 0x13 /* EP1-2 IN CSR MSB 8-bit */
142 +#define JZ_REG_UDC_OUTMAXP 0x14 /* EP1 OUT Max Pkt Size 16-bit */
143 +#define JZ_REG_UDC_OUTCSR 0x16 /* EP1 OUT CSR LSB 8/16bit */
144 +#define JZ_REG_UDC_OUTCSRH 0x17 /* EP1 OUT CSR MSB 8-bit */
145 +#define JZ_REG_UDC_OUTCOUNT 0x18 /* bytes in EP0/1 OUT FIFO 16-bit */
146 +
147 +#define JZ_REG_UDC_EP_FIFO(x) (4 * (x) + 0x20)
148 +
149 +#define JZ_REG_UDC_EPINFO 0x78 /* Endpoint information */
150 +#define JZ_REG_UDC_RAMINFO 0x79 /* RAM information */
151 +
152 +#define JZ_REG_UDC_INTR 0x200 /* DMA pending interrupts */
153 +#define JZ_REG_UDC_CNTL1 0x204 /* DMA channel 1 control */
154 +#define JZ_REG_UDC_ADDR1 0x208 /* DMA channel 1 AHB memory addr */
155 +#define JZ_REG_UDC_COUNT1 0x20c /* DMA channel 1 byte count */
156 +#define JZ_REG_UDC_CNTL2 0x214 /* DMA channel 2 control */
157 +#define JZ_REG_UDC_ADDR2 0x218 /* DMA channel 2 AHB memory addr */
158 +#define JZ_REG_UDC_COUNT2 0x21c /* DMA channel 2 byte count */
159 +
160 +/* Power register bit masks */
161 +#define USB_POWER_SUSPENDM 0x01
162 +#define USB_POWER_RESUME 0x04
163 +#define USB_POWER_HSMODE 0x10
164 +#define USB_POWER_HSENAB 0x20
165 +#define USB_POWER_SOFTCONN 0x40
166 +
167 +/* Interrupt register bit masks */
168 +#define USB_INTR_SUSPEND 0x01
169 +#define USB_INTR_RESUME 0x02
170 +#define USB_INTR_RESET 0x04
171 +
172 +#define USB_INTR_EP0 0x0001
173 +#define USB_INTR_INEP1 0x0002
174 +#define USB_INTR_INEP2 0x0004
175 +#define USB_INTR_OUTEP1 0x0002
176 +
177 +/* CSR0 bit masks */
178 +#define USB_CSR0_OUTPKTRDY 0x01
179 +#define USB_CSR0_INPKTRDY 0x02
180 +#define USB_CSR0_SENTSTALL 0x04
181 +#define USB_CSR0_DATAEND 0x08
182 +#define USB_CSR0_SETUPEND 0x10
183 +#define USB_CSR0_SENDSTALL 0x20
184 +#define USB_CSR0_SVDOUTPKTRDY 0x40
185 +#define USB_CSR0_SVDSETUPEND 0x80
186 +
187 +/* Endpoint CSR register bits */
188 +#define USB_INCSRH_AUTOSET 0x80
189 +#define USB_INCSRH_ISO 0x40
190 +#define USB_INCSRH_MODE 0x20
191 +#define USB_INCSRH_DMAREQENAB 0x10
192 +#define USB_INCSRH_DMAREQMODE 0x04
193 +#define USB_INCSR_CDT 0x40
194 +#define USB_INCSR_SENTSTALL 0x20
195 +#define USB_INCSR_SENDSTALL 0x10
196 +#define USB_INCSR_FF 0x08
197 +#define USB_INCSR_UNDERRUN 0x04
198 +#define USB_INCSR_FFNOTEMPT 0x02
199 +#define USB_INCSR_INPKTRDY 0x01
200 +#define USB_OUTCSRH_AUTOCLR 0x80
201 +#define USB_OUTCSRH_ISO 0x40
202 +#define USB_OUTCSRH_DMAREQENAB 0x20
203 +#define USB_OUTCSRH_DNYT 0x10
204 +#define USB_OUTCSRH_DMAREQMODE 0x08
205 +#define USB_OUTCSR_CDT 0x80
206 +#define USB_OUTCSR_SENTSTALL 0x40
207 +#define USB_OUTCSR_SENDSTALL 0x20
208 +#define USB_OUTCSR_FF 0x10
209 +#define USB_OUTCSR_DATAERR 0x08
210 +#define USB_OUTCSR_OVERRUN 0x04
211 +#define USB_OUTCSR_FFFULL 0x02
212 +#define USB_OUTCSR_OUTPKTRDY 0x01
213 +
214 +/* Testmode register bits */
215 +#define USB_TEST_SE0NAK 0x01
216 +#define USB_TEST_J 0x02
217 +#define USB_TEST_K 0x04
218 +#define USB_TEST_PACKET 0x08
219 +
220 +/* DMA control bits */
221 +#define USB_CNTL_ENA 0x01
222 +#define USB_CNTL_DIR_IN 0x02
223 +#define USB_CNTL_MODE_1 0x04
224 +#define USB_CNTL_INTR_EN 0x08
225 +#define USB_CNTL_EP(n) ((n) << 4)
226 +#define USB_CNTL_BURST_0 (0 << 9)
227 +#define USB_CNTL_BURST_4 (1 << 9)
228 +#define USB_CNTL_BURST_8 (2 << 9)
229 +#define USB_CNTL_BURST_16 (3 << 9)
230 +
231 +
232 +#ifndef DEBUG
233 +# define DEBUG(fmt,args...) do {} while(0)
234 +#endif
235 +#ifndef DEBUG_EP0
236 +# define NO_STATES
237 +# define DEBUG_EP0(fmt,args...) do {} while(0)
238 +#endif
239 +#ifndef DEBUG_SETUP
240 +# define DEBUG_SETUP(fmt,args...) do {} while(0)
241 +#endif
242 +
243 +static unsigned int use_dma = 0; /* 1: use DMA, 0: use PIO */
244 +
245 +module_param(use_dma, int, 0);
246 +MODULE_PARM_DESC(use_dma, "DMA mode enable flag");
247 +
248 +struct jz4740_udc *the_controller;
249 +
250 +/*
251 + * Local declarations.
252 + */
253 +static void jz4740_ep0_kick(struct jz4740_udc *dev, struct jz4740_ep *ep);
254 +static void jz4740_handle_ep0(struct jz4740_udc *dev, uint32_t intr);
255 +
256 +static void done(struct jz4740_ep *ep, struct jz4740_request *req,
257 + int status);
258 +static void pio_irq_enable(struct jz4740_ep *ep);
259 +static void pio_irq_disable(struct jz4740_ep *ep);
260 +static void stop_activity(struct jz4740_udc *dev,
261 + struct usb_gadget_driver *driver);
262 +static void nuke(struct jz4740_ep *ep, int status);
263 +static void flush(struct jz4740_ep *ep);
264 +static void udc_set_address(struct jz4740_udc *dev, unsigned char address);
265 +
266 +/*-------------------------------------------------------------------------*/
267 +
268 +/* inline functions of register read/write/set/clear */
269 +
270 +static inline uint8_t usb_readb(struct jz4740_udc *udc, size_t reg)
271 +{
272 + return readb(udc->base + reg);
273 +}
274 +
275 +static inline uint16_t usb_readw(struct jz4740_udc *udc, size_t reg)
276 +{
277 + return readw(udc->base + reg);
278 +}
279 +
280 +static inline uint32_t usb_readl(struct jz4740_udc *udc, size_t reg)
281 +{
282 + return readl(udc->base + reg);
283 +}
284 +
285 +static inline void usb_writeb(struct jz4740_udc *udc, size_t reg, uint8_t val)
286 +{
287 + writeb(val, udc->base + reg);
288 +}
289 +
290 +static inline void usb_writew(struct jz4740_udc *udc, size_t reg, uint16_t val)
291 +{
292 + writew(val, udc->base + reg);
293 +}
294 +
295 +static inline void usb_writel(struct jz4740_udc *udc, size_t reg, uint32_t val)
296 +{
297 + writel(val, udc->base + reg);
298 +}
299 +
300 +static inline void usb_setb(struct jz4740_udc *udc, size_t reg, uint8_t mask)
301 +{
302 + usb_writeb(udc, reg, usb_readb(udc, reg) | mask);
303 +}
304 +
305 +static inline void usb_setw(struct jz4740_udc *udc, size_t reg, uint8_t mask)
306 +{
307 + usb_writew(udc, reg, usb_readw(udc, reg) | mask);
308 +}
309 +
310 +static inline void usb_setl(struct jz4740_udc *udc, size_t reg, uint32_t mask)
311 +{
312 + usb_writel(udc, reg, usb_readl(udc, reg) | mask);
313 +}
314 +
315 +static inline void usb_clearb(struct jz4740_udc *udc, size_t reg, uint8_t mask)
316 +{
317 + usb_writeb(udc, reg, usb_readb(udc, reg) & ~mask);
318 +}
319 +
320 +static inline void usb_clearw(struct jz4740_udc *udc, size_t reg, uint16_t mask)
321 +{
322 + usb_writew(udc, reg, usb_readw(udc, reg) & ~mask);
323 +}
324 +
325 +static inline void usb_clearl(struct jz4740_udc *udc, size_t reg, uint32_t mask)
326 +{
327 + usb_writel(udc, reg, usb_readl(udc, reg) & ~mask);
328 +}
329 +
330 +/*-------------------------------------------------------------------------*/
331 +
332 +static inline void jz_udc_set_index(struct jz4740_udc *udc, uint8_t index)
333 +{
334 + usb_writeb(udc, JZ_REG_UDC_INDEX, index);
335 +}
336 +
337 +static inline void jz_udc_select_ep(struct jz4740_ep *ep)
338 +{
339 + jz_udc_set_index(ep->dev, ep_index(ep));
340 +}
341 +
342 +static inline int write_packet(struct jz4740_ep *ep,
343 + struct jz4740_request *req, int max)
344 +{
345 + uint8_t *buf;
346 + int length, nlong, nbyte;
347 + DEBUG("%s:%s[%d]\n", __FILE__, __func__, __LINE__);
348 +
349 + buf = req->req.buf + req->req.actual;
350 + prefetch(buf);
351 +
352 + length = req->req.length - req->req.actual;
353 + length = min(length, max);
354 + req->req.actual += length;
355 +
356 + DEBUG("Write %d (max %d), fifo %x\n", length, max, ep->fifo);
357 +
358 + nlong = length >> 2;
359 + nbyte = length & 0x3;
360 + while (nlong--) {
361 + usb_writel(ep->dev, ep->fifo, *((uint32_t *)buf));
362 + buf += 4;
363 + }
364 + while (nbyte--) {
365 + usb_writeb(ep->dev, ep->fifo, *buf++);
366 + }
367 +
368 + return length;
369 +}
370 +
371 +static inline int read_packet(struct jz4740_ep *ep,
372 + struct jz4740_request *req, int count)
373 +{
374 + uint8_t *buf;
375 + int length, nlong, nbyte;
376 + DEBUG("%s:%s[%d]\n", __FILE__, __func__, __LINE__);
377 +
378 + buf = req->req.buf + req->req.actual;
379 + prefetchw(buf);
380 +
381 + length = req->req.length - req->req.actual;
382 + length = min(length, count);
383 + req->req.actual += length;
384 +
385 + DEBUG("Read %d, fifo %x\n", length, ep->fifo);
386 +
387 + nlong = length >> 2;
388 + nbyte = length & 0x3;
389 + while (nlong--) {
390 + *((uint32_t *)buf) = usb_readl(ep->dev, ep->fifo);
391 + buf += 4;
392 + }
393 + while (nbyte--) {
394 + *buf++ = usb_readb(ep->dev, ep->fifo);
395 + }
396 +
397 + return length;
398 +}
399 +
400 +/*-------------------------------------------------------------------------*/
401 +
402 +/*
403 + * udc_disable - disable USB device controller
404 + */
405 +static void udc_disable(struct jz4740_udc *dev)
406 +{
407 + DEBUG("%s:%s[%d]\n", __FILE__, __func__, __LINE__);
408 +
409 + udc_set_address(dev, 0);
410 +
411 + /* Disable interrupts */
412 + usb_writew(dev, JZ_REG_UDC_INTRINE, 0);
413 + usb_writew(dev, JZ_REG_UDC_INTROUTE, 0);
414 + usb_writeb(dev, JZ_REG_UDC_INTRUSBE, 0);
415 +
416 + /* Disable DMA */
417 + usb_writel(dev, JZ_REG_UDC_CNTL1, 0);
418 + usb_writel(dev, JZ_REG_UDC_CNTL2, 0);
419 +
420 + /* Disconnect from usb */
421 + usb_clearb(dev, JZ_REG_UDC_POWER, USB_POWER_SOFTCONN);
422 +
423 + /* Disable the USB PHY */
424 + clk_disable(dev->clk);
425 +
426 + dev->ep0state = WAIT_FOR_SETUP;
427 + dev->gadget.speed = USB_SPEED_UNKNOWN;
428 +
429 + return;
430 +}
431 +
432 +/*
433 + * udc_reinit - initialize software state
434 + */
435 +static void udc_reinit(struct jz4740_udc *dev)
436 +{
437 + int i;
438 + DEBUG("%s:%s[%d]\n", __FILE__, __func__, __LINE__);
439 +
440 + /* device/ep0 records init */
441 + INIT_LIST_HEAD(&dev->gadget.ep_list);
442 + INIT_LIST_HEAD(&dev->gadget.ep0->ep_list);
443 + dev->ep0state = WAIT_FOR_SETUP;
444 +
445 + for (i = 0; i < UDC_MAX_ENDPOINTS; i++) {
446 + struct jz4740_ep *ep = &dev->ep[i];
447 +
448 + if (i != 0)
449 + list_add_tail(&ep->ep.ep_list, &dev->gadget.ep_list);
450 +
451 + INIT_LIST_HEAD(&ep->queue);
452 + ep->desc = 0;
453 + ep->stopped = 0;
454 + ep->pio_irqs = 0;
455 + }
456 +}
457 +
458 +/* until it's enabled, this UDC should be completely invisible
459 + * to any USB host.
460 + */
461 +static void udc_enable(struct jz4740_udc *dev)
462 +{
463 + int i;
464 + DEBUG("%s:%s[%d]\n", __FILE__, __func__, __LINE__);
465 +
466 + /* UDC state is incorrect - Added by River */
467 + if (dev->state != UDC_STATE_ENABLE) {
468 + return;
469 + }
470 +
471 + dev->gadget.speed = USB_SPEED_UNKNOWN;
472 +
473 + /* Flush FIFO for each */
474 + for (i = 0; i < UDC_MAX_ENDPOINTS; i++) {
475 + struct jz4740_ep *ep = &dev->ep[i];
476 +
477 + jz_udc_set_index(dev, ep_index(ep));
478 + flush(ep);
479 + }
480 +
481 + /* Set this bit to allow the UDC entering low-power mode when
482 + * there are no actions on the USB bus.
483 + * UDC still works during this bit was set.
484 + */
485 + jz4740_clock_udc_enable_auto_suspend();
486 +
487 + /* Enable the USB PHY */
488 + clk_enable(dev->clk);
489 +
490 + /* Disable interrupts */
491 +/* usb_writew(dev, JZ_REG_UDC_INTRINE, 0);
492 + usb_writew(dev, JZ_REG_UDC_INTROUTE, 0);
493 + usb_writeb(dev, JZ_REG_UDC_INTRUSBE, 0);*/
494 +
495 + /* Enable interrupts */
496 + usb_setw(dev, JZ_REG_UDC_INTRINE, USB_INTR_EP0);
497 + usb_setb(dev, JZ_REG_UDC_INTRUSBE, USB_INTR_RESET);
498 + /* Don't enable rest of the interrupts */
499 + /* usb_setw(dev, JZ_REG_UDC_INTRINE, USB_INTR_INEP1 | USB_INTR_INEP2);
500 + usb_setw(dev, JZ_REG_UDC_INTROUTE, USB_INTR_OUTEP1); */
501 +
502 + /* Enable SUSPEND */
503 + /* usb_setb(dev, JZ_REG_UDC_POWER, USB_POWER_SUSPENDM); */
504 +
505 + /* Enable HS Mode */
506 + usb_setb(dev, JZ_REG_UDC_POWER, USB_POWER_HSENAB);
507 +
508 + /* Let host detect UDC:
509 + * Software must write a 1 to the PMR:USB_POWER_SOFTCONN bit to turn this
510 + * transistor on and pull the USBDP pin HIGH.
511 + */
512 + usb_setb(dev, JZ_REG_UDC_POWER, USB_POWER_SOFTCONN);
513 +
514 + return;
515 +}
516 +
517 +/*-------------------------------------------------------------------------*/
518 +
519 +/* keeping it simple:
520 + * - one bus driver, initted first;
521 + * - one function driver, initted second
522 + */
523 +
524 +/*
525 + * Register entry point for the peripheral controller driver.
526 + */
527 +
528 +int usb_gadget_register_driver(struct usb_gadget_driver *driver)
529 +{
530 + struct jz4740_udc *dev = the_controller;
531 + int retval;
532 +
533 + if (!driver || !driver->bind) {
534 + return -EINVAL;
535 + }
536 +
537 + if (!dev) {
538 + return -ENODEV;
539 + }
540 +
541 + if (dev->driver) {
542 + return -EBUSY;
543 + }
544 +
545 + /* hook up the driver */
546 + dev->driver = driver;
547 + dev->gadget.dev.driver = &driver->driver;
548 +
549 + retval = driver->bind(&dev->gadget);
550 + if (retval) {
551 + DEBUG("%s: bind to driver %s --> error %d\n", dev->gadget.name,
552 + driver->driver.name, retval);
553 + dev->driver = 0;
554 + return retval;
555 + }
556 +
557 + /* then enable host detection and ep0; and we're ready
558 + * for set_configuration as well as eventual disconnect.
559 + */
560 + udc_enable(dev);
561 +
562 + DEBUG("%s: registered gadget driver '%s'\n", dev->gadget.name,
563 + driver->driver.name);
564 +
565 + return 0;
566 +}
567 +
568 +EXPORT_SYMBOL(usb_gadget_register_driver);
569 +
570 +static void stop_activity(struct jz4740_udc *dev,
571 + struct usb_gadget_driver *driver)
572 +{
573 + int i;
574 +
575 + DEBUG("%s:%s[%d]\n", __FILE__, __func__, __LINE__);
576 +
577 + /* don't disconnect drivers more than once */
578 + if (dev->gadget.speed == USB_SPEED_UNKNOWN)
579 + driver = 0;
580 + dev->gadget.speed = USB_SPEED_UNKNOWN;
581 +
582 + /* prevent new request submissions, kill any outstanding requests */
583 + for (i = 0; i < UDC_MAX_ENDPOINTS; i++) {
584 + struct jz4740_ep *ep = &dev->ep[i];
585 +
586 + ep->stopped = 1;
587 +
588 + jz_udc_set_index(dev, ep_index(ep));
589 + nuke(ep, -ESHUTDOWN);
590 + }
591 +
592 + /* report disconnect; the driver is already quiesced */
593 + if (driver) {
594 + spin_unlock(&dev->lock);
595 + driver->disconnect(&dev->gadget);
596 + spin_lock(&dev->lock);
597 + }
598 +
599 + /* re-init driver-visible data structures */
600 + udc_reinit(dev);
601 +}
602 +
603 +
604 +/*
605 + * Unregister entry point for the peripheral controller driver.
606 + */
607 +int usb_gadget_unregister_driver(struct usb_gadget_driver *driver)
608 +{
609 + struct jz4740_udc *dev = the_controller;
610 + unsigned long flags;
611 + DEBUG("%s:%s[%d]\n", __FILE__, __func__, __LINE__);
612 +
613 + if (!dev)
614 + return -ENODEV;
615 + if (!driver || driver != dev->driver)
616 + return -EINVAL;
617 + if (!driver->unbind)
618 + return -EBUSY;
619 +
620 + spin_lock_irqsave(&dev->lock, flags);
621 + dev->driver = 0;
622 + stop_activity(dev, driver);
623 + spin_unlock_irqrestore(&dev->lock, flags);
624 +
625 + driver->unbind(&dev->gadget);
626 +
627 + udc_disable(dev);
628 +
629 + DEBUG("unregistered driver '%s'\n", driver->driver.name);
630 +
631 + return 0;
632 +}
633 +
634 +EXPORT_SYMBOL(usb_gadget_unregister_driver);
635 +
636 +/*-------------------------------------------------------------------------*/
637 +
638 +/*
639 + * Starting DMA using mode 1
640 + */
641 +static void kick_dma(struct jz4740_ep *ep, struct jz4740_request *req)
642 +{
643 + struct jz4740_udc *dev = ep->dev;
644 + uint32_t count = req->req.length;
645 + uint32_t physaddr = virt_to_phys((void *)req->req.buf);
646 +
647 + DEBUG("%s:%s[%d]\n", __FILE__, __func__, __LINE__);
648 +
649 + jz_udc_select_ep(ep);
650 +
651 + if (ep_is_in(ep)) { /* Bulk-IN transfer using DMA channel 1 */
652 + ep->reg_addr = JZ_REG_UDC_ADDR1;
653 +
654 + dma_cache_wback_inv((unsigned long)req->req.buf, count);
655 +
656 + pio_irq_enable(ep);
657 +
658 + usb_writeb(dev, JZ_REG_UDC_INCSRH,
659 + USB_INCSRH_DMAREQENAB | USB_INCSRH_AUTOSET | USB_INCSRH_DMAREQMODE);
660 +
661 + usb_writel(dev, JZ_REG_UDC_ADDR1, physaddr);
662 + usb_writel(dev, JZ_REG_UDC_COUNT1, count);
663 + usb_writel(dev, JZ_REG_UDC_CNTL1, USB_CNTL_ENA | USB_CNTL_DIR_IN | USB_CNTL_MODE_1 |
664 + USB_CNTL_INTR_EN | USB_CNTL_BURST_16 | USB_CNTL_EP(ep_index(ep)));
665 + }
666 + else { /* Bulk-OUT transfer using DMA channel 2 */
667 + ep->reg_addr = JZ_REG_UDC_ADDR2;
668 +
669 + dma_cache_wback_inv((unsigned long)req->req.buf, count);
670 +
671 + pio_irq_enable(ep);
672 +
673 + usb_setb(dev, JZ_REG_UDC_OUTCSRH,
674 + USB_OUTCSRH_DMAREQENAB | USB_OUTCSRH_AUTOCLR | USB_OUTCSRH_DMAREQMODE);
675 +
676 + usb_writel(dev, JZ_REG_UDC_ADDR2, physaddr);
677 + usb_writel(dev, JZ_REG_UDC_COUNT2, count);
678 + usb_writel(dev, JZ_REG_UDC_CNTL2, USB_CNTL_ENA | USB_CNTL_MODE_1 |
679 + USB_CNTL_INTR_EN | USB_CNTL_BURST_16 | USB_CNTL_EP(ep_index(ep)));
680 + }
681 +}
682 +
683 +/*-------------------------------------------------------------------------*/
684 +
685 +/** Write request to FIFO (max write == maxp size)
686 + * Return: 0 = still running, 1 = completed, negative = errno
687 + * NOTE: INDEX register must be set for EP
688 + */
689 +static int write_fifo(struct jz4740_ep *ep, struct jz4740_request *req)
690 +{
691 + struct jz4740_udc *dev = ep->dev;
692 + uint32_t max, csr;
693 + uint32_t physaddr = virt_to_phys((void *)req->req.buf);
694 +
695 + DEBUG("%s:%s[%d]\n", __FILE__, __func__, __LINE__);
696 + max = le16_to_cpu(ep->desc->wMaxPacketSize);
697 +
698 + if (use_dma) {
699 + uint32_t dma_count;
700 +
701 + /* DMA interrupt generated due to the last packet loaded into the FIFO */
702 +
703 + dma_count = usb_readl(dev, ep->reg_addr) - physaddr;
704 + req->req.actual += dma_count;
705 +
706 + if (dma_count % max) {
707 + /* If the last packet is less than MAXP, set INPKTRDY manually */
708 + usb_setb(dev, ep->csr, USB_INCSR_INPKTRDY);
709 + }
710 +
711 + done(ep, req, 0);
712 + if (list_empty(&ep->queue)) {
713 + pio_irq_disable(ep);
714 + return 1;
715 + }
716 + else {
717 + /* advance the request queue */
718 + req = list_entry(ep->queue.next, struct jz4740_request, queue);
719 + kick_dma(ep, req);
720 + return 0;
721 + }
722 + }
723 +
724 + /*
725 + * PIO mode handling starts here ...
726 + */
727 +
728 + csr = usb_readb(dev, ep->csr);
729 +
730 + if (!(csr & USB_INCSR_FFNOTEMPT)) {
731 + unsigned count;
732 + int is_last, is_short;
733 +
734 + count = write_packet(ep, req, max);
735 + usb_setb(dev, ep->csr, USB_INCSR_INPKTRDY);
736 +
737 + /* last packet is usually short (or a zlp) */
738 + if (unlikely(count != max))
739 + is_last = is_short = 1;
740 + else {
741 + if (likely(req->req.length != req->req.actual)
742 + || req->req.zero)
743 + is_last = 0;
744 + else
745 + is_last = 1;
746 + /* interrupt/iso maxpacket may not fill the fifo */
747 + is_short = unlikely(max < ep_maxpacket(ep));
748 + }
749 +
750 + DEBUG("%s: wrote %s %d bytes%s%s %d left %p\n", __FUNCTION__,
751 + ep->ep.name, count,
752 + is_last ? "/L" : "", is_short ? "/S" : "",
753 + req->req.length - req->req.actual, req);
754 +
755 + /* requests complete when all IN data is in the FIFO */
756 + if (is_last) {
757 + done(ep, req, 0);
758 + if (list_empty(&ep->queue)) {
759 + pio_irq_disable(ep);
760 + }
761 + return 1;
762 + }
763 + } else {
764 + DEBUG("Hmm.. %d ep FIFO is not empty!\n", ep_index(ep));
765 + }
766 +
767 + return 0;
768 +}
769 +
770 +/** Read to request from FIFO (max read == bytes in fifo)
771 + * Return: 0 = still running, 1 = completed, negative = errno
772 + * NOTE: INDEX register must be set for EP
773 + */
774 +static int read_fifo(struct jz4740_ep *ep, struct jz4740_request *req)
775 +{
776 + struct jz4740_udc *dev = ep->dev;
777 + uint32_t csr;
778 + unsigned count, is_short;
779 + uint32_t physaddr = virt_to_phys((void *)req->req.buf);
780 +
781 + if (use_dma) {
782 + uint32_t dma_count;
783 +
784 + /* DMA interrupt generated due to a packet less than MAXP loaded into the FIFO */
785 +
786 + dma_count = usb_readl(dev, ep->reg_addr) - physaddr;
787 + req->req.actual += dma_count;
788 +
789 + /* Disable interrupt and DMA */
790 + pio_irq_disable(ep);
791 + usb_writel(dev, JZ_REG_UDC_CNTL2, 0);
792 +
793 + /* Read all bytes from this packet */
794 + count = usb_readw(dev, JZ_REG_UDC_OUTCOUNT);
795 + count = read_packet(ep, req, count);
796 +
797 + if (count) {
798 + /* If the last packet is greater than zero, clear OUTPKTRDY manually */
799 + usb_clearb(dev, ep->csr, USB_OUTCSR_OUTPKTRDY);
800 + }
801 + done(ep, req, 0);
802 +
803 + if (!list_empty(&ep->queue)) {
804 + /* advance the request queue */
805 + req = list_entry(ep->queue.next, struct jz4740_request, queue);
806 + kick_dma(ep, req);
807 + }
808 +
809 + return 1;
810 + }
811 +
812 + /*
813 + * PIO mode handling starts here ...
814 + */
815 +
816 + /* make sure there's a packet in the FIFO. */
817 + csr = usb_readb(dev, ep->csr);
818 + if (!(csr & USB_OUTCSR_OUTPKTRDY)) {
819 + DEBUG("%s: Packet NOT ready!\n", __FUNCTION__);
820 + return -EINVAL;
821 + }
822 +
823 + /* read all bytes from this packet */
824 + count = usb_readw(dev, JZ_REG_UDC_OUTCOUNT);
825 +
826 + is_short = (count < ep->ep.maxpacket);
827 +
828 + count = read_packet(ep, req, count);
829 +
830 + DEBUG("read %s %02x, %d bytes%s req %p %d/%d\n",
831 + ep->ep.name, csr, count,
832 + is_short ? "/S" : "", req, req->req.actual, req->req.length);
833 +
834 + /* Clear OutPktRdy */
835 + usb_clearb(dev, ep->csr, USB_OUTCSR_OUTPKTRDY);
836 +
837 + /* completion */
838 + if (is_short || req->req.actual == req->req.length) {
839 + done(ep, req, 0);
840 +
841 + if (list_empty(&ep->queue))
842 + pio_irq_disable(ep);
843 + return 1;
844 + }
845 +
846 + /* finished that packet. the next one may be waiting... */
847 + return 0;
848 +}
849 +
850 +/*
851 + * done - retire a request; caller blocked irqs
852 + * INDEX register is preserved to keep same
853 + */
854 +static void done(struct jz4740_ep *ep, struct jz4740_request *req, int status)
855 +{
856 + unsigned int stopped = ep->stopped;
857 + uint32_t index;
858 +
859 + DEBUG("%s, %p\n", __FUNCTION__, ep);
860 + list_del_init(&req->queue);
861 +
862 + if (likely(req->req.status == -EINPROGRESS))
863 + req->req.status = status;
864 + else
865 + status = req->req.status;
866 +
867 + if (status && status != -ESHUTDOWN)
868 + DEBUG("complete %s req %p stat %d len %u/%u\n",
869 + ep->ep.name, &req->req, status,
870 + req->req.actual, req->req.length);
871 +
872 + /* don't modify queue heads during completion callback */
873 + ep->stopped = 1;
874 + /* Read current index (completion may modify it) */
875 + index = usb_readb(ep->dev, JZ_REG_UDC_INDEX);
876 + spin_unlock_irqrestore(&ep->dev->lock, ep->dev->lock_flags);
877 +
878 + req->req.complete(&ep->ep, &req->req);
879 +
880 + spin_lock_irqsave(&ep->dev->lock, ep->dev->lock_flags);
881 + /* Restore index */
882 + jz_udc_set_index(ep->dev, index);
883 + ep->stopped = stopped;
884 +}
885 +
886 +/** Enable EP interrupt */
887 +static void pio_irq_enable(struct jz4740_ep *ep)
888 +{
889 + uint8_t index = ep_index(ep);
890 + struct jz4740_udc *dev = ep->dev;
891 + DEBUG("%s: EP%d %s\n", __FUNCTION__, ep_index(ep), ep_is_in(ep) ? "IN": "OUT");
892 +
893 + if (ep_is_in(ep)) {
894 + switch (index) {
895 + case 1:
896 + case 2:
897 + usb_setw(dev, JZ_REG_UDC_INTRINE, BIT(index));
898 + dev->in_mask |= BIT(index);
899 + break;
900 + default:
901 + DEBUG("Unknown endpoint: %d\n", index);
902 + break;
903 + }
904 + }
905 + else {
906 + switch (index) {
907 + case 1:
908 + usb_setw(dev, JZ_REG_UDC_INTROUTE, BIT(index));
909 + dev->out_mask |= BIT(index);
910 + break;
911 + default:
912 + DEBUG("Unknown endpoint: %d\n", index);
913 + break;
914 + }
915 + }
916 +}
917 +
918 +/** Disable EP interrupt */
919 +static void pio_irq_disable(struct jz4740_ep *ep)
920 +{
921 + uint8_t index = ep_index(ep);
922 + struct jz4740_udc *dev = ep->dev;
923 +
924 + DEBUG("%s: EP%d %s\n", __FUNCTION__, ep_index(ep), ep_is_in(ep) ? "IN": "OUT");
925 +
926 + if (ep_is_in(ep)) {
927 + switch (ep_index(ep)) {
928 + case 1:
929 + case 2:
930 + usb_clearw(ep->dev, JZ_REG_UDC_INTRINE, BIT(index));
931 + dev->in_mask &= ~BIT(index);
932 + break;
933 + default:
934 + DEBUG("Unknown endpoint: %d\n", index);
935 + break;
936 + }
937 + }
938 + else {
939 + switch (ep_index(ep)) {
940 + case 1:
941 + usb_clearw(ep->dev, JZ_REG_UDC_INTROUTE, BIT(index));
942 + dev->out_mask &= ~BIT(index);
943 + break;
944 + default:
945 + DEBUG("Unknown endpoint: %d\n", index);
946 + break;
947 + }
948 + }
949 +}
950 +
951 +/*
952 + * nuke - dequeue ALL requests
953 + */
954 +static void nuke(struct jz4740_ep *ep, int status)
955 +{
956 + struct jz4740_request *req;
957 +
958 + DEBUG("%s, %p\n", __FUNCTION__, ep);
959 +
960 + /* Flush FIFO */
961 + flush(ep);
962 +
963 + /* called with irqs blocked */
964 + while (!list_empty(&ep->queue)) {
965 + req = list_entry(ep->queue.next, struct jz4740_request, queue);
966 + done(ep, req, status);
967 + }
968 +
969 + /* Disable IRQ if EP is enabled (has descriptor) */
970 + if (ep->desc)
971 + pio_irq_disable(ep);
972 +}
973 +
974 +/** Flush EP FIFO
975 + * NOTE: INDEX register must be set before this call
976 + */
977 +static void flush(struct jz4740_ep *ep)
978 +{
979 + DEBUG("%s: %s\n", __FUNCTION__, ep->ep.name);
980 +
981 + switch (ep->type) {
982 + case ep_bulk_in:
983 + case ep_interrupt:
984 + usb_setb(ep->dev, ep->csr, USB_INCSR_FF);
985 + break;
986 + case ep_bulk_out:
987 + usb_setb(ep->dev, ep->csr, USB_OUTCSR_FF);
988 + break;
989 + case ep_control:
990 + break;
991 + }
992 +}
993 +
994 +/**
995 + * jz4740_in_epn - handle IN interrupt
996 + */
997 +static void jz4740_in_epn(struct jz4740_udc *dev, uint32_t ep_idx, uint32_t intr)
998 +{
999 + uint32_t csr;
1000 + struct jz4740_ep *ep = &dev->ep[ep_idx + 1];
1001 + struct jz4740_request *req;
1002 + DEBUG("%s:%s[%d]\n", __FILE__, __func__, __LINE__);
1003 +
1004 + jz_udc_set_index(dev, ep_index(ep));
1005 +
1006 + csr = usb_readb(dev, ep->csr);
1007 + DEBUG("%s: %d, csr %x\n", __FUNCTION__, ep_idx, csr);
1008 +
1009 + if (csr & USB_INCSR_SENTSTALL) {
1010 + DEBUG("USB_INCSR_SENTSTALL\n");
1011 + usb_clearb(dev, ep->csr, USB_INCSR_SENTSTALL);
1012 + return;
1013 + }
1014 +
1015 + if (!ep->desc) {
1016 + DEBUG("%s: NO EP DESC\n", __FUNCTION__);
1017 + return;
1018 + }
1019 +
1020 + if (list_empty(&ep->queue))
1021 + req = 0;
1022 + else
1023 + req = list_entry(ep->queue.next, struct jz4740_request, queue);
1024 +
1025 + DEBUG("req: %p\n", req);
1026 +
1027 + if (!req)
1028 + return;
1029 +
1030 + write_fifo(ep, req);
1031 +}
1032 +
1033 +/*
1034 + * Bulk OUT (recv)
1035 + */
1036 +static void jz4740_out_epn(struct jz4740_udc *dev, uint32_t ep_idx, uint32_t intr)
1037 +{
1038 + struct jz4740_ep *ep = &dev->ep[ep_idx];
1039 + struct jz4740_request *req;
1040 +
1041 + DEBUG("%s: %d\n", __FUNCTION__, ep_idx);
1042 +
1043 + jz_udc_set_index(dev, ep_index(ep));
1044 + if (ep->desc) {
1045 + uint32_t csr;
1046 +
1047 + if (use_dma) {
1048 + /* DMA starts here ... */
1049 + if (list_empty(&ep->queue))
1050 + req = 0;
1051 + else
1052 + req = list_entry(ep->queue.next, struct jz4740_request, queue);
1053 +
1054 + if (req)
1055 + read_fifo(ep, req);
1056 + return;
1057 + }
1058 +
1059 + /*
1060 + * PIO mode starts here ...
1061 + */
1062 +
1063 + while ((csr = usb_readb(dev, ep->csr)) &
1064 + (USB_OUTCSR_OUTPKTRDY | USB_OUTCSR_SENTSTALL)) {
1065 + DEBUG("%s: %x\n", __FUNCTION__, csr);
1066 +
1067 + if (csr & USB_OUTCSR_SENTSTALL) {
1068 + DEBUG("%s: stall sent, flush fifo\n",
1069 + __FUNCTION__);
1070 + /* usb_set(USB_OUT_CSR1_FIFO_FLUSH, ep->csr1); */
1071 + flush(ep);
1072 + } else if (csr & USB_OUTCSR_OUTPKTRDY) {
1073 + if (list_empty(&ep->queue))
1074 + req = 0;
1075 + else
1076 + req =
1077 + list_entry(ep->queue.next,
1078 + struct jz4740_request,
1079 + queue);
1080 +
1081 + if (!req) {
1082 + DEBUG("%s: NULL REQ %d\n",
1083 + __FUNCTION__, ep_idx);
1084 + break;
1085 + } else {
1086 + read_fifo(ep, req);
1087 + }
1088 + }
1089 + }
1090 + } else {
1091 + /* Throw packet away.. */
1092 + DEBUG("%s: ep %p ep_indx %d No descriptor?!?\n", __FUNCTION__, ep, ep_idx);
1093 + flush(ep);
1094 + }
1095 +}
1096 +
1097 +/** Halt specific EP
1098 + * Return 0 if success
1099 + * NOTE: Sets INDEX register to EP !
1100 + */
1101 +static int jz4740_set_halt(struct usb_ep *_ep, int value)
1102 +{
1103 + struct jz4740_udc *dev;
1104 + struct jz4740_ep *ep;
1105 + unsigned long flags;
1106 +
1107 + DEBUG("%s:%s[%d]\n", __FILE__, __func__, __LINE__);
1108 +
1109 + ep = container_of(_ep, struct jz4740_ep, ep);
1110 + if (unlikely(!_ep || (!ep->desc && ep->type != ep_control))) {
1111 + DEBUG("%s, bad ep\n", __FUNCTION__);
1112 + return -EINVAL;
1113 + }
1114 +
1115 + dev = ep->dev;
1116 +
1117 + spin_lock_irqsave(&dev->lock, flags);
1118 +
1119 + jz_udc_select_ep(ep);
1120 +
1121 + DEBUG("%s, ep %d, val %d\n", __FUNCTION__, ep_index(ep), value);
1122 +
1123 + if (ep_index(ep) == 0) {
1124 + /* EP0 */
1125 + usb_setb(dev, JZ_REG_UDC_CSR0, USB_CSR0_SENDSTALL);
1126 + } else if (ep_is_in(ep)) {
1127 + uint32_t csr = usb_readb(dev, ep->csr);
1128 + if (value && ((csr & USB_INCSR_FFNOTEMPT)
1129 + || !list_empty(&ep->queue))) {
1130 + /*
1131 + * Attempts to halt IN endpoints will fail (returning -EAGAIN)
1132 + * if any transfer requests are still queued, or if the controller
1133 + * FIFO still holds bytes that the host hasn\92t collected.
1134 + */
1135 + spin_unlock_irqrestore(&dev->lock, flags);
1136 + DEBUG
1137 + ("Attempt to halt IN endpoint failed (returning -EAGAIN) %d %d\n",
1138 + (csr & USB_INCSR_FFNOTEMPT),
1139 + !list_empty(&ep->queue));
1140 + return -EAGAIN;
1141 + }
1142 + flush(ep);
1143 + if (value) {
1144 + usb_setb(dev, ep->csr, USB_INCSR_SENDSTALL);
1145 + }
1146 + else {
1147 + usb_clearb(dev, ep->csr, USB_INCSR_SENDSTALL);
1148 + usb_setb(dev, ep->csr, USB_INCSR_CDT);
1149 + }
1150 + } else {
1151 +
1152 + flush(ep);
1153 + if (value) {
1154 + usb_setb(dev, ep->csr, USB_OUTCSR_SENDSTALL);
1155 + }
1156 + else {
1157 + usb_clearb(dev, ep->csr, USB_OUTCSR_SENDSTALL);
1158 + usb_setb(dev, ep->csr, USB_OUTCSR_CDT);
1159 + }
1160 + }
1161 +
1162 + if (value) {
1163 + ep->stopped = 1;
1164 + } else {
1165 + ep->stopped = 0;
1166 + }
1167 +
1168 + spin_unlock_irqrestore(&dev->lock, flags);
1169 +
1170 + DEBUG("%s %s halted\n", _ep->name, value == 0 ? "NOT" : "IS");
1171 +
1172 + return 0;
1173 +}
1174 +
1175 +
1176 +static int jz4740_ep_enable(struct usb_ep *_ep,
1177 + const struct usb_endpoint_descriptor *desc)
1178 +{
1179 + struct jz4740_ep *ep;
1180 + struct jz4740_udc *dev;
1181 + unsigned long flags;
1182 + uint32_t max, csrh = 0;
1183 +
1184 + DEBUG("%s: trying to enable %s\n", __FUNCTION__, _ep->name);
1185 +
1186 + if (!_ep || !desc)
1187 + return -EINVAL;
1188 +
1189 + ep = container_of(_ep, struct jz4740_ep, ep);
1190 + if (ep->desc || ep->type == ep_control
1191 + || desc->bDescriptorType != USB_DT_ENDPOINT
1192 + || ep->bEndpointAddress != desc->bEndpointAddress) {
1193 + DEBUG("%s, bad ep or descriptor\n", __FUNCTION__);
1194 + return -EINVAL;
1195 + }
1196 +
1197 + /* xfer types must match, except that interrupt ~= bulk */
1198 + if (ep->bmAttributes != desc->bmAttributes
1199 + && ep->bmAttributes != USB_ENDPOINT_XFER_BULK
1200 + && desc->bmAttributes != USB_ENDPOINT_XFER_INT) {
1201 + DEBUG("%s, %s type mismatch\n", __FUNCTION__, _ep->name);
1202 + return -EINVAL;
1203 + }
1204 +
1205 + dev = ep->dev;
1206 + if (!dev->driver || dev->gadget.speed == USB_SPEED_UNKNOWN) {
1207 + DEBUG("%s, bogus device state\n", __FUNCTION__);
1208 + return -ESHUTDOWN;
1209 + }
1210 +
1211 + max = le16_to_cpu(desc->wMaxPacketSize);
1212 +
1213 + spin_lock_irqsave(&ep->dev->lock, flags);
1214 +
1215 + /* Configure the endpoint */
1216 + jz_udc_set_index(dev, desc->bEndpointAddress & 0x0F);
1217 + if (ep_is_in(ep)) {
1218 + usb_writew(dev, JZ_REG_UDC_INMAXP, max);
1219 + switch (desc->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK) {
1220 + case USB_ENDPOINT_XFER_BULK:
1221 + case USB_ENDPOINT_XFER_INT:
1222 + csrh &= ~USB_INCSRH_ISO;
1223 + break;
1224 + case USB_ENDPOINT_XFER_ISOC:
1225 + csrh |= USB_INCSRH_ISO;
1226 + break;
1227 + }
1228 + usb_writeb(dev, JZ_REG_UDC_INCSRH, csrh);
1229 + }
1230 + else {
1231 + usb_writew(dev, JZ_REG_UDC_OUTMAXP, max);
1232 + switch (desc->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK) {
1233 + case USB_ENDPOINT_XFER_BULK:
1234 + csrh &= ~USB_OUTCSRH_ISO;
1235 + break;
1236 + case USB_ENDPOINT_XFER_INT:
1237 + csrh &= ~USB_OUTCSRH_ISO;
1238 + csrh |= USB_OUTCSRH_DNYT;
1239 + break;
1240 + case USB_ENDPOINT_XFER_ISOC:
1241 + csrh |= USB_OUTCSRH_ISO;
1242 + break;
1243 + }
1244 + usb_writeb(dev, JZ_REG_UDC_OUTCSRH, csrh);
1245 + }
1246 +
1247 +
1248 + ep->stopped = 0;
1249 + ep->desc = desc;
1250 + ep->pio_irqs = 0;
1251 + ep->ep.maxpacket = max;
1252 +
1253 + spin_unlock_irqrestore(&ep->dev->lock, flags);
1254 +
1255 + /* Reset halt state (does flush) */
1256 + jz4740_set_halt(_ep, 0);
1257 +
1258 + DEBUG("%s: enabled %s\n", __FUNCTION__, _ep->name);
1259 +
1260 + return 0;
1261 +}
1262 +
1263 +/** Disable EP
1264 + * NOTE: Sets INDEX register
1265 + */
1266 +static int jz4740_ep_disable(struct usb_ep *_ep)
1267 +{
1268 + struct jz4740_ep *ep;
1269 + unsigned long flags;
1270 +
1271 + DEBUG("%s, %p\n", __FUNCTION__, _ep);
1272 +
1273 + ep = container_of(_ep, struct jz4740_ep, ep);
1274 + if (!_ep || !ep->desc) {
1275 + DEBUG("%s, %s not enabled\n", __FUNCTION__,
1276 + _ep ? ep->ep.name : NULL);
1277 + return -EINVAL;
1278 + }
1279 +
1280 + spin_lock_irqsave(&ep->dev->lock, flags);
1281 +
1282 + jz_udc_select_ep(ep);
1283 +
1284 + /* Nuke all pending requests (does flush) */
1285 + nuke(ep, -ESHUTDOWN);
1286 +
1287 + /* Disable ep IRQ */
1288 + pio_irq_disable(ep);
1289 +
1290 + ep->desc = 0;
1291 + ep->stopped = 1;
1292 +
1293 + spin_unlock_irqrestore(&ep->dev->lock, flags);
1294 +
1295 + DEBUG("%s: disabled %s\n", __FUNCTION__, _ep->name);
1296 + return 0;
1297 +}
1298 +
1299 +static struct usb_request *jz4740_alloc_request(struct usb_ep *ep, gfp_t gfp_flags)
1300 +{
1301 + struct jz4740_request *req;
1302 +
1303 + DEBUG("%s, %p\n", __FUNCTION__, ep);
1304 +
1305 + req = kzalloc(sizeof(*req), gfp_flags);
1306 + if (!req)
1307 + return 0;
1308 +
1309 + INIT_LIST_HEAD(&req->queue);
1310 +
1311 + return &req->req;
1312 +}
1313 +
1314 +static void jz4740_free_request(struct usb_ep *ep, struct usb_request *_req)
1315 +{
1316 + struct jz4740_request *req;
1317 +
1318 + DEBUG("%s, %p\n", __FUNCTION__, ep);
1319 +
1320 + req = container_of(_req, struct jz4740_request, req);
1321 + WARN_ON(!list_empty(&req->queue));
1322 + kfree(req);
1323 +}
1324 +
1325 +/*--------------------------------------------------------------------*/
1326 +
1327 +/** Queue one request
1328 + * Kickstart transfer if needed
1329 + * NOTE: Sets INDEX register
1330 + */
1331 +static int jz4740_queue(struct usb_ep *_ep, struct usb_request *_req,
1332 + gfp_t gfp_flags)
1333 +{
1334 + struct jz4740_request *req;
1335 + struct jz4740_ep *ep;
1336 + struct jz4740_udc *dev;
1337 +
1338 + DEBUG("%s, %p\n", __FUNCTION__, _ep);
1339 +
1340 + req = container_of(_req, struct jz4740_request, req);
1341 + if (unlikely
1342 + (!_req || !_req->complete || !_req->buf
1343 + || !list_empty(&req->queue))) {
1344 + DEBUG("%s, bad params\n", __FUNCTION__);
1345 + return -EINVAL;
1346 + }
1347 +
1348 + ep = container_of(_ep, struct jz4740_ep, ep);
1349 + if (unlikely(!_ep || (!ep->desc && ep->type != ep_control))) {
1350 + DEBUG("%s, bad ep\n", __FUNCTION__);
1351 + return -EINVAL;
1352 + }
1353 +
1354 + dev = ep->dev;
1355 + if (unlikely(!dev->driver || dev->gadget.speed == USB_SPEED_UNKNOWN)) {
1356 + DEBUG("%s, bogus device state %p\n", __FUNCTION__, dev->driver);
1357 + return -ESHUTDOWN;
1358 + }
1359 +
1360 + DEBUG("%s queue req %p, len %d buf %p\n", _ep->name, _req, _req->length,
1361 + _req->buf);
1362 +
1363 + spin_lock_irqsave(&dev->lock, dev->lock_flags);
1364 +
1365 + _req->status = -EINPROGRESS;
1366 + _req->actual = 0;
1367 +
1368 + /* kickstart this i/o queue? */
1369 + DEBUG("Add to %d Q %d %d\n", ep_index(ep), list_empty(&ep->queue),
1370 + ep->stopped);
1371 + if (list_empty(&ep->queue) && likely(!ep->stopped)) {
1372 + uint32_t csr;
1373 +
1374 + if (unlikely(ep_index(ep) == 0)) {
1375 + /* EP0 */
1376 + list_add_tail(&req->queue, &ep->queue);
1377 + jz4740_ep0_kick(dev, ep);
1378 + req = 0;
1379 + } else if (use_dma) {
1380 + /* DMA */
1381 + kick_dma(ep, req);
1382 + }
1383 + /* PIO */
1384 + else if (ep_is_in(ep)) {
1385 + /* EP1 & EP2 */
1386 + jz_udc_set_index(dev, ep_index(ep));
1387 + csr = usb_readb(dev, ep->csr);
1388 + pio_irq_enable(ep);
1389 + if (!(csr & USB_INCSR_FFNOTEMPT)) {
1390 + if (write_fifo(ep, req) == 1)
1391 + req = 0;
1392 + }
1393 + } else {
1394 + /* EP1 */
1395 + jz_udc_set_index(dev, ep_index(ep));
1396 + csr = usb_readb(dev, ep->csr);
1397 + pio_irq_enable(ep);
1398 + if (csr & USB_OUTCSR_OUTPKTRDY) {
1399 + if (read_fifo(ep, req) == 1)
1400 + req = 0;
1401 + }
1402 + }
1403 + }
1404 +
1405 + /* pio or dma irq handler advances the queue. */
1406 + if (likely(req != 0))
1407 + list_add_tail(&req->queue, &ep->queue);
1408 +
1409 + spin_unlock_irqrestore(&dev->lock, dev->lock_flags);
1410 +
1411 + return 0;
1412 +}
1413 +
1414 +/* dequeue JUST ONE request */
1415 +static int jz4740_dequeue(struct usb_ep *_ep, struct usb_request *_req)
1416 +{
1417 + struct jz4740_ep *ep;
1418 + struct jz4740_request *req;
1419 + unsigned long flags;
1420 +
1421 + DEBUG("%s, %p\n", __FUNCTION__, _ep);
1422 +
1423 + ep = container_of(_ep, struct jz4740_ep, ep);
1424 + if (!_ep || ep->type == ep_control)
1425 + return -EINVAL;
1426 +
1427 + spin_lock_irqsave(&ep->dev->lock, flags);
1428 +
1429 + /* make sure it's actually queued on this endpoint */
1430 + list_for_each_entry(req, &ep->queue, queue) {
1431 + if (&req->req == _req)
1432 + break;
1433 + }
1434 + if (&req->req != _req) {
1435 + spin_unlock_irqrestore(&ep->dev->lock, flags);
1436 + return -EINVAL;
1437 + }
1438 + done(ep, req, -ECONNRESET);
1439 +
1440 + spin_unlock_irqrestore(&ep->dev->lock, flags);
1441 + return 0;
1442 +}
1443 +
1444 +/** Return bytes in EP FIFO
1445 + * NOTE: Sets INDEX register to EP
1446 + */
1447 +static int jz4740_fifo_status(struct usb_ep *_ep)
1448 +{
1449 + uint32_t csr;
1450 + int count = 0;
1451 + struct jz4740_ep *ep;
1452 + unsigned long flags;
1453 +
1454 + ep = container_of(_ep, struct jz4740_ep, ep);
1455 + if (!_ep) {
1456 + DEBUG("%s, bad ep\n", __FUNCTION__);
1457 + return -ENODEV;
1458 + }
1459 +
1460 + DEBUG("%s, %d\n", __FUNCTION__, ep_index(ep));
1461 +
1462 + /* LPD can't report unclaimed bytes from IN fifos */
1463 + if (ep_is_in(ep))
1464 + return -EOPNOTSUPP;
1465 +
1466 + spin_lock_irqsave(&ep->dev->lock, flags);
1467 + jz_udc_set_index(ep->dev, ep_index(ep));
1468 +
1469 + csr = usb_readb(ep->dev, ep->csr);
1470 + if (ep->dev->gadget.speed != USB_SPEED_UNKNOWN ||
1471 + csr & 0x1) {
1472 + count = usb_readw(ep->dev, JZ_REG_UDC_OUTCOUNT);
1473 + }
1474 +
1475 + spin_unlock_irqrestore(&ep->dev->lock, flags);
1476 +
1477 + return count;
1478 +}
1479 +
1480 +/** Flush EP FIFO
1481 + * NOTE: Sets INDEX register to EP
1482 + */
1483 +static void jz4740_fifo_flush(struct usb_ep *_ep)
1484 +{
1485 + struct jz4740_ep *ep;
1486 + unsigned long flags;
1487 +
1488 + DEBUG("%s:%s[%d]\n", __FILE__, __func__, __LINE__);
1489 +
1490 + ep = container_of(_ep, struct jz4740_ep, ep);
1491 + if (unlikely(!_ep || (!ep->desc && ep->type == ep_control))) {
1492 + DEBUG("%s, bad ep\n", __FUNCTION__);
1493 + return;
1494 + }
1495 +
1496 + spin_lock_irqsave(&ep->dev->lock, flags);
1497 +
1498 + jz_udc_set_index(ep->dev, ep_index(ep));
1499 + flush(ep);
1500 +
1501 + spin_unlock_irqrestore(&ep->dev->lock, flags);
1502 +}
1503 +
1504 +/****************************************************************/
1505 +/* End Point 0 related functions */
1506 +/****************************************************************/
1507 +
1508 +/* return: 0 = still running, 1 = completed, negative = errno */
1509 +static int write_fifo_ep0(struct jz4740_ep *ep, struct jz4740_request *req)
1510 +{
1511 + uint32_t max;
1512 + unsigned count;
1513 + int is_last;
1514 +
1515 + DEBUG("%s:%s[%d]\n", __FILE__, __func__, __LINE__);
1516 + max = ep_maxpacket(ep);
1517 +
1518 + count = write_packet(ep, req, max);
1519 +
1520 + /* last packet is usually short (or a zlp) */
1521 + if (unlikely(count != max))
1522 + is_last = 1;
1523 + else {
1524 + if (likely(req->req.length != req->req.actual) || req->req.zero)
1525 + is_last = 0;
1526 + else
1527 + is_last = 1;
1528 + }
1529 +
1530 + DEBUG_EP0("%s: wrote %s %d bytes%s %d left %p\n", __FUNCTION__,
1531 + ep->ep.name, count,
1532 + is_last ? "/L" : "", req->req.length - req->req.actual, req);
1533 +
1534 + /* requests complete when all IN data is in the FIFO */
1535 + if (is_last) {
1536 + done(ep, req, 0);
1537 + return 1;
1538 + }
1539 +
1540 + return 0;
1541 +}
1542 +
1543 +static inline int jz4740_fifo_read(struct jz4740_ep *ep,
1544 + unsigned char *cp, int max)
1545 +{
1546 + int bytes;
1547 + int count = usb_readw(ep->dev, JZ_REG_UDC_OUTCOUNT);
1548 +
1549 + if (count > max)
1550 + count = max;
1551 + bytes = count;
1552 + while (count--)
1553 + *cp++ = usb_readb(ep->dev, ep->fifo);
1554 +
1555 + return bytes;
1556 +}
1557 +
1558 +static inline void jz4740_fifo_write(struct jz4740_ep *ep,
1559 + unsigned char *cp, int count)
1560 +{
1561 + DEBUG("fifo_write: %d %d\n", ep_index(ep), count);
1562 + while (count--)
1563 + usb_writeb(ep->dev, ep->fifo, *cp++);
1564 +}
1565 +
1566 +static int read_fifo_ep0(struct jz4740_ep *ep, struct jz4740_request *req)
1567 +{
1568 + struct jz4740_udc *dev = ep->dev;
1569 + uint32_t csr;
1570 + uint8_t *buf;
1571 + unsigned bufferspace, count, is_short;
1572 +
1573 + DEBUG_EP0("%s\n", __FUNCTION__);
1574 +
1575 + csr = usb_readb(dev, JZ_REG_UDC_CSR0);
1576 + if (!(csr & USB_CSR0_OUTPKTRDY))
1577 + return 0;
1578 +
1579 + buf = req->req.buf + req->req.actual;
1580 + prefetchw(buf);
1581 + bufferspace = req->req.length - req->req.actual;
1582 +
1583 + /* read all bytes from this packet */
1584 + if (likely(csr & USB_CSR0_OUTPKTRDY)) {
1585 + count = usb_readw(dev, JZ_REG_UDC_OUTCOUNT);
1586 + req->req.actual += min(count, bufferspace);
1587 + } else /* zlp */
1588 + count = 0;
1589 +
1590 + is_short = (count < ep->ep.maxpacket);
1591 + DEBUG_EP0("read %s %02x, %d bytes%s req %p %d/%d\n",
1592 + ep->ep.name, csr, count,
1593 + is_short ? "/S" : "", req, req->req.actual, req->req.length);
1594 +
1595 + while (likely(count-- != 0)) {
1596 + uint8_t byte = (uint8_t)usb_readl(dev, ep->fifo);
1597 +
1598 + if (unlikely(bufferspace == 0)) {
1599 + /* this happens when the driver's buffer
1600 + * is smaller than what the host sent.
1601 + * discard the extra data.
1602 + */
1603 + if (req->req.status != -EOVERFLOW)
1604 + DEBUG_EP0("%s overflow %d\n", ep->ep.name,
1605 + count);
1606 + req->req.status = -EOVERFLOW;
1607 + } else {
1608 + *buf++ = byte;
1609 + bufferspace--;
1610 + }
1611 + }
1612 +
1613 + /* completion */
1614 + if (is_short || req->req.actual == req->req.length) {
1615 + done(ep, req, 0);
1616 + return 1;
1617 + }
1618 +
1619 + /* finished that packet. the next one may be waiting... */
1620 + return 0;
1621 +}
1622 +
1623 +/**
1624 + * udc_set_address - set the USB address for this device
1625 + * @address:
1626 + *
1627 + * Called from control endpoint function after it decodes a set address setup packet.
1628 + */
1629 +static void udc_set_address(struct jz4740_udc *dev, unsigned char address)
1630 +{
1631 + DEBUG_EP0("%s: %d\n", __FUNCTION__, address);
1632 +
1633 + dev->usb_address = address;
1634 + usb_writeb(dev, JZ_REG_UDC_FADDR, address);
1635 +}
1636 +
1637 +/*
1638 + * DATA_STATE_RECV (USB_CSR0_OUTPKTRDY)
1639 + * - if error
1640 + * set USB_CSR0_SVDOUTPKTRDY | USB_CSR0_DATAEND | USB_CSR0_SENDSTALL bits
1641 + * - else
1642 + * set USB_CSR0_SVDOUTPKTRDY bit
1643 + if last set USB_CSR0_DATAEND bit
1644 + */
1645 +static void jz4740_ep0_out(struct jz4740_udc *dev, uint32_t csr, int kickstart)
1646 +{
1647 + struct jz4740_request *req;
1648 + struct jz4740_ep *ep = &dev->ep[0];
1649 + int ret;
1650 +
1651 + DEBUG_EP0("%s: %x\n", __FUNCTION__, csr);
1652 +
1653 + if (list_empty(&ep->queue))
1654 + req = 0;
1655 + else
1656 + req = list_entry(ep->queue.next, struct jz4740_request, queue);
1657 +
1658 + if (req) {
1659 + if (req->req.length == 0) {
1660 + DEBUG_EP0("ZERO LENGTH OUT!\n");
1661 + usb_setb(dev, JZ_REG_UDC_CSR0, (USB_CSR0_SVDOUTPKTRDY | USB_CSR0_DATAEND));
1662 + dev->ep0state = WAIT_FOR_SETUP;
1663 + return;
1664 + } else if (kickstart) {
1665 + usb_setb(dev, JZ_REG_UDC_CSR0, (USB_CSR0_SVDOUTPKTRDY));
1666 + return;
1667 + }
1668 + ret = read_fifo_ep0(ep, req);
1669 + if (ret) {
1670 + /* Done! */
1671 + DEBUG_EP0("%s: finished, waiting for status\n",
1672 + __FUNCTION__);
1673 + usb_setb(dev, JZ_REG_UDC_CSR0, (USB_CSR0_SVDOUTPKTRDY | USB_CSR0_DATAEND));
1674 + dev->ep0state = WAIT_FOR_SETUP;
1675 + } else {
1676 + /* Not done yet.. */
1677 + DEBUG_EP0("%s: not finished\n", __FUNCTION__);
1678 + usb_setb(dev, JZ_REG_UDC_CSR0, USB_CSR0_SVDOUTPKTRDY);
1679 + }
1680 + } else {
1681 + DEBUG_EP0("NO REQ??!\n");
1682 + }
1683 +}
1684 +
1685 +/*
1686 + * DATA_STATE_XMIT
1687 + */
1688 +static int jz4740_ep0_in(struct jz4740_udc *dev, uint32_t csr)
1689 +{
1690 + struct jz4740_request *req;
1691 + struct jz4740_ep *ep = &dev->ep[0];
1692 + int ret, need_zlp = 0;
1693 +
1694 + DEBUG_EP0("%s: %x\n", __FUNCTION__, csr);
1695 +
1696 + if (list_empty(&ep->queue))
1697 + req = 0;
1698 + else
1699 + req = list_entry(ep->queue.next, struct jz4740_request, queue);
1700 +
1701 + if (!req) {
1702 + DEBUG_EP0("%s: NULL REQ\n", __FUNCTION__);
1703 + return 0;
1704 + }
1705 +
1706 + if (req->req.length == 0) {
1707 + usb_setb(dev, JZ_REG_UDC_CSR0, (USB_CSR0_INPKTRDY | USB_CSR0_DATAEND));
1708 + dev->ep0state = WAIT_FOR_SETUP;
1709 + return 1;
1710 + }
1711 +
1712 + if (req->req.length - req->req.actual == EP0_MAXPACKETSIZE) {
1713 + /* Next write will end with the packet size, */
1714 + /* so we need zero-length-packet */
1715 + need_zlp = 1;
1716 + }
1717 +
1718 + ret = write_fifo_ep0(ep, req);
1719 +
1720 + if (ret == 1 && !need_zlp) {
1721 + /* Last packet */
1722 + DEBUG_EP0("%s: finished, waiting for status\n", __FUNCTION__);
1723 +
1724 + usb_setb(dev, JZ_REG_UDC_CSR0, (USB_CSR0_INPKTRDY | USB_CSR0_DATAEND));
1725 + dev->ep0state = WAIT_FOR_SETUP;
1726 + } else {
1727 + DEBUG_EP0("%s: not finished\n", __FUNCTION__);
1728 + usb_setb(dev, JZ_REG_UDC_CSR0, USB_CSR0_INPKTRDY);
1729 + }
1730 +
1731 + if (need_zlp) {
1732 + DEBUG_EP0("%s: Need ZLP!\n", __FUNCTION__);
1733 + usb_setb(dev, JZ_REG_UDC_CSR0, USB_CSR0_INPKTRDY);
1734 + dev->ep0state = DATA_STATE_NEED_ZLP;
1735 + }
1736 +
1737 + return 1;
1738 +}
1739 +
1740 +static int jz4740_handle_get_status(struct jz4740_udc *dev,
1741 + struct usb_ctrlrequest *ctrl)
1742 +{
1743 + struct jz4740_ep *ep0 = &dev->ep[0];
1744 + struct jz4740_ep *qep;
1745 + int reqtype = (ctrl->bRequestType & USB_RECIP_MASK);
1746 + uint16_t val = 0;
1747 +
1748 + DEBUG("%s:%s[%d]\n", __FILE__, __func__, __LINE__);
1749 +
1750 + if (reqtype == USB_RECIP_INTERFACE) {
1751 + /* This is not supported.
1752 + * And according to the USB spec, this one does nothing..
1753 + * Just return 0
1754 + */
1755 + DEBUG_SETUP("GET_STATUS: USB_RECIP_INTERFACE\n");
1756 + } else if (reqtype == USB_RECIP_DEVICE) {
1757 + DEBUG_SETUP("GET_STATUS: USB_RECIP_DEVICE\n");
1758 + val |= (1 << 0); /* Self powered */
1759 + /*val |= (1<<1); *//* Remote wakeup */
1760 + } else if (reqtype == USB_RECIP_ENDPOINT) {
1761 + int ep_num = (ctrl->wIndex & ~USB_DIR_IN);
1762 +
1763 + DEBUG_SETUP
1764 + ("GET_STATUS: USB_RECIP_ENDPOINT (%d), ctrl->wLength = %d\n",
1765 + ep_num, ctrl->wLength);
1766 +
1767 + if (ctrl->wLength > 2 || ep_num > 3)
1768 + return -EOPNOTSUPP;
1769 +
1770 + qep = &dev->ep[ep_num];
1771 + if (ep_is_in(qep) != ((ctrl->wIndex & USB_DIR_IN) ? 1 : 0)
1772 + && ep_index(qep) != 0) {
1773 + return -EOPNOTSUPP;
1774 + }
1775 +
1776 + jz_udc_set_index(dev, ep_index(qep));
1777 +
1778 + /* Return status on next IN token */
1779 + switch (qep->type) {
1780 + case ep_control:
1781 + val =
1782 + (usb_readb(dev, qep->csr) & USB_CSR0_SENDSTALL) ==
1783 + USB_CSR0_SENDSTALL;
1784 + break;
1785 + case ep_bulk_in:
1786 + case ep_interrupt:
1787 + val =
1788 + (usb_readb(dev, qep->csr) & USB_INCSR_SENDSTALL) ==
1789 + USB_INCSR_SENDSTALL;
1790 + break;
1791 + case ep_bulk_out:
1792 + val =
1793 + (usb_readb(dev, qep->csr) & USB_OUTCSR_SENDSTALL) ==
1794 + USB_OUTCSR_SENDSTALL;
1795 + break;
1796 + }
1797 +
1798 + /* Back to EP0 index */
1799 + jz_udc_set_index(dev, 0);
1800 +
1801 + DEBUG_SETUP("GET_STATUS, ep: %d (%x), val = %d\n", ep_num,
1802 + ctrl->wIndex, val);
1803 + } else {
1804 + DEBUG_SETUP("Unknown REQ TYPE: %d\n", reqtype);
1805 + return -EOPNOTSUPP;
1806 + }
1807 +
1808 + /* Clear "out packet ready" */
1809 + usb_setb(dev, JZ_REG_UDC_CSR0, USB_CSR0_SVDOUTPKTRDY);
1810 + /* Put status to FIFO */
1811 + jz4740_fifo_write(ep0, (uint8_t *)&val, sizeof(val));
1812 + /* Issue "In packet ready" */
1813 + usb_setb(dev, JZ_REG_UDC_CSR0, (USB_CSR0_INPKTRDY | USB_CSR0_DATAEND));
1814 +
1815 + return 0;
1816 +}
1817 +
1818 +/*
1819 + * WAIT_FOR_SETUP (OUTPKTRDY)
1820 + * - read data packet from EP0 FIFO
1821 + * - decode command
1822 + * - if error
1823 + * set USB_CSR0_SVDOUTPKTRDY | USB_CSR0_DATAEND | USB_CSR0_SENDSTALL bits
1824 + * - else
1825 + * set USB_CSR0_SVDOUTPKTRDY | USB_CSR0_DATAEND bits
1826 + */
1827 +static void jz4740_ep0_setup(struct jz4740_udc *dev, uint32_t csr)
1828 +{
1829 + struct jz4740_ep *ep = &dev->ep[0];
1830 + struct usb_ctrlrequest ctrl;
1831 + int i;
1832 +
1833 + DEBUG_SETUP("%s: %x\n", __FUNCTION__, csr);
1834 +
1835 + /* Nuke all previous transfers */
1836 + nuke(ep, -EPROTO);
1837 +
1838 + /* read control req from fifo (8 bytes) */
1839 + jz4740_fifo_read(ep, (unsigned char *)&ctrl, 8);
1840 +
1841 + DEBUG_SETUP("SETUP %02x.%02x v%04x i%04x l%04x\n",
1842 + ctrl.bRequestType, ctrl.bRequest,
1843 + ctrl.wValue, ctrl.wIndex, ctrl.wLength);
1844 +
1845 + /* Set direction of EP0 */
1846 + if (likely(ctrl.bRequestType & USB_DIR_IN)) {
1847 + ep->bEndpointAddress |= USB_DIR_IN;
1848 + } else {
1849 + ep->bEndpointAddress &= ~USB_DIR_IN;
1850 + }
1851 +
1852 + /* Handle some SETUP packets ourselves */
1853 + switch (ctrl.bRequest) {
1854 + case USB_REQ_SET_ADDRESS:
1855 + if (ctrl.bRequestType != (USB_TYPE_STANDARD | USB_RECIP_DEVICE))
1856 + break;
1857 +
1858 + DEBUG_SETUP("USB_REQ_SET_ADDRESS (%d)\n", ctrl.wValue);
1859 + udc_set_address(dev, ctrl.wValue);
1860 + usb_setb(dev, JZ_REG_UDC_CSR0, (USB_CSR0_SVDOUTPKTRDY | USB_CSR0_DATAEND));
1861 + return;
1862 +
1863 + case USB_REQ_SET_CONFIGURATION:
1864 + if (ctrl.bRequestType != (USB_TYPE_STANDARD | USB_RECIP_DEVICE))
1865 + break;
1866 +
1867 + DEBUG_SETUP("USB_REQ_SET_CONFIGURATION (%d)\n", ctrl.wValue);
1868 +/* usb_setb(JZ_REG_UDC_CSR0, (USB_CSR0_SVDOUTPKTRDY | USB_CSR0_DATAEND));*/
1869 +
1870 + /* Enable RESUME and SUSPEND interrupts */
1871 + usb_setb(dev, JZ_REG_UDC_INTRUSBE, (USB_INTR_RESUME | USB_INTR_SUSPEND));
1872 + break;
1873 +
1874 + case USB_REQ_SET_INTERFACE:
1875 + if (ctrl.bRequestType != (USB_TYPE_STANDARD | USB_RECIP_DEVICE))
1876 + break;
1877 +
1878 + DEBUG_SETUP("USB_REQ_SET_INTERFACE (%d)\n", ctrl.wValue);
1879 +/* usb_setb(JZ_REG_UDC_CSR0, (USB_CSR0_SVDOUTPKTRDY | USB_CSR0_DATAEND));*/
1880 + break;
1881 +
1882 + case USB_REQ_GET_STATUS:
1883 + if (jz4740_handle_get_status(dev, &ctrl) == 0)
1884 + return;
1885 +
1886 + case USB_REQ_CLEAR_FEATURE:
1887 + case USB_REQ_SET_FEATURE:
1888 + if (ctrl.bRequestType == USB_RECIP_ENDPOINT) {
1889 + struct jz4740_ep *qep;
1890 + int ep_num = (ctrl.wIndex & 0x0f);
1891 +
1892 + /* Support only HALT feature */
1893 + if (ctrl.wValue != 0 || ctrl.wLength != 0
1894 + || ep_num > 3 || ep_num < 1)
1895 + break;
1896 +
1897 + qep = &dev->ep[ep_num];
1898 + spin_unlock(&dev->lock);
1899 + if (ctrl.bRequest == USB_REQ_SET_FEATURE) {
1900 + DEBUG_SETUP("SET_FEATURE (%d)\n",
1901 + ep_num);
1902 + jz4740_set_halt(&qep->ep, 1);
1903 + } else {
1904 + DEBUG_SETUP("CLR_FEATURE (%d)\n",
1905 + ep_num);
1906 + jz4740_set_halt(&qep->ep, 0);
1907 + }
1908 + spin_lock(&dev->lock);
1909 +
1910 + jz_udc_set_index(dev, 0);
1911 +
1912 + /* Reply with a ZLP on next IN token */
1913 + usb_setb(dev, JZ_REG_UDC_CSR0,
1914 + (USB_CSR0_SVDOUTPKTRDY | USB_CSR0_DATAEND));
1915 + return;
1916 + }
1917 + break;
1918 +
1919 + default:
1920 + break;
1921 + }
1922 +
1923 + /* gadget drivers see class/vendor specific requests,
1924 + * {SET,GET}_{INTERFACE,DESCRIPTOR,CONFIGURATION},
1925 + * and more.
1926 + */
1927 + if (dev->driver) {
1928 + /* device-2-host (IN) or no data setup command, process immediately */
1929 + spin_unlock(&dev->lock);
1930 +
1931 + i = dev->driver->setup(&dev->gadget, &ctrl);
1932 + spin_lock(&dev->lock);
1933 +
1934 + if (unlikely(i < 0)) {
1935 + /* setup processing failed, force stall */
1936 + DEBUG_SETUP
1937 + (" --> ERROR: gadget setup FAILED (stalling), setup returned %d\n",
1938 + i);
1939 + jz_udc_set_index(dev, 0);
1940 + usb_setb(dev, JZ_REG_UDC_CSR0, (USB_CSR0_SVDOUTPKTRDY | USB_CSR0_DATAEND | USB_CSR0_SENDSTALL));
1941 +
1942 + /* ep->stopped = 1; */
1943 + dev->ep0state = WAIT_FOR_SETUP;
1944 + }
1945 + else {
1946 + DEBUG_SETUP("gadget driver setup ok (%d)\n", ctrl.wLength);
1947 +/* if (!ctrl.wLength) {
1948 + usb_setb(JZ_REG_UDC_CSR0, USB_CSR0_SVDOUTPKTRDY);
1949 + }*/
1950 + }
1951 + }
1952 +}
1953 +
1954 +/*
1955 + * DATA_STATE_NEED_ZLP
1956 + */
1957 +static void jz4740_ep0_in_zlp(struct jz4740_udc *dev, uint32_t csr)
1958 +{
1959 + DEBUG_EP0("%s: %x\n", __FUNCTION__, csr);
1960 +
1961 + usb_setb(dev, JZ_REG_UDC_CSR0, (USB_CSR0_INPKTRDY | USB_CSR0_DATAEND));
1962 + dev->ep0state = WAIT_FOR_SETUP;
1963 +}
1964 +
1965 +/*
1966 + * handle ep0 interrupt
1967 + */
1968 +static void jz4740_handle_ep0(struct jz4740_udc *dev, uint32_t intr)
1969 +{
1970 + struct jz4740_ep *ep = &dev->ep[0];
1971 + uint32_t csr;
1972 +
1973 + DEBUG("%s:%s[%d]\n", __FILE__, __func__, __LINE__);
1974 + /* Set index 0 */
1975 + jz_udc_set_index(dev, 0);
1976 + csr = usb_readb(dev, JZ_REG_UDC_CSR0);
1977 +
1978 + DEBUG_EP0("%s: csr = %x state = \n", __FUNCTION__, csr);//, state_names[dev->ep0state]);
1979 +
1980 + /*
1981 + * if SENT_STALL is set
1982 + * - clear the SENT_STALL bit
1983 + */
1984 + if (csr & USB_CSR0_SENTSTALL) {
1985 + DEBUG_EP0("%s: USB_CSR0_SENTSTALL is set: %x\n", __FUNCTION__, csr);
1986 + usb_clearb(dev, JZ_REG_UDC_CSR0, USB_CSR0_SENDSTALL | USB_CSR0_SENTSTALL);
1987 + nuke(ep, -ECONNABORTED);
1988 + dev->ep0state = WAIT_FOR_SETUP;
1989 + return;
1990 + }
1991 +
1992 + /*
1993 + * if a transfer is in progress && INPKTRDY and OUTPKTRDY are clear
1994 + * - fill EP0 FIFO
1995 + * - if last packet
1996 + * - set IN_PKT_RDY | DATA_END
1997 + * - else
1998 + * set IN_PKT_RDY
1999 + */
2000 + if (!(csr & (USB_CSR0_INPKTRDY | USB_CSR0_OUTPKTRDY))) {
2001 + DEBUG_EP0("%s: INPKTRDY and OUTPKTRDY are clear\n",
2002 + __FUNCTION__);
2003 +
2004 + switch (dev->ep0state) {
2005 + case DATA_STATE_XMIT:
2006 + DEBUG_EP0("continue with DATA_STATE_XMIT\n");
2007 + jz4740_ep0_in(dev, csr);
2008 + return;
2009 + case DATA_STATE_NEED_ZLP:
2010 + DEBUG_EP0("continue with DATA_STATE_NEED_ZLP\n");
2011 + jz4740_ep0_in_zlp(dev, csr);
2012 + return;
2013 + default:
2014 + /* Stall? */
2015 +// DEBUG_EP0("Odd state!! state = %s\n",
2016 +// state_names[dev->ep0state]);
2017 + dev->ep0state = WAIT_FOR_SETUP;
2018 + /* nuke(ep, 0); */
2019 + /* usb_setb(ep->csr, USB_CSR0_SENDSTALL); */
2020 +// break;
2021 + return;
2022 + }
2023 + }
2024 +
2025 + /*
2026 + * if SETUPEND is set
2027 + * - abort the last transfer
2028 + * - set SERVICED_SETUP_END_BIT
2029 + */
2030 + if (csr & USB_CSR0_SETUPEND) {
2031 + DEBUG_EP0("%s: USB_CSR0_SETUPEND is set: %x\n", __FUNCTION__, csr);
2032 +
2033 + usb_setb(dev, JZ_REG_UDC_CSR0, USB_CSR0_SVDSETUPEND);
2034 + nuke(ep, 0);
2035 + dev->ep0state = WAIT_FOR_SETUP;
2036 + }
2037 +
2038 + /*
2039 + * if USB_CSR0_OUTPKTRDY is set
2040 + * - read data packet from EP0 FIFO
2041 + * - decode command
2042 + * - if error
2043 + * set SVDOUTPKTRDY | DATAEND | SENDSTALL bits
2044 + * - else
2045 + * set SVDOUTPKTRDY | DATAEND bits
2046 + */
2047 + if (csr & USB_CSR0_OUTPKTRDY) {
2048 +
2049 + DEBUG_EP0("%s: EP0_OUT_PKT_RDY is set: %x\n", __FUNCTION__,
2050 + csr);
2051 +
2052 + switch (dev->ep0state) {
2053 + case WAIT_FOR_SETUP:
2054 + DEBUG_EP0("WAIT_FOR_SETUP\n");
2055 + jz4740_ep0_setup(dev, csr);
2056 + break;
2057 +
2058 + case DATA_STATE_RECV:
2059 + DEBUG_EP0("DATA_STATE_RECV\n");
2060 + jz4740_ep0_out(dev, csr, 0);
2061 + break;
2062 +
2063 + default:
2064 + /* send stall? */
2065 + DEBUG_EP0("strange state!! 2. send stall? state = %d\n",
2066 + dev->ep0state);
2067 + break;
2068 + }
2069 + }
2070 +}
2071 +
2072 +static void jz4740_ep0_kick(struct jz4740_udc *dev, struct jz4740_ep *ep)
2073 +{
2074 + uint32_t csr;
2075 +
2076 + jz_udc_set_index(dev, 0);
2077 +
2078 + DEBUG_EP0("%s: %x\n", __FUNCTION__, csr);
2079 +
2080 + /* Clear "out packet ready" */
2081 +
2082 + if (ep_is_in(ep)) {
2083 + usb_setb(dev, JZ_REG_UDC_CSR0, USB_CSR0_SVDOUTPKTRDY);
2084 + csr = usb_readb(dev, JZ_REG_UDC_CSR0);
2085 + dev->ep0state = DATA_STATE_XMIT;
2086 + jz4740_ep0_in(dev, csr);
2087 + } else {
2088 + csr = usb_readb(dev, JZ_REG_UDC_CSR0);
2089 + dev->ep0state = DATA_STATE_RECV;
2090 + jz4740_ep0_out(dev, csr, 1);
2091 + }
2092 +}
2093 +
2094 +/** Handle USB RESET interrupt
2095 + */
2096 +static void jz4740_reset_irq(struct jz4740_udc *dev)
2097 +{
2098 + dev->gadget.speed = (usb_readb(dev, JZ_REG_UDC_POWER) & USB_POWER_HSMODE) ?
2099 + USB_SPEED_HIGH : USB_SPEED_FULL;
2100 +
2101 + DEBUG_SETUP("%s: address = %d, speed = %s\n", __FUNCTION__, dev->usb_address,
2102 + (dev->gadget.speed == USB_SPEED_HIGH) ? "HIGH":"FULL" );
2103 +}
2104 +
2105 +/*
2106 + * jz4740 usb device interrupt handler.
2107 + */
2108 +static irqreturn_t jz4740_udc_irq(int irq, void *_dev)
2109 +{
2110 + struct jz4740_udc *dev = _dev;
2111 + uint8_t index;
2112 +
2113 + uint32_t intr_usb = usb_readb(dev, JZ_REG_UDC_INTRUSB) & 0x7; /* mask SOF */
2114 + uint32_t intr_in = usb_readw(dev, JZ_REG_UDC_INTRIN);
2115 + uint32_t intr_out = usb_readw(dev, JZ_REG_UDC_INTROUT);
2116 + uint32_t intr_dma = usb_readb(dev, JZ_REG_UDC_INTR);
2117 +
2118 + if (!intr_usb && !intr_in && !intr_out && !intr_dma)
2119 + return IRQ_HANDLED;
2120 +
2121 +
2122 + DEBUG("intr_out=%x intr_in=%x intr_usb=%x\n",
2123 + intr_out, intr_in, intr_usb);
2124 +
2125 + spin_lock(&dev->lock);
2126 + index = usb_readb(dev, JZ_REG_UDC_INDEX);
2127 +
2128 + /* Check for resume from suspend mode */
2129 + if ((intr_usb & USB_INTR_RESUME) &&
2130 + (usb_readb(dev, JZ_REG_UDC_INTRUSBE) & USB_INTR_RESUME)) {
2131 + DEBUG("USB resume\n");
2132 + dev->driver->resume(&dev->gadget); /* We have suspend(), so we must have resume() too. */
2133 + }
2134 +
2135 + /* Check for system interrupts */
2136 + if (intr_usb & USB_INTR_RESET) {
2137 + DEBUG("USB reset\n");
2138 + jz4740_reset_irq(dev);
2139 + }
2140 +
2141 + /* Check for endpoint 0 interrupt */
2142 + if (intr_in & USB_INTR_EP0) {
2143 + DEBUG("USB_INTR_EP0 (control)\n");
2144 + jz4740_handle_ep0(dev, intr_in);
2145 + }
2146 +
2147 + /* Check for Bulk-IN DMA interrupt */
2148 + if (intr_dma & 0x1) {
2149 + int ep_num;
2150 + struct jz4740_ep *ep;
2151 + ep_num = (usb_readl(dev, JZ_REG_UDC_CNTL1) >> 4) & 0xf;
2152 + ep = &dev->ep[ep_num + 1];
2153 + jz_udc_set_index(dev, ep_num);
2154 + usb_setb(dev, ep->csr, USB_INCSR_INPKTRDY);
2155 +/* jz4740_in_epn(dev, ep_num, intr_in);*/
2156 + }
2157 +
2158 + /* Check for Bulk-OUT DMA interrupt */
2159 + if (intr_dma & 0x2) {
2160 + int ep_num;
2161 + ep_num = (usb_readl(dev, JZ_REG_UDC_CNTL2) >> 4) & 0xf;
2162 + jz4740_out_epn(dev, ep_num, intr_out);
2163 + }
2164 +
2165 + /* Check for each configured endpoint interrupt */
2166 + if (intr_in & USB_INTR_INEP1) {
2167 + DEBUG("USB_INTR_INEP1\n");
2168 + jz4740_in_epn(dev, 1, intr_in);
2169 + }
2170 +
2171 + if (intr_in & USB_INTR_INEP2) {
2172 + DEBUG("USB_INTR_INEP2\n");
2173 + jz4740_in_epn(dev, 2, intr_in);
2174 + }
2175 +
2176 + if (intr_out & USB_INTR_OUTEP1) {
2177 + DEBUG("USB_INTR_OUTEP1\n");
2178 + jz4740_out_epn(dev, 1, intr_out);
2179 + }
2180 +
2181 + /* Check for suspend mode */
2182 + if ((intr_usb & USB_INTR_SUSPEND) &&
2183 + (usb_readb(dev, JZ_REG_UDC_INTRUSBE) & USB_INTR_SUSPEND)) {
2184 + DEBUG("USB suspend\n");
2185 + dev->driver->suspend(&dev->gadget);
2186 + /* Host unloaded from us, can do something, such as flushing
2187 + the NAND block cache etc. */
2188 + }
2189 +
2190 + jz_udc_set_index(dev, index);
2191 +
2192 + spin_unlock(&dev->lock);
2193 +
2194 + return IRQ_HANDLED;
2195 +}
2196 +
2197 +
2198 +
2199 +/*-------------------------------------------------------------------------*/
2200 +
2201 +/* Common functions - Added by River */
2202 +static struct jz4740_udc udc_dev;
2203 +
2204 +static inline struct jz4740_udc *gadget_to_udc(struct usb_gadget *gadget)
2205 +{
2206 + return container_of(gadget, struct jz4740_udc, gadget);
2207 +}
2208 +/* End added */
2209 +
2210 +static int jz4740_udc_get_frame(struct usb_gadget *_gadget)
2211 +{
2212 + DEBUG("%s, %p\n", __FUNCTION__, _gadget);
2213 + return usb_readw(gadget_to_udc(_gadget), JZ_REG_UDC_FRAME);
2214 +}
2215 +
2216 +static int jz4740_udc_wakeup(struct usb_gadget *_gadget)
2217 +{
2218 + /* host may not have enabled remote wakeup */
2219 + /*if ((UDCCS0 & UDCCS0_DRWF) == 0)
2220 + return -EHOSTUNREACH;
2221 + udc_set_mask_UDCCR(UDCCR_RSM); */
2222 + return -ENOTSUPP;
2223 +}
2224 +
2225 +static int jz4740_udc_pullup(struct usb_gadget *_gadget, int on)
2226 +{
2227 + struct jz4740_udc *udc = gadget_to_udc(_gadget);
2228 + unsigned long flags;
2229 +
2230 + local_irq_save(flags);
2231 +
2232 + if (on) {
2233 + udc->state = UDC_STATE_ENABLE;
2234 + udc_enable(udc);
2235 + } else {
2236 + udc->state = UDC_STATE_DISABLE;
2237 + udc_disable(udc);
2238 + }
2239 +
2240 + local_irq_restore(flags);
2241 +
2242 + return 0;
2243 +}
2244 +
2245 +
2246 +static const struct usb_gadget_ops jz4740_udc_ops = {
2247 + .get_frame = jz4740_udc_get_frame,
2248 + .wakeup = jz4740_udc_wakeup,
2249 + .pullup = jz4740_udc_pullup,
2250 + /* current versions must always be self-powered */
2251 +};
2252 +
2253 +static struct usb_ep_ops jz4740_ep_ops = {
2254 + .enable = jz4740_ep_enable,
2255 + .disable = jz4740_ep_disable,
2256 +
2257 + .alloc_request = jz4740_alloc_request,
2258 + .free_request = jz4740_free_request,
2259 +
2260 + .queue = jz4740_queue,
2261 + .dequeue = jz4740_dequeue,
2262 +
2263 + .set_halt = jz4740_set_halt,
2264 + .fifo_status = jz4740_fifo_status,
2265 + .fifo_flush = jz4740_fifo_flush,
2266 +};
2267 +
2268 +
2269 +/*-------------------------------------------------------------------------*/
2270 +
2271 +static struct jz4740_udc udc_dev = {
2272 + .usb_address = 0,
2273 + .gadget = {
2274 + .ops = &jz4740_udc_ops,
2275 + .ep0 = &udc_dev.ep[0].ep,
2276 + .name = "jz-udc",
2277 + .dev = {
2278 + .init_name = "gadget",
2279 + },
2280 + },
2281 +
2282 + /* control endpoint */
2283 + .ep[0] = {
2284 + .ep = {
2285 + .name = "ep0",
2286 + .ops = &jz4740_ep_ops,
2287 + .maxpacket = EP0_MAXPACKETSIZE,
2288 + },
2289 + .dev = &udc_dev,
2290 +
2291 + .bEndpointAddress = 0,
2292 + .bmAttributes = 0,
2293 +
2294 + .type = ep_control,
2295 + .fifo = JZ_REG_UDC_EP_FIFO(0),
2296 + .csr = JZ_REG_UDC_CSR0,
2297 + },
2298 +
2299 + /* bulk out endpoint */
2300 + .ep[1] = {
2301 + .ep = {
2302 + .name = "ep1out-bulk",
2303 + .ops = &jz4740_ep_ops,
2304 + .maxpacket = EPBULK_MAXPACKETSIZE,
2305 + },
2306 + .dev = &udc_dev,
2307 +
2308 + .bEndpointAddress = 1,
2309 + .bmAttributes = USB_ENDPOINT_XFER_BULK,
2310 +
2311 + .type = ep_bulk_out,
2312 + .fifo = JZ_REG_UDC_EP_FIFO(1),
2313 + .csr = JZ_REG_UDC_OUTCSR,
2314 + },
2315 +
2316 + /* bulk in endpoint */
2317 + .ep[2] = {
2318 + .ep = {
2319 + .name = "ep1in-bulk",
2320 + .ops = &jz4740_ep_ops,
2321 + .maxpacket = EPBULK_MAXPACKETSIZE,
2322 + },
2323 + .dev = &udc_dev,
2324 +
2325 + .bEndpointAddress = 1 | USB_DIR_IN,
2326 + .bmAttributes = USB_ENDPOINT_XFER_BULK,
2327 +
2328 + .type = ep_bulk_in,
2329 + .fifo = JZ_REG_UDC_EP_FIFO(1),
2330 + .csr = JZ_REG_UDC_INCSR,
2331 + },
2332 +
2333 + /* interrupt in endpoint */
2334 + .ep[3] = {
2335 + .ep = {
2336 + .name = "ep2in-int",
2337 + .ops = &jz4740_ep_ops,
2338 + .maxpacket = EPINTR_MAXPACKETSIZE,
2339 + },
2340 + .dev = &udc_dev,
2341 +
2342 + .bEndpointAddress = 2 | USB_DIR_IN,
2343 + .bmAttributes = USB_ENDPOINT_XFER_INT,
2344 +
2345 + .type = ep_interrupt,
2346 + .fifo = JZ_REG_UDC_EP_FIFO(2),
2347 + .csr = JZ_REG_UDC_INCSR,
2348 + },
2349 +};
2350 +
2351 +static void gadget_release(struct device *_dev)
2352 +{
2353 +}
2354 +
2355 +
2356 +static int __devinit jz4740_udc_probe(struct platform_device *pdev)
2357 +{
2358 + struct jz4740_udc *dev = &udc_dev;
2359 + int ret;
2360 +
2361 + spin_lock_init(&dev->lock);
2362 + the_controller = dev;
2363 +
2364 + dev->dev = &pdev->dev;
2365 + dev_set_name(&dev->gadget.dev, "gadget");
2366 + dev->gadget.dev.parent = &pdev->dev;
2367 + dev->gadget.dev.dma_mask = pdev->dev.dma_mask;
2368 + dev->gadget.dev.release = gadget_release;
2369 +
2370 + ret = device_register(&dev->gadget.dev);
2371 + if (ret)
2372 + return ret;
2373 +
2374 + dev->clk = clk_get(&pdev->dev, "udc");
2375 + if (IS_ERR(dev->clk)) {
2376 + ret = PTR_ERR(dev->clk);
2377 + dev_err(&pdev->dev, "Failed to get udc clock: %d\n", ret);
2378 + goto err_device_unregister;
2379 + }
2380 +
2381 + platform_set_drvdata(pdev, dev);
2382 +
2383 + dev->mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2384 +
2385 + if (!dev->mem) {
2386 + ret = -ENOENT;
2387 + dev_err(&pdev->dev, "Failed to get mmio memory resource\n");
2388 + goto err_clk_put;
2389 + }
2390 +
2391 + dev->mem = request_mem_region(dev->mem->start, resource_size(dev->mem), pdev->name);
2392 +
2393 + if (!dev->mem) {
2394 + ret = -EBUSY;
2395 + dev_err(&pdev->dev, "Failed to request mmio memory region\n");
2396 + goto err_device_unregister;
2397 + }
2398 +
2399 + dev->base = ioremap(dev->mem->start, resource_size(dev->mem));
2400 +
2401 + if (!dev->base) {
2402 + ret = -EBUSY;
2403 + dev_err(&pdev->dev, "Failed to ioremap mmio memory\n");
2404 + goto err_release_mem_region;
2405 + }
2406 +
2407 + dev->irq = platform_get_irq(pdev, 0);
2408 +
2409 + ret = request_irq(dev->irq, jz4740_udc_irq, IRQF_DISABLED,
2410 + pdev->name, dev);
2411 + if (ret) {
2412 + dev_err(&pdev->dev, "Failed to request irq: %d\n", ret);
2413 + goto err_iounmap;
2414 + }
2415 +
2416 + udc_disable(dev);
2417 + udc_reinit(dev);
2418 +
2419 + return 0;
2420 +
2421 +err_iounmap:
2422 + iounmap(dev->base);
2423 +err_release_mem_region:
2424 + release_mem_region(dev->mem->start, resource_size(dev->mem));
2425 +err_clk_put:
2426 + clk_put(dev->clk);
2427 +err_device_unregister:
2428 + device_unregister(&dev->gadget.dev);
2429 + platform_set_drvdata(pdev, NULL);
2430 +
2431 + the_controller = 0;
2432 +
2433 + return ret;
2434 +}
2435 +
2436 +static int __devexit jz4740_udc_remove(struct platform_device *pdev)
2437 +{
2438 + struct jz4740_udc *dev = platform_get_drvdata(pdev);
2439 +
2440 + if (dev->driver)
2441 + return -EBUSY;
2442 +
2443 + udc_disable(dev);
2444 +
2445 + free_irq(dev->irq, dev);
2446 + iounmap(dev->base);
2447 + release_mem_region(dev->mem->start, resource_size(dev->mem));
2448 + clk_put(dev->clk);
2449 +
2450 + platform_set_drvdata(pdev, NULL);
2451 + device_unregister(&dev->gadget.dev);
2452 + the_controller = NULL;
2453 +
2454 + return 0;
2455 +}
2456 +
2457 +#ifdef CONFIG_PM
2458 +
2459 +static int jz4740_udc_suspend(struct device *dev)
2460 +{
2461 + struct jz4740_udc *udc = dev_get_drvdata(dev);
2462 +
2463 + if (udc->state == UDC_STATE_ENABLE)
2464 + udc_disable(udc);
2465 +
2466 + return 0;
2467 +}
2468 +
2469 +static int jz4740_udc_resume(struct device *dev)
2470 +{
2471 + struct jz4740_udc *udc = dev_get_drvdata(dev);
2472 +
2473 + if (udc->state == UDC_STATE_ENABLE)
2474 + udc_enable(udc);
2475 +
2476 + return 0;
2477 +}
2478 +
2479 +static struct dev_pm_ops jz4740_udc_pm_ops = {
2480 + .suspend = jz4740_udc_suspend,
2481 + .resume = jz4740_udc_resume,
2482 +};
2483 +
2484 +#define JZ4740_UDC_PM_OPS (&jz4740_udc_pm_ops)
2485 +
2486 +#else
2487 +
2488 +#define JZ4740_UDC_PM_OPS NULL
2489 +
2490 +#endif
2491 +
2492 +static struct platform_driver udc_driver = {
2493 + .probe = jz4740_udc_probe,
2494 + .remove = __devexit_p(jz4740_udc_remove),
2495 + .driver = {
2496 + .name = "jz-udc",
2497 + .owner = THIS_MODULE,
2498 + .pm = JZ4740_UDC_PM_OPS,
2499 + },
2500 +};
2501 +
2502 +/*-------------------------------------------------------------------------*/
2503 +
2504 +static int __init udc_init (void)
2505 +{
2506 + return platform_driver_register(&udc_driver);
2507 +}
2508 +module_init(udc_init);
2509 +
2510 +static void __exit udc_exit (void)
2511 +{
2512 + platform_driver_unregister(&udc_driver);
2513 +}
2514 +module_exit(udc_exit);
2515 +
2516 +MODULE_DESCRIPTION("JZ4740 USB Device Controller");
2517 +MODULE_AUTHOR("Wei Jianli <jlwei@ingenic.cn>");
2518 +MODULE_LICENSE("GPL");
2519 --- /dev/null
2520 +++ b/drivers/usb/gadget/jz4740_udc.h
2521 @@ -0,0 +1,100 @@
2522 +/*
2523 + * linux/drivers/usb/gadget/jz4740_udc.h
2524 + *
2525 + * Ingenic JZ4740 on-chip high speed USB device controller
2526 + *
2527 + * Copyright (C) 2006 Ingenic Semiconductor Inc.
2528 + * Author: <jlwei@ingenic.cn>
2529 + *
2530 + * This program is free software; you can redistribute it and/or modify
2531 + * it under the terms of the GNU General Public License as published by
2532 + * the Free Software Foundation; either version 2 of the License, or
2533 + * (at your option) any later version.
2534 + */
2535 +
2536 +#ifndef __USB_GADGET_JZ4740_H__
2537 +#define __USB_GADGET_JZ4740_H__
2538 +
2539 +/*-------------------------------------------------------------------------*/
2540 +
2541 +// Max packet size
2542 +#define EP0_MAXPACKETSIZE 64
2543 +#define EPBULK_MAXPACKETSIZE 512
2544 +#define EPINTR_MAXPACKETSIZE 64
2545 +
2546 +#define UDC_MAX_ENDPOINTS 4
2547 +
2548 +/*-------------------------------------------------------------------------*/
2549 +
2550 +typedef enum ep_type {
2551 + ep_control, ep_bulk_in, ep_bulk_out, ep_interrupt
2552 +} ep_type_t;
2553 +
2554 +struct jz4740_ep {
2555 + struct usb_ep ep;
2556 + struct jz4740_udc *dev;
2557 +
2558 + const struct usb_endpoint_descriptor *desc;
2559 + unsigned long pio_irqs;
2560 +
2561 + uint8_t stopped;
2562 + uint8_t bEndpointAddress;
2563 + uint8_t bmAttributes;
2564 +
2565 + ep_type_t type;
2566 + size_t fifo;
2567 + u32 csr;
2568 +
2569 + uint32_t reg_addr;
2570 + struct list_head queue;
2571 +};
2572 +
2573 +struct jz4740_request {
2574 + struct usb_request req;
2575 + struct list_head queue;
2576 +};
2577 +
2578 +enum ep0state {
2579 + WAIT_FOR_SETUP, /* between STATUS ack and SETUP report */
2580 + DATA_STATE_XMIT, /* data tx stage */
2581 + DATA_STATE_NEED_ZLP, /* data tx zlp stage */
2582 + WAIT_FOR_OUT_STATUS, /* status stages */
2583 + DATA_STATE_RECV, /* data rx stage */
2584 +};
2585 +
2586 +/* For function binding with UDC Disable - Added by River */
2587 +typedef enum {
2588 + UDC_STATE_ENABLE = 0,
2589 + UDC_STATE_DISABLE,
2590 +}udc_state_t;
2591 +
2592 +struct jz4740_udc {
2593 + struct usb_gadget gadget;
2594 + struct usb_gadget_driver *driver;
2595 + struct device *dev;
2596 + spinlock_t lock;
2597 + unsigned long lock_flags;
2598 +
2599 + enum ep0state ep0state;
2600 + struct jz4740_ep ep[UDC_MAX_ENDPOINTS];
2601 +
2602 + unsigned char usb_address;
2603 +
2604 + udc_state_t state;
2605 +
2606 + struct resource *mem;
2607 + void __iomem *base;
2608 + int irq;
2609 + uint32_t in_mask;
2610 + uint32_t out_mask;
2611 +
2612 + struct clk *clk;
2613 +};
2614 +
2615 +extern struct jz4740_udc *the_controller;
2616 +
2617 +#define ep_is_in(EP) (((EP)->bEndpointAddress&USB_DIR_IN)==USB_DIR_IN)
2618 +#define ep_maxpacket(EP) ((EP)->ep.maxpacket)
2619 +#define ep_index(EP) ((EP)->bEndpointAddress&0xF)
2620 +
2621 +#endif /* __USB_GADGET_JZ4740_H__ */
Personal OpenWRT clone
This page took 0.152431 seconds and 5 git commands to generate.