target/linux/adm5120/files/arch/mips/pci/pci-adm5120.c

   1 /*
   2  *  $Id$
   3  *
   4  *  ADM5120 PCI Host Controller driver
   5  *
   6  *  Copyright (C) 2007 OpenWrt.org
   7  *  Copyright (C) 2007 Gabor Juhos <juhosg at openwrt.org>
   8  *
   9  *  This code was based on the ADM5120 specific port of the Linux 2.6.10 kernel
  10  *  done by Jeroen Vreeken
  11  *      Copyright (C) 2005 Jeroen Vreeken (pe1rxq@amsat.org)
  12  *
  13  *  Jeroen's code was based on the Linux 2.4.xx source codes found in various
  14  *  tarballs released by Edimax for it's ADM5120 based devices
  15  *      Copyright (C) ADMtek Incorporated
  16  *
  17  *  This program is free software; you can redistribute it and/or modify it
  18  *  under the terms of the GNU General Public License version 2 as published
  19  *  by the Free Software Foundation.
  20  *
  21  */
  22 #include <linux/types.h>
  23 #include <linux/kernel.h>
  24 #include <linux/init.h>
  25 #include <linux/spinlock.h>
  26 #include <linux/io.h>
  27
  28 #include <linux/pci.h>
  29 #include <linux/pci_ids.h>
  30 #include <linux/pci_regs.h>
  31
  32 #include <asm/delay.h>
  33 #include <asm/bootinfo.h>
  34
  35 #include <adm5120_defs.h>
  36 #include <adm5120_info.h>
  37 #include <adm5120_defs.h>
  38 #include <adm5120_platform.h>
  39
  40 #undef DEBUG
  41
  42 #ifdef DEBUG
  43 #define DBG(f, a...)    printk(KERN_DEBUG f, ## a)
  44 #else
  45 #define DBG(f, a...)    do {} while (0)
  46 #endif
  47
  48 #define PCI_ENABLE 0x80000000
  49
  50 /* -------------------------------------------------------------------------*/
  51
  52 static unsigned int adm5120_pci_nr_irqs __initdata;
  53 static struct adm5120_pci_irq *adm5120_pci_irq_map __initdata;
  54
  55 static spinlock_t pci_lock = SPIN_LOCK_UNLOCKED;
  56
  57 /* -------------------------------------------------------------------------*/
  58
  59 static inline void write_cfgaddr(u32 addr)
  60 {
  61         __raw_writel((addr | PCI_ENABLE),
  62                 (void __iomem *)(KSEG1ADDR(ADM5120_PCICFG_ADDR)));
  63 }
  64
  65 static inline void write_cfgdata(u32 data)
  66 {
  67         __raw_writel(data, (void __iomem *)KSEG1ADDR(ADM5120_PCICFG_DATA));
  68 }
  69
  70 static inline u32 read_cfgdata(void)
  71 {
  72         return __raw_readl((void __iomem *)KSEG1ADDR(ADM5120_PCICFG_DATA));
  73 }
  74
  75 static inline u32 mkaddr(struct pci_bus *bus, unsigned int devfn, int where)
  76 {
  77         return (((bus->number & 0xFF) << 16) | ((devfn & 0xFF) << 8) | \
  78                 (where & 0xFC));
  79 }
  80
  81 /* -------------------------------------------------------------------------*/
  82
  83 static int pci_config_read(struct pci_bus *bus, unsigned int devfn, int where,
  84                 int size, u32 *val)
  85 {
  86         unsigned long flags;
  87         u32 data;
  88
  89         spin_lock_irqsave(&pci_lock, flags);
  90
  91         write_cfgaddr(mkaddr(bus, devfn, where));
  92         data = read_cfgdata();
  93
  94         DBG("PCI: cfg_read  %02u.%02u.%01u/%02X:%01d, cfg:0x%08X",
  95                 bus->number, PCI_SLOT(devfn), PCI_FUNC(devfn),
  96                 where, size, data);
  97
  98         switch (size) {
  99         case 1:
 100                 if (where & 1)
 101                         data >>= 8;
 102                 if (where & 2)
 103                         data >>= 16;
 104                 data &= 0xFF;
 105                 break;
 106         case 2:
 107                 if (where & 2)
 108                         data >>= 16;
 109                 data &= 0xFFFF;
 110                 break;
 111         }
 112
 113         *val = data;
 114         DBG(", 0x%08X returned\n", data);
 115
 116         spin_unlock_irqrestore(&pci_lock, flags);
 117
 118         return PCIBIOS_SUCCESSFUL;
 119 }
 120
 121 static int pci_config_write(struct pci_bus *bus, unsigned int devfn, int where,
 122                 int size, u32 val)
 123 {
 124         unsigned long flags;
 125         u32 data;
 126         int s;
 127
 128         spin_lock_irqsave(&pci_lock, flags);
 129
 130         write_cfgaddr(mkaddr(bus, devfn, where));
 131         data = read_cfgdata();
 132
 133         DBG("PCI: cfg_write %02u.%02u.%01u/%02X:%01d, cfg:0x%08X",
 134                 bus->number, PCI_SLOT(devfn), PCI_FUNC(devfn),
 135                 where, size, data);
 136
 137         switch (size) {
 138         case 1:
 139                 s = ((where & 3) << 3);
 140                 data &= ~(0xFF << s);
 141                 data |= ((val & 0xFF) << s);
 142                 break;
 143         case 2:
 144                 s = ((where & 2) << 4);
 145                 data &= ~(0xFFFF << s);
 146                 data |= ((val & 0xFFFF) << s);
 147                 break;
 148         case 4:
 149                 data = val;
 150                 break;
 151         }
 152
 153         write_cfgdata(data);
 154         DBG(", 0x%08X written\n", data);
 155
 156         spin_unlock_irqrestore(&pci_lock, flags);
 157
 158         return PCIBIOS_SUCCESSFUL;
 159 }
 160
 161 struct pci_ops adm5120_pci_ops = {
 162         .read   = pci_config_read,
 163         .write  = pci_config_write,
 164 };
 165
 166 /* -------------------------------------------------------------------------*/
 167
 168 static void adm5120_pci_fixup(struct pci_dev *dev)
 169 {
 170         if (dev->devfn != 0)
 171                 return;
 172
 173         /* setup COMMAND register */
 174         pci_write_config_word(dev, PCI_COMMAND,
 175                 (PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER));
 176
 177         /* setup CACHE_LINE_SIZE register */
 178         pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, 4);
 179
 180         /* setup BARS */
 181         pci_write_config_dword(dev, PCI_BASE_ADDRESS_0, 0);
 182         pci_write_config_dword(dev, PCI_BASE_ADDRESS_1, 0);
 183 }
 184
 185 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ADMTEK, PCI_DEVICE_ID_ADMTEK_ADM5120,
 186         adm5120_pci_fixup);
 187
 188 /* -------------------------------------------------------------------------*/
 189
 190 void __init adm5120_pci_set_irq_map(unsigned int nr_irqs,
 191                 struct adm5120_pci_irq *map)
 192 {
 193         adm5120_pci_nr_irqs = nr_irqs;
 194         adm5120_pci_irq_map = map;
 195 }
 196
 197 int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
 198 {
 199         int irq = -1;
 200         int i;
 201
 202         if ((!adm5120_pci_nr_irqs) || (!adm5120_pci_irq_map)) {
 203                 printk(KERN_ALERT "PCI: pci_irq_map is not initialized\n");
 204                 goto out;
 205         }
 206
 207         if (slot < 1 || slot > 3) {
 208                 printk(KERN_ALERT "PCI: slot number %u is not supported\n",
 209                         slot);
 210                 goto out;
 211         }
 212
 213         for (i = 0; i < adm5120_pci_nr_irqs; i++) {
 214                 if ((adm5120_pci_irq_map[i].slot == slot)
 215                         && (adm5120_pci_irq_map[i].func == PCI_FUNC(dev->devfn))
 216                         && (adm5120_pci_irq_map[i].pin == pin)) {
 217                         irq = adm5120_pci_irq_map[i].irq;
 218                         break;
 219                 }
 220         }
 221
 222         if (irq < 0) {
 223                 printk(KERN_ALERT "PCI: no irq found for %s pin:%u\n",
 224                         pci_name((struct pci_dev *)dev), pin);
 225         } else {
 226                 printk(KERN_INFO "PCI: mapping irq for %s pin:%u, irq:%d\n",
 227                         pci_name((struct pci_dev *)dev), pin, irq);
 228         }
 229
 230 out:
 231         return irq;
 232 }
 233
 234 int pcibios_plat_dev_init(struct pci_dev *dev)
 235 {
 236         return 0;
 237 }
 238
 239 /* -------------------------------------------------------------------------*/
 240
 241 static struct resource pci_io_resource = {
 242         .name   = "ADM5120 PCI I/O",
 243         .start  = ADM5120_PCIIO_BASE,
 244         .end    = ADM5120_PCICFG_ADDR-1,
 245         .flags  = IORESOURCE_IO
 246 };
 247
 248 static struct resource pci_mem_resource = {
 249         .name   = "ADM5120 PCI MEM",
 250         .start  = ADM5120_PCIMEM_BASE,
 251         .end    = ADM5120_PCIIO_BASE-1,
 252         .flags  = IORESOURCE_MEM
 253 };
 254
 255 static struct pci_controller adm5120_controller = {
 256         .pci_ops        = &adm5120_pci_ops,
 257         .io_resource    = &pci_io_resource,
 258         .mem_resource   = &pci_mem_resource,
 259 };
 260
 261 static int __init adm5120_pci_setup(void)
 262 {
 263         int pci_bios;
 264
 265         pci_bios = adm5120_has_pci();
 266
 267         printk(KERN_INFO "adm5120: system has %sPCI BIOS\n",
 268                 pci_bios ? "" : "no ");
 269         if (pci_bios == 0)
 270                 return -1;
 271
 272         /* Avoid ISA compat ranges.  */
 273         PCIBIOS_MIN_IO = 0x00000000;
 274         PCIBIOS_MIN_MEM = 0x00000000;
 275
 276         /* Set I/O resource limits.  */
 277         ioport_resource.end = 0x1fffffff;
 278         iomem_resource.end = 0xffffffff;
 279
 280         register_pci_controller(&adm5120_controller);
 281         return 0;
 282 }
 283
 284 arch_initcall(adm5120_pci_setup);